US20140203429A1 - Fan-out package structure and methods for forming the same - Google Patents
Fan-out package structure and methods for forming the same Download PDFInfo
- Publication number
- US20140203429A1 US20140203429A1 US13/896,889 US201313896889A US2014203429A1 US 20140203429 A1 US20140203429 A1 US 20140203429A1 US 201313896889 A US201313896889 A US 201313896889A US 2014203429 A1 US2014203429 A1 US 2014203429A1
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- US
- United States
- Prior art keywords
- die
- metal pillars
- dielectric layer
- package
- device die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 229920000642 polymer Polymers 0.000 claims abstract description 31
- 230000015654 memory Effects 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 238000000465 moulding Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 35
- 239000012778 molding material Substances 0.000 description 19
- 239000012790 adhesive layer Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
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- 239000010949 copper Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- IOPBNBSKOPJKEG-UHFFFAOYSA-N 1,2-dichloro-3-(3,5-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC(C=2C(=C(Cl)C=CC=2)Cl)=C1 IOPBNBSKOPJKEG-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Definitions
- 3G video elements In integrated circuit applications, more and more functions are integrated into products. For example, different functional elements such as 3G video elements, WiFi elements, Bluetooth elements, and audio/video elements may need to be integrated together to form an application.
- 3G video elements In integrated circuit applications, more and more functions are integrated into products.
- WiFi elements WiFi elements, Bluetooth elements, and audio/video elements may need to be integrated together to form an application.
- audio/video elements may need to be integrated together to form an application.
- a power management integrated circuit die, a transceiver die, and a multi-layer ceramic capacitor may be bonded using this scheme.
- the resulting package is typically very thick and large in area.
- FIGS. 1 through 8 include cross-sectional views of intermediate stages in the manufacturing of a fan-out package structure in accordance with some exemplary embodiments, wherein a fan-out package structure is built from molded devices.
- a fan-out package structure and the methods of forming the same are provided in accordance with various exemplary embodiments.
- the intermediate stages of forming the fan-out package structure are illustrated.
- the variations of the embodiments are discussed.
- like reference numbers are used to designate like elements.
- FIGS. 1 through 8 include cross-sectional views of intermediate stages in the manufacturing of a fan-out structure in accordance with some exemplary embodiments.
- FIG. 1 illustrates carrier 20 , and adhesive layer 22 on carrier 20 .
- Carrier 20 may be a glass carrier, a ceramic carrier, or the like.
- Adhesive layer 22 may be formed of an adhesive such as an Ultra-Violet (UV) glue.
- UV Ultra-Violet
- FIG. 2 illustrates the placement of device die(s) 24 and die stacks 124 and 224 .
- Device die 24 and die stacks 124 and 224 are placed over carrier 20 .
- device die 24 and die stacks 124 and 224 are attached to adhesive layer 22 , which is adhered to carrier 20 .
- Device die 24 may be a logic device die including logic transistors therein.
- device die 24 is a Central Processing Unit (CPU) die.
- device die 24 is a Graphics Processing Unit (GPU) die.
- Device die 24 may include a semiconductor substrate and active devices (such as transistors, not shown) formed on a surface of the semiconductor substrate.
- Each of die stacks 124 and 224 may include a plurality of memory dies 324 bonded together to form a memory stack.
- Die stacks 124 and 224 may include Dynamic Random Access Memory (DRAM) dies, Static Random Access Memory (SRAM) dies, or memory dies formed of other types of memories.
- memory dies 324 are pre-bonded (for example, through solder bonding, direct metal-to-metal bonding, or the like) to form die stacks 124 and 224 , and then the bonded die stacks 124 and 224 are placed over carrier 20 .
- die stacks 124 and 224 are formed of a same type of memory (such as SRAM or DRAM).
- die stacks 124 and 224 are the stacks of different types of memories.
- Electrical connectors 26 are formed as the top portions of device die 24 and die stacks 124 and 224 , and are electrically coupled to the devices in device die 24 and die stacks 124 and 224 .
- electrical connectors 26 include metal pillars 26 (such as copper pillars), which may be pre-formed before device die 24 and die stacks 124 and 224 are placed over carrier 20 .
- Metal pillars 26 may be solder-free, and may comprise vertical sidewalls.
- dielectric layers 27 are formed at the top surfaces of device die 24 and die stacks 124 and 224 , with metal pillars 26 having at least lower portions, or entireties, in dielectric layer 27 .
- dielectric layers 27 may also be substantially level with the top ends of metal pillars 26 .
- Dielectric layers 27 may comprise polyimide, polybenzoxazole (PBO), an oxide layer, a nitride layer, or multi-layers thereof. Alternatively, dielectric layers 27 are not formed, and metal pillars 26 protrude above the remaining portions of device die 24 and die stacks 124 and 224 . In subsequently illustrated drawings, dielectric layers 27 are not illustrated, although they may also exist in some embodiments.
- the thicknesses of device die 24 , die stacks 124 and 224 , and the heights of metal pillars 26 are controlled so that the top ends of metal pillars 26 of device die 24 are substantially level with the top ends of metal pillars 26 of die stacks 124 and 224 . Furthermore, since device die 24 and die stacks 124 and 224 are placed over carrier 20 (for example, on adhesive 22 ), the back surfaces of device die 24 and die stacks 124 and 224 are level with each other.
- FIG. 2B illustrates a top view of the structure in FIG. 2A .
- the cross-sectional view in FIG. 2A is obtained from a plane crossing line 2 A- 2 A in FIG. 2B .
- device die 24 and die stacks 124 and 224 are shown in the same plane in FIG. 2A for clarity, although they are not necessarily in the same plane, as shown in FIG. 2B , for example.
- the placement of device die 24 and die stacks 124 and 224 is at the wafer level, and hence there are a plurality of device dies 24 and a plurality of die stacks 124 and 224 placed over carrier 20 .
- FIG. 2B illustrates that carrier 20 has a round top-view shape.
- carrier 20 may also have a rectangular top-view shape, and device die 24 and die stacks 124 and 224 may be laid out as an array.
- the rectangles (not marked) encircling each groups of device die 24 and die stacks 124 and 224 mark the boundaries of the respective packages 48 ( FIG. 7 ), which packages are formed in subsequent steps.
- molding material 40 is dispensed and molded on device die 24 and die stacks 124 and 224 .
- Molding material 40 fills the gaps between device die 24 and die stacks 124 and 224 , and may be in contact with adhesive layer 22 . Furthermore, molding material 40 may be filled into the gaps between metal pillars 26 if dielectric layers 27 ( FIG. 2 ) are not formed.
- Molding material 40 comprises a polymer in some embodiments.
- molding material 40 may include a molding compound, a molding underfill, an epoxy, or a resin.
- the top surface of molding material 40 is higher than the top ends of metal pillars 26 .
- the bottom surface of molding material 40 is level with the back surfaces of device die 24 and die stacks 124 and 224 . After being dispensed, molding material 40 is cured.
- a planarization step which may be a grinding step or a Chemical Mechanical Polish (CMP) is performed to thin molding material 40 , until metal pillars 26 are exposed.
- CMP Chemical Mechanical Polish
- the resulting structure is shown in FIG. 4 .
- the top ends 26 A of metal pillars 26 in device die 24 and die stacks 124 and 224 are level with each other, and are level with top surface 40 A of molding material 40 .
- molding material 40 encircles, and is in contact with, each of metal pillars 26 .
- the top ends 26 A of metal pillars 26 are level with each other, and are substantially level with the surfaces of dielectric layers 27 and top surface 40 A of molding material 40 .
- Redistribution Lines (RDLs) 42 are formed over molding material 40 .
- RDLs 42 are also electrically connected to, and may interconnect, metal pillars 26 .
- RDLs 42 are formed in dielectric layers 44 . There may be one, two, three, or more redistribution layer, each including a plurality of RDLs 42 that is at the same level.
- RDLs 42 further include vias that interconnect the RDLs in neighboring redistribution layers.
- the RDLs 42 in the bottom redistribution layer and the respective dielectric layer 44 have bottom surfaces in contact with the top ends of metal pillars 26 and the top surface of molding material 40 .
- RDLs 42 are formed by forming and patterning dielectric layers 44 , and forming RDLs 42 in the openings in the patterned dielectric layers 44 .
- RDLs 42 are formed by depositing metal layers, patterning the metal layers, and filling the gaps between RDLs 42 with dielectric layers 44 .
- RDLs 42 and dielectric layers 44 are formed using damascene processes.
- RDLs 42 may comprise copper, nickel, palladium, aluminum, tungsten, or the like.
- Dielectric layers 44 may comprise photo-sensitive materials such as polyimide, PBO, or the like, which may be patterned without using additional photo resists.
- Dielectric layers 44 may also be formed of a non-organic material or materials such as oxides and/or nitrides.
- RDLs 42 and dielectric layers 44 are in combination referred to as interposer 45 throughout the description.
- interposer 45 is formed starting from molding material 40 , device die 24 , and die stacks 124 and 224 , which in combination act as a wafer having enough thickness and strength to support the formation of interposer 45 .
- interposer 45 may be very thin, for example, with a thickness smaller than about 50 ⁇ m without the concern that it may break during its formation and the subsequent handling.
- FIG. 5 also illustrates the formation of electrical connectors 46 in accordance with some exemplary embodiments.
- the formation of connectors 46 may include placing solder balls on the exposed portions of RDLs 42 , and then reflowing the solder balls.
- the formation of connectors 46 includes performing a plating step to form solder regions over RDLs 42 , and then reflowing the solder regions.
- Connectors 46 may also include metal pillars, or metal pillars and solder caps, which may also be formed through plating.
- package 48 the combined structure including device die 24 , die stacks 124 and 224 , molding material 40 , and the overlying RDLs 42 and dielectric layers 44 is referred to as package 48 hereinafter.
- Package 48 is a part of a wafer 148 that includes a plurality of packages 48 .
- dicing tap 50 is attached to package 48 and the respective wafer 148 , wherein carrier 20 and dicing tape 50 are on the opposite sides of package 48 .
- carrier 20 is detached from package 48 .
- Adhesive layer 22 is then removed.
- adhesive layer 22 is formed of the UV glue, adhesive layer 22 may be exposed to UV light, so that adhesive layer 22 loses adhesion, and hence carrier 20 and adhesive layer 22 can be removed from package 48 .
- the resulting structure is shown in FIG. 7 .
- wafer 148 is sawed apart along scribe lines 52 to separate wafer 148 into a plurality of packages 48 .
- packages 48 may include device die 24 and die stacks 124 and 224 , molding material 40 , and a piece of interposer 45 that includes RDLs 42 and dielectric layers 44 .
- the edges of dielectric layers 44 are aligned to the respective edges of molding material 40 .
- FIG. 8 illustrates the bonding and/or the attachment of package 48 to other package components.
- connectors 46 are used to bond package 48 to another package component 58 , which is a Printed Circuit Board (PCB) in some exemplary embodiments.
- PCB Printed Circuit Board
- no additional interposer and package substrate are bonded between package 48 and PCB 58 .
- Interposer 45 which is built in package 48 , is used to electrically couple device die 24 and device stacks 124 and 224 to package component 58 .
- package 48 is bonded to an additional package substrate (not shown), which is further bonded to a PCB.
- FIG. 8 also illustrates that the back surface of package 48 is attached to heat spreader 54 .
- thermal tape (or Thermal Interface Material (TIM)) 56 which has a thermal conductivity higher than the thermal conductivity of typical glues, is used to attach heat spreader 54 to package 48 . Accordingly, the heat generated in device die 24 and device stacks 124 and 224 may be dissipated to heat spreader 54 .
- interposer 45 is built over the device die and device stacks after the device die and device stacks are molded. This is different from the conventional interposers that are manufactured first, and then bonded with device dies and/or device stacks.
- a molding material, a device die, and/or a device stack act as the carrier for forming interposer 45 . Since interposer 45 does not need to be separated from the carrier (the molding compound and the dies molded therein), it can be made very thin without the concern that it may break in the subsequent handling. The thickness of the resulting package is hence significantly reduced.
- a package in accordance with some embodiments, includes a device die including a first plurality of metal pillars at a top surface of the device die.
- the package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack.
- a polymer region includes first portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack.
- a top surface of the polymer region is level with top ends of the first plurality of metal pillars and top ends of the second plurality of metal pillars. Redistribution lines are formed over and electrically coupled to the first and the second plurality of metal pillars.
- a package in accordance with other embodiments, includes a device die including a first plurality of metal pillars at a top surface of the device die.
- the package further includes a die stack, which includes a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack.
- a polymer region molds the device die and the die stack therein, wherein a top surface of the polymer region, top ends of the first plurality of metal pillars, and top ends of the second plurality of metal pillars form a first planar surface.
- a dielectric layer is disposed over the polymer region, wherein edges of the dielectric layer are aligned to respective edges of the polymer region.
- Redistribution lines are disposed in the dielectric layer. The redistribution lines are electrically coupled to the first and the second plurality of metal pillars, and wherein bottom surfaces of the redistribution lines and the dielectric layer form a second planar surface in contact with the first planar surface
- a method includes placing a device die over a carrier, wherein the device die includes a first plurality of metal pillars.
- a die stack is placed over the carrier, wherein the die stack includes a second plurality of metal pillars.
- a polymer is dispensed to mold the device die and the die stack therein.
- a planarization is performed on the polymer until the first and the second plurality of metal pillars are exposed.
- a plurality of redistribution lines is formed over the device die and the die stack. The plurality of redistribution lines is electrically coupled to the first and the second plurality of metal pillars.
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Abstract
Description
- This application claims the benefit of the following provisionally filed U.S. patent application Ser. No. 61/754,362, filed Jan. 18, 2013, and entitled “Fan-Out Package Structure and Methods for Forming the Same,” which application is hereby incorporated herein by reference.
- In integrated circuit applications, more and more functions are integrated into products. For example, different functional elements such as 3G video elements, WiFi elements, Bluetooth elements, and audio/video elements may need to be integrated together to form an application.
- In conventional integration schemes, different components are bonded to an interposer, which is further bonded to a package substrate. For example, in mobile applications, a power management integrated circuit die, a transceiver die, and a multi-layer ceramic capacitor may be bonded using this scheme. The resulting package is typically very thick and large in area.
- For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1 through 8 include cross-sectional views of intermediate stages in the manufacturing of a fan-out package structure in accordance with some exemplary embodiments, wherein a fan-out package structure is built from molded devices. - The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
- A fan-out package structure and the methods of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the fan-out package structure are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
-
FIGS. 1 through 8 include cross-sectional views of intermediate stages in the manufacturing of a fan-out structure in accordance with some exemplary embodiments.FIG. 1 illustratescarrier 20, andadhesive layer 22 oncarrier 20.Carrier 20 may be a glass carrier, a ceramic carrier, or the like.Adhesive layer 22 may be formed of an adhesive such as an Ultra-Violet (UV) glue. -
FIG. 2 illustrates the placement of device die(s) 24 and diestacks stacks carrier 20. In some embodiments, device die 24 and diestacks adhesive layer 22, which is adhered tocarrier 20. Device die 24 may be a logic device die including logic transistors therein. In some exemplary embodiments, device die 24 is a Central Processing Unit (CPU) die. In other embodiments, device die 24 is a Graphics Processing Unit (GPU) die. Device die 24 may include a semiconductor substrate and active devices (such as transistors, not shown) formed on a surface of the semiconductor substrate. - Each of die
stacks stacks die stacks bonded die stacks carrier 20. In some embodiments, diestacks stacks -
Electrical connectors 26 are formed as the top portions of device die 24 and diestacks stacks electrical connectors 26 include metal pillars 26 (such as copper pillars), which may be pre-formed before device die 24 and diestacks carrier 20.Metal pillars 26 may be solder-free, and may comprise vertical sidewalls. In some embodiments,dielectric layers 27 are formed at the top surfaces of device die 24 and diestacks metal pillars 26 having at least lower portions, or entireties, indielectric layer 27. The top surfaces ofdielectric layers 27 may also be substantially level with the top ends ofmetal pillars 26.Dielectric layers 27 may comprise polyimide, polybenzoxazole (PBO), an oxide layer, a nitride layer, or multi-layers thereof. Alternatively,dielectric layers 27 are not formed, andmetal pillars 26 protrude above the remaining portions of device die 24 and diestacks dielectric layers 27 are not illustrated, although they may also exist in some embodiments. The thicknesses of device die 24,die stacks metal pillars 26 are controlled so that the top ends ofmetal pillars 26 of device die 24 are substantially level with the top ends ofmetal pillars 26 of diestacks stacks stacks -
FIG. 2B illustrates a top view of the structure inFIG. 2A . The cross-sectional view inFIG. 2A is obtained from aplane crossing line 2A-2A inFIG. 2B . Furthermore, device die 24 and diestacks FIG. 2A for clarity, although they are not necessarily in the same plane, as shown inFIG. 2B , for example. In some embodiments, the placement of device die 24 and diestacks stacks carrier 20.FIG. 2B illustrates thatcarrier 20 has a round top-view shape. In alternative embodiments,carrier 20 may also have a rectangular top-view shape, and device die 24 and diestacks FIG. 2B , the rectangles (not marked) encircling each groups of device die 24 and diestacks FIG. 7 ), which packages are formed in subsequent steps. - Referring to
FIG. 3 ,molding material 40 is dispensed and molded on device die 24 and diestacks material 40 fills the gaps between device die 24 and diestacks adhesive layer 22. Furthermore,molding material 40 may be filled into the gaps betweenmetal pillars 26 if dielectric layers 27 (FIG. 2 ) are not formed.Molding material 40 comprises a polymer in some embodiments. For example,molding material 40 may include a molding compound, a molding underfill, an epoxy, or a resin. The top surface ofmolding material 40 is higher than the top ends ofmetal pillars 26. The bottom surface ofmolding material 40 is level with the back surfaces of device die 24 and diestacks molding material 40 is cured. - Next, a planarization step, which may be a grinding step or a Chemical Mechanical Polish (CMP), is performed to
thin molding material 40, untilmetal pillars 26 are exposed. The resulting structure is shown inFIG. 4 . The top ends 26A ofmetal pillars 26 in device die 24 and diestacks top surface 40A ofmolding material 40. In some embodiments in which no dielectric layer 27 (FIG. 2 ) is formed,molding material 40 encircles, and is in contact with, each ofmetal pillars 26. In alternative embodiments in which dielectric layers 27 (FIG. 2 ) are formed, the top ends 26A ofmetal pillars 26 are level with each other, and are substantially level with the surfaces ofdielectric layers 27 andtop surface 40A ofmolding material 40. - Next, referring to
FIG. 5 , Redistribution Lines (RDLs) 42 are formed overmolding material 40.RDLs 42 are also electrically connected to, and may interconnect,metal pillars 26.RDLs 42 are formed indielectric layers 44. There may be one, two, three, or more redistribution layer, each including a plurality ofRDLs 42 that is at the same level.RDLs 42 further include vias that interconnect the RDLs in neighboring redistribution layers. The RDLs 42 in the bottom redistribution layer and therespective dielectric layer 44 have bottom surfaces in contact with the top ends ofmetal pillars 26 and the top surface ofmolding material 40. In some embodiments,RDLs 42 are formed by forming and patterningdielectric layers 44, and formingRDLs 42 in the openings in the patterned dielectric layers 44. In alternative embodiments,RDLs 42 are formed by depositing metal layers, patterning the metal layers, and filling the gaps betweenRDLs 42 withdielectric layers 44. In yet alternative embodiments,RDLs 42 anddielectric layers 44 are formed using damascene processes.RDLs 42 may comprise copper, nickel, palladium, aluminum, tungsten, or the like.Dielectric layers 44 may comprise photo-sensitive materials such as polyimide, PBO, or the like, which may be patterned without using additional photo resists.Dielectric layers 44 may also be formed of a non-organic material or materials such as oxides and/or nitrides. RDLs 42 anddielectric layers 44 are in combination referred to asinterposer 45 throughout the description. In accordance with the embodiments of the present disclosure,interposer 45 is formed starting frommolding material 40, device die 24, and diestacks interposer 45. As a result,interposer 45 may be very thin, for example, with a thickness smaller than about 50 μm without the concern that it may break during its formation and the subsequent handling. -
FIG. 5 also illustrates the formation ofelectrical connectors 46 in accordance with some exemplary embodiments. The formation ofconnectors 46 may include placing solder balls on the exposed portions ofRDLs 42, and then reflowing the solder balls. In alternative embodiments, the formation ofconnectors 46 includes performing a plating step to form solder regions over RDLs 42, and then reflowing the solder regions.Connectors 46 may also include metal pillars, or metal pillars and solder caps, which may also be formed through plating. Throughout the description, the combined structure including device die 24, diestacks molding material 40, and the overlying RDLs 42 anddielectric layers 44 is referred to aspackage 48 hereinafter.Package 48 is a part of awafer 148 that includes a plurality ofpackages 48. - Referring to
FIG. 6 , dicingtap 50 is attached to package 48 and therespective wafer 148, whereincarrier 20 and dicingtape 50 are on the opposite sides ofpackage 48. Next,carrier 20 is detached frompackage 48.Adhesive layer 22 is then removed. Whenadhesive layer 22 is formed of the UV glue,adhesive layer 22 may be exposed to UV light, so thatadhesive layer 22 loses adhesion, and hencecarrier 20 andadhesive layer 22 can be removed frompackage 48. The resulting structure is shown inFIG. 7 . - Further referring to
FIG. 7 ,wafer 148 is sawed apart alongscribe lines 52 to separatewafer 148 into a plurality ofpackages 48. Each ofpackages 48 may include device die 24 and diestacks molding material 40, and a piece ofinterposer 45 that includes RDLs 42 and dielectric layers 44. As a result of the sawing, in the resultingpackages 48, the edges ofdielectric layers 44 are aligned to the respective edges ofmolding material 40. -
FIG. 8 illustrates the bonding and/or the attachment ofpackage 48 to other package components. In some embodiments,connectors 46 are used tobond package 48 to anotherpackage component 58, which is a Printed Circuit Board (PCB) in some exemplary embodiments. In some embodiments, no additional interposer and package substrate are bonded betweenpackage 48 andPCB 58.Interposer 45, which is built inpackage 48, is used to electrically couple device die 24 anddevice stacks component 58. In alternative embodiments,package 48 is bonded to an additional package substrate (not shown), which is further bonded to a PCB. -
FIG. 8 also illustrates that the back surface ofpackage 48 is attached to heatspreader 54. In some embodiments, thermal tape (or Thermal Interface Material (TIM)) 56, which has a thermal conductivity higher than the thermal conductivity of typical glues, is used to attachheat spreader 54 to package 48. Accordingly, the heat generated in device die 24 anddevice stacks heat spreader 54. - In accordance with the embodiments of the present disclosure,
interposer 45 is built over the device die and device stacks after the device die and device stacks are molded. This is different from the conventional interposers that are manufactured first, and then bonded with device dies and/or device stacks. In the process for forming the packages in accordance with some embodiments, a molding material, a device die, and/or a device stack act as the carrier for forminginterposer 45. Sinceinterposer 45 does not need to be separated from the carrier (the molding compound and the dies molded therein), it can be made very thin without the concern that it may break in the subsequent handling. The thickness of the resulting package is hence significantly reduced. - In accordance with some embodiments, a package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. A polymer region includes first portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first plurality of metal pillars and top ends of the second plurality of metal pillars. Redistribution lines are formed over and electrically coupled to the first and the second plurality of metal pillars.
- In accordance with other embodiments, a package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack, which includes a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. A polymer region molds the device die and the die stack therein, wherein a top surface of the polymer region, top ends of the first plurality of metal pillars, and top ends of the second plurality of metal pillars form a first planar surface. A dielectric layer is disposed over the polymer region, wherein edges of the dielectric layer are aligned to respective edges of the polymer region. Redistribution lines are disposed in the dielectric layer. The redistribution lines are electrically coupled to the first and the second plurality of metal pillars, and wherein bottom surfaces of the redistribution lines and the dielectric layer form a second planar surface in contact with the first planar surface.
- In accordance with yet other embodiments, a method includes placing a device die over a carrier, wherein the device die includes a first plurality of metal pillars. A die stack is placed over the carrier, wherein the die stack includes a second plurality of metal pillars. A polymer is dispensed to mold the device die and the die stack therein. A planarization is performed on the polymer until the first and the second plurality of metal pillars are exposed. A plurality of redistribution lines is formed over the device die and the die stack. The plurality of redistribution lines is electrically coupled to the first and the second plurality of metal pillars.
- Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims (20)
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