US20140147942A1 - Memory device and method for manufacturing the same - Google Patents
Memory device and method for manufacturing the same Download PDFInfo
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- US20140147942A1 US20140147942A1 US14/172,000 US201414172000A US2014147942A1 US 20140147942 A1 US20140147942 A1 US 20140147942A1 US 201414172000 A US201414172000 A US 201414172000A US 2014147942 A1 US2014147942 A1 US 2014147942A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
-
- H01L45/1675—
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02601—Nanoparticles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02606—Nanotubes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
- H10N70/8845—Carbon or carbides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
Definitions
- Embodiments described herein relate generally to a memory device and a method for manufacturing the same.
- ReRAM Resistance Random Access Memory
- a 3-dimensional cross-point structure has been proposed for the structure of an actual ReRAM device, in which memory cells are disposed at the intersection points of word lines (WL) and bit lines (BL), from the point of view of large scale integration. Also, for commercialization of ReRAM, high reliability is required.
- FIG. 1 is a perspective view illustrating a memory device according to a first embodiment
- FIG. 2 is a schematic cross-sectional view illustrating a pillar of the first embodiment
- FIGS. 3A to 5B are process cross-sectional views illustrating a method for manufacturing a memory device according to the first embodiment
- FIG. 6 is a schematic cross-sectional view illustrating a pillar of a second embodiment.
- FIGS. 7A to 9B are process cross-sectional views illustrating a method for manufacturing a memory device according to the second embodiment.
- a memory device in general, includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer.
- the nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors.
- the first electrode layer is provided on the nanomaterial assembly layer.
- the second electrode layer is provided on the first electrode layer.
- a method for manufacturing a memory device.
- the method can include forming a nanomaterial assembly layer formed of an assembly of a plurality of micro conductors via gaps between the micro conductors.
- the method can include forming a first electrode layer on the nanomaterial assembly layer by depositing a conductive material by a first method in which a coverage is relatively low.
- the method can include forming a second electrode layer on the first electrode layer by depositing a conductive material by a second method in which the coverage is relatively high.
- FIG. 1 is a perspective view illustrating a memory device according to the embodiment.
- FIG. 2 is a schematic cross-sectional view illustrating a pillar of the embodiment.
- the memory device is a ReRAM.
- a silicon substrate 11 is provided, and the drive circuit (not illustrated on the drawing) of the memory device 1 is formed on the top layer portion and top surface of the silicon substrate 11 .
- word line interconnect layers 14 that include a plurality of word lines WL extending in a direction parallel to the top surface of the silicon substrate 11 (hereafter referred to as the “word line direction”) and bit line interconnect layers 15 that include a plurality of bit lines BL extending in a direction parallel to the top surface of the silicon substrate 11 and that intersect the word line direction at, for example, right angles (hereafter referred to as the “bit line direction”) are stacked alternately, with insulating layers disposed therebetween. Also, there is no contact between word lines WL, between bit lines BL, or between word lines WL and bit lines BL.
- pillars 16 extending in the direction normal to the top surface of the silicon substrate 11 (hereafter referred to as the “vertical direction”) are provided at the points of closest proximity between each word line WL and each bit line BL.
- the pillars 16 are formed between word lines WL and bit lines BL.
- a single memory cell is constituted from a single pillar 16 .
- a nonvolatile memory device 1 is a cross-point type device in which memory cells are disposed at each of the nearest neighbor of the word lines WL and the bit lines BL.
- An inter-layer insulating film 17 (see FIGS. 5A and 5B ) is embedded between the word lines WL, the bit lines BL, and the pillars 16 .
- a barrier metal layer 21 in each pillar 16 , a barrier metal layer 21 , a rectifying element layer 22 that has a rectifying action, a lower electrode layer 23 , a nanomaterial assembly layer 24 , a low coverage electrode layer 25 , and a high coverage electrode layer 26 are stacked subsequently from the bottom up.
- the low coverage electrode layer 25 and the high coverage electrode layer 26 form an upper electrode layer for the nanomaterial assembly layer 24 .
- the barrier metal layer 21 is in contact with, for example, the word line WL (see FIG. 1 ), and the high coverage electrode layer 26 is in contact with, for example, the bit line BL (see FIG. 1 ).
- a barrier metal layer 29 is provided between the lowermost word line WL and the inter-layer insulating film 12 .
- the barrier metal layer 29 is a layer for preventing diffusion between the inter-layer insulating film 12 and the word line WL, as well as improving adhesion
- the barrier metal layer 21 is a layer for preventing diffusion between the word line WL and the rectifying element layer 22 , as well as improving adhesion.
- the barrier metal layers 29 and 21 are, for example, formed from a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like.
- the rectifying element layer 22 is made from, for example, a polysilicon diode layer, with a n-type layer of an n + conductivity type, an i-type layer made from an intrinsic semiconductor, and a p-type layers of a p + conductivity type stacked subsequently from the bottom layer side up. In this way, the rectifying element layer 22 functions as a selective element layer in which current only flows when, for example, a potential is supplied to the bit line that is higher than that supplied to the word line WL, and current does not flow in the opposite direction.
- the lower electrode layer 23 is formed from a conductive material such as tungsten or titanium nitride or the like.
- the nanomaterial assembly layer 24 is, for example, an assembly of carbon nanotubes (CNT) 31 as micro conductors, with gaps 32 disposed therebetween.
- the gaps 32 form an air layer, so the structure of the nanomaterial assembly layer 24 is a hollow structure.
- the number of layers of CNT 31 stacked in the thickness direction of the nanomaterial assembly layer 24 is, for example, several layers to several tens of layers.
- the low coverage electrode layer 25 and the high coverage electrode layer 26 are formed from metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like, or metals such as tantalum (Ta), tungsten (W), molybdenum (Mo), or the like.
- the low coverage electrode layer 25 and the high coverage electrode layer 26 may be formed from the same type of material, or they may be formed from mutually different types of materials.
- the thickness of the low coverage electrode layer 25 is, for example, not less than 20 nm
- the thickness of the high coverage electrode layer 26 is, for example, not less than 5 nm.
- parts of the CNT 31 that constitute the nanomaterial assembly layer 24 are embedded in a lower layer 25 b of the low coverage electrode layer 25 .
- the film properties of the low coverage electrode layer 25 and the high coverage electrode layer 26 differ, the coverage of the high coverage electrode layer 26 is higher than the coverage of the low coverage electrode layer 25 .
- the density of the high coverage electrode layer 26 is higher than the density of the low coverage electrode layer 25 .
- the crystalline structure of both the low coverage electrode layer 25 and the high coverage electrode layer 26 is a polycrystalline structure, but the average crystal grain size of the high coverage electrode layer 26 is larger than the average crystal grain size of the low coverage electrode layer 25 .
- the crystalline structure of the low coverage electrode layer 25 may be polycrystalline, and the crystalline structure of the high coverage electrode layer 26 may be an amorphous structure. The differences in these crystalline structures may be confirmed by observing a cross-section of the pillar 16 that includes the vertical direction using a transmission electron microscope (TEM), for example.
- TEM transmission electron microscope
- the low coverage electrode layer 25 is formed by a physical vapor deposition (PVD) method
- the high coverage electrode layer 26 is formed by a chemical vapor deposition (CVD) method. Therefore the high coverage electrode layer 26 includes halogen impurities, but the low coverage electrode layer 25 includes substantially no impurities. In other words, the halogen concentration of the high coverage electrode layer 26 is higher than the halogen concentration of the low coverage electrode layer 25 .
- FIGS. 3A , 3 B, 4 A, 4 B, 5 A, and 5 B are process cross-sectional views illustrating the method for manufacturing the memory device according to the embodiment.
- the drive circuit for driving the memory cell unit 13 is formed on the surface of the silicon substrate 11 .
- the inter-layer insulating film 12 is formed on the silicon substrate 11 .
- a contact (not illustrated on the drawings) that extends as far as the drive circuit is formed within the inter-layer insulating film 12 .
- a plurality of grooves that extend parallel to the word line direction is formed in the top layer portion of the inter-layer insulating film 12 .
- the barrier metal layer 29 is formed on the inner faces of the grooves.
- the word lines WL are formed by embedding tungsten within the grooves.
- a plurality of word lines WL is formed, mutually parallel in the word line direction.
- the word line interconnect layer 14 is formed by the plurality of word lines WL.
- a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like is deposited on the word line interconnect layer 14 by, for example, the sputtering method to form the barrier metal layer 21 .
- amorphous silicon is deposited on the barrier metal layer 21 by, for example, the low pressure chemical vapor deposition (LP-CVD) method.
- LP-CVD low pressure chemical vapor deposition
- each of the impurities is introduced while depositing the amorphous silicon, to continuously form the n-type layer, the i-type layer, and the p-type layer to form the rectifying element layer 22 .
- a conductive material such as tungsten or titanium nitride or the like is deposited on the rectifying element layer 22 to form the lower electrode layer 23 .
- a dispersion liquid in which the CNTs 31 (see FIG. 2 ) are dispersed is applied on top of the lower electrode layer 23 , and dried.
- the nanomaterial assembly layer 24 is formed.
- the plurality of CNT 31 are loosely joined, with the gaps 32 formed between the CNT 31 .
- the direction of extension of the CNT 31 approaches the horizontal direction, in other words, the direction parallel to the plane formed by the word line direction and the bit line direction.
- a conductive material for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like, or a metal such as tantalum (Ta), tungsten (W), molybdenum (Mo) or the like is deposited on the nanomaterial assembly layer 24 to form the low coverage electrode layer 25 .
- the thickness of the low coverage electrode layer 25 is, for example, not less than 20 nm.
- Deposition of the conductive material to form the low coverage electrode layer 25 is carried out by a method with relatively low coverage, such as for example the PVD method by, for example, the sputtering method or the deposition method.
- the conductive material penetrates into the gaps 32 of the nanomaterial assembly layer 24 , but this penetration can be suppressed by depositing the conductive material by a method with a low coverage.
- the depth of penetration of the conductive material can be reduced to not more than 20 nm.
- the CNTs 31 are embedded within the bottom layer 25 b of the low coverage electrode layer 25 .
- the high coverage electrode layer 26 is formed on the low coverage electrode layer 25 by, for example, depositing the same type of conductive material from which the low coverage electrode layer 25 is formed.
- a material that is different from the conductive material from which the low coverage electrode layer 25 is formed may be deposited.
- a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like, or a metal such as tantalum (Ta), tungsten (W), molybdenum (Mo) or the like can be deposited.
- the thickness of the high coverage electrode layer 26 is, for example, not less than 5 nm.
- Deposition of the conductive material for forming the high coverage electrode layer 26 is carried out by a method having a relatively high coverage, for example, by a CVD method such as, for example, the thermal CVD method or the plasma CVD method.
- a CVD method such as, for example, the thermal CVD method or the plasma CVD method.
- the high coverage electrode layer 26 by a method with a high coverage, it is possible to prevent a chemical solution used in the subsequent process, and moisture contained in the layer formed in the process after that, and so on, from penetrating into the nanomaterial assembly layer 24 .
- the low coverage electrode layer 25 is provided between the high coverage electrode layer 26 and the nanomaterial assembly layer 24 , so the conductive material that forms the high coverage electrode layer 26 does not penetrate into the nanomaterial assembly layer 24 .
- the high coverage electrode layer 26 is formed by the CVD method, impurities such as halogen and the like contained in the source gas of the CVD method will remain within the high coverage electrode layer 26 .
- impurities such as halogen and the like contained in the source gas of the CVD method will remain within the high coverage electrode layer 26 .
- the high coverage electrode layer 26 is formed using tungsten (W), tungsten fluoride (WF 6 ) is used as the source gas in the CVD method, so fluorine (F) will remain in the high coverage electrode layer 26 .
- TiN titanium nitride
- TiCl 4 titanium chloride
- chlorine (Cl) will remain in the high coverage electrode layer 26 .
- a hard mask 41 made from, for example, silicon oxide is formed on the high coverage electrode layer 26 .
- a resist film 42 is formed on the hard mask 41 .
- the resist film 42 is patterned using the lithography method to form a resist pattern 42 a.
- the processes illustrated in FIG. 5A are carried out when the resist pattern 42 a is formed properly.
- a rework process is carried out. The rework process includes removing the resist pattern 42 a with the defect, and re-forming a new resist pattern 42 a.
- a defect occurs in the resist pattern 42 a formed in the process illustrated in FIG. 4B , a wet process using for example a chemical solution that includes sulfuric acid and hydrogen peroxide solution is carried out, and the resist pattern 42 a is removed. Then, a new resist film 42 is formed as illustrated in FIG. 4A . Next, as illustrated in FIG. 4B , the resist film 42 is patterned to form a new resist pattern 42 a. If a defect also occurs in the newly formed resist pattern 42 a, the process of removing the resist pattern 42 a, the process of forming the resist film 42 , and the process of forming the resist pattern 42 a as described above are carried out again.
- the hard mask 41 (see FIGS. 4A and 4B ) is patterned using the resist pattern 42 a (see FIG. 4B ) as a mask, as illustrated in FIG. 5A .
- etching such as reactive ion etching (RIE) or the like is carried out using the patterned hard mask 41 as the mask, and the high coverage electrode layer 26 , the low coverage electrode layer 25 , the nanomaterial assembly layer 24 , the lower electrode layer 23 , the rectifying element layer 22 , and the barrier metal layer 21 are selectively removed. In this way, the pillar 16 is formed.
- RIE reactive ion etching
- a hydrofluoric acid-based chemical solution for example diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF)
- DHF diluted hydrofluoric acid
- BHF buffered hydrofluoric acid
- wet cleaning is carried out and by-products (not illustrated on the drawings) adhering to the side surfaces of the pillars 16 are removed.
- silicon nitride for example, is deposited, and a side wall (not illustrated on the drawings) is formed on the side surface of the pillars 16 .
- an insulating material such as silicon oxide or silicon nitride or the like is deposited to fill in between the pillars 16 to form the inter-layer insulating film 17 .
- CMP chemical mechanical polishing
- bit lines BL is formed on the high coverage electrode layer 26 .
- the bit line interconnect layer 15 is formed by the plurality of bit lines BL extending in the bit line direction.
- the barrier metal layer 21 , the rectifying element layer 22 , the lower electrode layer 23 , the nanomaterial assembly layer 24 , the low coverage electrode layer 25 , and the high coverage electrode layer 26 are deposited in that sequence by a method similar to that described above, patterning is carried out and the pillars 16 are formed, cleaning is carried out, the side wall is formed, and filling in with the inter-layer insulating film 17 is carried out. In this way, the pillars 16 are formed on the bit lines BL.
- the deposition sequence of the n-type layer, the i-type layer, and the p-type layer on the rectifying element layer 22 is reversed with respect to the pillars 16 formed on the word line WL. Thereafter, the word line interconnect layer 14 , the plurality of pillars 16 , the bit line interconnect layer 15 , and the plurality of pillars 16 are repeatedly formed by the same method. In this way, the memory device 1 according to the embodiment is manufactured.
- the nanomaterial assembly layer 24 can have a “high resistance state” and a “low resistance state”.
- the mechanism has not been fully described, but for example, may be considered as follows.
- the CNT 31 When a voltage is not applied to the thickness direction of the nanomaterial assembly layer 24 , the CNT 31 are generally separated from each other, so the nanomaterial assembly layer 24 is in the high resistance state. On the other hand, when a voltage is applied to the thickness direction of the nanomaterial assembly layer 24 , Coulomb forces are generated between the CNT 31 , and they are drawn together. If this voltage is applied continuously for not less than a fixed period of time, the CNT 31 move and rotate, and adjacent CNT 31 contact, and a current path is formed between the lower electrode layer 23 and the low coverage electrode layer 25 via the plurality of CNT 31 . As a result, the nanomaterial assembly layer 24 is in the low resistance state. This state is maintained even if the application of the voltage on the nanomaterial assembly layer 24 is eliminated.
- the nanomaterial assembly layer 24 can have the two states, high resistance state and low resistance state, and as a result binary data can be stored. In order to achieve this operation, it is necessary that an appropriate gap 32 be formed between the CNT 31 .
- a resistance change layer is realized by the nanomaterial assembly layer 24 in which the carbon nanotubes (CNT) 31 are assembled, and as a result a ReRAM is realized.
- the metal oxides are fundamentally insulators, so there was the problem that operation was unstable.
- the resistance change layer is formed using CNT which are conductors, so it is possible to operate with a low voltage, and operation is stable. In this way, it is possible to realize a highly reliable memory device.
- the conductive material when forming the low coverage electrode layer 25 on the nanomaterial assembly layer 24 , the conductive material is deposited using a method such as the PVD method with a relatively low coverage. In this way, it is possible to suppress the conductive material from penetrating into the gaps 32 in the nanomaterial assembly layer 24 . As a result, it is possible to prevent the conductive material that has penetrated into the gaps 32 from penetrating into the thickness direction of the nanomaterial assembly layer 24 , and causing a short circuit.
- the conductive material when forming the high coverage electrode layer 26 on the low coverage electrode layer 25 , the conductive material is deposited using a method such as the CVD method with a relatively high coverage.
- the film density of the high coverage electrode layer 26 is high, and pin holes are few.
- the low coverage electrode layer 25 exists as a base material, so there is no penetration of the conductive material that forms the high coverage electrode layer 26 into the nanomaterial assembly layer 24 .
- the high coverage electrode layer 26 By forming the high coverage electrode layer 26 , it is possible to prevent moisture included in the hard mask 41 , moisture included in the resist film 42 , and chemical solution or the like used in rework processes from passing through pin holes in the hard mask 41 and pin holes in the low coverage electrode layer 25 and penetrating into the nanomaterial assembly layer 24 . In this way, there is no vaporization of moisture or chemical solution or the like that has penetrated into the nanomaterial assembly layer 24 within the nanomaterial assembly layer 24 due to the heat treatment associated with forming the film of the hard mask 41 or baking the resist film 42 , and so on, and reactions such as oxidation reactions or the like are not caused. As a result, the nanomaterial assembly layer 24 does not separate due to this vaporization or reaction.
- FIG. 6 is a schematic cross-sectional view illustrating a pillar of a memory device according to the embodiment.
- the configuration of the upper electrode layer of the pillar 16 is different compared with the memory device 1 (see FIGS. 1 and 2 ) according to the first embodiment as described above.
- an upper electrode layer 27 is provided instead of the low coverage electrode layer 25 and the high coverage electrode layer 26 (see FIG. 2 ) in the first embodiment as described above.
- the upper electrode layer 27 is formed from a metal nitride such as, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like, or a metal such as tantalum (Ta), tungsten (W), molybdenum (Mo), or the like.
- TiN titanium nitride
- TaN tantalum nitride
- WN tungsten nitride
- Mo molybdenum
- the nitrided portion of the upper electrode layer 27 is indicated as a nitrided portion 27 a.
- the nitrided portion 27 a mainly the crystal grain boundaries of the upper electrode layer 27 are nitrided.
- the nitrogen concentration within the upper electrode layer 27 is highest at the top surface of the upper electrode layer 27 , and decreases downwards, in other words, towards the nanomaterial assembly layer 24 .
- the boundary between the nitrided portion 27 a and the other portion in the upper electrode layer 27 is indicated by a broken line, but in reality there is no clear boundary, and the nitrogen concentration continuously changes.
- CNT 31 that constitute the nanomaterial assembly layer 24 are embedded in a lower layer 27 b of the upper electrode layer 27 .
- the upper electrode layer 27 is a layer that is formed by a method with low coverage, for example the PVD method.
- the configuration of the embodiment other than that described above is the same as the first embodiment as described previously.
- FIGS. 7A , 7 B, 8 A, 8 B, 9 A, and 9 B are process cross-sectional views illustrating the method for manufacturing the memory device according to the embodiment.
- FIGS. 7 through 9 the CNT 31 and the gaps 32 (see FIG. 6 ) are omitted from the drawings.
- the process of forming the word line interconnect layer 14 and the bit line interconnect layer 15 alternately on the inter-layer insulating film 12 is the same as for the first embodiment as described previously.
- the method of forming the pillars 16 the method of forming from the barrier metal layer 21 to the nanomaterial assembly layer 24 is the same as that for the first embodiment. The following is an explanation of the method for manufacturing the memory device according to the embodiment, concentrating on the portions that are different from the first embodiment as described previously.
- the barrier metal layer 21 , the rectifying element layer 22 , the lower electrode layer 23 , and the nanomaterial assembly layer 24 are, for example, formed on the word line interconnect layer 14 , by a method that is the same as that for the first embodiment as described previously.
- the upper electrode layer 27 is formed on the nanomaterial assembly layer 24 .
- the method of forming the upper electrode layer 27 is the same as the method of forming the low coverage electrode layer 25 in the first embodiment.
- a conductive material such as titanium nitride (TiN) or the like is deposited using a method with a relatively low coverage, for example a PVD method such as the sputtering method or the deposition method.
- a part of the conductive material penetrates into the gaps 32 of the nanomaterial assembly layer 24 , but because the deposition is done by a method with a low coverage, it is possible to suppress this penetration.
- the CNT 31 (see FIG. 2 ) is embedded within the lower layer 27 b of the upper electrode layer 27 .
- silicon nitride is deposited by a method with a relatively high coverage, for example by a CVD method such as the LPCVD method.
- a silicon nitride layer 46 is formed on the upper electrode layer 27 .
- the thickness of the silicon nitride layer 46 is, for example, not less than 5 nm.
- the nitrogen included in the source gas which is ammonia (NH 3 ) diffuses mainly into the upper electrode layer 27 via the crystal grain boundaries, forming the nitrided portion 27 a in the topmost layer of the nitrided portion 27 a.
- a hard mask 41 made from silicon oxide, for example, is formed on the silicon nitride layer 46 .
- the resist film 42 is formed on the hard mask 41 .
- the resist film 42 is patterned by the lithography method, to form the resist pattern 42 a. Then, if the resist pattern 42 a is properly formed, the process illustrated in FIG. 8B is performed. On the other hand, if a defect occurs in the resist pattern 42 a, for example, if the positional deviation of the resist pattern 42 a is outside the permitted range, a rework process is carried out. Specifically, after the resist pattern 42 a is removed by a wet process using a chemical solution, the resist film 42 illustrated in FIG. 7B is formed, and the resist pattern 42 a illustrated in FIG. 8A is formed again.
- the hard mask 41 is patterned using the resist pattern 42 a as a mask, and etching such as RIE or the like is carried out using the patterned hard mask 41 as the mask.
- etching such as RIE or the like is carried out using the patterned hard mask 41 as the mask.
- the silicon nitride layer 46 , the upper electrode layer 27 , the nanomaterial assembly layer 24 , the lower electrode layer 23 , the rectifying element layer 22 , and the barrier metal layer 21 are selectively removed to form the pillars 16 .
- the pillars 16 are cleaned, and the side walls (not illustrated on the drawings) are formed.
- an insulating material such as silicon oxide or silicon nitride or the like is deposited thereby embedding the pillars 16 , and thus forming the inter-layer insulating film 17 .
- a flattening process such as CMP or the like is carried out using the upper electrode layer 27 as a stopper, to flatten the top surface of the inter-layer insulating film 17 .
- the top of the inter-layer insulating film 17 is removed together with the hard mask 41 and the silicon nitride layer 46 (see FIGS. 8A and 8B ), and the upper electrode layer 27 is exposed.
- the manufacturing method according to the embodiment apart from the above is the same as the first embodiment as described previously.
- conductive material is deposited by a method with a relatively low coverage, such as PVD or the like. In this way it is possible to suppress penetration of the conductive material into the gaps 32 of the nanomaterial assembly layer 24 .
- silicon nitride layer 46 is deposited by a method with a relatively high coverage, such as the CVD method or the like. In this way, the film density of the silicon nitride layer 46 increases, and the number of pin holes decreases.
- the upper electrode layer 27 exists as a base material, so the silicon nitride does not penetrate into the nanomaterial assembly layer 24 .
- the silicon nitride layer 46 By forming the silicon nitride layer 46 , moisture included in the hard mask 41 , moisture included in the resist film 42 , and chemical solution used in rework processes can be prevented from passing through pin holes in the hard mask 41 and pin holes in the upper electrode layer 27 and penetrating into the nanomaterial assembly layer 24 .
- the silicon nitride layer 46 is removed by the CMP process illustrated in FIG. 9A , so there is nothing to impede the electrical conductivity of the pillars 16 in the memory device 2 after manufacturing.
- the operation and effect of the embodiment other than that described above is the same as the first embodiment as described previously.
- CNTs carbon nanotubes
- the invention is not limited to this.
- Carbon nanomaterial having a nanoscale crystalline structure such as fullerene, graphene, carbon nanoribbon, or the like may be used as the micro structural bodies that constitute the nanomaterial assembly layer 24 , or nanoscale structural bodies made from a conductive material other than carbon may be used.
- the nanomaterial assembly layer 24 was formed by the spincoat method were described, but the invention is not limited to this, and they can be formed by, for example, the CVD method.
- the rectifying element layer be a layer that is capable of selecting whether or not current flows in a pillar 16 , for example, it may be a Schottky diode made from a silicon layer and a metal layer, or a silicon transistor layer of npn-type or pnp-type.
Abstract
According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.
Description
- This application is a division of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 13/052,426 filed Mar. 21, 2011, and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application No. 2010-246525 filed Nov. 2, 2010; the entire contents of each of which are incorporated herein by reference.
- Embodiments described herein relate generally to a memory device and a method for manufacturing the same.
- In recent years a phenomenon has been discovered in which certain metal oxide-based materials can have a low resistance state and a high resistance state when a voltage is applied, depending on the resistivity prior to application of the voltage and the magnitude of the applied voltage. Interest has been focused on new nonvolatile memory devices that use this phenomenon. This nonvolatile memory device is referred to as a Resistance Random Access Memory (ReRAM). A 3-dimensional cross-point structure has been proposed for the structure of an actual ReRAM device, in which memory cells are disposed at the intersection points of word lines (WL) and bit lines (BL), from the point of view of large scale integration. Also, for commercialization of ReRAM, high reliability is required.
-
FIG. 1 is a perspective view illustrating a memory device according to a first embodiment; -
FIG. 2 is a schematic cross-sectional view illustrating a pillar of the first embodiment; -
FIGS. 3A to 5B are process cross-sectional views illustrating a method for manufacturing a memory device according to the first embodiment; -
FIG. 6 is a schematic cross-sectional view illustrating a pillar of a second embodiment; and -
FIGS. 7A to 9B are process cross-sectional views illustrating a method for manufacturing a memory device according to the second embodiment. - In general, according to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.
- In general, according to one other embodiment, a method is disclosed for manufacturing a memory device. The method can include forming a nanomaterial assembly layer formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The method can include forming a first electrode layer on the nanomaterial assembly layer by depositing a conductive material by a first method in which a coverage is relatively low. In addition, the method can include forming a second electrode layer on the first electrode layer by depositing a conductive material by a second method in which the coverage is relatively high.
- Various embodiments will be described hereinafter with reference to the accompanying drawings.
- First, a first embodiment will be described.
-
FIG. 1 is a perspective view illustrating a memory device according to the embodiment. -
FIG. 2 is a schematic cross-sectional view illustrating a pillar of the embodiment. - The memory device according to the embodiment is a ReRAM.
- As illustrated in
FIG. 1 , in amemory device 1 according to the embodiment, asilicon substrate 11 is provided, and the drive circuit (not illustrated on the drawing) of thememory device 1 is formed on the top layer portion and top surface of thesilicon substrate 11. An inter-layerinsulating film 12 made from silicon oxide, for example, is provided on thesilicon substrate 11 encapsulating the drive circuit, and amemory cell unit 13 is provided on the inter-layerinsulating film 12. - In the
memory cell unit 13, wordline interconnect layers 14 that include a plurality of word lines WL extending in a direction parallel to the top surface of the silicon substrate 11 (hereafter referred to as the “word line direction”) and bitline interconnect layers 15 that include a plurality of bit lines BL extending in a direction parallel to the top surface of thesilicon substrate 11 and that intersect the word line direction at, for example, right angles (hereafter referred to as the “bit line direction”) are stacked alternately, with insulating layers disposed therebetween. Also, there is no contact between word lines WL, between bit lines BL, or between word lines WL and bit lines BL. - Also,
pillars 16 extending in the direction normal to the top surface of the silicon substrate 11 (hereafter referred to as the “vertical direction”) are provided at the points of closest proximity between each word line WL and each bit line BL. Thepillars 16 are formed between word lines WL and bit lines BL. A single memory cell is constituted from asingle pillar 16. In other words, anonvolatile memory device 1 is a cross-point type device in which memory cells are disposed at each of the nearest neighbor of the word lines WL and the bit lines BL. An inter-layer insulating film 17 (seeFIGS. 5A and 5B ) is embedded between the word lines WL, the bit lines BL, and thepillars 16. - Hereinafter, a configuration of the
pillar 16 will be described with reference toFIG. 2 . - As illustrated in
FIG. 2 , in eachpillar 16, abarrier metal layer 21, a rectifyingelement layer 22 that has a rectifying action, alower electrode layer 23, ananomaterial assembly layer 24, a lowcoverage electrode layer 25, and a highcoverage electrode layer 26 are stacked subsequently from the bottom up. The lowcoverage electrode layer 25 and the highcoverage electrode layer 26 form an upper electrode layer for thenanomaterial assembly layer 24. Thebarrier metal layer 21 is in contact with, for example, the word line WL (seeFIG. 1 ), and the highcoverage electrode layer 26 is in contact with, for example, the bit line BL (seeFIG. 1 ). Also, a barrier metal layer 29 (seeFIGS. 5A and 5B ) is provided between the lowermost word line WL and the inter-layerinsulating film 12. - The
barrier metal layer 29 is a layer for preventing diffusion between the inter-layer insulatingfilm 12 and the word line WL, as well as improving adhesion, and thebarrier metal layer 21 is a layer for preventing diffusion between the word line WL and the rectifyingelement layer 22, as well as improving adhesion. Thebarrier metal layers - The rectifying
element layer 22 is made from, for example, a polysilicon diode layer, with a n-type layer of an n+ conductivity type, an i-type layer made from an intrinsic semiconductor, and a p-type layers of a p+ conductivity type stacked subsequently from the bottom layer side up. In this way, the rectifyingelement layer 22 functions as a selective element layer in which current only flows when, for example, a potential is supplied to the bit line that is higher than that supplied to the word line WL, and current does not flow in the opposite direction. Thelower electrode layer 23 is formed from a conductive material such as tungsten or titanium nitride or the like. - The
nanomaterial assembly layer 24 is, for example, an assembly of carbon nanotubes (CNT) 31 as micro conductors, withgaps 32 disposed therebetween. Thegaps 32 form an air layer, so the structure of thenanomaterial assembly layer 24 is a hollow structure. The number of layers ofCNT 31 stacked in the thickness direction of thenanomaterial assembly layer 24 is, for example, several layers to several tens of layers. - Also, the low
coverage electrode layer 25 and the highcoverage electrode layer 26 are formed from metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like, or metals such as tantalum (Ta), tungsten (W), molybdenum (Mo), or the like. The lowcoverage electrode layer 25 and the highcoverage electrode layer 26 may be formed from the same type of material, or they may be formed from mutually different types of materials. The thickness of the lowcoverage electrode layer 25 is, for example, not less than 20 nm, and the thickness of the highcoverage electrode layer 26 is, for example, not less than 5 nm. Also, parts of theCNT 31 that constitute thenanomaterial assembly layer 24 are embedded in alower layer 25 b of the lowcoverage electrode layer 25. - However, the film properties of the low
coverage electrode layer 25 and the highcoverage electrode layer 26 differ, the coverage of the highcoverage electrode layer 26 is higher than the coverage of the lowcoverage electrode layer 25. Also, when the lowcoverage electrode layer 25 and the highcoverage electrode layer 26 are formed from the same type of material, the density of the highcoverage electrode layer 26 is higher than the density of the lowcoverage electrode layer 25. In addition, the crystalline structure of both the lowcoverage electrode layer 25 and the highcoverage electrode layer 26 is a polycrystalline structure, but the average crystal grain size of the highcoverage electrode layer 26 is larger than the average crystal grain size of the lowcoverage electrode layer 25. Alternatively, the crystalline structure of the lowcoverage electrode layer 25 may be polycrystalline, and the crystalline structure of the highcoverage electrode layer 26 may be an amorphous structure. The differences in these crystalline structures may be confirmed by observing a cross-section of thepillar 16 that includes the vertical direction using a transmission electron microscope (TEM), for example. - As described later, the low
coverage electrode layer 25 is formed by a physical vapor deposition (PVD) method, and the highcoverage electrode layer 26 is formed by a chemical vapor deposition (CVD) method. Therefore the highcoverage electrode layer 26 includes halogen impurities, but the lowcoverage electrode layer 25 includes substantially no impurities. In other words, the halogen concentration of the highcoverage electrode layer 26 is higher than the halogen concentration of the lowcoverage electrode layer 25. - Next, a method for manufacturing the memory device according to the embodiment will be described.
-
FIGS. 3A , 3B, 4A, 4B, 5A, and 5B are process cross-sectional views illustrating the method for manufacturing the memory device according to the embodiment. - In
FIGS. 3 through 5 , theCNT 31 and thegaps 32 are omitted. - First, as illustrated on
FIG. 1 , the drive circuit for driving thememory cell unit 13 is formed on the surface of thesilicon substrate 11. Next, the inter-layer insulatingfilm 12 is formed on thesilicon substrate 11. Next, a contact (not illustrated on the drawings) that extends as far as the drive circuit is formed within theinter-layer insulating film 12. - Next, as illustrated in
FIG. 3A , a plurality of grooves that extend parallel to the word line direction is formed in the top layer portion of the inter-layer insulatingfilm 12. Next, thebarrier metal layer 29 is formed on the inner faces of the grooves. Next, the word lines WL are formed by embedding tungsten within the grooves. A plurality of word lines WL is formed, mutually parallel in the word line direction. The wordline interconnect layer 14 is formed by the plurality of word lines WL. - Next, as illustrated in
FIG. 3B , a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like is deposited on the wordline interconnect layer 14 by, for example, the sputtering method to form thebarrier metal layer 21. Next, amorphous silicon is deposited on thebarrier metal layer 21 by, for example, the low pressure chemical vapor deposition (LP-CVD) method. At this time, each of the impurities is introduced while depositing the amorphous silicon, to continuously form the n-type layer, the i-type layer, and the p-type layer to form therectifying element layer 22. Next, a conductive material such as tungsten or titanium nitride or the like is deposited on therectifying element layer 22 to form thelower electrode layer 23. - Next, a dispersion liquid in which the CNTs 31 (see
FIG. 2 ) are dispersed is applied on top of thelower electrode layer 23, and dried. In this way thenanomaterial assembly layer 24 is formed. As illustrated inFIG. 2 , in thenanomaterial assembly layer 24, the plurality ofCNT 31 are loosely joined, with thegaps 32 formed between theCNT 31. Also, in the process of reducing the thickness by drying the dispersion liquid, the direction of extension of theCNT 31 approaches the horizontal direction, in other words, the direction parallel to the plane formed by the word line direction and the bit line direction. - Next, a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like, or a metal such as tantalum (Ta), tungsten (W), molybdenum (Mo) or the like is deposited on the
nanomaterial assembly layer 24 to form the lowcoverage electrode layer 25. The thickness of the lowcoverage electrode layer 25 is, for example, not less than 20 nm. Deposition of the conductive material to form the lowcoverage electrode layer 25 is carried out by a method with relatively low coverage, such as for example the PVD method by, for example, the sputtering method or the deposition method. At this time, a part of the conductive material penetrates into thegaps 32 of thenanomaterial assembly layer 24, but this penetration can be suppressed by depositing the conductive material by a method with a low coverage. For example, the depth of penetration of the conductive material can be reduced to not more than 20 nm. As a result of the penetration of the conductive material into thegaps 32, the CNTs 31 (seeFIG. 2 ) are embedded within thebottom layer 25 b of the lowcoverage electrode layer 25. - Next, as illustrated in
FIG. 4A , the highcoverage electrode layer 26 is formed on the lowcoverage electrode layer 25 by, for example, depositing the same type of conductive material from which the lowcoverage electrode layer 25 is formed. A material that is different from the conductive material from which the lowcoverage electrode layer 25 is formed may be deposited. In either case, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or the like, or a metal such as tantalum (Ta), tungsten (W), molybdenum (Mo) or the like can be deposited. The thickness of the highcoverage electrode layer 26 is, for example, not less than 5 nm. - Deposition of the conductive material for forming the high
coverage electrode layer 26 is carried out by a method having a relatively high coverage, for example, by a CVD method such as, for example, the thermal CVD method or the plasma CVD method. By forming the highcoverage electrode layer 26 by a method with a high coverage, it is possible to prevent a chemical solution used in the subsequent process, and moisture contained in the layer formed in the process after that, and so on, from penetrating into thenanomaterial assembly layer 24. Also, the lowcoverage electrode layer 25 is provided between the highcoverage electrode layer 26 and thenanomaterial assembly layer 24, so the conductive material that forms the highcoverage electrode layer 26 does not penetrate into thenanomaterial assembly layer 24. - If the high
coverage electrode layer 26 is formed by the CVD method, impurities such as halogen and the like contained in the source gas of the CVD method will remain within the highcoverage electrode layer 26. For example, if the highcoverage electrode layer 26 is formed using tungsten (W), tungsten fluoride (WF6) is used as the source gas in the CVD method, so fluorine (F) will remain in the highcoverage electrode layer 26. Also, if the highcoverage electrode layer 26 is formed using titanium nitride (TiN), titanium chloride (TiCl4) is used as the source gas for the CVD method, so chlorine (Cl) will remain in the highcoverage electrode layer 26. - Next, a
hard mask 41 made from, for example, silicon oxide is formed on the highcoverage electrode layer 26. Next, a resistfilm 42 is formed on thehard mask 41. Next, as illustrated inFIG. 4B , the resistfilm 42 is patterned using the lithography method to form a resistpattern 42 a. Then, the processes illustrated inFIG. 5A are carried out when the resistpattern 42 a is formed properly. On the other hand, if a defect occurs in the resistpattern 42 a, for example, if the shift of the resistpattern 42 a exceeds the allowable range, a rework process is carried out. The rework process includes removing the resistpattern 42 a with the defect, and re-forming a new resistpattern 42 a. - In other words, if a defect occurs in the resist
pattern 42 a formed in the process illustrated inFIG. 4B , a wet process using for example a chemical solution that includes sulfuric acid and hydrogen peroxide solution is carried out, and the resistpattern 42 a is removed. Then, a new resistfilm 42 is formed as illustrated inFIG. 4A . Next, as illustrated inFIG. 4B , the resistfilm 42 is patterned to form a new resistpattern 42 a. If a defect also occurs in the newly formed resistpattern 42 a, the process of removing the resistpattern 42 a, the process of forming the resistfilm 42, and the process of forming the resistpattern 42 a as described above are carried out again. - Then, when a resist
pattern 42 a with no defect has been formed, the hard mask 41 (seeFIGS. 4A and 4B ) is patterned using the resistpattern 42 a (seeFIG. 4B ) as a mask, as illustrated inFIG. 5A . Next, etching such as reactive ion etching (RIE) or the like is carried out using the patternedhard mask 41 as the mask, and the highcoverage electrode layer 26, the lowcoverage electrode layer 25, thenanomaterial assembly layer 24, thelower electrode layer 23, the rectifyingelement layer 22, and thebarrier metal layer 21 are selectively removed. In this way, thepillar 16 is formed. - Next, using for example a hydrofluoric acid-based chemical solution, for example diluted hydrofluoric acid (DHF) or buffered hydrofluoric acid (BHF), wet cleaning is carried out and by-products (not illustrated on the drawings) adhering to the side surfaces of the
pillars 16 are removed. Next, silicon nitride, for example, is deposited, and a side wall (not illustrated on the drawings) is formed on the side surface of thepillars 16. Next, an insulating material such as silicon oxide or silicon nitride or the like is deposited to fill in between thepillars 16 to form theinter-layer insulating film 17. - Next, chemical mechanical polishing (CMP) is carried out using the high
coverage electrode layer 26 as a stopper, and the top surface of the inter-layer insulatingfilm 17 is flattened. At this time, the highcoverage electrode layer 26 remains with a thickness of not less than 5 nm. - Next, as illustrated in
FIG. 5B , a plurality of bit lines BL is formed on the highcoverage electrode layer 26. The bitline interconnect layer 15 is formed by the plurality of bit lines BL extending in the bit line direction. Next, thebarrier metal layer 21, the rectifyingelement layer 22, thelower electrode layer 23, thenanomaterial assembly layer 24, the lowcoverage electrode layer 25, and the highcoverage electrode layer 26 are deposited in that sequence by a method similar to that described above, patterning is carried out and thepillars 16 are formed, cleaning is carried out, the side wall is formed, and filling in with the inter-layer insulatingfilm 17 is carried out. In this way, thepillars 16 are formed on the bit lines BL. When forming thepillars 16, the deposition sequence of the n-type layer, the i-type layer, and the p-type layer on therectifying element layer 22 is reversed with respect to thepillars 16 formed on the word line WL. Thereafter, the wordline interconnect layer 14, the plurality ofpillars 16, the bitline interconnect layer 15, and the plurality ofpillars 16 are repeatedly formed by the same method. In this way, thememory device 1 according to the embodiment is manufactured. - Next, the operation of the embodiment will be described.
- In the
memory device 1 according to the embodiment, thenanomaterial assembly layer 24 can have a “high resistance state” and a “low resistance state”. The mechanism has not been fully described, but for example, may be considered as follows. - When a voltage is not applied to the thickness direction of the
nanomaterial assembly layer 24, theCNT 31 are generally separated from each other, so thenanomaterial assembly layer 24 is in the high resistance state. On the other hand, when a voltage is applied to the thickness direction of thenanomaterial assembly layer 24, Coulomb forces are generated between theCNT 31, and they are drawn together. If this voltage is applied continuously for not less than a fixed period of time, theCNT 31 move and rotate, andadjacent CNT 31 contact, and a current path is formed between thelower electrode layer 23 and the lowcoverage electrode layer 25 via the plurality ofCNT 31. As a result, thenanomaterial assembly layer 24 is in the low resistance state. This state is maintained even if the application of the voltage on thenanomaterial assembly layer 24 is eliminated. Also, if a short pulse voltage in the order of, for example, several nanoseconds is applied in the thickness direction of thenanomaterial assembly layer 24, heat is generated at the contacting portions of theCNT 31, and theCNT 31 separate from each other. As a result, thenanomaterial assembly layer 24 returns to the high resistance state. In this way thenanomaterial assembly layer 24 can have the two states, high resistance state and low resistance state, and as a result binary data can be stored. In order to achieve this operation, it is necessary that anappropriate gap 32 be formed between theCNT 31. - Next, the effect of the embodiment will be described.
- According to the embodiment, a resistance change layer is realized by the
nanomaterial assembly layer 24 in which the carbon nanotubes (CNT) 31 are assembled, and as a result a ReRAM is realized. In a conventional resistance change layer using metal oxides, the metal oxides are fundamentally insulators, so there was the problem that operation was unstable. In contrast, according to the embodiment, the resistance change layer is formed using CNT which are conductors, so it is possible to operate with a low voltage, and operation is stable. In this way, it is possible to realize a highly reliable memory device. - Also, in the embodiment, when forming the low
coverage electrode layer 25 on thenanomaterial assembly layer 24, the conductive material is deposited using a method such as the PVD method with a relatively low coverage. In this way, it is possible to suppress the conductive material from penetrating into thegaps 32 in thenanomaterial assembly layer 24. As a result, it is possible to prevent the conductive material that has penetrated into thegaps 32 from penetrating into the thickness direction of thenanomaterial assembly layer 24, and causing a short circuit. On the other hand, when forming the highcoverage electrode layer 26 on the lowcoverage electrode layer 25, the conductive material is deposited using a method such as the CVD method with a relatively high coverage. In this way the film density of the highcoverage electrode layer 26 is high, and pin holes are few. When forming the highcoverage electrode layer 26, the lowcoverage electrode layer 25 exists as a base material, so there is no penetration of the conductive material that forms the highcoverage electrode layer 26 into thenanomaterial assembly layer 24. - By forming the high
coverage electrode layer 26, it is possible to prevent moisture included in thehard mask 41, moisture included in the resistfilm 42, and chemical solution or the like used in rework processes from passing through pin holes in thehard mask 41 and pin holes in the lowcoverage electrode layer 25 and penetrating into thenanomaterial assembly layer 24. In this way, there is no vaporization of moisture or chemical solution or the like that has penetrated into thenanomaterial assembly layer 24 within thenanomaterial assembly layer 24 due to the heat treatment associated with forming the film of thehard mask 41 or baking the resistfilm 42, and so on, and reactions such as oxidation reactions or the like are not caused. As a result, thenanomaterial assembly layer 24 does not separate due to this vaporization or reaction. Also, there is no variation in the electrical characteristics of the memory cells as a result of non-uniform distribution of the moisture or chemical solution or the like that has penetrated into thenanomaterial assembly layer 24. In this way, it is possible to manufacture a highlyreliable memory device 1. - Next, a second embodiment will be described.
-
FIG. 6 is a schematic cross-sectional view illustrating a pillar of a memory device according to the embodiment. - As illustrated in
FIG. 6 , in amemory device 2 according to the embodiment, the configuration of the upper electrode layer of thepillar 16 is different compared with the memory device 1 (seeFIGS. 1 and 2 ) according to the first embodiment as described above. - In other words, in the embodiment, an
upper electrode layer 27 is provided instead of the lowcoverage electrode layer 25 and the high coverage electrode layer 26 (seeFIG. 2 ) in the first embodiment as described above. Theupper electrode layer 27 is formed from a metal nitride such as, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like, or a metal such as tantalum (Ta), tungsten (W), molybdenum (Mo), or the like. However, the topmost layer portion of theupper electrode layer 27 is nitrided. InFIG. 6 , the nitrided portion of theupper electrode layer 27 is indicated as anitrided portion 27 a. In thenitrided portion 27 a, mainly the crystal grain boundaries of theupper electrode layer 27 are nitrided. The nitrogen concentration within theupper electrode layer 27 is highest at the top surface of theupper electrode layer 27, and decreases downwards, in other words, towards thenanomaterial assembly layer 24. For convenience of illustration, inFIG. 6 , the boundary between thenitrided portion 27 a and the other portion in theupper electrode layer 27 is indicated by a broken line, but in reality there is no clear boundary, and the nitrogen concentration continuously changes. Also,CNT 31 that constitute thenanomaterial assembly layer 24 are embedded in alower layer 27 b of theupper electrode layer 27. As described later, theupper electrode layer 27 is a layer that is formed by a method with low coverage, for example the PVD method. The configuration of the embodiment other than that described above is the same as the first embodiment as described previously. - Next, a manufacturing method of the memory device according to the embodiment will be described.
-
FIGS. 7A , 7B, 8A, 8B, 9A, and 9B are process cross-sectional views illustrating the method for manufacturing the memory device according to the embodiment. - In
FIGS. 7 through 9 , theCNT 31 and the gaps 32 (seeFIG. 6 ) are omitted from the drawings. - In the method for manufacturing the memory device according to the embodiment, the process of forming the word
line interconnect layer 14 and the bitline interconnect layer 15 alternately on theinter-layer insulating film 12 is the same as for the first embodiment as described previously. Also, in the method of forming thepillars 16, the method of forming from thebarrier metal layer 21 to thenanomaterial assembly layer 24 is the same as that for the first embodiment. The following is an explanation of the method for manufacturing the memory device according to the embodiment, concentrating on the portions that are different from the first embodiment as described previously. - As illustrated in
FIG. 7A , thebarrier metal layer 21, the rectifyingelement layer 22, thelower electrode layer 23, and thenanomaterial assembly layer 24 are, for example, formed on the wordline interconnect layer 14, by a method that is the same as that for the first embodiment as described previously. - Next, the
upper electrode layer 27 is formed on thenanomaterial assembly layer 24. The method of forming theupper electrode layer 27 is the same as the method of forming the lowcoverage electrode layer 25 in the first embodiment. In other words, a conductive material such as titanium nitride (TiN) or the like is deposited using a method with a relatively low coverage, for example a PVD method such as the sputtering method or the deposition method. At this time, a part of the conductive material penetrates into thegaps 32 of thenanomaterial assembly layer 24, but because the deposition is done by a method with a low coverage, it is possible to suppress this penetration. The portion of the conductive material that penetrates into thegaps 32 of thenanomaterial assembly layer 24 becomes thelower layer 27 b of theupper electrode layer 27. Conversely, the CNT 31 (seeFIG. 2 ) is embedded within thelower layer 27 b of theupper electrode layer 27. - Next, as illustrated in
FIG. 7B , silicon nitride is deposited by a method with a relatively high coverage, for example by a CVD method such as the LPCVD method. In this way, asilicon nitride layer 46 is formed on theupper electrode layer 27. The thickness of thesilicon nitride layer 46 is, for example, not less than 5 nm. At this time, the nitrogen included in the source gas, which is ammonia (NH3) diffuses mainly into theupper electrode layer 27 via the crystal grain boundaries, forming thenitrided portion 27 a in the topmost layer of thenitrided portion 27 a. Next, ahard mask 41 made from silicon oxide, for example, is formed on thesilicon nitride layer 46. Next, the resistfilm 42 is formed on thehard mask 41. - Next, as illustrated in
FIG. 8A , the resistfilm 42 is patterned by the lithography method, to form the resistpattern 42 a. Then, if the resistpattern 42 a is properly formed, the process illustrated inFIG. 8B is performed. On the other hand, if a defect occurs in the resistpattern 42 a, for example, if the positional deviation of the resistpattern 42 a is outside the permitted range, a rework process is carried out. Specifically, after the resistpattern 42 a is removed by a wet process using a chemical solution, the resistfilm 42 illustrated inFIG. 7B is formed, and the resistpattern 42 a illustrated inFIG. 8A is formed again. - Then, if a proper resist
pattern 42 a is formed, as illustrated inFIG. 8B , thehard mask 41 is patterned using the resistpattern 42 a as a mask, and etching such as RIE or the like is carried out using the patternedhard mask 41 as the mask. In this way, thesilicon nitride layer 46, theupper electrode layer 27, thenanomaterial assembly layer 24, thelower electrode layer 23, the rectifyingelement layer 22, and thebarrier metal layer 21 are selectively removed to form thepillars 16. Next, thepillars 16 are cleaned, and the side walls (not illustrated on the drawings) are formed. - Next, as illustrated in
FIG. 9A , an insulating material such as silicon oxide or silicon nitride or the like is deposited thereby embedding thepillars 16, and thus forming the inter-layer insulatingfilm 17. Next, a flattening process such as CMP or the like is carried out using theupper electrode layer 27 as a stopper, to flatten the top surface of the inter-layer insulatingfilm 17. In this way, the top of the inter-layer insulatingfilm 17 is removed together with thehard mask 41 and the silicon nitride layer 46 (seeFIGS. 8A and 8B ), and theupper electrode layer 27 is exposed. At this time all thesilicon nitride layer 46 is removed, but thenitrided portion 27 a of theupper electrode layer 27 remains. Next, as illustrated inFIG. 9B , the plurality of bit lines BL is formed on thepillars 16 to form the bitline interconnect layer 15. The manufacturing method according to the embodiment apart from the above is the same as the first embodiment as described previously. - Next, the effect of the embodiment will be described.
- In the embodiment, when forming the
upper electrode layer 27 on thenanomaterial assembly layer 24, conductive material is deposited by a method with a relatively low coverage, such as PVD or the like. In this way it is possible to suppress penetration of the conductive material into thegaps 32 of thenanomaterial assembly layer 24. On the other hand, when forming thesilicon nitride layer 46 on theupper electrode layer 27, silicon nitride is deposited by a method with a relatively high coverage, such as the CVD method or the like. In this way, the film density of thesilicon nitride layer 46 increases, and the number of pin holes decreases. When forming thesilicon nitride layer 46, theupper electrode layer 27 exists as a base material, so the silicon nitride does not penetrate into thenanomaterial assembly layer 24. - By forming the
silicon nitride layer 46, moisture included in thehard mask 41, moisture included in the resistfilm 42, and chemical solution used in rework processes can be prevented from passing through pin holes in thehard mask 41 and pin holes in theupper electrode layer 27 and penetrating into thenanomaterial assembly layer 24. Thesilicon nitride layer 46 is removed by the CMP process illustrated inFIG. 9A , so there is nothing to impede the electrical conductivity of thepillars 16 in thememory device 2 after manufacturing. The operation and effect of the embodiment other than that described above is the same as the first embodiment as described previously. - In the first and second embodiments as described above, examples were given in which carbon nanotubes (CNTs) were used as the micro conductors, but the invention is not limited to this. Carbon nanomaterial having a nanoscale crystalline structure such as fullerene, graphene, carbon nanoribbon, or the like may be used as the micro structural bodies that constitute the
nanomaterial assembly layer 24, or nanoscale structural bodies made from a conductive material other than carbon may be used. Also, in the first and second embodiments as described above, examples in which thenanomaterial assembly layer 24 was formed by the spincoat method were described, but the invention is not limited to this, and they can be formed by, for example, the CVD method. - Also, in the first and second embodiments as described above, examples in which a polysilicon diode layer is provided as the rectifying element layer are described, but the invention is not limited to this. It is sufficient that the rectifying element layer be a layer that is capable of selecting whether or not current flows in a
pillar 16, for example, it may be a Schottky diode made from a silicon layer and a metal layer, or a silicon transistor layer of npn-type or pnp-type. - According to the embodiment as described above, it is possible to realize a highly reliable memory device and manufacturing method for same.
- While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
Claims (7)
1. A method for manufacturing a memory device, comprising:
forming a nanomaterial assembly layer formed of an assembly of a plurality of micro conductors via gaps between the micro conductors;
forming a first electrode layer on the nanomaterial assembly layer by depositing a conductive material by a first method in which a coverage is relatively low; and
forming a second electrode layer on the first electrode layer by depositing a conductive material by a second method in which the coverage is relatively high.
2. The method according to claim 1 , further comprising:
forming a hard mask layer on the second electrode layer;
forming a resist film on the hard mask layer;
forming a resist pattern by selectively removing the resist film;
patterning the hard mask layer by etching using the resist pattern as a mask; and
forming pillars by selectively removing the second electrode layer, the first electrode layer, and the nanomaterial assembly layer by etching using the patterned hard mask as the mask,
when a defect occurs in the resist pattern, the resist pattern being removed using a chemical solution, and the forming the resist film and the forming the resist pattern being carried out again.
3. The method according to claim 1 , wherein the first method is a physical vapor deposition method, and the second method is a chemical vapor deposition method.
4. The method according to claim 1 , wherein the micro conductors are carbon nanotubes.
5. A method for manufacturing a memory device, comprising:
forming a nanomaterial assembly layer formed of an assembly of a plurality of micro conductors via gaps between the micro conductors;
forming an electrode layer on the nanomaterial assembly layer by depositing a conductive material by a first method in which a coverage is relatively low;
forming a silicon nitride layer on the electrode layer by depositing silicon nitride by a second method in which the coverage is relatively high;
forming a hard mask layer on the silicon nitride layer;
forming a resist film on the hard mask layer;
forming a resist pattern by selectively removing the resist film;
patterning the hard mask layer by etching using the resist pattern as a mask;
forming pillars by selectively removing the silicon nitride layer, the electrode layer, and the nanomaterial assembly layer by etching using the patterned hard mask as the mask;
forming an inter-layer insulating film around the pillars;
flattening a top surface of the inter-layer insulating film by performing a flattening process using the electrode layer as a stopper; and
removing the hard mask and the silicon nitride film,
when a defect occurs in the resist pattern, the resist pattern being removed using a chemical solution, and the forming the resist film and the forming the resist pattern being carried out again.
6. The method according to claim 5 , wherein the first method is a physical vapor deposition method, and the second method is a chemical vapor deposition method.
7. The method according to claim 5 , wherein the micro conductors are carbon nanotubes.
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JP2012059862A (en) * | 2010-09-08 | 2012-03-22 | Toshiba Corp | Non-volatile memory device and method of manufacturing the same |
WO2015126139A1 (en) * | 2014-02-19 | 2015-08-27 | Samsung Electronics Co., Ltd. | Wiring structure and electronic device employing the same |
US9634245B2 (en) * | 2015-01-09 | 2017-04-25 | Micron Technology, Inc. | Structures incorporating and methods of forming metal lines including carbon |
US10269825B2 (en) * | 2016-03-14 | 2019-04-23 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing same |
US11201280B2 (en) * | 2019-08-23 | 2021-12-14 | Western Digital Technologies, Inc. | Bottom leads chemical mechanical planarization for TMR magnetic sensors |
TWI734516B (en) * | 2020-06-10 | 2021-07-21 | 華邦電子股份有限公司 | Resistive random access memory and method of manufacturing the same |
US11495637B2 (en) | 2020-07-01 | 2022-11-08 | Winbond Electronics Corp. | Resistive random access memory and method of manufacturing the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7544546B2 (en) * | 2006-05-15 | 2009-06-09 | International Business Machines Corporation | Formation of carbon and semiconductor nanomaterials using molecular assemblies |
US20100264392A1 (en) * | 2007-11-15 | 2010-10-21 | Yoshio Kawashima | Nonvolatile memory apparatus and manufacturing method thereof |
US20100276656A1 (en) * | 2008-09-22 | 2010-11-04 | Nishant Sinha | Devices Comprising Carbon Nanotubes, And Methods Of Forming Devices Comprising Carbon Nanotubes |
US8264866B2 (en) * | 2009-09-24 | 2012-09-11 | Kabushiki Kaisha Toshiba | Nonvolatile memory device and method for manufacturing same |
Family Cites Families (7)
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US7733685B2 (en) * | 2008-07-09 | 2010-06-08 | Sandisk 3D Llc | Cross point memory cell with distributed diodes and method of making same |
WO2010079827A1 (en) * | 2009-01-09 | 2010-07-15 | 日本電気株式会社 | Semiconductor device and manufacturing method therefor |
JP2010165950A (en) * | 2009-01-16 | 2010-07-29 | Toshiba Corp | Nonvolatile semiconductor memory and method of manufacturing the same |
JP5364407B2 (en) * | 2009-03-24 | 2013-12-11 | 株式会社東芝 | Nonvolatile memory device and manufacturing method thereof |
JP2011014640A (en) * | 2009-06-30 | 2011-01-20 | Toshiba Corp | Nonvolatile semiconductor memory device |
KR20110008553A (en) * | 2009-07-20 | 2011-01-27 | 삼성전자주식회사 | Semiconductor memory device and method of forming the same |
JP2012059862A (en) * | 2010-09-08 | 2012-03-22 | Toshiba Corp | Non-volatile memory device and method of manufacturing the same |
-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7544546B2 (en) * | 2006-05-15 | 2009-06-09 | International Business Machines Corporation | Formation of carbon and semiconductor nanomaterials using molecular assemblies |
US7855133B2 (en) * | 2006-05-15 | 2010-12-21 | International Business Machines Corporation | Formation of carbon and semiconductor nanomaterials using molecular assemblies |
US20100264392A1 (en) * | 2007-11-15 | 2010-10-21 | Yoshio Kawashima | Nonvolatile memory apparatus and manufacturing method thereof |
US8242479B2 (en) * | 2007-11-15 | 2012-08-14 | Panasonic Corporation | Nonvolatile memory apparatus and manufacturing method thereof |
US20100276656A1 (en) * | 2008-09-22 | 2010-11-04 | Nishant Sinha | Devices Comprising Carbon Nanotubes, And Methods Of Forming Devices Comprising Carbon Nanotubes |
US8264866B2 (en) * | 2009-09-24 | 2012-09-11 | Kabushiki Kaisha Toshiba | Nonvolatile memory device and method for manufacturing same |
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