US20130058007A1 - Method for forming a capacitor dielectric and method for manufacturing a capacitor using the capacitor dielectric - Google Patents

Method for forming a capacitor dielectric and method for manufacturing a capacitor using the capacitor dielectric Download PDF

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US20130058007A1
US20130058007A1 US13/603,291 US201213603291A US2013058007A1 US 20130058007 A1 US20130058007 A1 US 20130058007A1 US 201213603291 A US201213603291 A US 201213603291A US 2013058007 A1 US2013058007 A1 US 2013058007A1
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oxide layer
approximately
tantalum
zirconium
introducing
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US13/603,291
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Jong-Bum Park
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/405—Oxides of refractory metals or yttrium
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • H—ELECTRICITY
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    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
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    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1236—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates
    • H01G4/1245—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates containing also titanates
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31641—Deposition of Zirconium oxides, e.g. ZrO2
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/435—Solid dielectric type

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device; and, more particularly, to a method for forming a capacitor dielectric having a zirconium oxide layer and a tantalum oxide layer, and a method for manufacturing a capacitor using the capacitor dielectric.
  • hafnium oxide HfO 2
  • aluminum oxide Al 2 O 3
  • hafnium oxide is conventionally used as a capacitor dielectric in a metal-insulator-metal (MIM) capacitor for enhancing capacitance and minimizing leakage current.
  • Hafnium oxide is a high-dielectric-constant material with a crystalline phase
  • aluminum oxide is a low-dielectric-constant material with an amorphous phase.
  • FIG. 1 is a cross-sectional view of a conventional capacitor structure.
  • the conventional capacitor includes a lower electrode 11 , a capacitor dielectric 12 having a stacked structure of HfO 2 /Al 2 O 3 /HfO 2 disposed on the lower electrode 11 , and an upper electrode 13 disposed on the capacitor dielectric 12 .
  • Hafnium oxide increases the dielectric constant in the capacitor dielectric 12 .
  • the leakage current performance characteristic deteriorates when hafnium oxide crystallizes.
  • the hafnium oxide should be cautiously crystallized in the conventional capacitor structure to achieve a favorable leakage current performance characteristic.
  • an amount by which the capacitance may be increased may be limited when using hafnium oxide for the capacitor dielectric.
  • applying hafnium oxide to the capacitor dielectric is difficult when the design rule of the capacitor is reduced.
  • Specific embodiments of the present invention provide a method for forming a capacitor dielectric having a zirconium oxide layer and a tantalum oxide layer. Both the zirconium oxide layer and the tantalum oxide layer have a tetragonal phase. The resulting capacitor dielectric maintains a favorable leakage current performance characteristic and a high dielectric constant. A method for manufacturing a capacitor using the disclosed capacitor dielectric is also provided.
  • a method for forming a capacitor dielectric includes depositing a zirconium oxide layer.
  • a post-treatment is performed on the zirconium layer such that the zirconium oxide layer has a tetragonal phase.
  • a tantalum oxide layer having a tetragonal phase is deposited over the zirconium oxide layer.
  • a method for forming a capacitor dielectric includes depositing a tantalum oxide layer. A post-treatment is performed on the tantalum oxide layer such that the tantalum oxide layer has a tetragonal phase. A zirconium oxide layer having a tetragonal phase is deposited over the tantalum oxide layer.
  • a method for manufacturing a capacitor includes forming a lower electrode.
  • a capacitor dielectric is formed over the lower electrode.
  • the capacitor dielectric includes a zirconium oxide layer having a tetragonal phase and a tantalum oxide layer having a tetragonal phase.
  • An upper electrode is formed over the capacitor dielectric.
  • a capacitor comprises a lower electrode.
  • a capacitor dielectric is formed over the lower electrode, wherein the capacitor dielectric includes a zirconium oxide layer having a tetragonal phase and a tantalum oxide layer having a tetragonal phase.
  • An upper electrode is formed over the capacitor dielectric.
  • FIG. 1 is a cross-sectional view of a conventional capacitor structure.
  • FIG. 2 is a cross-sectional view of a capacitor structure in accordance with a first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a capacitor structure in accordance with a second embodiment of the present invention.
  • FIGS. 4A to 4C illustrate a method for manufacturing the capacitor according to the first embodiment of the present invention.
  • FIGS. 5A to 5C illustrate a method for manufacturing the capacitor according to the second embodiment of the present invention.
  • FIG. 2 illustrates a cross-sectional view of a capacitor structure in accordance with a first embodiment of the present invention.
  • a capacitor in accordance with the first embodiment includes a lower electrode 21 , a capacitor dielectric 100 disposed on the lower electrode 21 , and an upper electrode 24 disposed on the capacitor dielectric 100 .
  • the capacitor dielectric 100 includes a zirconium oxide (ZrO 2 ) layer 22 A e and a tantalum oxide layer (Ta 2 O 5 ) 23 .
  • the zirconium oxide layer 22 A and the tantalum oxide layer 23 are sequentially stacked on the lower electrode 21 .
  • FIG. 3 is a cross-sectional view of a capacitor structure in accordance with a second embodiment of the present invention.
  • a capacitor in accordance with the second embodiment includes a lower electrode 31 , a capacitor dielectric 200 disposed on the lower electrode 31 , and an upper electrode 34 disposed on the capacitor dielectric 200 .
  • the capacitor dielectric 200 is configured with a tantalum oxide layer 32 A and a zirconium oxide layer 33 .
  • the tantalum oxide layer 32 A and the zirconium oxide layer 33 are sequentially stacked on the lower electrode 31 .
  • both the zirconium oxide layers 22 A and 33 and the tantalum oxide layers 23 and 32 A that are used for each capacitor dielectric 100 and 200 have a tetragonal phase.
  • the zirconium oxide layer 22 A and 33 and the tantalum oxide layer 23 and 32 A are represented as reference symbols T-ZrO 2 and T-Ta 2 O 5 , respectively.
  • the tetragonal phase may be obtained using ozone (O 3 ) treatment between two deposition processes for the zirconium oxide and the tantalum oxide layers.
  • O 3 ozone
  • the lower electrodes 21 and 31 and the upper electrodes 24 and 34 each include a metal electrode.
  • Each electrode is formed of one material selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), platinum (Pt), iridium (Ir) and hafnium nitride (HfN).
  • FIGS. 4A to 4C illustrate a method for manufacturing the capacitor according to the first embodiment of the present invention.
  • the lower electrode 21 is formed.
  • the lower electrode 21 includes a metal electrode.
  • the lower electrode is formed of one material selected from the group consisting of: TiN, Ru, Pt, Ir and HfN.
  • the surface of the lower electrode 21 is cleaned using fluoric acid or buffered oxide etchant.
  • a wafer formed with the lower electrode 21 is loaded into a chamber in which an atomic layer deposition process will be performed.
  • the deposition of the zirconium oxide layer 22 is performed under a chamber pressure of approximately 0.1 torr to approximately 10 torr, and at a process temperature of approximately 250° C. to approximately 350° C.
  • the atomic layer deposition process is performed repeatedly until the zirconium oxide layer 22 has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle.
  • the unit deposition cycle includes: loading the substrate with the lower electrode 21 into the deposition chamber; introducing a zirconium source; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • the zirconium source After loading the substrate into the deposition chamber, the zirconium source is introduced into the chamber so that it is adsorbed on the lower electrode 21 .
  • the zirconium source uses a precursor selected from the group consisting of: Zr[NC 2 H 5 CH 3 ] 4 ], Zr[OC(CH 3 ) 2 CH 2 OCH 3 ] 4 , Zr [OC(CH 3 ) 3 ] 4 , ZrCl 4 and ZrI 4 .
  • the zirconium source flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber to remove any unreacted zirconium source from the deposition chamber that was not adsorbed on the surface of the lower electrode.
  • Inert gas e.g., Ar, He, N 2 gas or the like, and combinations thereof
  • the purge gas flows for approximately 0.1 to 10 seconds.
  • the reactant is introduced into the deposition chamber.
  • the reactant may include O 3 or O 2 plasma.
  • the reactant flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber again to remove any unreacted reactant and any by-products.
  • the inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 seconds.
  • the zirconium oxide layer is deposited on the lower electrode 21 at a desired thickness.
  • the desired thickness is from approximately 40 ⁇ to approximately 100 ⁇ .
  • an ozone treatment is performed on the zirconium oxide layer 22 so that the zirconium oxide layer 22 has a tetragonal phase.
  • the ozone treatment is performed at a process temperature of approximately 300° C. to approximately 500° C.
  • the ozone concentration is approximately 180 g/m 3 to approximately 300 g/m 3 .
  • the zirconium oxide layer 22 with the tetragonal phase is referred to as a T-zirconium oxide layer (T-ZrO 2 ) 22 A.
  • a tantalum oxide layer 23 is deposited on the T-zirconium oxide layer 22 A.
  • the tantalum oxide layer 23 has a thickness of approximately 20 ⁇ to approximately 100 ⁇ using the atomic layer deposition process described above.
  • the atomic layer deposition process is performed at a chamber pressure of approximately 0.1 torr to approximately 10 torr, and at a process temperature of approximately 250° C. to approximately 350° C.
  • a deposition method of the tantalum oxide layer 23 is described in detail below.
  • the atomic layer deposition process is performed repeatedly until the tantalum oxide layer 23 has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle in a deposition chamber.
  • the unit deposition cycle includes: introducing tantalum source onto the substrate on which the T-zirconium oxide layer 22 A is formed; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • the tantalum source is introduced into the deposition chamber to be adsorbed on the T-zirconium oxide layer 22 A.
  • the tantalum source uses a precursor of tantalum chloride (TaCl 5 ).
  • the tantalum source flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber to remove any unreacted remaining tantalum source which is not adsorbed on the surface of the T-zirconium oxide layer 22 A.
  • Inert gas e.g., Ar, He, N 2 gas or the like, and combinations thereof
  • the purge gas flows for approximately 0.1 to 10 seconds.
  • the reactant is introduced into the deposition chamber.
  • the reactant may include O 3 or O 2 plasma.
  • the reactant flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber again to remove any unreacted reactant and by-products.
  • the inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 seconds.
  • the tantalum oxide layer 23 is deposited on the T-zirconium oxide layer 22 A at a desired thickness.
  • the desired thickness is from approximately 20 ⁇ to approximately 100 ⁇ .
  • the tantalum oxide layer 23 When the tantalum oxide layer 23 is deposited as described above, the tantalum oxide layer 23 has a tetragonal phase. In other words, when the tantalum oxide layer 23 is deposited on the T-zirconium oxide layer 22 A having the tetragonal phase, the tantalum oxide layer 23 also has the tetragonal phase.
  • the tantalum oxide layer 23 with the tetragonal phase is referred to as a T-tantalum oxide layer (T-Ta 2 O 5 ).
  • FIGS. 5A to 5C illustrate a method for manufacturing a capacitor according to the second embodiment of the present invention.
  • the lower electrode 31 is formed.
  • the lower electrode 31 includes a metal.
  • the lower electrode 31 is formed of one material selected from the group consisting of: TiN, Ru, Pt, Ir and HfN.
  • the surface of the lower electrode 31 is cleaned using fluoric acid or buffered oxide etchant.
  • a wafer that is formed with the lower electrode 31 is loaded into a chamber in which an atomic layer deposition process will be performed.
  • the deposition of the tantalum oxide layer 32 is performed at a chamber pressure of approximately 0.1 torr to approximately 10 torr, and at a process temperature of approximately 250° C. to approximately 350° C.
  • the tantalum oxide layer 32 is deposited on the lower electrode 31 at a thickness of approximately 20 ⁇ to approximately 100 ⁇ using the atomic layer deposition process.
  • the atomic layer deposition process is performed under a chamber pressure of approximately 0.1 torr to approximately 10 torr and at a process temperature of approximately 250° C. to approximately 350° C.
  • a deposition method of the tantalum oxide layer 32 is described in detail below.
  • the atomic layer deposition process is performed repeatedly until the tantalum oxide layer 32 has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle.
  • the unit deposition cycle includes: introducing a tantalum source into the deposition chamber; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • the tantalum source is introduced into the deposition chamber so that the tantalum source is adsorbed on the lower electrode 31 .
  • the tantalum source uses a precursor of tantalum chloride (TaCl 5 ).
  • the tantalum source flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber to remove any unreacted remaining tantalum source.
  • the unreacted tantalum source may include tantalum source that is not adsorbed on the surface of the lower electrode 31 .
  • Inert gas e.g., Ar, He, N 2 gas, or the like, and combinations thereof
  • the purge gas flows for approximately 0.1 to 10 seconds.
  • the reactant is introduced into the deposition chamber.
  • the reactant may include O 3 or O 2 plasma.
  • the reactant flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber again to remove any unreacted reactant and by-products.
  • the inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 second(s).
  • the tantalum oxide layer 32 is deposited on the lower electrode 31 at a desired thickness.
  • the desired thickness of the tantalum oxide layer 32 is from approximately 20 ⁇ to approximately 100 ⁇ .
  • ozone treatment is performed to provide the tantalum oxide layer 32 with a tetragonal phase, as illustrated in FIG. 5B .
  • the ozone treatment is performed at a process temperature of approximately 300° C. to approximately 500° C., and at an ozone concentration of approximately 180 g/m 3 to approximately 300 g/m 3 .
  • the tantalum oxide layer 32 is converted into the tantalum oxide with the tetragonal phase (T-Ta 2 O 5 ) after the ozone treatment.
  • a zirconium oxide layer 33 is deposited on the T-tantalum oxide layer 32 A.
  • the atomic layer deposition process is performed repeatedly until the zirconium oxide layer has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle.
  • the unit deposition process includes: loading the substrate formed with the T-tantalum oxide layer 32 A into the deposition chamber; introducing a zirconium source; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • the zirconium source is introduced into the chamber so that it is adsorbed on the T-tantalum oxide layer 32 A.
  • the zirconium source uses a precursor selected from the group consisting of: Zr[NC 2 H 5 CH 3 ] 4 ], Zr[OC(CH 3 ) 2 CH 2 OCH 3 ] 4 , Zr[OC(CH 3 ) 3 ] 4 , ZrC 1 4 and ZrI 4 .
  • the zirconium source flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber to remove any unreacted remaining zirconium source from the deposition chamber.
  • the unreacted zirconium source may include any zirconium source that is not adsorbed on the surface of the T-tantalum oxide layer 32 A.
  • Inert gas e.g., Ar, He, N 2 gas or the like, and combinations thereof
  • the purge gas flows for approximately 0.1 to 10 seconds.
  • the reactant is introduced into the deposition chamber.
  • the reactant may include O 3 or O 2 plasma.
  • the reactant flows for approximately 0.1 to 10 seconds.
  • the purge gas is introduced into the deposition chamber again to remove any unreacted reactant and by-products.
  • the inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 seconds.
  • the zirconium oxide layer 33 is deposited on the T-tantalum oxide layer 32 A at a desired thickness.
  • the desired thickness of the zirconium oxide layer 33 is from approximately 40 ⁇ to approximately 100 ⁇ .
  • the zirconium oxide layer 33 When the zirconium oxide layer 33 is deposited as described above, the zirconium oxide layer 33 has a tetragonal phase . In other words, when the zirconium oxide layer 33 is deposited on the T-tantalum oxide layer 32 A having the tetragonal phase, the zirconium oxide layer 33 also has the tetragonal phase.
  • the deposition of the zirconium oxide layer, the ozone treatment and the deposition of the tantalum oxide layer are performed in situ.
  • the capacitor dielectric is configured as a bilayer with Ta 2 O 5 /ZrO 2 or ZrO 2 /Ta 2 O 5 , instead of a multi-stacked layer such as a conventional triple layer with HfO 2 /Al 2 O 3 /HfO 2 .
  • a first dielectric layer i.e., the zirconium oxide layer (or tantalum oxide layer) is deposited with a predetermined thickness. The ozone treatment is performed to provide the first dielectric layer with the tetragonal phase.
  • a second dielectric layer i.e., the tantalum oxide layer (or zirconium oxide layer) is deposited on the ozone-treated first dielectric layer such that the second dielectric layer also has the tetragonal phase.
  • the second dielectric layer is deposited with the tetragonal phase on the first dielectric layer.
  • the tantalum oxide layer is deposited on the T-zirconium oxide layer
  • the tantalum oxide layer formed on the T-zirconium oxide layer also has the tetragonal phase.
  • both the zirconium oxide layer and the tantalum oxide layer have the tetragonal phase, they provide better leakage current performance characteristic than the zirconium oxide and the tantalum oxide layers at other phases.
  • the dielectric constant of the zirconium oxide layer is nearly two times greater in the tetragonal phase than in a cubic phase. Specifically, the zirconium oxide layer has a dielectric constant of approximately 23 in the cubic phase, but it has a dielectric constant of approximately 40 in the tetragonal phase. Thus, the leakage current performance characteristic is enhanced.
  • the tantalum oxide layer has a dielectric constant of approximately 20 in the amorphous phase, whereas it has a dielectric constant of approximately 25 to approximately 50 during crystallization. Therefore, the capacitance of the tantalum oxide layer is improved.
  • the capacitor dielectric having the tetragonal phase can be formed by controlling the process temperature and the deposition thickness of each dielectric layer.
  • the stacked structure of the zirconium oxide layer and the tantalum oxide layer is used as the capacitor dielectric.
  • the ozone treatment is performed between two deposition processes so that both the zirconium oxide layer and the tantalum oxide layer have the tetragonal phase.
  • the tetragonal phase enhances the leakage current performance characteristics and increases the capacitance.
  • the stacked structure of the zirconium oxide layer and the tantalum oxide layer has an effective oxide thickness of approximately 9 ⁇ or smaller due to a high dielectric constant. Accordingly, it is possible to secure sufficient capacitance even though a design rule is reduced

Abstract

A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present invention claims priority to Korean patent application number 10-2006-0059998, filed on Jun. 29, 2006 which is incorporated herein by reference in its entirety.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to a method for manufacturing a semiconductor device; and, more particularly, to a method for forming a capacitor dielectric having a zirconium oxide layer and a tantalum oxide layer, and a method for manufacturing a capacitor using the capacitor dielectric.
  • A stacked structure of hafnium oxide (HfO2)/aluminum oxide (Al2O3)/hafnium oxide is conventionally used as a capacitor dielectric in a metal-insulator-metal (MIM) capacitor for enhancing capacitance and minimizing leakage current. Hafnium oxide is a high-dielectric-constant material with a crystalline phase, and aluminum oxide is a low-dielectric-constant material with an amorphous phase.
  • FIG. 1 is a cross-sectional view of a conventional capacitor structure. The conventional capacitor includes a lower electrode 11, a capacitor dielectric 12 having a stacked structure of HfO2/Al2O3/HfO2 disposed on the lower electrode 11, and an upper electrode 13 disposed on the capacitor dielectric 12.
  • Hafnium oxide increases the dielectric constant in the capacitor dielectric 12. However, the leakage current performance characteristic deteriorates when hafnium oxide crystallizes. Thus, the hafnium oxide should be cautiously crystallized in the conventional capacitor structure to achieve a favorable leakage current performance characteristic.
  • Furthermore, an amount by which the capacitance may be increased may be limited when using hafnium oxide for the capacitor dielectric. Hence, applying hafnium oxide to the capacitor dielectric is difficult when the design rule of the capacitor is reduced.
    • SUMMARY OF THE INVENTION
  • Specific embodiments of the present invention provide a method for forming a capacitor dielectric having a zirconium oxide layer and a tantalum oxide layer. Both the zirconium oxide layer and the tantalum oxide layer have a tetragonal phase. The resulting capacitor dielectric maintains a favorable leakage current performance characteristic and a high dielectric constant. A method for manufacturing a capacitor using the disclosed capacitor dielectric is also provided.
  • In accordance with an aspect of the present invention, a method for forming a capacitor dielectric includes depositing a zirconium oxide layer. A post-treatment is performed on the zirconium layer such that the zirconium oxide layer has a tetragonal phase. A tantalum oxide layer having a tetragonal phase is deposited over the zirconium oxide layer.
  • In accordance with another aspect of the present invention, a method for forming a capacitor dielectric includes depositing a tantalum oxide layer. A post-treatment is performed on the tantalum oxide layer such that the tantalum oxide layer has a tetragonal phase. A zirconium oxide layer having a tetragonal phase is deposited over the tantalum oxide layer.
  • In accordance with another aspect of the present invention, a method for manufacturing a capacitor includes forming a lower electrode. A capacitor dielectric is formed over the lower electrode. The capacitor dielectric includes a zirconium oxide layer having a tetragonal phase and a tantalum oxide layer having a tetragonal phase. An upper electrode is formed over the capacitor dielectric.
  • In accordance with another aspect of the present invention, a capacitor comprises a lower electrode. A capacitor dielectric is formed over the lower electrode, wherein the capacitor dielectric includes a zirconium oxide layer having a tetragonal phase and a tantalum oxide layer having a tetragonal phase. An upper electrode is formed over the capacitor dielectric.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a conventional capacitor structure.
  • FIG. 2 is a cross-sectional view of a capacitor structure in accordance with a first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a capacitor structure in accordance with a second embodiment of the present invention.
  • FIGS. 4A to 4C illustrate a method for manufacturing the capacitor according to the first embodiment of the present invention.
  • FIGS. 5A to 5C illustrate a method for manufacturing the capacitor according to the second embodiment of the present invention.
    •  DESCRIPTION OF SPECIFIC EMBODIMENTS
  • FIG. 2 illustrates a cross-sectional view of a capacitor structure in accordance with a first embodiment of the present invention. A capacitor in accordance with the first embodiment includes a lower electrode 21, a capacitor dielectric 100 disposed on the lower electrode 21, and an upper electrode 24 disposed on the capacitor dielectric 100. The capacitor dielectric 100 includes a zirconium oxide (ZrO2) layer 22A e and a tantalum oxide layer (Ta2O5) 23. The zirconium oxide layer 22A and the tantalum oxide layer 23 are sequentially stacked on the lower electrode 21.
  • FIG. 3 is a cross-sectional view of a capacitor structure in accordance with a second embodiment of the present invention. A capacitor in accordance with the second embodiment includes a lower electrode 31, a capacitor dielectric 200 disposed on the lower electrode 31, and an upper electrode 34 disposed on the capacitor dielectric 200. The capacitor dielectric 200 is configured with a tantalum oxide layer 32A and a zirconium oxide layer 33. The tantalum oxide layer 32A and the zirconium oxide layer 33 are sequentially stacked on the lower electrode 31.
  • In FIGS. 2 and 3, both the zirconium oxide layers 22A and 33 and the tantalum oxide layers 23 and 32A that are used for each capacitor dielectric 100 and 200 have a tetragonal phase. Thus, the zirconium oxide layer 22A and 33 and the tantalum oxide layer 23 and 32A are represented as reference symbols T-ZrO2 and T-Ta2O5, respectively.
  • An atomic layer deposition process is performed to obtain the tetragonal phase. The tetragonal phase may be obtained using ozone (O3) treatment between two deposition processes for the zirconium oxide and the tantalum oxide layers. A method for forming the capacitor dielectric is described in detail below.
  • The lower electrodes 21 and 31 and the upper electrodes 24 and 34 each include a metal electrode. Each electrode is formed of one material selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), platinum (Pt), iridium (Ir) and hafnium nitride (HfN).
  • FIGS. 4A to 4C illustrate a method for manufacturing the capacitor according to the first embodiment of the present invention. Referring to FIG. 4A, the lower electrode 21 is formed. The lower electrode 21 includes a metal electrode. Specifically, the lower electrode is formed of one material selected from the group consisting of: TiN, Ru, Pt, Ir and HfN. The surface of the lower electrode 21 is cleaned using fluoric acid or buffered oxide etchant.
  • A wafer formed with the lower electrode 21 is loaded into a chamber in which an atomic layer deposition process will be performed. The deposition of the zirconium oxide layer 22 is performed under a chamber pressure of approximately 0.1 torr to approximately 10 torr, and at a process temperature of approximately 250° C. to approximately 350° C.
  • The atomic layer deposition process is performed repeatedly until the zirconium oxide layer 22 has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle. The unit deposition cycle includes: loading the substrate with the lower electrode 21 into the deposition chamber; introducing a zirconium source; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • After loading the substrate into the deposition chamber, the zirconium source is introduced into the chamber so that it is adsorbed on the lower electrode 21. The zirconium source uses a precursor selected from the group consisting of: Zr[NC2H5CH3]4], Zr[OC(CH3)2CH2OCH3]4, Zr [OC(CH3)3]4, ZrCl4 and ZrI4. The zirconium source flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber to remove any unreacted zirconium source from the deposition chamber that was not adsorbed on the surface of the lower electrode. Inert gas (e.g., Ar, He, N2 gas or the like, and combinations thereof) is used as the purge gas. The purge gas flows for approximately 0.1 to 10 seconds.
  • The reactant is introduced into the deposition chamber. The reactant may include O3 or O2 plasma. The reactant flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber again to remove any unreacted reactant and any by-products. The inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 seconds.
  • By repeating the unit deposition cycle described above, the zirconium oxide layer is deposited on the lower electrode 21 at a desired thickness. In one embodiment, the desired thickness is from approximately 40 Å to approximately 100 Å.
  • Referring to FIG. 4B, after depositing the zirconium oxide layer 22, an ozone treatment is performed on the zirconium oxide layer 22 so that the zirconium oxide layer 22 has a tetragonal phase. The ozone treatment is performed at a process temperature of approximately 300° C. to approximately 500° C. In addition, the ozone concentration is approximately 180 g/m3 to approximately 300 g/m3. Hereinafter, the zirconium oxide layer 22 with the tetragonal phase is referred to as a T-zirconium oxide layer (T-ZrO2) 22A.
  • Referring to FIG. 4C, a tantalum oxide layer 23 is deposited on the T-zirconium oxide layer 22A. The tantalum oxide layer 23 has a thickness of approximately 20 Å to approximately 100 Å using the atomic layer deposition process described above. The atomic layer deposition process is performed at a chamber pressure of approximately 0.1 torr to approximately 10 torr, and at a process temperature of approximately 250° C. to approximately 350° C. A deposition method of the tantalum oxide layer 23 is described in detail below.
  • The atomic layer deposition process is performed repeatedly until the tantalum oxide layer 23 has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle in a deposition chamber. The unit deposition cycle includes: introducing tantalum source onto the substrate on which the T-zirconium oxide layer 22A is formed; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • The tantalum source is introduced into the deposition chamber to be adsorbed on the T-zirconium oxide layer 22A. The tantalum source uses a precursor of tantalum chloride (TaCl5). The tantalum source flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber to remove any unreacted remaining tantalum source which is not adsorbed on the surface of the T-zirconium oxide layer 22A. Inert gas (e.g., Ar, He, N2 gas or the like, and combinations thereof) is used as the purge gas. The purge gas flows for approximately 0.1 to 10 seconds.
  • The reactant is introduced into the deposition chamber. The reactant may include O3 or O2 plasma. The reactant flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber again to remove any unreacted reactant and by-products. The inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 seconds.
  • By repeating the unit deposition cycle described above, the tantalum oxide layer 23 is deposited on the T-zirconium oxide layer 22A at a desired thickness. In one embodiment, the desired thickness is from approximately 20 Å to approximately 100 Å.
  • When the tantalum oxide layer 23 is deposited as described above, the tantalum oxide layer 23 has a tetragonal phase. In other words, when the tantalum oxide layer 23 is deposited on the T-zirconium oxide layer 22A having the tetragonal phase, the tantalum oxide layer 23 also has the tetragonal phase. Hereinafter, the tantalum oxide layer 23 with the tetragonal phase is referred to as a T-tantalum oxide layer (T-Ta2O5).
  • FIGS. 5A to 5C illustrate a method for manufacturing a capacitor according to the second embodiment of the present invention. Referring to FIG. 5A, the lower electrode 31 is formed. In one embodiment, the lower electrode 31 includes a metal. Specifically, the lower electrode 31 is formed of one material selected from the group consisting of: TiN, Ru, Pt, Ir and HfN. The surface of the lower electrode 31 is cleaned using fluoric acid or buffered oxide etchant.
  • A wafer that is formed with the lower electrode 31 is loaded into a chamber in which an atomic layer deposition process will be performed. The deposition of the tantalum oxide layer 32 is performed at a chamber pressure of approximately 0.1 torr to approximately 10 torr, and at a process temperature of approximately 250° C. to approximately 350° C.
  • The tantalum oxide layer 32 is deposited on the lower electrode 31 at a thickness of approximately 20 Å to approximately 100 Å using the atomic layer deposition process. The atomic layer deposition process is performed under a chamber pressure of approximately 0.1 torr to approximately 10 torr and at a process temperature of approximately 250° C. to approximately 350° C. A deposition method of the tantalum oxide layer 32 is described in detail below.
  • The atomic layer deposition process is performed repeatedly until the tantalum oxide layer 32 has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle. The unit deposition cycle includes: introducing a tantalum source into the deposition chamber; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • The tantalum source is introduced into the deposition chamber so that the tantalum source is adsorbed on the lower electrode 31. In one embodiment, the tantalum source uses a precursor of tantalum chloride (TaCl5). The tantalum source flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber to remove any unreacted remaining tantalum source. The unreacted tantalum source may include tantalum source that is not adsorbed on the surface of the lower electrode 31. Inert gas (e.g., Ar, He, N2 gas, or the like, and combinations thereof) is used as the purge gas. The purge gas flows for approximately 0.1 to 10 seconds.
  • The reactant is introduced into the deposition chamber. The reactant may include O3 or O2 plasma. The reactant flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber again to remove any unreacted reactant and by-products. The inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 second(s).
  • By repeating the unit deposition cycle, the tantalum oxide layer 32 is deposited on the lower electrode 31 at a desired thickness. In one embodiment, the desired thickness of the tantalum oxide layer 32 is from approximately 20 Å to approximately 100 Å.
  • After depositing the tantalum oxide layer 32, ozone treatment is performed to provide the tantalum oxide layer 32 with a tetragonal phase, as illustrated in FIG. 5B. In one embodiment, the ozone treatment is performed at a process temperature of approximately 300° C. to approximately 500° C., and at an ozone concentration of approximately 180 g/m3 to approximately 300 g/m3. The tantalum oxide layer 32 is converted into the tantalum oxide with the tetragonal phase (T-Ta2O5) after the ozone treatment.
  • Subsequently, referring to FIG. 5C, a zirconium oxide layer 33 is deposited on the T-tantalum oxide layer 32A.
  • A deposition method of the zirconium oxide layer using the atomic layer deposition process will be described. The atomic layer deposition process is performed repeatedly until the zirconium oxide layer has a desired predetermined thickness. Specifically, the atomic layer deposition process is performed by repeating a unit deposition cycle. The unit deposition process includes: loading the substrate formed with the T-tantalum oxide layer 32A into the deposition chamber; introducing a zirconium source; introducing a purge gas; introducing a reactant; and introducing a purge gas again.
  • After loading the substrate into the deposition chamber, the zirconium source is introduced into the chamber so that it is adsorbed on the T-tantalum oxide layer 32A. In one embodiment, the zirconium source uses a precursor selected from the group consisting of: Zr[NC2H5CH3]4], Zr[OC(CH3)2CH2OCH3]4, Zr[OC(CH3)3]4, ZrC1 4 and ZrI4. The zirconium source flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber to remove any unreacted remaining zirconium source from the deposition chamber. The unreacted zirconium source may include any zirconium source that is not adsorbed on the surface of the T-tantalum oxide layer 32A. Inert gas (e.g., Ar, He, N2 gas or the like, and combinations thereof) is used as the purge gas. The purge gas flows for approximately 0.1 to 10 seconds.
  • The reactant is introduced into the deposition chamber. The reactant may include O3 or O2 plasma. The reactant flows for approximately 0.1 to 10 seconds.
  • The purge gas is introduced into the deposition chamber again to remove any unreacted reactant and by-products. The inert gas is used as the purge gas, and the purge gas flows for approximately 0.1 to 10 seconds.
  • By repeating the unit deposition cycle, the zirconium oxide layer 33 is deposited on the T-tantalum oxide layer 32A at a desired thickness. In one embodiment, the desired thickness of the zirconium oxide layer 33 is from approximately 40 Å to approximately 100 Å.
  • When the zirconium oxide layer 33 is deposited as described above, the zirconium oxide layer 33 has a tetragonal phase . In other words, when the zirconium oxide layer 33 is deposited on the T-tantalum oxide layer 32A having the tetragonal phase, the zirconium oxide layer 33 also has the tetragonal phase.
  • In the embodiments described, the deposition of the zirconium oxide layer, the ozone treatment and the deposition of the tantalum oxide layer are performed in situ.
  • In accordance with the embodiments described above, the capacitor dielectric is configured as a bilayer with Ta2O5/ZrO2 or ZrO2/Ta2O5, instead of a multi-stacked layer such as a conventional triple layer with HfO2/Al2O3/HfO2. In the present embodiments, a first dielectric layer, i.e., the zirconium oxide layer (or tantalum oxide layer), is deposited with a predetermined thickness. The ozone treatment is performed to provide the first dielectric layer with the tetragonal phase. Subsequently, a second dielectric layer, i.e., the tantalum oxide layer (or zirconium oxide layer), is deposited on the ozone-treated first dielectric layer such that the second dielectric layer also has the tetragonal phase. In other words, by depositing the second dielectric layer on the ozone-treated first dielectric layer with the tetragonal phase at a predetermined temperature, the second dielectric layer is deposited with the tetragonal phase on the first dielectric layer. For example, if the tantalum oxide layer is deposited on the T-zirconium oxide layer, the tantalum oxide layer formed on the T-zirconium oxide layer also has the tetragonal phase.
  • When both the zirconium oxide layer and the tantalum oxide layer have the tetragonal phase, they provide better leakage current performance characteristic than the zirconium oxide and the tantalum oxide layers at other phases.
  • The dielectric constant of the zirconium oxide layer is nearly two times greater in the tetragonal phase than in a cubic phase. Specifically, the zirconium oxide layer has a dielectric constant of approximately 23 in the cubic phase, but it has a dielectric constant of approximately 40 in the tetragonal phase. Thus, the leakage current performance characteristic is enhanced.
  • Furthermore, it is possible to obtain a higher capacitance than the conventional capacitor dielectric.
  • Similarly, the tantalum oxide layer has a dielectric constant of approximately 20 in the amorphous phase, whereas it has a dielectric constant of approximately 25 to approximately 50 during crystallization. Therefore, the capacitance of the tantalum oxide layer is improved.
  • When forming the capacitor dielectric by sequentially performing the deposition of the first dielectric layer, the ozone treatment, and the deposition of the second dielectric layer, the capacitor dielectric having the tetragonal phase can be formed by controlling the process temperature and the deposition thickness of each dielectric layer. Thus, it is possible to form a capacitor dielectric that can provide high capacitance as well as excellent leakage current performance characteristics.
  • As described above, in accordance with the present invention, the stacked structure of the zirconium oxide layer and the tantalum oxide layer is used as the capacitor dielectric. The ozone treatment is performed between two deposition processes so that both the zirconium oxide layer and the tantalum oxide layer have the tetragonal phase. The tetragonal phase enhances the leakage current performance characteristics and increases the capacitance.
  • In one embodiment, the stacked structure of the zirconium oxide layer and the tantalum oxide layer has an effective oxide thickness of approximately 9 Å or smaller due to a high dielectric constant. Accordingly, it is possible to secure sufficient capacitance even though a design rule is reduced
  • While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (21)

1.-24. (canceled)
25. A method for manufacturing a capacitor, the method comprising:
forming a lower electrode over a substrate;
forming a capacitor dielectric over the lower electrode, wherein the capacitor dielectric includes a zirconium oxide layer having a tetragonal phase and a tantalum oxide layer having a tetragonal phase; and
forming an upper electrode over the capacitor dielectric.
26. The method of claim 25, wherein forming the capacitor dielectric comprises:
depositing a zirconium oxide layer;
performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase; and
depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.
27. The method of claim 25, wherein forming the capacitor dielectric comprises:
depositing a tantalum oxide layer;
performing a post-treatment on the tantalum oxide layer such that the tantalum oxide layer has a tetragonal phase; and
depositing a zirconium oxide layer over the tantalum oxide layer such that the zirconium oxide layer has a tetragonal phase.
28. The method of claim 26, wherein the post-treatment includes a use of ozone.
29. The method of claim 26, wherein the post-treatment includes use of oxygen, wherein the treatment is performed at a temperature of approximately 300° C. to approximately 500° C., in an environment with an oxygen concentration of approximately 180 g/m3 to approximately 300 g/m3.
30. The method of claim 26, wherein depositing the zirconium oxide layer and depositing the tantalum oxide layer are performed using an atomic layer deposition process.
31. The method of claim 30, wherein the atomic layer deposition process of the zirconium oxide layer is performed by repeating a unit deposition cycle until the zirconium oxide layer has a thickness of approximately 40 Å to approximately 100 Å, the unit deposition cycle comprising introducing a zirconium source, introducing a first purge gas, introducing a reactant, and introducing a second purge gas.
32. The method of claim 31, wherein the zirconium source uses a precursor selected from a group consisting of: Zr[NC2H5CH3]4], Zr[OC(CH3)2CH2OCH3]4, Zr[OC(CH3)3]4, ZrCl4 and ZrI4, and further wherein the zirconium source flows for approximately 0.1 to 10 seconds.
33. The method of claim 30, wherein the atomic layer deposition process of the tantalum oxide layer is performed by repeating a unit deposition cycle until the tantalum oxide layer has a thickness of approximately 20 Å to approximately 100 Å, the unit deposition cycle comprising: introducing a tantalum source, introducing a first purge gas, introducing a reactant, and introducing a second purge gas.
34. The method of claim 33, wherein the tantalum source uses a precursor of tantalum chloride, and further wherein the tantalum source flows for approximately 0.1 to 10 seconds.
35. The method of claim 30, wherein depositing the zirconium oxide layer and depositing the tantalum oxide layer are performed at a temperature range of approximately 250° C. to approximately 350° C. and under a pressure of approximately 0.1 torr to approximately 10 torr.
36. The method of claim 26, wherein the depositing-a-tantalum-oxide-layer step, the performing-a-post-treatment step, and the depositing-a-zirconium-oxide-layer step are performed in situ.
37. The method of claim 27, wherein depositing the zirconium oxide layer and depositing the tantalum oxide layer are performed using an atomic layer deposition process.
38. The method of claim 37, wherein the atomic layer deposition process of the zirconium oxide layer is performed by repeating a unit deposition cycle until the zirconium oxide layer has a thickness of approximately 40 Å to approximately 100 Å, the unit deposition process comprising: introducing a zirconium source, introducing a first purge gas, introducing a reactant, and introducing a second purge gas.
39. The method of claim 38, wherein the zirconium source uses a precursor selected from a group consisting of: Zr[NC2H5CH3]4], Zr[OC(CH3)2CH2OCH3]4, Zr[OC(CH3)3]4, ZrCl4 and ZrI4, and further wherein the zirconium source flows for approximately 0.1 to 10 seconds.
40. The method of claim 37, wherein the atomic layer deposition process of the tantalum oxide layer is performed by repeating a unit deposition cycle until the tantalum oxide layer has a thickness of approximately 20 Å to approximately 100 Å, the unit deposition cycle comprising: introducing a tantalum source, introducing a first purge gas, introducing a reactant, and introducing a second purge gas.
41. The method of claim 40, wherein the tantalum source uses a precursor of tantalum chloride, and further wherein the tantalum source flows for approximately 0.1 to 10 seconds.
42. The method of claim 37, wherein depositing the zirconium oxide layer and depositing the tantalum oxide layer are performed at a temperature of approximately 250° C. to approximately 350° C. and under a pressure of approximately 0.1 torr to approximately 10 torr.
43. The method of claim 37, wherein the depositing-a-tantalum-oxide-layer step, the performing-a-post-treatment step, and the depositing-a-zirconium-oxide-layer step are performed in situ.
44. A capacitor comprising:
a lower electrode;
a capacitor dielectric formed over the lower electrode, wherein the capacitor dielectric includes a zirconium oxide layer having a tetragonal phase and a tantalum oxide layer having a tetragonal phase; and
an upper electrode formed over the capacitor dielectric.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113054105A (en) * 2021-03-09 2021-06-29 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
US11515157B2 (en) * 2019-04-17 2022-11-29 SK Hynix Inc. Semiconductor device and method for fabricating the same

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100716655B1 (en) * 2006-06-29 2007-05-09 주식회사 하이닉스반도체 Method for forming capacitor dielectric with zrconium oxide and tantalum oxide stack and method of manufacturing capacitor using the same
KR100849854B1 (en) * 2007-02-23 2008-08-01 삼성전자주식회사 Semiconductor device and method of fabricating the same
WO2008126365A1 (en) * 2007-03-29 2008-10-23 Panasonic Corporation Nonvolatile memory device, nonvolatile memory element, and nonvolatile memory element array
KR100965771B1 (en) * 2007-05-07 2010-06-24 주식회사 하이닉스반도체 Method for fabricating dielectric layer with tantanlum oxide and method for fabricating capacitor using the same
US8159012B2 (en) 2007-09-28 2012-04-17 Samsung Electronics Co., Ltd. Semiconductor device including insulating layer of cubic system or tetragonal system
US8969188B2 (en) 2008-09-26 2015-03-03 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US7968406B2 (en) 2009-01-09 2011-06-28 Micron Technology, Inc. Memory cells, methods of forming dielectric materials, and methods of forming memory cells
TW201044426A (en) * 2009-01-15 2010-12-16 Tokyo Electron Ltd Capacitor and process for manufacturing capacitor
US9012294B2 (en) * 2010-07-27 2015-04-21 Panasonic Intellectual Property Management Co., Ltd. Manufacturing method of non-volatile memory device
US8921911B2 (en) * 2012-09-11 2014-12-30 Rexchip Electronics Corporation Vertical semiconductor charge storage structure
US20150170837A1 (en) * 2013-12-18 2015-06-18 Intermolecular, Inc. Dielectric K Value Tuning of HAH Stack for Improved TDDB Performance of Logic Decoupling Capacitor or Embedded DRAM
US9966425B1 (en) * 2017-02-28 2018-05-08 United Microelectronics Corp. Method for fabricating a MIM capacitor
JP6989207B2 (en) * 2018-05-15 2022-01-05 住友電工デバイス・イノベーション株式会社 Capacitor manufacturing method
JP7167344B2 (en) * 2018-11-29 2022-11-08 キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション Solid electrolytic capacitors containing sequentially deposited dielectric films
US11502160B2 (en) * 2020-03-02 2022-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for forming metal-insulator-metal capacitors
KR20220048302A (en) 2020-10-12 2022-04-19 삼성전자주식회사 integrated circuit device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274454B1 (en) * 1998-01-30 2001-08-14 Sony Corporation Method for fabricating dielectric capacitor
US6340621B1 (en) * 1996-10-30 2002-01-22 The Research Foundation Of State University Of New York Thin film capacitor and method of manufacture
US8110473B2 (en) * 2007-02-23 2012-02-07 Samsung Electronics Co., Ltd. Semiconductor device comprising multilayer dielectric film and related method
US8256077B2 (en) * 2006-06-29 2012-09-04 Hynix Semiconductor Inc. Method for forming a capacitor dielectric having tetragonal phase

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3582729A (en) * 1969-10-01 1971-06-01 Gen Electric Thick film capacitors and method of forming
US5189503A (en) * 1988-03-04 1993-02-23 Kabushiki Kaisha Toshiba High dielectric capacitor having low current leakage
US5099437A (en) * 1990-10-09 1992-03-24 Fugitive Emissions Control, Inc. Emissions monitoring and tracking system
US5206818A (en) * 1991-09-19 1993-04-27 International Business Machines Corporation Fugitive emissions monitoring system including integrated fugitive emissions analyzer and source identifier
US5356594A (en) * 1992-03-03 1994-10-18 Thermo Environmental Instruments Inc. Portable volatile organic compound monitoring system
US5479359A (en) * 1993-03-17 1995-12-26 Metcalf & Eddy, Inc. Automated data collection system for fugitive emission sources
US5760432A (en) * 1994-05-20 1998-06-02 Kabushiki Kaisha Toshiba Thin film strained layer ferroelectric capacitors
US5578834A (en) * 1994-06-21 1996-11-26 Tracker Technologies, Inc. Electrical/optical interface coupler
US5625529A (en) * 1995-03-28 1997-04-29 Samsung Electronics Co., Ltd. PZT thin films for ferroelectric capacitor and method for preparing the same
KR100207467B1 (en) * 1996-02-29 1999-07-15 윤종용 Fabricating method for capacitor in semiconductor device
US6235594B1 (en) * 1999-01-13 2001-05-22 Agere Systems Guardian Corp. Methods of fabricating an integrated circuit device with composite oxide dielectric
JP2001351913A (en) * 2000-06-07 2001-12-21 Nec Corp Semiconductor device and manufacturing of the same
US6548368B1 (en) * 2000-08-23 2003-04-15 Applied Materials, Inc. Method of forming a MIS capacitor
US6660660B2 (en) * 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
US6951804B2 (en) * 2001-02-02 2005-10-04 Applied Materials, Inc. Formation of a tantalum-nitride layer
US7164165B2 (en) * 2002-05-16 2007-01-16 Micron Technology, Inc. MIS capacitor
US6875678B2 (en) * 2002-09-10 2005-04-05 Samsung Electronics Co., Ltd. Post thermal treatment methods of forming high dielectric layers in integrated circuit devices
KR20040102277A (en) * 2003-05-27 2004-12-04 삼성전자주식회사 Method of forming dielectric films
KR20050033323A (en) * 2003-10-06 2005-04-12 삼성전자주식회사 Method of fabricating hafnium oxide film
US6989573B2 (en) * 2003-10-10 2006-01-24 Micron Technology, Inc. Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics
KR20050062132A (en) * 2003-12-19 2005-06-23 주식회사 하이닉스반도체 Fabricating method for capacitor with composite dielectric
KR100568516B1 (en) * 2004-02-24 2006-04-07 삼성전자주식회사 Method of fabricating an analog capacitor using a post-treatment technique
JP4324796B2 (en) 2004-08-30 2009-09-02 セイコーエプソン株式会社 Ferroelectric film, ferroelectric film manufacturing method, ferroelectric capacitor, and ferroelectric memory
DE112005002160T5 (en) * 2004-09-09 2009-03-12 Tokyo Electron Ltd. Thin film capacitor and method of forming the same and computer readable storage medium
KR100655755B1 (en) * 2004-10-04 2006-12-11 삼성전자주식회사 Method for manufacturing a semiconductor device
KR100728962B1 (en) * 2004-11-08 2007-06-15 주식회사 하이닉스반도체 Capacitor of semiconductor device with zrconium oxide and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6340621B1 (en) * 1996-10-30 2002-01-22 The Research Foundation Of State University Of New York Thin film capacitor and method of manufacture
US6274454B1 (en) * 1998-01-30 2001-08-14 Sony Corporation Method for fabricating dielectric capacitor
US8256077B2 (en) * 2006-06-29 2012-09-04 Hynix Semiconductor Inc. Method for forming a capacitor dielectric having tetragonal phase
US8110473B2 (en) * 2007-02-23 2012-02-07 Samsung Electronics Co., Ltd. Semiconductor device comprising multilayer dielectric film and related method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11515157B2 (en) * 2019-04-17 2022-11-29 SK Hynix Inc. Semiconductor device and method for fabricating the same
CN113054105A (en) * 2021-03-09 2021-06-29 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

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