US20130056753A1 - Semiconductor Device with Low-Conducting Field-controlling Element - Google Patents
Semiconductor Device with Low-Conducting Field-controlling Element Download PDFInfo
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- US20130056753A1 US20130056753A1 US13/604,984 US201213604984A US2013056753A1 US 20130056753 A1 US20130056753 A1 US 20130056753A1 US 201213604984 A US201213604984 A US 201213604984A US 2013056753 A1 US2013056753 A1 US 2013056753A1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
Definitions
- the disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including one or more low conducting field-controlling elements.
- a semiconductor device is biased at Direct Current (DC) and/or modulated at relatively low frequencies, for example, below ten megahertz (MHz). Concurrently, the device can generate, amplify, and/or manipulate signals at much higher frequencies (for example, above one gigahertz (GHz)).
- DC Direct Current
- GHz gigahertz
- FIG. 1 shows an illustrative heterostructure field effect transistor (HFET) 2 A according to the prior art, which can be operated as a switch. When implemented in circuits such as power converters, the device dynamic on-resistance of the HFET 2 A should be minimized.
- HFET heterostructure field effect transistor
- a total channel length between the source electrode S and drain electrode D e.g., the sum of the distances L GS , L G , and L GD .
- the distance, L GD , between the gate electrode G and the drain electrode D must be sufficiently large, since most of the external voltage drop will occur between these two electrodes. Therefore, the requirements for large breakdown voltage and low on resistance are clashing.
- FIG. 2 shows an alternative HFET 2 B, which illustrates one approach to address the breakdown problem, according to the prior art.
- HFET 2 B includes a dielectric 3 A, 3 B deposited in the gate-source and gate-drain spacing and a field-modulating plate (FP). While the field-modulating plate FP is shown connected to the gate electrode G, other approaches connect one or several field-modulating plates FP to the source electrode S, drain electrode D, and/or the gate electrode G. Regardless, the field-modulating plate FP decreases a peak field near the electrode edge by splitting it into two or more peaks, thereby increasing the breakdown voltage of the HFET 2 B. However, the field-modulating plate FP increases the inter-electrode and electrode-semiconductor capacitances, and thus decreases a maximum operating frequency for the HFET 2 B.
- FP field-modulating plate
- FIGS. 3A and 3B show an illustrative HFET 2 C in the on state and the off state, respectively, when being operated as a radio frequency (RF) switch according to the prior art.
- RF radio frequency
- embodiments of the invention can provide a semiconductor device with an increased frequency range, an increased operating voltage, and/or an increased maximum power compared to semiconductor devices of the prior art.
- aspects of the invention provide a semiconductor device including a low conducting field-controlling element.
- the device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region.
- the field-controlling element can be coupled to one or more of the contacts in the set of contacts.
- the field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.
- the field-controlling element can behave similar to a metal electrode at direct current and/or low frequencies. However, within the device operating frequency range, the field-controlling element can behave similar to an insulator.
- a first aspect of the invention provides a device comprising: a semiconductor including an active region; a set of contacts to the active region; and a field-controlling element located on a first side of the active region, wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.
- a second aspect of the invention provides a field-effect transistor comprising: a source contact, a drain contact, and a device channel there between; a gate located on a first side of the device channel; and a low conducting field-controlling element located on the first side of the device channel, wherein the field-controlling element is coupled to at least one of: the source contact, the drain contact, or the gate and wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.
- a third aspect of the invention provides a method comprising: designing a semiconductor device including an active region, a set of contacts to the active region, and a field-controlling element located on a first side of the active region, wherein the designing includes: determining a target minimal operating frequency of the device and a target maximum control frequency of the device; determining a target lateral resistance for the field-controlling element such that the target lateral resistance is both larger than an inverse of the target minimal operating frequency and smaller than an inverse of the target maximum control frequency; and designing the field-controlling element based on the target lateral resistance.
- the illustrative aspects of the invention are designed to solve one or more of the problems herein described and/or one or more other problems not discussed.
- FIG. 1 shows an illustrative heterostructure field effect transistor (HFET) according to the prior art.
- FIG. 2 shows an alternative HFET according to the prior art.
- FIGS. 3A and 3B show an illustrative HFET in the on state and the off state, respectively, when being operated as a radio frequency switch according to the prior art.
- FIG. 4 shows an illustrative semiconductor device according to a first embodiment.
- FIG. 5 shows a schematic comparison of electric field profiles in the gate-drain spacing of various HFETs according to an embodiment.
- FIG. 6 shows experimental breakdown voltage characteristics of a conventional HFET and an HFET including a field-controlling electrode according to an embodiment.
- FIG. 7 shows an illustrative device according to a second embodiment.
- FIG. 8 shows an illustrative device according to a third embodiment.
- FIG. 9 shows an illustrative device according to a fourth embodiment.
- FIG. 10 shows an illustrative device according to a fifth embodiment.
- FIGS. 11A and 11B show an illustrative HFET configured to operate as a radio frequency (RF) switch according to an embodiment.
- RF radio frequency
- FIG. 12 shows experimental insertion loss and isolation characteristics of a prior art RF switch and an RF switch made using an HFET according to an embodiment.
- FIG. 13 shows an illustrative device according to a sixth embodiment.
- FIG. 14 shows an illustrative flow diagram for fabricating a circuit according to an embodiment.
- aspects of the invention provide a semiconductor device including a low conducting field-controlling element.
- the device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region.
- the field-controlling element can be coupled to one or more of the contacts in the set of contacts.
- the field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.
- the field-controlling element can behave similar to a metal electrode at direct current and/or low frequencies. However, within the device operating frequency range, the field-controlling element can behave similar to an insulator.
- the field-controlling element can be configured to increase a frequency range, an operating voltage, a maximum power, and/or the like, for operating the corresponding semiconductor device.
- the term “set” means one or more (i.e., at least one) and the phrase “any solution” means any now known or later developed solution.
- FIG. 4 shows an illustrative semiconductor device 10 according to a first embodiment.
- the device 10 is shown including a substrate 12 , an initiation layer 13 , a buffer layer 15 , an active layer 14 , a barrier layer 16 , a source contact 18 A, a drain contact 18 B, and a gate 20 , each of which can be manufactured and fabricated using any solution.
- the substrate 12 can be formed of any of various types of compound semiconductor or dielectric materials, including for example, sapphire, diamond, germanium (Ge), gallium nitride (GaN), silicon, silicon carbide (SiC), gallium arsenic (GaAs), and/or the like.
- the substrate 12 can comprise a conducting and/or semiconducting substrate.
- an initiation layer 13 and a buffer layer 15 can be located between the substrate 12 and the active layer 14 .
- the heterostructure of the device 10 can include various layers made from any of a plurality of materials systems.
- one or more of the layers in a heterostructure described herein can include one or more attributes to alleviate strain.
- a layer can be formed of a superlattice structure.
- the substrate 12 is formed of SiC
- the active layer 14 is formed of gallium nitride (GaN)
- the barrier layer 16 is formed of aluminum gallium nitride (AlGaN).
- AlGaN aluminum gallium nitride
- group III nitride materials include AlN, GaN, InN, BN, AlGaN, AlInN, AlBN, InGaN, AlGaInN, AlGaBN, AlInBN, and AlGaInBN with any molar fraction of group III elements.
- the device 10 can be formed from other semiconductor materials, including other types of group III-V materials, such as such as GaAs, GaAlAs, InGaAs, indium phosphorus (InP), and/or the like.
- the device 10 includes a low conducting field-controlling element 22 , which is located in the region between the gate 20 and the drain contact 18 B of the device 10 (gate-drain region).
- a device can include one or more field-controlling elements 22 located in any combination of one or more of: the gate-source region; the gate-drain region; source-drain region; and/or the like.
- a device can include a field-controlling element 22 that forms an additional contact or passivation layer.
- a field-controlling element 22 with low surface conductivity as described herein can be used in addition to or instead of regular metal electrodes.
- the field-controlling element 22 can be formed of a layer of low conducting material.
- the low conducting material can have a surface resistance that is significantly higher than that of metal electrodes, but is also much lower than that of a dielectric material.
- the low conducting material can have a surface conductivity that is significantly lower than that of metal electrodes, but is also much higher than that of a dielectric material.
- the associated characteristic charging-recharging time of the field-controlling element 22 is much higher than that of metal electrodes.
- the field-controlling element 22 will behave similar to metal electrodes.
- Illustrative low conducting materials include, for example: InGaN; a semiconductor; a low conducting dielectric single crystal; a textured, poly-crystalline or amorphous material; a semimetal material; oxides of nickel and other metals, and/or the like.
- the low conducting field-controlling element 22 can be implemented in various types of field-effect transistors, including, for example, a field-effect transistor, a heterostructure field-effect transistor, an insulated gate field-effect transistor, an insulated gate heterostructure field-effect transistor, a multiple heterostructure field-effect transistor, a multiple heterostructure insulated gate field-effect transistor, an inverted field-effect transistor, an inverted heterostructure field-effect transistor, an inverted insulated gate field-effect transistor, an inverted insulated gate heterostructure field-effect transistor, an inverted multiple heterostructure field-effect transistor, an inverted insulated gate multiple heterostructure field-effect transistor, and/or the like.
- the low conducting field-controlling element can be implemented in other types of semiconductor devices, including for example, a diode of any type, a semiconductor resistor, a semiconductor sensor, a light emitting diode, a laser, an integrated element, and/or the like.
- the low conducting field-controlling element 22 it is desired for the low conducting field-controlling element 22 to act as a conductor (e.g., electrode) when the device 10 is operating at low frequencies, and act as a dielectric when the device 10 is operating within a target device operating frequency range (high frequencies).
- the field-controlling element 22 makes a minor increase in the total electrode area and, as a result, in the device capacitance.
- the design and configuration of the field-controlling element 22 accounts for the frequency response for the resulting device 10 .
- the design and configuration of the field-controlling element 22 identifies a range of acceptable lateral and/or sheet resistances and/or a target lateral and/or sheet resistance for a set of field-controlling elements 22 included in a device 10 based on a target operating frequency (e.g., a minimal operating frequency), a target control frequency (e.g., a maximum control frequency), and/or the like.
- a target operating frequency e.g., a minimal operating frequency
- a target control frequency e.g., a maximum control frequency
- ⁇ FC a corresponding time constant for the field-controlling element 22 , ⁇ FC , must be much larger than 1/(2 ⁇ f), where f is the operating frequency for the device 10 .
- condition (1) can be rewritten as:
- the lateral resistance of the field-controlling element 22 , R FC is related to the low conducting layer sheet resistance, R LCSH , as:
- L and W are the length and width, respectively, of the field-controlling element 22 with respect to a direction of the current flow in the device 10 .
- the field-controlling element 22 should be sufficiently fast to allow for pulsed modulation of a bias applied to the gate 20 of the device 10 .
- a control frequency, f C and following the derivation that led to condition (2) above, the required ⁇ FC also should meet the following condition:
- the value of the ⁇ FC can be selected as follows:
- a value for the time constant for the field-controlling element 22 can be calculated as, ⁇ FC ⁇ 7.1 ns.
- the field-controlling element resistance R FC ⁇ FC /C FC .
- inclusion of the field-controlling element 22 in the gate-drain spacing as shown in FIG. 4 can substantially reduce/remove the electric field nonuniformity in the gate-drain spacing, thereby increasing the breakdown voltage of the device 10 over those of the prior art.
- the field-controlling element 22 with a sheet and/or lateral resistance designed as described herein behaves as an insulator and therefore does not increase or leads to a very minor increase in the capacitance of the device 10 .
- FIG. 5 shows a schematic comparison of electric field profiles in the gate-drain spacing of various devices according to an embodiment.
- FIG. 5 includes: an electric field profile corresponding to the HFET 2 A of FIG. 1 (identified as HFET); an electric field profile corresponding to the HFET 2 B of FIG. 2 (identified as FP HFET); and an electric field profile corresponding to the device 10 of FIG. 4 (identified as LC-FC HFET).
- the electric field of the device 10 is significantly more uniform over the gate-drain spacing than that of either HFET 2 A or HFET 2 B.
- FIG. 6 shows experimental breakdown voltage characteristics of a conventional HFET 2 A ( FIG. 1 , labeled as HFET in FIG. 6 ) and a device 10 including the field-controlling element 22 according to an embodiment (labeled as LC-FC HFET in FIG. 6 ).
- a conventional HFET 2 A FIG. 1 , labeled as HFET in FIG. 6
- a device 10 including the field-controlling element 22 according to an embodiment
- LC-FC HFET in FIG. 6 shows experimental breakdown voltage characteristics of a conventional HFET 2 A ( FIG. 1 , labeled as HFET in FIG. 6 ) and a device 10 including the field-controlling element 22 according to an embodiment (labeled as LC-FC HFET in FIG. 6 ).
- LC-FC HFETs LC-FC HFETs
- the field-controlling element 22 for the device 10 was formed by a Metallo Organic Chemical Vapor Deposition (MOCVD) deposited InGaN film
- a device can include one or more field-controlling elements located in various locations of the device depending on the desired function.
- an embodiment of a device can include a field-controlling element comprising a surface layer located in the gate-source spacing of the device.
- the field-controlling element can form an additional contact or passivation layer, form a strain relieving layer, replace a metal electrode, be buried/grown in the epitaxial structure, and/or the like. Regardless, in each case and in the additional embodiments described herein, the field-controlling element can be formed of a low conducting material.
- FIG. 7 shows an illustrative device 30 according to a second embodiment.
- Device 30 is shown including a set of low conducting field-controlling elements 22 A, 22 B, each of which comprises a surface layer of low conducting material located in the source-gate spacing and gate-drain spacing of the device 30 , respectively.
- the set of field-controlling elements 22 A, 22 B comprise a single, unitary surface layer, which can completely extend across (cover) the source-drain spacing or only partially cover the source-drain spacing.
- the set of field-controlling elements 22 A, 22 B can be contacting only the gate electrode 20 , one or more of the device electrodes 18 A, 18 B, 20 , or not contacting any of the device electrodes 18 A, 18 B, 20 .
- the device 30 includes an isolation layer 26 , which can be formed of a dielectric material, a semiconductor material, and/or the like, and can have a sheet resistance at least one order of magnitude higher than that of the field-controlling elements 22 A, 22 B. To this extent, the isolation layer 26 can partially or fully isolate the field-controlling elements 22 A, 22 B and the gate 20 from the semiconductor structure, thereby reducing any additional capacitance to the channel 24 provided by the field-controlling elements 22 A, 22 B.
- the set of field-controlling elements 22 A, 22 B can serve as a conduction path to remove trapped charges, and therefore reduce the gate and/or drain lags, which can be observed in group III nitride HFETs and other types of devices.
- FIG. 8 shows an illustrative device 32 according to a third embodiment.
- the device 32 includes a set of isolation layers 26 A, 26 B located in both the source-gate and gate-drain spacings, respectively.
- the device 32 includes a low conducting field-controlling element 22 , which forms a field-modulating plate connected to the gate 20 .
- the isolation layers 26 A, 26 B can partially or fully isolate the field-controlling element 22 from the semiconductor structure.
- the field-controlling element 22 does not form any significant additional capacitance to the drain electrode 18 B or the channel 24 , and therefore does not deteriorate the frequency performance of the device 32 .
- FIG. 9 shows an illustrative device 34 according to a fourth embodiment.
- the device 34 includes a first field-controlling element 28 A connected to the gate electrode 20 , and a second field-controlling element 28 B connected to the source electrode 18 A.
- An isolation layer 26 encapsulates the gate 20 and the first field-controlling element 28 A, thereby isolating the second field-controlling element 28 B from the gate 20 and the first field-controlling element 28 A.
- at least one of the first field-controlling element 28 A or the second field-controlling element 28 B is formed of a low conducting layer of material as described herein while one of the elements 28 A, 28 B can be made of metal.
- FIG. 10 shows an illustrative device 36 according to a fifth embodiment.
- the device 36 is configured similar to the device 34 of FIG. 9 , but also includes a third field-controlling element 28 C connected to the drain electrode 18 B. Additionally, the isolation layer 26 is extended over the second field-controlling element 28 B, thereby isolating the third field-controlling element 28 C from the second field-controlling element 28 B.
- one or more of the field-controlling elements 28 A- 28 C can be formed of a low conducting layer of material, while at most two of the field-controlling elements 28 A- 28 C can be formed of metal.
- one or more of the field-controlling elements 28 A- 28 C can be made of metal. It is understood that a particular configuration of field-controlling elements 28 A- 28 C formed of a low conducting layer of material and/or metal, if included, can be selected based on a particular set of device requirements and/or operating frequencies.
- FIGS. 11A and 11B show an illustrative HFET 40 configured to operate as a radio frequency (RF) switch in the on and off states, respectively, according to an embodiment.
- HFET 40 includes a low conducting field-controlling element 42 located within the source-drain spacing. Similar to the device 30 ( FIG. 7 ), the field-controlling element 42 of HFET 40 can be electrically connected to the gate electrode 20 and partially or entirely cover the source-drain spacing. In this configuration, the field-controlling element 42 can be used to deplete the channel 24 in the entire source-drain spacing. For example, an external bias applies the same potential to the low conducting element 42 as that at the gate electrode 20 .
- the depletion 25 extends under the low conducting element 42 as illustrated by the arrows in FIG. 11B .
- the depletion 25 can significantly reduce an internal capacitance of the HFET 40 when it is in the off state.
- a low conducting field-controlling element 42 with a lateral and/or sheet resistance designed as described herein, can have a minimal effect on a source-drain coupling of the HFET 40 in the off state.
- FIG. 12 shows experimental insertion loss and isolation characteristics of a prior art RF switch (labeled Conventional in FIG. 12 ) and an RF switch made using an HFET according to an embodiment (labeled LC-FC in FIG. 12 ).
- identical geometry prior art HFET and low conducting element HFET RF switches were fabricated and their corresponding insertion loss and isolation were compared.
- the low conducting element was formed by a MOCVD deposited InGaN film as shown in FIGS. 11A , 11 B.
- the insertion loss and isolation frequency dependencies for the resulting single-pole-double-throw (SPDT) RF switches are illustrated in FIG. 12 . As illustrated, at an operating frequency of approximately six gigahertz, nearly a two-fold decrease in the insertion loss and approximately a six decibel increase in the isolation were obtained for the low conducting element HFET RF switch.
- SPDT single-pole-double-throw
- FIG. 13 shows an illustrative device 44 according to a sixth embodiment.
- Device 44 includes a pair of low conducting field-controlling elements 46 A, 46 B, each of which is located adjacent to a corresponding source electrode 18 A and drain electrode 18 B, respectively.
- the field-controlling elements 46 A, 46 B are isolated from the respective electrodes 18 A, 18 B and the semiconductor structure by an isolation layer 26 (e.g., a dielectric layer), which also extends beneath the gate 20 .
- the isolation enables the application of external bias voltages and/or signals to the low conducting elements 46 A, 46 B via connectors V S1 , V D1 , respectively.
- the external bias voltages and/or signals can be independent from external voltages/signals applied to the corresponding electrodes 18 A, 18 B via connectors V S , V D .
- the field-controlling elements 46 A, 46 B are used to provide voltage controlled changes in a conductance of the device channel 24 .
- a voltage bias at a field-controlling element 46 A, 46 B that is positive with respect to a voltage potential of the channel 24 a two-dimensional electron gas (2DEG) accumulation can be achieved in the corresponding access region without affecting the electron concentration, and therefore the threshold voltage, under the gate 20 .
- 2DEG two-dimensional electron gas
- the field-controlling elements 46 A, 46 B allow for direct control of the conductivity of the access regions without requiring gate recessing, selective doping, material regrowth, and/or the like.
- a device heterostructure can be formed using any solution, e.g., by obtaining (e.g., forming, preparing, acquiring, and/or the like) a substrate 12 , forming (e.g., growing, depositing, adhering, and/or the like) an initiation layer 13 and/or a buffer layer 15 thereon, forming an active layer 14 thereon, and forming a barrier layer 16 on the active layer 14 .
- metal electrode(s), dielectric layer(s), and/or the like can be formed on the device heterostructure using any solution.
- the manufacture of the device can include the formation of one or more low conducting field-controlling elements using any solution. It is understood that the manufacture of a device described herein can include additional processing, including for example: the deposition and removal of a temporary layer, such as mask layer; the patterning one or more layers; the formation of one or more additional layers/contacts not shown; application to a submount (e.g., via contact pads); and/or the like.
- additional processing including for example: the deposition and removal of a temporary layer, such as mask layer; the patterning one or more layers; the formation of one or more additional layers/contacts not shown; application to a submount (e.g., via contact pads); and/or the like.
- the invention provides a method of designing and/or fabricating a circuit that includes one or more of the semiconductor devices designed and fabricated as described herein.
- FIG. 14 shows an illustrative flow diagram for fabricating a circuit 126 according to an embodiment.
- a user can utilize a device design system 110 to generate a device design 112 for a semiconductor device as described herein.
- the device design 112 can comprise program code, which can be used by a device fabrication system 114 to generate a set of physical devices 116 according to the features defined by the device design 112 .
- the device design 112 can be provided to a circuit design system 120 (e.g., as an available component for use in circuits), which a user can utilize to generate a circuit design 122 (e.g., by connecting one or more inputs and outputs to various devices included in a circuit).
- the circuit design 122 can comprise program code that includes a device designed as described herein.
- the circuit design 122 and/or one or more physical devices 116 can be provided to a circuit fabrication system 124 , which can generate a physical circuit 126 according to the circuit design 122 .
- the physical circuit 126 can include one or more devices 116 designed as described herein.
- the invention provides a device design system 110 for designing and/or a device fabrication system 114 for fabricating a semiconductor device 116 as described herein.
- the system 110 , 114 can comprise a general purpose computing device, which is programmed to implement a method of designing and/or fabricating the semiconductor device 116 as described herein.
- an embodiment of the invention provides a circuit design system 120 for designing and/or a circuit fabrication system 124 for fabricating a circuit 126 that includes at least one device 116 designed and/or fabricated as described herein.
- the system 120 , 124 can comprise a general purpose computing device, which is programmed to implement a method of designing and/or fabricating the circuit 126 including at least one semiconductor device 116 as described herein.
- the invention provides a computer program fixed in at least one computer-readable medium, which when executed, enables a computer system to implement a method of designing and/or fabricating a semiconductor device as described herein.
- the computer program can enable the device design system 110 to generate the device design 112 as described herein.
- the computer-readable medium includes program code, which implements some or all of a process described herein when executed by the computer system. It is understood that the term “computer-readable medium” comprises one or more of any type of tangible medium of expression, now known or later developed, from which a stored copy of the program code can be perceived, reproduced, or otherwise communicated by a computing device.
- the invention provides a method of providing a copy of program code, which implements some or all of a process described herein when executed by a computer system.
- a computer system can process a copy of the program code to generate and transmit, for reception at a second, distinct location, a set of data signals that has one or more of its characteristics set and/or changed in such a manner as to encode a copy of the program code in the set of data signals.
- an embodiment of the invention provides a method of acquiring a copy of program code that implements some or all of a process described herein, which includes a computer system receiving the set of data signals described herein, and translating the set of data signals into a copy of the computer program fixed in at least one computer-readable medium. In either case, the set of data signals can be transmitted/received using any type of communications link.
- the invention provides a method of generating a device design system 110 for designing and/or a device fabrication system 114 for fabricating a semiconductor device as described herein.
- a computer system can be obtained (e.g., created, maintained, made available, etc.) and one or more components for performing a process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer system.
- the deployment can comprise one or more of: (1) installing program code on a computing device; (2) adding one or more computing and/or I/O devices to the computer system; (3) incorporating and/or modifying the computer system to enable it to perform a process described herein; and/or the like.
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Abstract
A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.
Description
- The current application claims the benefit of co-pending U.S. Provisional Application No. 61/531,585, titled “Semiconductor device with low-conducting field-controlling electrodes,” which was filed on 6 Sep. 2011, and which is hereby incorporated by reference. Aspects of the invention also are related to U.S. patent application Ser. No. 13/396,059, titled “Semiconductor device with low-conducting field-controlling element,” which was filed on 14 Feb. 2012, which is hereby incorporated by reference.
- The disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including one or more low conducting field-controlling elements.
- Typically, a semiconductor device is biased at Direct Current (DC) and/or modulated at relatively low frequencies, for example, below ten megahertz (MHz). Concurrently, the device can generate, amplify, and/or manipulate signals at much higher frequencies (for example, above one gigahertz (GHz)). A requirement for optimizing the device design at DC and low frequencies, on one hand, and at high frequencies are clashing and difficult or impossible to satisfy simultaneously. For example,
FIG. 1 shows an illustrative heterostructure field effect transistor (HFET) 2A according to the prior art, which can be operated as a switch. When implemented in circuits such as power converters, the device dynamic on-resistance of theHFET 2A should be minimized. As a result, it is desirable to minimize a total channel length between the source electrode S and drain electrode D (e.g., the sum of the distances LGS, LG, and LGD). However, in order for theHFET 2A to withstand high voltage levels without breakdown, the distance, LGD, between the gate electrode G and the drain electrode D must be sufficiently large, since most of the external voltage drop will occur between these two electrodes. Therefore, the requirements for large breakdown voltage and low on resistance are clashing. -
FIG. 2 shows analternative HFET 2B, which illustrates one approach to address the breakdown problem, according to the prior art. HFET 2B includes a dielectric 3A, 3B deposited in the gate-source and gate-drain spacing and a field-modulating plate (FP). While the field-modulating plate FP is shown connected to the gate electrode G, other approaches connect one or several field-modulating plates FP to the source electrode S, drain electrode D, and/or the gate electrode G. Regardless, the field-modulating plate FP decreases a peak field near the electrode edge by splitting it into two or more peaks, thereby increasing the breakdown voltage of theHFET 2B. However, the field-modulating plate FP increases the inter-electrode and electrode-semiconductor capacitances, and thus decreases a maximum operating frequency for theHFET 2B. -
FIGS. 3A and 3B show anillustrative HFET 2C in the on state and the off state, respectively, when being operated as a radio frequency (RF) switch according to the prior art. In the on state illustrated inFIG. 3A , a conductingchannel 4 exists between the source electrode S and the drain electrode D. To turn theHFET 2C off, a corresponding bias is applied at the gate electrode G, which removes the channel under the gate electrode G thereby disconnecting the drain electrode D from the source electrode S. However, this disconnection is only true at low frequencies. At high frequencies as illustrated inFIG. 3B , a capacitive coupling is present between the source and drain sides of the channel which reduces a maximum operating frequency for theHFET 2C. If thechannel 4 had been fully depleted in the entire source—drain spacing, the device capacitance would be lower and the maximum operating frequency would be higher. - In light of the above, the inventors recognize that a solution providing, for example, increased (e.g., full) control over the electric field distribution in the gate-drain spacing can result in significant improvement of the high voltage and high frequency (e.g., microwave) characteristics of a field effect transistor. For example, embodiments of the invention can provide a semiconductor device with an increased frequency range, an increased operating voltage, and/or an increased maximum power compared to semiconductor devices of the prior art. Aspects of the invention provide a semiconductor device including a low conducting field-controlling element. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device. The field-controlling element can behave similar to a metal electrode at direct current and/or low frequencies. However, within the device operating frequency range, the field-controlling element can behave similar to an insulator.
- A first aspect of the invention provides a device comprising: a semiconductor including an active region; a set of contacts to the active region; and a field-controlling element located on a first side of the active region, wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.
- A second aspect of the invention provides a field-effect transistor comprising: a source contact, a drain contact, and a device channel there between; a gate located on a first side of the device channel; and a low conducting field-controlling element located on the first side of the device channel, wherein the field-controlling element is coupled to at least one of: the source contact, the drain contact, or the gate and wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.
- A third aspect of the invention provides a method comprising: designing a semiconductor device including an active region, a set of contacts to the active region, and a field-controlling element located on a first side of the active region, wherein the designing includes: determining a target minimal operating frequency of the device and a target maximum control frequency of the device; determining a target lateral resistance for the field-controlling element such that the target lateral resistance is both larger than an inverse of the target minimal operating frequency and smaller than an inverse of the target maximum control frequency; and designing the field-controlling element based on the target lateral resistance.
- The illustrative aspects of the invention are designed to solve one or more of the problems herein described and/or one or more other problems not discussed.
- These and other features of the disclosure will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various aspects of the invention.
-
FIG. 1 shows an illustrative heterostructure field effect transistor (HFET) according to the prior art. -
FIG. 2 shows an alternative HFET according to the prior art. -
FIGS. 3A and 3B show an illustrative HFET in the on state and the off state, respectively, when being operated as a radio frequency switch according to the prior art. -
FIG. 4 shows an illustrative semiconductor device according to a first embodiment. -
FIG. 5 shows a schematic comparison of electric field profiles in the gate-drain spacing of various HFETs according to an embodiment. -
FIG. 6 shows experimental breakdown voltage characteristics of a conventional HFET and an HFET including a field-controlling electrode according to an embodiment. -
FIG. 7 shows an illustrative device according to a second embodiment. -
FIG. 8 shows an illustrative device according to a third embodiment. -
FIG. 9 shows an illustrative device according to a fourth embodiment. -
FIG. 10 shows an illustrative device according to a fifth embodiment. -
FIGS. 11A and 11B show an illustrative HFET configured to operate as a radio frequency (RF) switch according to an embodiment. -
FIG. 12 shows experimental insertion loss and isolation characteristics of a prior art RF switch and an RF switch made using an HFET according to an embodiment. -
FIG. 13 shows an illustrative device according to a sixth embodiment. -
FIG. 14 shows an illustrative flow diagram for fabricating a circuit according to an embodiment. - It is noted that the drawings may not be to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
- As indicated above, aspects of the invention provide a semiconductor device including a low conducting field-controlling element. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device. The field-controlling element can behave similar to a metal electrode at direct current and/or low frequencies. However, within the device operating frequency range, the field-controlling element can behave similar to an insulator. In an embodiment, the field-controlling element can be configured to increase a frequency range, an operating voltage, a maximum power, and/or the like, for operating the corresponding semiconductor device. As used herein, unless otherwise noted, the term “set” means one or more (i.e., at least one) and the phrase “any solution” means any now known or later developed solution.
- Returning to the drawings,
FIG. 4 shows anillustrative semiconductor device 10 according to a first embodiment. Thedevice 10 is shown including asubstrate 12, aninitiation layer 13, abuffer layer 15, anactive layer 14, abarrier layer 16, asource contact 18A, adrain contact 18B, and agate 20, each of which can be manufactured and fabricated using any solution. Thesubstrate 12 can be formed of any of various types of compound semiconductor or dielectric materials, including for example, sapphire, diamond, germanium (Ge), gallium nitride (GaN), silicon, silicon carbide (SiC), gallium arsenic (GaAs), and/or the like. Furthermore, thesubstrate 12 can comprise a conducting and/or semiconducting substrate. - As illustrated, an
initiation layer 13 and abuffer layer 15 can be located between thesubstrate 12 and theactive layer 14. However, it is understood that this is only illustrative of various possible configurations, each of which can include or not include theinitiation layer 13 and/or thebuffer layer 15. Regardless, the heterostructure of thedevice 10 can include various layers made from any of a plurality of materials systems. Furthermore, one or more of the layers in a heterostructure described herein can include one or more attributes to alleviate strain. For example, a layer can be formed of a superlattice structure. - In an embodiment, the
substrate 12 is formed of SiC, theactive layer 14 is formed of gallium nitride (GaN), and thebarrier layer 16 is formed of aluminum gallium nitride (AlGaN). However, it is understood that this is only illustrative of various possible group III nitride based devices. To this extent, layers 13, 14, 15, 16 can be formed of any combination of various types of group III nitride materials comprising one or more group III elements (e.g., boron (B), aluminum (Al), gallium (Ga), and indium (In)) and nitrogen (N), such that BWAlXGaYInZN, where 0≦W, X, Y, Z≦1, and W+X+Y+Z=1. Illustrative group III nitride materials include AlN, GaN, InN, BN, AlGaN, AlInN, AlBN, InGaN, AlGaInN, AlGaBN, AlInBN, and AlGaInBN with any molar fraction of group III elements. Furthermore, it is understood that thedevice 10 can be formed from other semiconductor materials, including other types of group III-V materials, such as such as GaAs, GaAlAs, InGaAs, indium phosphorus (InP), and/or the like. - Additionally, the
device 10 includes a low conducting field-controllingelement 22, which is located in the region between thegate 20 and thedrain contact 18B of the device 10 (gate-drain region). However, it is understood that a device can include one or more field-controllingelements 22 located in any combination of one or more of: the gate-source region; the gate-drain region; source-drain region; and/or the like. Furthermore, a device can include a field-controllingelement 22 that forms an additional contact or passivation layer. To this extent, a field-controllingelement 22 with low surface conductivity as described herein can be used in addition to or instead of regular metal electrodes. - The field-controlling
element 22 can be formed of a layer of low conducting material. The low conducting material can have a surface resistance that is significantly higher than that of metal electrodes, but is also much lower than that of a dielectric material. Similarly, the low conducting material can have a surface conductivity that is significantly lower than that of metal electrodes, but is also much higher than that of a dielectric material. As a result, the associated characteristic charging-recharging time of the field-controllingelement 22 is much higher than that of metal electrodes. To this extent, during operation of thedevice 10 at DC or low frequencies (e.g., below 10 megahertz (MHz)), typically used for pulse or sinusoidal modulation, the field-controllingelement 22 will behave similar to metal electrodes. However, during operation of thedevice 10 at high (signal) frequencies, (e.g., typically exceeding 100 MHz) the field-controllingelement 22 will behave similar to an insulator, thereby not deteriorating the device frequency performance. Illustrative low conducting materials include, for example: InGaN; a semiconductor; a low conducting dielectric single crystal; a textured, poly-crystalline or amorphous material; a semimetal material; oxides of nickel and other metals, and/or the like. - Aspects of the invention are shown and described primarily with reference to a heterostructure field effect transistor. However, it is understood that the low conducting field-controlling
element 22 can be implemented in various types of field-effect transistors, including, for example, a field-effect transistor, a heterostructure field-effect transistor, an insulated gate field-effect transistor, an insulated gate heterostructure field-effect transistor, a multiple heterostructure field-effect transistor, a multiple heterostructure insulated gate field-effect transistor, an inverted field-effect transistor, an inverted heterostructure field-effect transistor, an inverted insulated gate field-effect transistor, an inverted insulated gate heterostructure field-effect transistor, an inverted multiple heterostructure field-effect transistor, an inverted insulated gate multiple heterostructure field-effect transistor, and/or the like. Additionally, the low conducting field-controlling element can be implemented in other types of semiconductor devices, including for example, a diode of any type, a semiconductor resistor, a semiconductor sensor, a light emitting diode, a laser, an integrated element, and/or the like. - As described herein, in an embodiment, it is desired for the low conducting field-controlling
element 22 to act as a conductor (e.g., electrode) when thedevice 10 is operating at low frequencies, and act as a dielectric when thedevice 10 is operating within a target device operating frequency range (high frequencies). In this case, the field-controllingelement 22 makes a minor increase in the total electrode area and, as a result, in the device capacitance. In an embodiment, the design and configuration of the field-controllingelement 22 accounts for the frequency response for the resultingdevice 10. For example, contrary to other approaches, the design and configuration of the field-controllingelement 22 identifies a range of acceptable lateral and/or sheet resistances and/or a target lateral and/or sheet resistance for a set of field-controllingelements 22 included in adevice 10 based on a target operating frequency (e.g., a minimal operating frequency), a target control frequency (e.g., a maximum control frequency), and/or the like. The following discussion provides a theoretical basis for determining an illustrative set of attributes of thedevice 10 and the low conducting field-controllingelement 22 as currently understood by the inventors. - In order for the field-controlling
element 22 to not significantly affect a radio frequency (RF) impedance of thedevice 10, a corresponding time constant for the field-controllingelement 22, τFC, must be much larger than 1/(2πf), where f is the operating frequency for thedevice 10. The time constant for the field-controllingelement 22 can be expressed as τFC=RFCCFC, where RFC is the lateral resistance of the field-controllingelement 22 measured in a direction of the current flow in thedevice 10 along the low conducting layer surface of the field-controllingelement 22 and CFC is the total capacitance between the field-controllingelement 22 and thedevice channel 24. This yields the following condition: -
τFC =R FC C FC>>1/(2πf) (1) - Assuming τFC is at least approximately six times (2π times) greater than 1/(2πf), the condition (1) can be rewritten as:
-
τFC =R FC C FC>1/f (2) - As used herein, the lateral resistance of the field-controlling
element 22, RFC, is related to the low conducting layer sheet resistance, RLCSH, as: -
R FC =R LCSH *L/W (2a) - where L and W are the length and width, respectively, of the field-controlling
element 22 with respect to a direction of the current flow in thedevice 10. - Furthermore, the field-controlling
element 22 should be sufficiently fast to allow for pulsed modulation of a bias applied to thegate 20 of thedevice 10. Assuming a control frequency, fC, and following the derivation that led to condition (2) above, the required τFC also should meet the following condition: -
τFC<1/f C (3) - As an example, for practical purposes and material selection, in order to meet both conditions (2) and (3), the value of the τFC can be selected as follows:
-
τFC=1/(f×f C)1/2 (4) - As an illustrative example, assume a field effect transistor has the following attributes: a source to drain distance, L=5 μm; a gate-channel separation (also equal to the field-controlling element-channel separation), d=20 nm; a channel width, W=1 mm; a relative dielectric permittivity of the material between the field-controlling
element 22 and thechannel 24, εr=9; an operating frequency, f=21 GHz; and a control frequency, fc=10 MHz. The field-controlling element-channel capacitance can be calculated as, C=ε0εrL*W/d≈20 pF, where ε0 is vacuum permittivity. Using equation (4) above, a value for the time constant for the field-controllingelement 22 can be calculated as, τFC≈7.1 ns. From equation (2), the field-controlling element resistance RFC=τFC/CFC. The corresponding sheet resistance of the low conducting layer forming the field-controllingelement 22 from equation (1a) is RLCSH=RFC*W/L≈71 kΩ/sq. Assuming a thickness of the low conducting layer of material forming the field-controllingelement 22, dLC, of approximately 100 nm, yields a low conducting layer resistivity, ρ=RLCSH×dLC=7×10−3 Ω×m. - In an embodiment, inclusion of the field-controlling
element 22 in the gate-drain spacing as shown inFIG. 4 can substantially reduce/remove the electric field nonuniformity in the gate-drain spacing, thereby increasing the breakdown voltage of thedevice 10 over those of the prior art. At high frequencies, the field-controllingelement 22 with a sheet and/or lateral resistance designed as described herein, behaves as an insulator and therefore does not increase or leads to a very minor increase in the capacitance of thedevice 10. - To this extent,
FIG. 5 shows a schematic comparison of electric field profiles in the gate-drain spacing of various devices according to an embodiment. In particular,FIG. 5 includes: an electric field profile corresponding to theHFET 2A ofFIG. 1 (identified as HFET); an electric field profile corresponding to theHFET 2B ofFIG. 2 (identified as FP HFET); and an electric field profile corresponding to thedevice 10 ofFIG. 4 (identified as LC-FC HFET). As illustrated, the electric field of thedevice 10 is significantly more uniform over the gate-drain spacing than that of eitherHFET 2A orHFET 2B. - Such a uniform electric field profile can result in a highest achievable breakdown voltage for a given gate-drain spacing. To this extent,
FIG. 6 shows experimental breakdown voltage characteristics of aconventional HFET 2A (FIG. 1 , labeled as HFET inFIG. 6 ) and adevice 10 including the field-controllingelement 22 according to an embodiment (labeled as LC-FC HFET inFIG. 6 ). As a proof of concept, identical geometryprior art HFET 2A and devices 10 (LC-FC HFETs) were fabricated, and the corresponding breakdown voltages compared. The field-controllingelement 22 for thedevice 10 was formed by a Metallo Organic Chemical Vapor Deposition (MOCVD) deposited InGaN film. As illustrated inFIG. 6 , thedevice 10 had more than a two-fold increase in breakdown voltage as compared to the breakdown voltage of theHFET 2A. - While the device 10 (
FIG. 4 ) is shown including a field-controllingelement 22 comprising a surface layer of low conducting material located within the gate-drain spacing of the device, it is understood that a device according to an embodiment can include one or more field-controlling elements located in various locations of the device depending on the desired function. To this extent, an embodiment of a device can include a field-controlling element comprising a surface layer located in the gate-source spacing of the device. Furthermore, the field-controlling element can form an additional contact or passivation layer, form a strain relieving layer, replace a metal electrode, be buried/grown in the epitaxial structure, and/or the like. Regardless, in each case and in the additional embodiments described herein, the field-controlling element can be formed of a low conducting material. - For example,
FIG. 7 shows anillustrative device 30 according to a second embodiment.Device 30 is shown including a set of low conducting field-controlling elements 22A, 22B, each of which comprises a surface layer of low conducting material located in the source-gate spacing and gate-drain spacing of thedevice 30, respectively. In an embodiment, the set of field-controlling elements 22A, 22B comprise a single, unitary surface layer, which can completely extend across (cover) the source-drain spacing or only partially cover the source-drain spacing. When partially covering a spacing, the set of field-controlling elements 22A, 22B can be contacting only thegate electrode 20, one or more of thedevice electrodes device electrodes device 30 includes anisolation layer 26, which can be formed of a dielectric material, a semiconductor material, and/or the like, and can have a sheet resistance at least one order of magnitude higher than that of the field-controlling elements 22A, 22B. To this extent, theisolation layer 26 can partially or fully isolate the field-controlling elements 22A, 22B and thegate 20 from the semiconductor structure, thereby reducing any additional capacitance to thechannel 24 provided by the field-controlling elements 22A, 22B. During operation of thedevice 30, the set of field-controlling elements 22A, 22B can serve as a conduction path to remove trapped charges, and therefore reduce the gate and/or drain lags, which can be observed in group III nitride HFETs and other types of devices. -
FIG. 8 shows anillustrative device 32 according to a third embodiment. Thedevice 32 includes a set of isolation layers 26A, 26B located in both the source-gate and gate-drain spacings, respectively. Furthermore, thedevice 32 includes a low conducting field-controllingelement 22, which forms a field-modulating plate connected to thegate 20. To this extent, the isolation layers 26A, 26B can partially or fully isolate the field-controllingelement 22 from the semiconductor structure. In this case, unlike the field plate FP (FIG. 2 ) of the prior art, the field-controllingelement 22 does not form any significant additional capacitance to thedrain electrode 18B or thechannel 24, and therefore does not deteriorate the frequency performance of thedevice 32. -
FIG. 9 shows anillustrative device 34 according to a fourth embodiment. In this case, thedevice 34 includes a first field-controllingelement 28A connected to thegate electrode 20, and a second field-controllingelement 28B connected to thesource electrode 18A. Anisolation layer 26 encapsulates thegate 20 and the first field-controllingelement 28A, thereby isolating the second field-controllingelement 28B from thegate 20 and the first field-controllingelement 28A. In an embodiment, at least one of the first field-controllingelement 28A or the second field-controllingelement 28B is formed of a low conducting layer of material as described herein while one of theelements -
FIG. 10 shows anillustrative device 36 according to a fifth embodiment. In this case, thedevice 36 is configured similar to thedevice 34 ofFIG. 9 , but also includes a third field-controllingelement 28C connected to thedrain electrode 18B. Additionally, theisolation layer 26 is extended over the second field-controllingelement 28B, thereby isolating the third field-controllingelement 28C from the second field-controllingelement 28B. In this case, one or more of the field-controllingelements 28A-28C can be formed of a low conducting layer of material, while at most two of the field-controllingelements 28A-28C can be formed of metal. As discussed herein, in eitherdevice elements 28A-28C can be made of metal. It is understood that a particular configuration of field-controllingelements 28A-28C formed of a low conducting layer of material and/or metal, if included, can be selected based on a particular set of device requirements and/or operating frequencies. -
FIGS. 11A and 11B show anillustrative HFET 40 configured to operate as a radio frequency (RF) switch in the on and off states, respectively, according to an embodiment.HFET 40 includes a low conducting field-controllingelement 42 located within the source-drain spacing. Similar to the device 30 (FIG. 7 ), the field-controllingelement 42 ofHFET 40 can be electrically connected to thegate electrode 20 and partially or entirely cover the source-drain spacing. In this configuration, the field-controllingelement 42 can be used to deplete thechannel 24 in the entire source-drain spacing. For example, an external bias applies the same potential to thelow conducting element 42 as that at thegate electrode 20. As a result, when thechannel 24 is depleted under thegate electrode 20, thedepletion 25 extends under thelow conducting element 42 as illustrated by the arrows inFIG. 11B . Thedepletion 25 can significantly reduce an internal capacitance of theHFET 40 when it is in the off state. A low conducting field-controllingelement 42 with a lateral and/or sheet resistance designed as described herein, can have a minimal effect on a source-drain coupling of theHFET 40 in the off state. -
FIG. 12 shows experimental insertion loss and isolation characteristics of a prior art RF switch (labeled Conventional inFIG. 12 ) and an RF switch made using an HFET according to an embodiment (labeled LC-FC inFIG. 12 ). In particular, identical geometry prior art HFET and low conducting element HFET RF switches were fabricated and their corresponding insertion loss and isolation were compared. The low conducting element was formed by a MOCVD deposited InGaN film as shown inFIGS. 11A , 11B. The insertion loss and isolation frequency dependencies for the resulting single-pole-double-throw (SPDT) RF switches are illustrated inFIG. 12 . As illustrated, at an operating frequency of approximately six gigahertz, nearly a two-fold decrease in the insertion loss and approximately a six decibel increase in the isolation were obtained for the low conducting element HFET RF switch. -
FIG. 13 shows anillustrative device 44 according to a sixth embodiment.Device 44 includes a pair of low conducting field-controllingelements corresponding source electrode 18A anddrain electrode 18B, respectively. The field-controllingelements respective electrodes gate 20. The isolation enables the application of external bias voltages and/or signals to thelow conducting elements electrodes - In an embodiment, the field-controlling
elements device channel 24. For example, by applying a voltage bias at a field-controllingelement channel 24, a two-dimensional electron gas (2DEG) accumulation can be achieved in the corresponding access region without affecting the electron concentration, and therefore the threshold voltage, under thegate 20. Such a configuration can be beneficial, for example, in a high frequency and high transconductance device, particularly one with asubmicron gate 20, where a resistance of the access regions has a very different can have a significant effect on a maximum frequency of operation of the device. To this extent, the highest electron concentration in the access regions is desirable, however, selective doping of the source-gate and gate-drain can be difficult to achieve. The field-controllingelements - It is understood that the various semiconductor devices described herein can be manufactured using any solution. For example, a device heterostructure can be formed using any solution, e.g., by obtaining (e.g., forming, preparing, acquiring, and/or the like) a
substrate 12, forming (e.g., growing, depositing, adhering, and/or the like) aninitiation layer 13 and/or abuffer layer 15 thereon, forming anactive layer 14 thereon, and forming abarrier layer 16 on theactive layer 14. Additionally, metal electrode(s), dielectric layer(s), and/or the like, can be formed on the device heterostructure using any solution. Furthermore, as described herein, the manufacture of the device can include the formation of one or more low conducting field-controlling elements using any solution. It is understood that the manufacture of a device described herein can include additional processing, including for example: the deposition and removal of a temporary layer, such as mask layer; the patterning one or more layers; the formation of one or more additional layers/contacts not shown; application to a submount (e.g., via contact pads); and/or the like. - While shown and described herein as a method of designing and/or fabricating a semiconductor device, it is understood that aspects of the invention further provide various alternative embodiments. For example, in one embodiment, the invention provides a method of designing and/or fabricating a circuit that includes one or more of the semiconductor devices designed and fabricated as described herein.
- To this extent,
FIG. 14 shows an illustrative flow diagram for fabricating acircuit 126 according to an embodiment. Initially, a user can utilize adevice design system 110 to generate adevice design 112 for a semiconductor device as described herein. Thedevice design 112 can comprise program code, which can be used by adevice fabrication system 114 to generate a set ofphysical devices 116 according to the features defined by thedevice design 112. Similarly, thedevice design 112 can be provided to a circuit design system 120 (e.g., as an available component for use in circuits), which a user can utilize to generate a circuit design 122 (e.g., by connecting one or more inputs and outputs to various devices included in a circuit). Thecircuit design 122 can comprise program code that includes a device designed as described herein. In any event, thecircuit design 122 and/or one or morephysical devices 116 can be provided to acircuit fabrication system 124, which can generate aphysical circuit 126 according to thecircuit design 122. Thephysical circuit 126 can include one ormore devices 116 designed as described herein. - In another embodiment, the invention provides a
device design system 110 for designing and/or adevice fabrication system 114 for fabricating asemiconductor device 116 as described herein. In this case, thesystem semiconductor device 116 as described herein. Similarly, an embodiment of the invention provides acircuit design system 120 for designing and/or acircuit fabrication system 124 for fabricating acircuit 126 that includes at least onedevice 116 designed and/or fabricated as described herein. In this case, thesystem circuit 126 including at least onesemiconductor device 116 as described herein. - In still another embodiment, the invention provides a computer program fixed in at least one computer-readable medium, which when executed, enables a computer system to implement a method of designing and/or fabricating a semiconductor device as described herein. For example, the computer program can enable the
device design system 110 to generate thedevice design 112 as described herein. To this extent, the computer-readable medium includes program code, which implements some or all of a process described herein when executed by the computer system. It is understood that the term “computer-readable medium” comprises one or more of any type of tangible medium of expression, now known or later developed, from which a stored copy of the program code can be perceived, reproduced, or otherwise communicated by a computing device. - In another embodiment, the invention provides a method of providing a copy of program code, which implements some or all of a process described herein when executed by a computer system. In this case, a computer system can process a copy of the program code to generate and transmit, for reception at a second, distinct location, a set of data signals that has one or more of its characteristics set and/or changed in such a manner as to encode a copy of the program code in the set of data signals. Similarly, an embodiment of the invention provides a method of acquiring a copy of program code that implements some or all of a process described herein, which includes a computer system receiving the set of data signals described herein, and translating the set of data signals into a copy of the computer program fixed in at least one computer-readable medium. In either case, the set of data signals can be transmitted/received using any type of communications link.
- In still another embodiment, the invention provides a method of generating a
device design system 110 for designing and/or adevice fabrication system 114 for fabricating a semiconductor device as described herein. In this case, a computer system can be obtained (e.g., created, maintained, made available, etc.) and one or more components for performing a process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer system. To this extent, the deployment can comprise one or more of: (1) installing program code on a computing device; (2) adding one or more computing and/or I/O devices to the computer system; (3) incorporating and/or modifying the computer system to enable it to perform a process described herein; and/or the like. - The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to an individual in the art are included within the scope of the invention as defined by the accompanying claims.
Claims (20)
1. A device comprising:
a semiconductor including an active region;
a set of contacts to the active region; and
a field-controlling element located on a first side of the active region, wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.
2. The device of claim 1 , wherein the field-controlling element is formed of one of: a semiconductor material; a semimetal material; or a dielectric material.
3. The device of claim 1 , wherein the device includes a set of field-controlling elements, and wherein the set of field-controlling elements covers substantially all of an area corresponding to the active region.
4. The device of claim 1 , wherein the field-controlling element is electrically coupled to the at least one of the set of contacts.
5. The device of claim 1 , wherein the field-controlling element is capacitively coupled to the at least one of the set of contacts.
6. The device of claim 1 , wherein the field-controlling element is a layer located in an epitaxial structure of the device within one micrometer from the active region.
7. The device of claim 1 , wherein the device is configured to operate as a field effect transistor.
8. The device of claim 1 , wherein the field-controlling element is at least partially isolated from the semiconductor by an isolation layer having a sheet resistance at least an order of magnitude higher than a sheet resistance of the field-controlling element.
9. The device of claim 1 , further comprising a connector for applying at least one of: an external bias or an external signal to the field-controlling element.
10. The device of claim 1 , wherein the field-controlling element forms a field-modulating plate for the at least one of the set of contacts.
11. The device of claim 1 , wherein the field-controlling element forms at least one of: a passivation layer or a strain relieving layer.
12. The device of claim 1 , wherein the semiconductor is formed of one of: silicon, silicon carbide, or a group III-V material.
13. The device of claim 1 , wherein the semiconductor is formed of a group III nitride material.
14. A field-effect transistor comprising:
a source contact, a drain contact, and a device channel there between;
a gate located on a first side of the device channel; and
a low conducting field-controlling element located on the first side of the device channel, wherein the field-controlling element is coupled to at least one of: the source contact, the drain contact, or the gate and wherein a lateral resistance of the field-controlling element is larger than an inverse of a minimal operating frequency of the device and the lateral resistance of the field-controlling element is smaller than an inverse of a maximum control frequency of the device.
15. The transistor of claim 14 , wherein the field-controlling element is a surface layer located between the gate and drain contact.
16. The transistor of claim 14 , wherein the field-controlling element is a surface layer located both between the source contact and the gate and between the gate and the drain contact.
17. The transistor of claim 14 , further comprising an insulating layer between the field-controlling element and the device channel, wherein the field-controlling element is attached to the gate and extends into an area between the gate and the drain.
18. The transistor of claim 14 , wherein the transistor includes a field-controlling plate for the gate and a field-controlling plate for at least one of: the source contact or the drain contact, and wherein at least one of the field-controlling plates is the field-controlling element.
19. The transistor of claim 14 , wherein the field-controlling element is capacitively coupled to the source contact, the transistor further comprising a second low conducting field-controlling element capacitively coupled to the drain contact.
20. A method comprising:
designing a semiconductor device including an active region, a set of contacts to the active region, and a field-controlling element located on a first side of the active region, wherein the designing includes:
determining a target minimal operating frequency of the device and a target maximum control frequency of the device;
determining a target lateral resistance for the field-controlling element such that the target lateral resistance is both larger than an inverse of the target minimal operating frequency and smaller than an inverse of the target maximum control frequency; and
designing the field-controlling element based on the target lateral resistance.
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US15/052,911 US9806184B2 (en) | 2011-09-06 | 2016-02-25 | Semiconductor device with low-conducting field-controlling element |
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WO2013036593A1 (en) | 2013-03-14 |
US20160181410A1 (en) | 2016-06-23 |
US9806184B2 (en) | 2017-10-31 |
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