US20120054464A1 - Single-port memory access control device - Google Patents
Single-port memory access control device Download PDFInfo
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- US20120054464A1 US20120054464A1 US13/221,587 US201113221587A US2012054464A1 US 20120054464 A1 US20120054464 A1 US 20120054464A1 US 201113221587 A US201113221587 A US 201113221587A US 2012054464 A1 US2012054464 A1 US 2012054464A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0038—System on Chip
Definitions
- the present disclosure generally relates to devices and methods for controlling accesses to memories, be they stand-alone memories or memories embedded in electronic circuits comprising other functions such as, for example, circuits for controlling digital data transmission networks or image processing circuits.
- the memory blocks have a single-port architecture.
- a single-port block can only perform one read operation or one write operation at the same time.
- This memory block architecture enables avoiding too complex memory architectures, or architectures consuming too much circuit surface area.
- a known solution to this problem is to use dual-port memories capable of performing two operations at the same time.
- the disadvantages of dual-port memories are their low densities and high access times. Such memories are thus poorly adapted to the storage of large data words.
- Another known solution to this problem is to use memory blocks performing operations at a clock frequency at least double that of the external circuit.
- a disadvantage of this solution is that memory blocks withstanding a high frequency must be available and that such blocks take up a large surface area.
- Another disadvantage of such a solution is that the circuit must be designed to be able to operate with several clock frequencies.
- Another known solution to this problem is to delay conflicting operations, such as a simultaneous reading from and writing into the same memory block.
- a disadvantage of this solution is that an additional memory space must be available to temporarily store the data to be written which have caused the conflict. To be protected against the worst case, for which each address of a memory block will be successively read, and then written, this additional memory space must have the same size as the initial memory.
- Another disadvantage of this solution is that the processing (writing) of the data stored in the additional memory space may block the access to the memory for a given time period.
- One embodiment of the present disclosure is a memory formed of a controller and several memory blocks overcoming all or part of the disadvantages of known devices.
- One embodiment can perform simultaneous operations in single-port memory blocks.
- each address of the memory comprising a first portion identifying a first block and a second portion identifying a same line in all blocks, and each first word of the third block identifying a free word among the second words sharing a same second address portion.
- the present disclosure also provides a method for controlling a memory comprising, in case of a simultaneous reading and writing, a step of comparison of first words.
- the present disclosure also provides a control method further comprising a step of reading from the third block identifying a block containing a free word, from among the second and fourth blocks.
- the present disclosure also provides a control method further comprising a step of updating the words contained in the first and third memory blocks.
- the present disclosure also provides a method for controlling a memory in which said comparison step is carried out before said reading step.
- the present disclosure also provides a method for controlling a memory in which, if the first words of said comparison step are equal, a word is written at a free address of one of the second and fourth blocks.
- FIG. 1 very schematically shows in the form of blocks an example of a device for managing the accesses to single-port memory blocks
- FIG. 2 illustrates, by means of blocks, an addressing architecture for the memory of FIG. 1 ;
- FIGS. 3 , 3 A, and 3 B illustrate, in the form of blocks, examples of read and write operations in a memory of the type of that in FIG. 2 ;
- FIG. 4 shows an example of a flowchart describing an embodiment of a chaining of the sequences executed by the memory according to an embodiment of the present disclosure.
- FIG. 1 shows in the form of blocks a memory 5 comprising:
- Controller 7 is, for example, connected to circuits performing the other functions by address and data buses 3 and 4 , to which one or several control buses are added. Controller 7 may also perform the address coding and decoding operations to access the banks and the tables.
- the number of data words in a bank and the number of address words in a table are identical.
- the first and third memory blocks 10 i , 12 for example, single-port memory blocks, cache memories, etc.
- Banks 14 i and 16 are formed of second and fourth single-port memory blocks.
- FIG. 2 is a more detailed representation of the memory blocks and an addressing architecture in memory 5 according to an embodiment of the present disclosure.
- Each first memory block 10 i including a set of address word locations 11 configured to respectively store the address words of the look-up table stored in the first memory block 10 i .
- Each second memory block 14 i includes a number of data word locations 15 , identical to the number of address word locations 11 in one of the memory blocks 10 i , that are configured to respectively store the data words of the second memory block 14 i .
- the third memory block 12 includes the same number of address word locations 13 as the address word locations 11 in each of the first memory blocks 10 i .
- the fourth memory block 16 includes the same number of data word locations 17 as the data word locations 15 in each of the banks 14 i.
- FIG. 2 shows each address word location 11 , 13 and data word location 15 , 17 as being a separate line of its memory block, but such an architecture is not required. However, the depiction in FIG. 2 allows one to immediately appreciate address and data words of same rank in the banks and the tables.
- the address of a data word stored in memory 5 and manipulated by other functions of the electronic circuit is formed of two portions 18 and 19 .
- This address will be designated hereafter as the external address (memory address).
- a first portion 18 identifies one of the first memory blocks 10 i .
- a second portion 19 identifies a same rank among memory blocks 10 i , 12 and banks 14 i and 16 .
- the data originating from portion 18 designates an address look-up table and the data originating from portion 19 designates a rank common to the address look-up tables and to the banks.
- the full address word thus defines the position of a data word in a bank 14 i or 16 .
- the addition of an additional memory block 16 provides an additional storage capacity having the size of a bank.
- the addition of additional address look-up table 12 enables to identify the number of the bank from among banks 14 i and 16 containing a free location (free word) for a given line.
- FIGS. 3 , 3 A, and 3 B illustrate an embodiment of the present disclosure with a memory formed of:
- Each of the banks and of the tables comprises five lines, respectively identified with addresses AD p , with p ranging between 1 and 5 (AD 1 to AD 5 ).
- FIGS. 3 and 3A describe an example of simultaneous read and write operations, with no bank collision, according to an embodiment of the present disclosure.
- FIG. 3 illustrates the operations affecting the banks.
- FIG. 3A illustrates the operations affecting the tables.
- step 100 Since bank B 2 resulting from step 100 is distinct from bank B 3 resulting from step 102 , the operations generate no collision.
- FIG. 3B illustrates, in relation with FIG. 3 , an example of simultaneous read and write operations, with a bank collision.
- FIG. 3B illustrates the operations affecting the tables.
- controller 7 The address coding and decoding, read, and write operations are performed by controller 7 .
- the third cycle may be systematically carried out, at the cost of an additional writing, sometimes unnecessary, to update the address look-up tables.
- table T FREE may be read from only if a collision is detected in the first cycle.
- FIG. 4 shows a flowchart describing an example of a sequence of steps executed by memory 5 to perform simultaneous operations.
- the type of operation (read, write) to be performed in memory 5 and the corresponding addresses are communicated thereto during steps 210 and 212 .
- steps 210 OPRD(T x , AD x )
- steps 212 OPWR(T y , AD y )
- memory 5 receives the order of simultaneously executing a read operation OPRD from table T x at address AD x and a write operation OPWR into table T y at address AD y .
- These operations and addresses are decoded by controller 7 to access tables 10 i , 12 and banks 14 i and 16 .
- the acquisition cycle takes place at steps 214 (OPRD(T x , AD x )->B x ; OPRD(T y , AD y )->B y ) and 218 (OPRD(T FREE , AD y )->B z ) to identify the numbers of the corresponding banks.
- table T x is read from at address AD x and B x is obtained.
- table T y is read from at address AD y and B y is obtained.
- Step 218 of reading from table T FREE at address AD y provides the number of the free bank B x (with Z ranging between 1 and 5) containing the location of a free data word (free word) for this address (free address).
- the execution cycle comprises a step 222 (OPRD(B x , AD x )) of reading a data word from bank B x at address AD X , and a step 224 (OPWR(B y , AD y )) of writing a data word into bank B y at address AD y .
- the process can then return to step 210 .
- the execution cycle comprises a data word reading step 232 (OPRD(B x , AD x )) identical to step 222 .
- a data word writing step 234 (OPWR(B Z , AD Y )) is performed into free bank B Z (obtained at step 218 ) at address AD Y .
- the address look-up table updating cycle enables, at a step 238 (B Z ->OPWR(T Y , AD Y )), to keep the new number of the bank where the data word previously described at step 234 is stored.
- the number of bank B X is thus written into table T Y at address AD Y .
- the new free bank number for address AD Y (B Y in this example) is written into table T Y .
- the process can then return to step 210 .
- the accesses to the tables may result in collisions. For example, simultaneous accesses to a same table in read and write mode will be impossible.
- a solution is to perform a write operation, followed by read operations on the other tables at the address of said read operation. An incomplete list of the bank numbers will be obtained. The set of bank numbers is finite and known, and the missing bank number can then easily be deduced therefrom. This missing bank number is the result of said read operation.
- the memory described in the above embodiment has the advantage of being seen as a dual-port memory while it keeps the advantage of the surface area of single-port memory blocks.
- Another advantage of the described embodiment is that it enables two simultaneous write operations if the designated banks and lines are different.
- Another advantage of the described embodiment is the absence of delayed conflicting operations to be processed subsequently.
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Abstract
Description
- 1. Technical Field
- The present disclosure generally relates to devices and methods for controlling accesses to memories, be they stand-alone memories or memories embedded in electronic circuits comprising other functions such as, for example, circuits for controlling digital data transmission networks or image processing circuits.
- 2. Description of the Related Art
- Generally, electronic circuits have a significant data storage capacity. Such a capacity is reached with large memories formed of several memory blocks for physical or logical reasons. For example, such memories are of SRAM (Static Random-Access Memory) or DRAM (Dynamic Access Memory) type only. A memory controller enables the other functions of the electronic circuit to see all the memory blocks as a single memory, in terms of address.
- Generally, the memory blocks have a single-port architecture. In other words, as seen from the other electronic circuit functions, a single-port block can only perform one read operation or one write operation at the same time. This memory block architecture enables avoiding too complex memory architectures, or architectures consuming too much circuit surface area. However, it may sometimes be desirable for some functions of the electronic circuit to simultaneously perform a read operation and a write operation, with no address constraint.
- A known solution to this problem is to use dual-port memories capable of performing two operations at the same time. The disadvantages of dual-port memories are their low densities and high access times. Such memories are thus poorly adapted to the storage of large data words.
- Another known solution to this problem is to use memory blocks performing operations at a clock frequency at least double that of the external circuit. A disadvantage of this solution is that memory blocks withstanding a high frequency must be available and that such blocks take up a large surface area. Another disadvantage of such a solution is that the circuit must be designed to be able to operate with several clock frequencies.
- Another known solution to this problem is to delay conflicting operations, such as a simultaneous reading from and writing into the same memory block. A disadvantage of this solution is that an additional memory space must be available to temporarily store the data to be written which have caused the conflict. To be protected against the worst case, for which each address of a memory block will be successively read, and then written, this additional memory space must have the same size as the initial memory. Another disadvantage of this solution is that the processing (writing) of the data stored in the additional memory space may block the access to the memory for a given time period.
- One embodiment of the present disclosure is a memory formed of a controller and several memory blocks overcoming all or part of the disadvantages of known devices.
- One embodiment can perform simultaneous operations in single-port memory blocks.
- One embodiment of the present disclosure provides a memory comprising:
-
- a set of first memory blocks of identical size, intended to contain first words,
- a set of second memory blocs of identical size, intended to contain second words, the number of second words being identical to the number of first words,
- a third memory block identical to the first blocks, and
- a fourth memory block identical to the second blocks,
- each address of the memory comprising a first portion identifying a first block and a second portion identifying a same line in all blocks, and each first word of the third block identifying a free word among the second words sharing a same second address portion.
- The present disclosure also provides a method for controlling a memory comprising, in case of a simultaneous reading and writing, a step of comparison of first words.
- The present disclosure also provides a control method further comprising a step of reading from the third block identifying a block containing a free word, from among the second and fourth blocks.
- The present disclosure also provides a control method further comprising a step of updating the words contained in the first and third memory blocks.
- The present disclosure also provides a method for controlling a memory in which said comparison step is carried out before said reading step.
- The present disclosure also provides a method for controlling a memory in which, if the first words of said comparison step are equal, a word is written at a free address of one of the second and fourth blocks.
- The foregoing and other features and advantages of the present disclosure will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
-
FIG. 1 very schematically shows in the form of blocks an example of a device for managing the accesses to single-port memory blocks; -
FIG. 2 illustrates, by means of blocks, an addressing architecture for the memory ofFIG. 1 ; -
FIGS. 3 , 3A, and 3B illustrate, in the form of blocks, examples of read and write operations in a memory of the type of that inFIG. 2 ; and -
FIG. 4 shows an example of a flowchart describing an embodiment of a chaining of the sequences executed by the memory according to an embodiment of the present disclosure. - The same elements have been designated with the same reference numerals in the different drawings, which have been drawn out of scale. For clarity, only those steps and elements which are useful to the understanding of the present disclosure have been shown and will be described.
-
FIG. 1 shows in the form of blocks a memory 5 comprising: -
- a controller 7 (CONTROLLER);
- a
set 10 of first memory blocks 10 i (with i ranging between 1 and N), of identical size, configured to store address look-up tables, respectively, each table containing address words; - a
set 14 of banks (second single-port memory blocks) 14 i (with i ranging from 1 to N), of identical size, each bank containing data words by a number identical to the number of address words of a corresponding one of the look-up tables; - a
third memory block 12, configured to store an additional address look-up table, identical to thefirst memory blocks 10 i; and - an additional bank 16 (fourth memory block) identical to
banks 14 i.
- Controller 7 is, for example, connected to circuits performing the other functions by address and
data buses 3 and 4, to which one or several control buses are added. Controller 7 may also perform the address coding and decoding operations to access the banks and the tables. - The number of data words in a bank and the number of address words in a table are identical.
- The first and third memory blocks 10 i, 12, for example, single-port memory blocks, cache memories, etc.
Banks -
FIG. 2 is a more detailed representation of the memory blocks and an addressing architecture in memory 5 according to an embodiment of the present disclosure. - Each
first memory block 10 i including a set ofaddress word locations 11 configured to respectively store the address words of the look-up table stored in thefirst memory block 10 i. Eachsecond memory block 14 i includes a number ofdata word locations 15, identical to the number ofaddress word locations 11 in one of thememory blocks 10 i, that are configured to respectively store the data words of thesecond memory block 14 i. Thethird memory block 12 includes the same number ofaddress word locations 13 as theaddress word locations 11 in each of thefirst memory blocks 10 i. Thefourth memory block 16 includes the same number ofdata word locations 17 as thedata word locations 15 in each of the banks 14 i. - It will be appreciated that the terms word, block, and banks are not intended to be limited to any particular size or type of memory. Also,
FIG. 2 shows eachaddress word location data word location FIG. 2 allows one to immediately appreciate address and data words of same rank in the banks and the tables. - The address of a data word stored in memory 5 and manipulated by other functions of the electronic circuit is formed of two
portions first portion 18 identifies one of the first memory blocks 10 i. Asecond portion 19 identifies a same rank among memory blocks 10 i, 12 andbanks portion 18 designates an address look-up table and the data originating fromportion 19 designates a rank common to the address look-up tables and to the banks. The full address word thus defines the position of a data word in abank - A large storage space accessible from the outside as a single memory, but actually formed of several blocks, for technical reasons, is desired to be formed. As seen from the outside, it is desired to have a memory standing simultaneous read and write operations, based on single-port blocks only.
- According to an embodiment of the present disclosure, the addition of an
additional memory block 16 provides an additional storage capacity having the size of a bank. The addition of additional address look-up table 12 enables to identify the number of the bank from amongbanks -
FIGS. 3 , 3A, and 3B illustrate an embodiment of the present disclosure with a memory formed of: -
- four
banks 14 x, with x ranging between 1 and 4 and arbitrarily identifying a bank (14 1 to 14 4 or B1 to B4); - four address tables T1 to T4 in memory blocks 10 y, with y ranging between 1 and 4 and arbitrarily identifying memory blocks 10 1 to 10 4;
- an additional bank 16 (BADD); and
- an additional address look-up table TFREE in the
additional memory block 12.
- four
- Each of the banks and of the tables comprises five lines, respectively identified with addresses ADp, with p ranging between 1 and 5 (AD1 to AD5).
-
FIGS. 3 and 3A describe an example of simultaneous read and write operations, with no bank collision, according to an embodiment of the present disclosure.FIG. 3 illustrates the operations affecting the banks.FIG. 3A illustrates the operations affecting the tables. - For example, the two following operations are performed simultaneously:
-
- reading the data located at external address T2, AD3, at which data DATA-1 have been previously stored; and
- writing data DATA-2 at external address T4, AD1.
- In a first so-called acquisition cycle:
-
- table T2 is read from at address AD3 (step 100) to prepare the read operation, and B2 is obtained;
- table T4 is then read from at address AD1 (step 102) to prepare the write operation, and B3 is obtained; and
- table TFREE is then read from at address AD1 (step 104) to have the number of the bank containing a free location on line AD1, and BADD is obtained.
- Since bank B2 resulting from
step 100 is distinct from bank B3 resulting fromstep 102, the operations generate no collision. - In a second so-called execution cycle:
-
- bank B2 is read from at address AD3 (step 106), and data DATA-1 are obtained; and
- data DATA-2 are written into B3 at address AD1 (step 108).
-
FIG. 3B illustrates, in relation withFIG. 3 , an example of simultaneous read and write operations, with a bank collision.FIG. 3B illustrates the operations affecting the tables. - For example, the two following operations are performed simultaneously:
-
- reading data located at external address T4, AD1, at which data DATA-2 have been previously stored; and
- writing data DATA-4 at external address T3, AD5.
- In the acquisition cycle:
-
- table T4 is read from at address AD1 (step 120) to prepare the read operation, and B3 is obtained;
- table T3 is then read from at address AD5 (step 122) to prepare the write operation, and B3 is obtained; and
- table TFREE is then read from at address AD5 (step 124) to obtain the number of the bank containing a free location at address AD5, and B1 is obtained.
- Since the numbers of the banks resulting from
steps - In the execution cycle:
-
- bank B3 is read from at address AD1 (step 126), and data DATA-2 are obtained;
- data DATA-4 are written into bank B1 at address AD5 (step 128);
- In a third so-called address look-up table updating cycle:
-
- the number of bank B1 is written into table T3 at address AD5 (step 130);
- the number of bank B3 is written into table TFREE at address AD5 (step 132).
- The address coding and decoding, read, and write operations are performed by controller 7.
- As a variation, the third cycle may be systematically carried out, at the cost of an additional writing, sometimes unnecessary, to update the address look-up tables.
- As another variation, and to avoid a sometimes unnecessary read operation, table TFREE may be read from only if a collision is detected in the first cycle.
-
FIG. 4 shows a flowchart describing an example of a sequence of steps executed by memory 5 to perform simultaneous operations. - The type of operation (read, write) to be performed in memory 5 and the corresponding addresses are communicated thereto during
steps banks - The acquisition cycle takes place at steps 214 (OPRD(Tx, ADx)->Bx; OPRD(Ty, ADy)->By) and 218 (OPRD(TFREE, ADy)->Bz) to identify the numbers of the corresponding banks. At
step 214, table Tx is read from at address ADx and Bx is obtained. Then, table Ty is read from at address ADy and By is obtained. Step 218 of reading from table TFREE at address ADy provides the number of the free bank Bx (with Z ranging between 1 and 5) containing the location of a free data word (free word) for this address (free address). - In a comparison step 220 (Bx=By?), the ranks of the banks obtained at
step 214 are compared. - If this rank is different (output N of step 220), each operation is performed simultaneously in different banks, with no risk of collision.
- In this case, the execution cycle comprises a step 222 (OPRD(Bx, ADx)) of reading a data word from bank Bx at address ADX, and a step 224 (OPWR(By, ADy)) of writing a data word into bank By at address ADy. The process can then return to step 210.
- If the numbers of the banks compared at
step 220 are identical (output Y), a collision is detected. The two operations should be performed in the same bank, which cannot be achieved with single-port memory blocks. The sequence then carries on with an execution cycle. - The execution cycle comprises a data word reading step 232 (OPRD(Bx, ADx)) identical to step 222. A data word writing step 234 (OPWR(BZ, ADY)) is performed into free bank BZ (obtained at step 218) at address ADY.
- The address look-up table updating cycle enables, at a step 238 (BZ->OPWR(TY, ADY)), to keep the new number of the bank where the data word previously described at
step 234 is stored. The number of bank BX is thus written into table TY at address ADY. At a step 240 (BY->OPWR(TFREE, ADY)), the new free bank number for address ADY (BY in this example) is written into table TY. The process can then return to step 210. - In certain cases, the accesses to the tables may result in collisions. For example, simultaneous accesses to a same table in read and write mode will be impossible. A solution is to perform a write operation, followed by read operations on the other tables at the address of said read operation. An incomplete list of the bank numbers will be obtained. The set of bank numbers is finite and known, and the missing bank number can then easily be deduced therefrom. This missing bank number is the result of said read operation.
- The memory described in the above embodiment has the advantage of being seen as a dual-port memory while it keeps the advantage of the surface area of single-port memory blocks.
- Another advantage of the described embodiment is that it enables two simultaneous write operations if the designated banks and lines are different.
- Another advantage of the described embodiment is the absence of delayed conflicting operations to be processed subsequently.
- Specific embodiments of the present disclosure have been described. Various alterations and modifications will occur to those skilled in the art. In particular, various embodiments with different variations have been described hereabove. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations.
- Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present disclosure. Accordingly, the foregoing description is by way of example only and is not intended to be limiting.
- These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Claims (17)
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FR1056876 | 2010-08-31 | ||
FR1056876A FR2964211B1 (en) | 2010-08-31 | 2010-08-31 | DEVICE FOR CONTROLLING ACCESS TO SIMPLE PORT MEMORIES |
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US20190012099A1 (en) * | 2017-07-05 | 2019-01-10 | Western Digital Technologies, Inc. | Distribution of logical-to-physical address entries across bank groups |
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US10001971B2 (en) * | 2012-01-10 | 2018-06-19 | Intel Corporation | Electronic apparatus having parallel memory banks |
US20190012099A1 (en) * | 2017-07-05 | 2019-01-10 | Western Digital Technologies, Inc. | Distribution of logical-to-physical address entries across bank groups |
US10635331B2 (en) * | 2017-07-05 | 2020-04-28 | Western Digital Technologies, Inc. | Distribution of logical-to-physical address entries across bank groups |
US11221771B2 (en) | 2017-07-05 | 2022-01-11 | Western Digital Technologies, Inc. | Distribution of logical-to-physical address entries across bank groups |
US11836354B2 (en) | 2017-07-05 | 2023-12-05 | Western Digital Technologies, Inc. | Distribution of logical-to-physical address entries across multiple memory areas |
Also Published As
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FR2964211B1 (en) | 2012-09-21 |
US8671262B2 (en) | 2014-03-11 |
FR2964211A1 (en) | 2012-03-02 |
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