US20110204491A1 - Dielectric layer structure - Google Patents
Dielectric layer structure Download PDFInfo
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- US20110204491A1 US20110204491A1 US13/102,060 US201113102060A US2011204491A1 US 20110204491 A1 US20110204491 A1 US 20110204491A1 US 201113102060 A US201113102060 A US 201113102060A US 2011204491 A1 US2011204491 A1 US 2011204491A1
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- Prior art keywords
- dielectric layer
- low
- layer
- single tensile
- layer structure
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- 239000010410 layer Substances 0.000 claims abstract description 150
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 3
- 230000002209 hydrophobic effect Effects 0.000 claims description 23
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 41
- 238000011282 treatment Methods 0.000 description 13
- 230000003405 preventing effect Effects 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010521 absorption reaction Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000005661 hydrophobic surface Effects 0.000 description 5
- 238000009832 plasma treatment Methods 0.000 description 5
- 238000004886 process control Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 229910008051 Si-OH Inorganic materials 0.000 description 3
- 229910006358 Si—OH Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- WZJUBBHODHNQPW-UHFFFAOYSA-N 2,4,6,8-tetramethyl-1,3,5,7,2$l^{3},4$l^{3},6$l^{3},8$l^{3}-tetraoxatetrasilocane Chemical compound C[Si]1O[Si](C)O[Si](C)O[Si](C)O1 WZJUBBHODHNQPW-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000003795 desorption Methods 0.000 description 2
- NBBQQQJUOYRZCA-UHFFFAOYSA-N diethoxymethylsilane Chemical compound CCOC([SiH3])OCC NBBQQQJUOYRZCA-UHFFFAOYSA-N 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910008045 Si-Si Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910006411 Si—Si Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001546 nitrifying effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Definitions
- the present invention relates to a dielectric layer structure and manufacturing method thereof, and more particularly, to a dielectric layer structure having superior process control and stability and manufacturing method thereof.
- dielectric layer etching has become a critical factor, particularly in some application such as damascene process or interconnection technique.
- a damascene process a dielectric layer is etched to form patterns comprising trenches or via. Then the trenches or via are filled with copper, and a planarization process is performed to complete formation of damascene structure.
- low-K material, ultra low-k (ULK) material, or porous low-k material is used to be the dielectric layer in the damascene structure.
- FIGS. 1-5 are schematic drawings of a conventional trench-first dual damascene process.
- a substrate 10 having at least a conductive layer 12 and a base layer 14 comprising silicon nitride sequentially formed thereon is provided.
- a dielectric layer 16 , a cap layer 18 , a metal hard mask layer 20 , and a bottom anti-reflective coating (BARC) layer 22 are sequentially formed on the base layer 14 .
- a photoresist layer 30 is formed and patterned to form an opening 32 by a well-known photolithography method. The opening 32 is used to define a trench pattern of a damascene structure.
- FIGS. 1 and 2 Please refer to FIGS. 1 and 2 .
- an etching process is performed. Accordingly a trench recess 34 is etched into the metal hard mask layer 20 and the cap layer 18 through the opening 32 . The etching is stopped on the cap layer 18 . The remaining photoresist layer 30 and the BARC layer 22 are then stripped off.
- another BARC layer 36 is deposited over the substrate 10 and fills the trench recess 34 .
- another photoresist layer 40 is formed on the BARC layer 36 .
- the photoresist layer 40 has an opening 42 patterned by a conventional photolithography method. The opening 42 is situated directly above the trench recess 34 and the conductive layer 12 , and is used to define a via pattern of a damascene structure.
- the BARC layer 36 , the cap layer 18 , and the dielectric layer 16 are etched through the opening 42 with the photoresist layer 40 being an etching mask.
- a partial via feature 44 is formed in an upper portion of the dielectric layer 16 .
- the remaining photoresist layer 40 and the BARC layer 36 are stripped off by an oxygen plasma.
- the metal hard mask layer 20 serves as an etching hard mask in an etching process, which is performed to etch away the cap layer 18 and the dielectric layer 16 through the trench recess 34 and the partial via 44 , thereby a dual damascene pattern comprising a trench opening 52 and a via opening 54 is obtained.
- the damascene pattern is filled with a conductive metal such as copper followed by a planarization process that is performed, thus a dual damascene structure is formed.
- the dielectric layer 16 possesses a low mechanical strength and a compressive stress which leads to line distortion occurring in the dielectric layer 16 .
- the cap layer 18 is a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) based silicon oxide layer with TEOS used as a precursor.
- TEOS tetra-ethyl-ortho-silicate
- the TEOS layer comprises lots of Si—OH bonds and Si—H dangling bonds
- the TEOS layer is a hydrophilic layer which is apt to absorb moisture. And the absorbed moisture is then desported from the TEOS layer and into the dielectric layer 16 in following process, thus Kelvin via open are formed in the dielectric layer 16 .
- Kelvin via open reduces reliability of the process and influences electrical performance of the damascene interconnects formed following.
- a multi-layered cap layer such as a tri-layered cap layer
- the tri-layered cap layer provides a tensile stress layer offering a tensile stress which is opposite to the compressive stress of the dielectric layer.
- the multi-layered cap layer also provides hermetical layers sandwiching the tensile stress layer to prevent the tri-layered cap layer itself from absorbing the moisture and to prevent the dielectric layer from the desported moisture.
- the process for the multi-layered cap layer has inferior process control, for example, it is not easy to form openings or recesses in the multi-layered cap layer.
- the multi-layered cap layer also has inferior process stability. Therefore, a simple layer capable of balancing stress in the dielectric layer and preventing itself from absorbing moisture is needed.
- the present invention provides a dielectric layer structure and a manufacturing method thereof to prevent line distortion and Kelvin via open formation in dielectric layer.
- a dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film.
- the ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.
- the single tensile film is used to be a cap layer on the dielectric layer structure. Therefore a tensile stress comparative to the stress of the dielectric layer is provided to prevent line distortion in the dielectric layer. And a hydrophobic characteristic of the single tensile film prevents itself from moisture absorption, thus the Kelvin via open in the dielectric layer resulted by water desorpted from the single tensile film in following processes is also avoided.
- FIGS. 1-5 are schematic drawings of a conventional trench-first dual damascene process.
- FIGS. 6-12 are schematic drawings illustrating a preferred embodiment of the method for manufacturing a dielectric layer structure.
- FIGS. 6-12 are schematic drawings illustrating a preferred embodiment of the method for manufacturing a dielectric layer structure according to the present invention.
- a substrate 100 is provided.
- the substrate 100 comprises a metal layer 102 serving as a conductive layer and a base layer 104 comprising silicon nitride or SiCHN.
- a low-k dielectric layer 106 is sequentially formed thereon.
- the low-k dielectric layer 106 comprises porous low-k dielectric material or ultra low-K (ULK) material.
- a thickness of the low-k dielectric layer 106 is about 800-5000 angstroms.
- a single tensile film 108 comprising tetra-ethyl-ortho-silicate (TEOS) is formed on the low-k dielectric layer 106 by a deposition process.
- the deposition process comprises a plasma-enhanced vapor deposition (PECVD) process, a sub-atmosphere chemical vapor deposition (SACVD) process, or an atmosphere chemical vapor deposition (APCVD) process.
- PECVD plasma-enhanced vapor deposition
- SACVD sub-atmosphere chemical vapor deposition
- APCVD atmosphere chemical vapor deposition
- a high-frequency RF power and a low-frequency RF power of the deposition process can be adjusted to control the tensile stress of the single tensile film 108 according to the stress in the low-k dielectric layer 106 .
- the tensile stress of the single tensile film 108 is about 50-100 MPa.
- a thickness of the single tensile film 108 is also adjustable according to the thickness of the low-k dielectric layer 106 . For example, when the thickness of the low-k dielectric layer 106 is 800-5000 angstroms, the thickness of the single tensile film 108 is about 200-1500 angstroms.
- Silane (SiH 4 ), TEOS, tetra-methyl silane (4MS), tetra-methyl cyclo tetra-siloxane (TMCTS), diethoxy-methyl-silane (DEMS) or other silicon-containing chemicals can be added in the deposition processes as a precursor, and CO 2 , N 2 O, O 2 , or O 3 can be added as an oxidizing agent.
- He, Ar, N 2 , NH 3 , CO 2 , or O 2 can be used in the preferred embodiment for a pre-treatment or a post-treatment.
- a moisture preventing treatment is performed to the single tensile film 108 .
- the moisture preventing treatment comprises an UV treatment, an electromagnetic treatment, or an N-plasma treatment.
- the moisture preventing treatment is used to alter the polarity of the single tensile film 108 for enhancing moisture preventing effect of the single tensile film 108 .
- the UV treatment is performed with an UV light 110 having a wavelength of 50-400 nanometers (nm) at a temperature of about 250-450° C. for 1-5 minutes.
- the UV light 110 is used to break the Si—OH bonds and the Si—H dangling bonds in the single tensile film 108 .
- the Si—OH bonds and the Si—H dangling bonds are eliminated and Si—O bonds or Si—Si bonds are formed.
- the polarity of the single tensile film 108 is altered from hydrophilic into hydrophobic and a single tensile hydrophobic film 112 is obtained as shown in FIG. 8 .
- the N-plasma treatment is performed with an N-containing plasma for nitrifying a surface of the single tensile film 108 , and thus a hydrophobic surface 122 is obtained as shown in FIG. 9 .
- a metal hard mask layer 130 comprising TiN is formed on the single tensile film 108 .
- the substrate 100 is placed in an nitrogen environment, then an N-plasma is introduced to bombard a Ti metal target, thus the metal hard mask layer 130 comprising TiN is formed.
- said N-plasma can be used in the N-plasma treatment, therefore the hydrophobic surface 122 is obtained and the step of forming the metal hard mask layer 130 can be performed in the same apparatus.
- the N-plasma treatment which is one approach of the moisture preventing treatment
- the step of forming the metal hard mask layer 130 can be performed in-situ.
- the moisture preventing treatment and the step of forming the metal hard mask layer 130 can be performed ex-situ.
- the single tensile film 108 can be altered to be the single tensile hydrophobic film 112 with the UV treatment first, then its surface can be treated to be the hydrophobic surface 122 with the N-plasma treatment, and the metal hard mask layer 130 can be formed in the same apparatus.
- a photoresist layer 140 is formed on the metal hard mask layer 130 .
- a bottom anti-reflective coating (BARC) layer (not shown) can be formed on the metal hard mask layer 130 .
- BARC bottom anti-reflective coating
- a conventional photolithography method is performed to pattern the photoresist 140 , thus an opening 142 used to define a pattern is formed as shown in FIG. 11 .
- an etching process is performed to etch the metal hard mask layer 130 to the single tensile hydrophobic film 112 through the opening 142 and to form an opening 144 .
- a depth of the opening 144 is not limited as shown in FIG. 12 and is adjustable according to requirements of the process, even to penetrate the single tensile hydrophobic film 112 .
- the compressive stress of the low-k dielectric layer 106 can be balanced by the tensile stress provided by the single tensile film 108 , therefore pattern or line distortion in the low-k dielectric layer 106 due to the compressive stress is avoided effectively.
- the single tensile film 108 which comprises hydrophilic TEOS is altered in to the single tensile hydrophobic film 112 , even to further comprise the hydrophobic surface 122 by the moisture preventing treatments, therefore the moisture absorption is effectively prevented.
- the present invention provides a dielectric layer structure comprising a low-k dielectric layer 106 and a single tensile hydrophobic film 112 positioned on the low-k dielectric layer 106 .
- the low-k dielectric layer 106 comprises porous low-k dielectric material or ULK material.
- a thickness of the low-k dielectric layer 106 is about 800-5000 angstroms.
- the single tensile hydrophobic film 112 comprises TEOS.
- a thickness of the single tensile hydrophobic film 112 can be adjusted according to the thickness of the low-k dielectric layer 106 therefore a range of the thickness of the single tensile hydrophobic film 112 is 200-5000 angstroms.
- the single tensile hydrophobic film 112 possesses a tensile stress which is comparative to a compressive stress of the low-k dielectric layer 106 .
- the single tensile hydrophobic film 112 can comprise a nitrified surface serving as a hydrophobic surface 122 .
- the compressive stress of the low-k dielectric layer 106 can be balanced by the tensile stress provided by the single tensile hydrophobic film 112 , therefore pattern or line distortion in the low-k dielectric layer 106 is avoided effectively.
- the single tensile hydrophobic film 112 has the hydrophobic feature, moisture will not be absorbed, therefore the moisture absorption is effectively prevented.
- problems of moisture absorption in the low-k dielectric layer 106 from the single tensile film 108 and moisture desorption from the low-k dielectric layer 106 in following processes which causes Kelvin via open are fundamentally prevented.
- the dielectric layer structure provided by the present invention further comprises a metal hard mask layer (shown in FIG. 10 ) positioned on the single tensile hydrophobic film 112 for defining patterns and protecting the low-k dielectric layer 106 .
- the single tensile hydrophobic film is used to balance a comparative stress of the former layer such as the dielectric layer, therefore pattern or line distortion in the dielectric layer is prevented.
- the hydrophobic characteristic of the single tensile hydrophobic film prevents itself from moisture absorption, thus the Kelvin via open in the dielectric layer resulted by water desorpted from the tensile hydrophobic film in following processes is also avoided.
- the dielectric layer structure provided by the present invention not only effectively improves the process control and process stability of the entire process, but also improves the process result.
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Abstract
A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.
Description
- This application is a continuation of U.S. patent application Ser. No. 12/948,789, filed on Nov. 18, 2010, which is a division of U.S. patent application Ser. No. 11/834,643, filed on Aug. 6, 2007 and issued as U.S. Pat. No. 7,858,532 on Dec. 28, 2010, the entire disclosures of which are hereby incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a dielectric layer structure and manufacturing method thereof, and more particularly, to a dielectric layer structure having superior process control and stability and manufacturing method thereof.
- 2. Description of the Prior Art
- Devices in semiconductor industry need to undergo several complicated processes such as photolithograph process, dry or wet etching process, ion implantation, and heat treatment, etc. to construct precise integrated circuits in layers. Among those complicated processes, the process control of dielectric layer etching has become a critical factor, particularly in some application such as damascene process or interconnection technique. For example, in a damascene process, a dielectric layer is etched to form patterns comprising trenches or via. Then the trenches or via are filled with copper, and a planarization process is performed to complete formation of damascene structure. Additionally, to satisfy requirements of low RC delay effects, low-K material, ultra low-k (ULK) material, or porous low-k material is used to be the dielectric layer in the damascene structure.
- Please refer to
FIGS. 1-5 , which are schematic drawings of a conventional trench-first dual damascene process. As shown inFIG. 1 , asubstrate 10 having at least aconductive layer 12 and abase layer 14 comprising silicon nitride sequentially formed thereon is provided. And adielectric layer 16, acap layer 18, a metalhard mask layer 20, and a bottom anti-reflective coating (BARC)layer 22 are sequentially formed on thebase layer 14. Then, aphotoresist layer 30 is formed and patterned to form anopening 32 by a well-known photolithography method. The opening 32 is used to define a trench pattern of a damascene structure. - Please refer to
FIGS. 1 and 2 . Subsequently, an etching process is performed. Accordingly atrench recess 34 is etched into the metalhard mask layer 20 and thecap layer 18 through theopening 32. The etching is stopped on thecap layer 18. The remainingphotoresist layer 30 and the BARClayer 22 are then stripped off. - As shown in
FIG. 3 , anotherBARC layer 36 is deposited over thesubstrate 10 and fills thetrench recess 34. And anotherphotoresist layer 40 is formed on the BARClayer 36. Thephotoresist layer 40 has anopening 42 patterned by a conventional photolithography method. Theopening 42 is situated directly above thetrench recess 34 and theconductive layer 12, and is used to define a via pattern of a damascene structure. As shown inFIG. 4 , theBARC layer 36, thecap layer 18, and thedielectric layer 16 are etched through theopening 42 with thephotoresist layer 40 being an etching mask. Thus, apartial via feature 44 is formed in an upper portion of thedielectric layer 16. Then the remainingphotoresist layer 40 and theBARC layer 36 are stripped off by an oxygen plasma. - Please refer to
FIG. 5 . Next, the metalhard mask layer 20 serves as an etching hard mask in an etching process, which is performed to etch away thecap layer 18 and thedielectric layer 16 through thetrench recess 34 and the partial via 44, thereby a dual damascene pattern comprising atrench opening 52 and a viaopening 54 is obtained. Then, the damascene pattern is filled with a conductive metal such as copper followed by a planarization process that is performed, thus a dual damascene structure is formed. It is noteworthy that thedielectric layer 16 possesses a low mechanical strength and a compressive stress which leads to line distortion occurring in thedielectric layer 16. - Furthermore, there is another phenomenon drawing attention in the conventional damascene formation process: Generally, the
cap layer 18 is a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) based silicon oxide layer with TEOS used as a precursor. Because the TEOS layer comprises lots of Si—OH bonds and Si—H dangling bonds, the TEOS layer is a hydrophilic layer which is apt to absorb moisture. And the absorbed moisture is then desported from the TEOS layer and into thedielectric layer 16 in following process, thus Kelvin via open are formed in thedielectric layer 16. Kelvin via open reduces reliability of the process and influences electrical performance of the damascene interconnects formed following. - To solve the problem mentioned above, those skilled in the art provide many approaches, for example, a multi-layered cap layer such as a tri-layered cap layer is provided. The tri-layered cap layer provides a tensile stress layer offering a tensile stress which is opposite to the compressive stress of the dielectric layer. The multi-layered cap layer also provides hermetical layers sandwiching the tensile stress layer to prevent the tri-layered cap layer itself from absorbing the moisture and to prevent the dielectric layer from the desported moisture. However, due to the multi-layered characteristic, the process for the multi-layered cap layer has inferior process control, for example, it is not easy to form openings or recesses in the multi-layered cap layer. And the multi-layered cap layer also has inferior process stability. Therefore, a simple layer capable of balancing stress in the dielectric layer and preventing itself from absorbing moisture is needed.
- Therefore the present invention provides a dielectric layer structure and a manufacturing method thereof to prevent line distortion and Kelvin via open formation in dielectric layer.
- According to the claimed invention, a dielectric layer structure is provided. The dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.
- According to the dielectric layer structure, the single tensile film is used to be a cap layer on the dielectric layer structure. Therefore a tensile stress comparative to the stress of the dielectric layer is provided to prevent line distortion in the dielectric layer. And a hydrophobic characteristic of the single tensile film prevents itself from moisture absorption, thus the Kelvin via open in the dielectric layer resulted by water desorpted from the single tensile film in following processes is also avoided.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-5 are schematic drawings of a conventional trench-first dual damascene process. -
FIGS. 6-12 are schematic drawings illustrating a preferred embodiment of the method for manufacturing a dielectric layer structure. - Please refer to
FIGS. 6-12 , which are schematic drawings illustrating a preferred embodiment of the method for manufacturing a dielectric layer structure according to the present invention. As shown inFIG. 6 , asubstrate 100 is provided. Thesubstrate 100 comprises ametal layer 102 serving as a conductive layer and abase layer 104 comprising silicon nitride or SiCHN. Then a low-k dielectric layer 106 is sequentially formed thereon. The low-kdielectric layer 106 comprises porous low-k dielectric material or ultra low-K (ULK) material. A thickness of the low-k dielectric layer 106 is about 800-5000 angstroms. - Please refer to
FIG. 7 . Next, a singletensile film 108 comprising tetra-ethyl-ortho-silicate (TEOS) is formed on the low-k dielectric layer 106 by a deposition process. The deposition process comprises a plasma-enhanced vapor deposition (PECVD) process, a sub-atmosphere chemical vapor deposition (SACVD) process, or an atmosphere chemical vapor deposition (APCVD) process. A high-frequency RF power and a low-frequency RF power of the deposition process can be adjusted to control the tensile stress of the singletensile film 108 according to the stress in the low-k dielectric layer 106. For example, when the high-frequency RF power is about 750-850 Watts and the low-frequency RF power is about 100-200 Watts, the tensile stress of the singletensile film 108 is about 50-100 MPa. A thickness of the singletensile film 108 is also adjustable according to the thickness of the low-k dielectric layer 106. For example, when the thickness of the low-k dielectric layer 106 is 800-5000 angstroms, the thickness of the singletensile film 108 is about 200-1500 angstroms. - Silane (SiH4), TEOS, tetra-methyl silane (4MS), tetra-methyl cyclo tetra-siloxane (TMCTS), diethoxy-methyl-silane (DEMS) or other silicon-containing chemicals can be added in the deposition processes as a precursor, and CO2, N2O, O2, or O3 can be added as an oxidizing agent. In addition, He, Ar, N2, NH3, CO2, or O2 can be used in the preferred embodiment for a pre-treatment or a post-treatment.
- Please refer to
FIG. 8 . Then, a moisture preventing treatment is performed to the singletensile film 108. The moisture preventing treatment comprises an UV treatment, an electromagnetic treatment, or an N-plasma treatment. The moisture preventing treatment is used to alter the polarity of the singletensile film 108 for enhancing moisture preventing effect of the singletensile film 108. For example, the UV treatment is performed with anUV light 110 having a wavelength of 50-400 nanometers (nm) at a temperature of about 250-450° C. for 1-5 minutes. In the UV treatment, theUV light 110 is used to break the Si—OH bonds and the Si—H dangling bonds in the singletensile film 108. Therefore the Si—OH bonds and the Si—H dangling bonds are eliminated and Si—O bonds or Si—Si bonds are formed. Thus the polarity of the singletensile film 108 is altered from hydrophilic into hydrophobic and a single tensilehydrophobic film 112 is obtained as shown inFIG. 8 . Moreover, the N-plasma treatment is performed with an N-containing plasma for nitrifying a surface of the singletensile film 108, and thus ahydrophobic surface 122 is obtained as shown inFIG. 9 . - Please refer to
FIG. 10 . After performing the moisture preventing treatment, a metalhard mask layer 130 comprising TiN is formed on the singletensile film 108. When forming the metalhard mask layer 130, thesubstrate 100 is placed in an nitrogen environment, then an N-plasma is introduced to bombard a Ti metal target, thus the metalhard mask layer 130 comprising TiN is formed. It is noteworthy that before bombarding the Ti metal target, said N-plasma can be used in the N-plasma treatment, therefore thehydrophobic surface 122 is obtained and the step of forming the metalhard mask layer 130 can be performed in the same apparatus. Thus it can be seen that the N-plasma treatment, which is one approach of the moisture preventing treatment, and the step of forming the metalhard mask layer 130 can be performed in-situ. Of course the moisture preventing treatment and the step of forming the metalhard mask layer 130 can be performed ex-situ. Furthermore, as shown inFIG. 10 , the singletensile film 108 can be altered to be the single tensilehydrophobic film 112 with the UV treatment first, then its surface can be treated to be thehydrophobic surface 122 with the N-plasma treatment, and the metalhard mask layer 130 can be formed in the same apparatus. - Please refer to
FIGS. 11-12 . Then, aphotoresist layer 140 is formed on the metalhard mask layer 130. Additionally, a bottom anti-reflective coating (BARC) layer (not shown) can be formed on the metalhard mask layer 130. And a conventional photolithography method is performed to pattern thephotoresist 140, thus anopening 142 used to define a pattern is formed as shown inFIG. 11 . Please refer toFIG. 12 , an etching process is performed to etch the metalhard mask layer 130 to the single tensilehydrophobic film 112 through theopening 142 and to form anopening 144. A depth of theopening 144 is not limited as shown inFIG. 12 and is adjustable according to requirements of the process, even to penetrate the single tensilehydrophobic film 112. - According to the method for manufacturing dielectric layer structure provided by the present invention, the compressive stress of the low-
k dielectric layer 106 can be balanced by the tensile stress provided by the singletensile film 108, therefore pattern or line distortion in the low-k dielectric layer 106 due to the compressive stress is avoided effectively. And the singletensile film 108 which comprises hydrophilic TEOS is altered in to the single tensilehydrophobic film 112, even to further comprise thehydrophobic surface 122 by the moisture preventing treatments, therefore the moisture absorption is effectively prevented. Thus problems of moisture absorption in the low-k dielectric layer 106 from the singletensile film 108 and moisture desorption from the low-k dielectric layer 106 in following processes which causes Kelvin via open are fundamentally prevented. Additionally, when the low-k dielectric layer 106 comprises porous low-k dielectric material or ULK material which is more susceptible to the contaminant and damage, the singletensile film 108 provided by the present invention can prevent defects such Kelvin via open more effectively. Therefore process stability is improved. What is noteworthy is that due to the single tensilehydrophobic film 112 comprising only one lamination, the entire process further benefits from simpler process control and superior process stability. - Please refer to
FIGS. 8 and 9 again. As mentioned above, the present invention provides a dielectric layer structure comprising a low-k dielectric layer 106 and a single tensilehydrophobic film 112 positioned on the low-k dielectric layer 106. The low-k dielectric layer 106 comprises porous low-k dielectric material or ULK material. A thickness of the low-k dielectric layer 106 is about 800-5000 angstroms. - The single tensile
hydrophobic film 112 comprises TEOS. A thickness of the single tensilehydrophobic film 112 can be adjusted according to the thickness of the low-k dielectric layer 106 therefore a range of the thickness of the single tensilehydrophobic film 112 is 200-5000 angstroms. The single tensilehydrophobic film 112 possesses a tensile stress which is comparative to a compressive stress of the low-k dielectric layer 106. The single tensilehydrophobic film 112 can comprise a nitrified surface serving as ahydrophobic surface 122. - According to the dielectric layer structure provided by the present invention, the compressive stress of the low-
k dielectric layer 106 can be balanced by the tensile stress provided by the single tensilehydrophobic film 112, therefore pattern or line distortion in the low-k dielectric layer 106 is avoided effectively. And since the single tensilehydrophobic film 112 has the hydrophobic feature, moisture will not be absorbed, therefore the moisture absorption is effectively prevented. Thus problems of moisture absorption in the low-k dielectric layer 106 from the singletensile film 108 and moisture desorption from the low-k dielectric layer 106 in following processes which causes Kelvin via open are fundamentally prevented. - Additionally, the dielectric layer structure provided by the present invention further comprises a metal hard mask layer (shown in
FIG. 10 ) positioned on the single tensilehydrophobic film 112 for defining patterns and protecting the low-k dielectric layer 106. - As mentioned above, according to the dielectric layer structure and the method manufacturing thereof, the single tensile hydrophobic film is used to balance a comparative stress of the former layer such as the dielectric layer, therefore pattern or line distortion in the dielectric layer is prevented. And the hydrophobic characteristic of the single tensile hydrophobic film prevents itself from moisture absorption, thus the Kelvin via open in the dielectric layer resulted by water desorpted from the tensile hydrophobic film in following processes is also avoided. In other words, the dielectric layer structure provided by the present invention not only effectively improves the process control and process stability of the entire process, but also improves the process result.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (9)
1. A dielectric layer structure comprising:
an interlayer dielectric (ILD) layer covering at least a metal interconnect structure, wherein the ILD layer comprises a low-k dielectric layer; and
a single tensile film positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.
2. The dielectric layer structure of claim 1 , wherein the low-k dielectric layer comprises porous low-k dielectric material or ultra low-k (ULK) dielectric material.
3. The dielectric layer structure of claim 1 , wherein the low-k dielectric layer comprises a thickness of 800-5000 angstroms.
4. The dielectric layer structure of claim 3 , wherein the single tensile film comprises a thickness of 200-1500 angstroms.
5. The dielectric layer structure of claim 1 , wherein the single tensile film comprises a hydrophobic film.
6. The dielectric layer structure of claim 1 , wherein the single tensile film comprises tetra-ethyl-ortho-silicate (TEOS).
7. The dielectric layer structure of claim 1 , wherein the single tensile film further comprises a nitrified surface.
8. The dielectric layer structure of claim 1 further comprises a hard mask layer positioned on the single tensile film.
9. The dielectric layer structure of claim 8 , wherein the metal hard mask, the single tensile film and the ILD layer further comprise at least an opening for exposing the metal interconnect structure.
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DE102010003560B4 (en) * | 2010-03-31 | 2018-04-05 | Globalfoundries Dresden Module One Llc & Co. Kg | A semiconductor device having a capacitor in a metallization system fabricated by a hardmask patterning scheme |
US8114769B1 (en) * | 2010-12-31 | 2012-02-14 | Globalfoundries Singapore Pte, Lte. | Methods and structures to enable self-aligned via etch for Cu damascene structure using trench first metal hard mask (TFMHM) scheme |
US8399359B2 (en) | 2011-06-01 | 2013-03-19 | United Microelectronics Corp. | Manufacturing method for dual damascene structure |
CN102446841B (en) * | 2011-11-07 | 2016-08-03 | 上海华力微电子有限公司 | A kind of preparation method of low stress metal hard mask layer |
KR101955332B1 (en) * | 2012-02-22 | 2019-05-30 | 삼성전자주식회사 | Plasmonic modulator and optical apparatus employing the same |
US8735295B2 (en) | 2012-06-19 | 2014-05-27 | United Microelectronics Corp. | Method of manufacturing dual damascene structure |
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Also Published As
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US20090042053A1 (en) | 2009-02-12 |
US20110065285A1 (en) | 2011-03-17 |
US8183166B2 (en) | 2012-05-22 |
US7858532B2 (en) | 2010-12-28 |
US20110062562A1 (en) | 2011-03-17 |
US7960826B2 (en) | 2011-06-14 |
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