US20110169170A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20110169170A1 US20110169170A1 US13/005,322 US201113005322A US2011169170A1 US 20110169170 A1 US20110169170 A1 US 20110169170A1 US 201113005322 A US201113005322 A US 201113005322A US 2011169170 A1 US2011169170 A1 US 2011169170A1
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- bonding electrodes
- semiconductor device
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- power supply
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Definitions
- the present invention relates to semiconductor devices and more particularly to technology for a semiconductor device including a semiconductor chip flip-chip coupled to a wiring substrate.
- a semiconductor device having a multilayer substrate in which a plurality of connecting terminals to which bumps for connection of an LSI chip are fixed are exposed on one outermost layer of the multilayer substrate and solder balls are fixed over metal pads on the other outermost layer to make up a ball grid array (BGA) structure for connection to a motherboard (for example, see Japanese Unexamined Patent Publication No. 2006-73622).
- BGA ball grid array
- the BGA (ball grid array) substrate type is selected rather than the lead frame type.
- the wiring substrate used here is often a multilayer substrate because of the multi-pin structure.
- package size depends on the number of pins, so if the chip is shrunk and the number of pins remains unchanged, the interval between pads (pad pitch) should be smaller. This may raise a problem that wirings cannot pass between pads.
- chip shrinkage may pose a problem that the pad pitch is too small for wirings to pass between pads.
- a multilayer wiring substrate is used and area arrangement of pads is adopted.
- a total of six wiring layers, three above the core layer and three below it, are formed by a build-up technique or the like and area arrangement of chip pads is also adopted.
- the number of layers of the multilayer wiring substrate must be increased to arrange wirings properly. This would lead to rise in semiconductor device cost.
- the pad pitch should be decreased, maybe making it difficult for wirings to pass between pads as mentioned above.
- the problem here is that area arrangement of pads is impossible.
- the use of the redistribution technique makes it possible to adopt area arrangement of pads, it involves difficulty in design and necessitates a chip cost increase. Since a rise in the chip cost leads to a rise in the semiconductor device cost, it is not a good solution.
- the BGA semiconductor device described in the above patent document also has a problem that if the number of pins is to be increased, the number of wiring layers of the multilayer substrate must be increased, leading to a rise in the semiconductor device cost.
- the present invention has been made in view of the above problem and an object thereof is to provide a technique which reduces the cost of multi-pin semiconductor devices.
- Another object of the invention is to provide a technique which enables area arrangement of pads in a semiconductor device with a shrunk chip.
- a semiconductor device which uses a multilayer wiring substrate having an upper surface and a lower surface opposite to the upper surface with a semiconductor chip flip-chip mounted on the upper surface includes the semiconductor chip having a main surface and a back surface opposite to the main surface with a plurality of electrode pads formed on the main surface, the multilayer wiring substrate in which a plurality of bonding electrodes are formed in a plurality of rows on the upper surface in a first region corresponding to a peripheral area of the main surface of the semiconductor chip and an array of fixed potential (power supply and GND) bonding electrodes are formed in a second region inside the first region, and a plurality of external terminals provided on the lower surface of the multilayer wiring substrate.
- the semiconductor chip having a main surface and a back surface opposite to the main surface with a plurality of electrode pads formed on the main surface
- the multilayer wiring substrate in which a plurality of bonding electrodes are formed in a plurality of rows on the upper surface in a first region corresponding to a peripheral area of the main surface of the semiconductor
- a plurality of signal bonding electrodes among the bonding electrodes in the first region of the upper surface of the multilayer wiring substrate are separated into inner and outer ones; each of a plurality of signal wirings drawn inside from the signal bonding electrodes is electrically coupled to an wiring portion in another wiring layer through a through hole; and the through holes are located between the first region and the second region.
- the semiconductor chip having a main surface and a back surface opposite to the main surface with a plurality of electrode pads formed on the main surface
- the multilayer wiring substrate in which a plurality of bonding electrodes are formed in two rows on the upper surface in a first region corresponding to a peripheral area of the main surface of the semiconductor chip and an array of fixed potential
- a plurality of signal bonding electrodes among the bonding electrodes in the first region of the upper surface of the multilayer wiring substrate are separated into inner and outer ones; each of a plurality of signal wirings drawn inside from the signal bonding electrodes is electrically coupled to an wiring portion in another wiring layer through a through hole; and the through holes are located between the first region and the second region.
- the chip can be shrunk without the need for an increase in the number of layers in its multilayer wiring substrate, so that the cost of the semiconductor device can be reduced.
- FIG. 1 is a partially broken perspective view of the structure of a semiconductor device according to a first embodiment of the invention
- FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1 ;
- FIG. 3 is a fragmentary enlarged sectional view of part A of FIG. 2 ;
- FIG. 4 is a plan view of an example of the electrode pad arrangement of the semiconductor chip mounted in the semiconductor device shown in FIG. 1 ;
- FIG. 5 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L 1 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 ;
- FIG. 6 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L 2 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 ;
- FIG. 7 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L 3 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 ;
- FIG. 8 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L 4 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 ;
- FIG. 9 is a fragmentary enlarged plan view of part A of FIG. 5 ;
- FIG. 10 is a fragmentary enlarged plan view of part A of FIG. 6 ;
- FIG. 11 is a fragmentary enlarged plan view of part A of FIG. 7 ;
- FIG. 12 is a fragmentary enlarged plan view of part A of FIG. 8 ;
- FIG. 13 is a fragmentary enlarged plan view of part B of FIG. 5 ;
- FIG. 14 shows data on the relation between pad arrangement type and substrate structure type in the semiconductor chip mounted in the semiconductor device shown in FIG. 1 ;
- FIG. 15 is a fragmentary enlarged sectional view combined with a fragmentary enlarged plan view, showing the positional relation between the bonding electrodes and bumps of the wiring substrate for peripheral pads and the electrode pads of the semiconductor chip in the semiconductor device according to the first embodiment;
- FIG. 16 is a fragmentary enlarged plan view showing the shape of bonding electrodes of the wiring substrate for central pads in the semiconductor device according to the first embodiment
- FIG. 17 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment
- FIG. 18 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment
- FIG. 19 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a first variation of the first embodiment
- FIG. 20 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a second variation of the first embodiment
- FIG. 21 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a third variation of the first embodiment
- FIG. 22 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fourth variation of the first embodiment
- FIG. 23 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fifth variation of the first embodiment
- FIG. 24 is a plan view of the wiring substrate built in the semiconductor device according to a sixth variation of the first embodiment.
- FIG. 25 is a sectional view of an example of the semiconductor device using the wiring substrate shown in FIG. 24 ;
- FIG. 26 is a plan view showing an example of the relation between the bonding electrode shape of the wiring substrate and the electrode pads of the semiconductor chip in the semiconductor device according to a seventh variation of the first embodiment
- FIG. 27 is a fragmentary enlarged sectional view of the semiconductor device according to an eighth variation of the first embodiment.
- FIG. 28 is a fragmentary enlarged sectional view of the semiconductor device according to a ninth variation of the first embodiment.
- FIG. 29 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L 1 ) of the wiring substrate built in the semiconductor device according to a second embodiment of the invention.
- FIG. 30 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L 2 ) of the wiring substrate built in the semiconductor device according to the second embodiment;
- FIG. 31 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L 3 ) of the wiring substrate built in the semiconductor device according to the second embodiment;
- FIG. 32 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L 4 ) of the wiring substrate built in the semiconductor device according to the second embodiment;
- FIG. 33 is a fragmentary enlarged plan view of part A of FIG. 29 ;
- FIG. 34 is a fragmentary enlarged plan view of part A of FIG. 30 ;
- FIG. 35 is a fragmentary enlarged plan view of part A of FIG. 31 ;
- FIG. 36 is a fragmentary enlarged plan view of part A of FIG. 32 ;
- FIG. 37 is a fragmentary enlarged plan view of part A of the wiring substrate built in the semiconductor device according to a variation of the second embodiment.
- FIG. 1 is a partially broken perspective view of the structure of a semiconductor device according to a first embodiment of the invention
- FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1
- FIG. 3 is a fragmentary enlarged sectional view of part A of FIG. 2
- FIG. 4 is a plan view of an example of the electrode pad arrangement of the semiconductor chip mounted in the semiconductor device shown in FIG. 1
- FIG. 5 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L 1 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 ;
- FIG. 1 is a partially broken perspective view of the structure of a semiconductor device according to a first embodiment of the invention
- FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1
- FIG. 3 is a fragmentary enlarged sectional view of part A of FIG. 2
- FIG. 4 is a plan view of an example of the electrode pad arrangement of the semiconductor chip mounted in the semiconductor device shown in FIG
- FIG. 6 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L 2 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 ;
- FIG. 7 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L 3 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 ;
- FIG. 8 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L 4 ) of the wiring substrate built in the semiconductor device shown in FIG. 1 .
- FIG. 9 is a fragmentary enlarged plan view of part A of FIG. 5 ;
- FIG. 10 is a fragmentary enlarged plan view of part A of FIG.
- FIG. 11 is a fragmentary enlarged plan view of part A of FIG. 7 ;
- FIG. 12 is a fragmentary enlarged plan view of part A of FIG. 8 ;
- FIG. 13 is a fragmentary enlarged plan view of part B of FIG. 5 .
- FIG. 14 shows data on the relation between pad arrangement type and substrate structure type in the semiconductor chip mounted in the semiconductor device shown in FIG. 1 ;
- FIG. 15 is a fragmentary enlarged sectional view combined with a fragmentary enlarged plan view, showing the positional relation between the bonding electrodes and bumps of the wiring substrate for peripheral pads and the electrode pads of the semiconductor chip in the semiconductor device according to the first embodiment;
- FIG. 15 is a fragmentary enlarged sectional view combined with a fragmentary enlarged plan view, showing the positional relation between the bonding electrodes and bumps of the wiring substrate for peripheral pads and the electrode pads of the semiconductor chip in the semiconductor device according to the first embodiment;
- FIG. 16 is a fragmentary enlarged plan view showing the shape of bonding electrodes of the wiring substrate for central pads in the semiconductor device according to the first embodiment
- FIG. 17 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment
- FIG. 18 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment.
- the semiconductor device according to the first embodiment as shown in FIGS. 1 and 2 is a semiconductor package in which a semiconductor chip 1 is flip-chip mounted over the upper surface 2 a of an wiring substrate by soldering.
- it is a BGA 9 in which a plurality of solder balls 5 as external terminals are arranged in a grid pattern on the lower surface 2 b of the wiring substrate.
- the semiconductor device according to the first embodiment is a flip-chip BGA 9 ; for example, it may be a multi-pin semiconductor package with not less than hundreds of pins as external terminals.
- the BGA 9 includes: a multilayer wiring substrate 2 having an upper surface 2 a and a lower surface 2 b opposite to the upper surface 2 a; a semiconductor chip 1 which has a main surface 1 a and a back surface 1 b opposite to the main surface 1 a and is flip-chip mounted over the upper surface 2 a of the multilayer wiring substrate 2 ; and an array of solder balls 5 as external terminals disposed on the lower surface 2 b of the multilayer wiring substrate 2 .
- the semiconductor chip 1 having a plurality of electrode pads 1 c as surface electrodes formed on its main surface la, is flip-chip (face-down) mounted over the upper surface 2 a of the multilayer wiring substrate 2 .
- the semiconductor chip 1 is mounted over the multilayer wiring substrate 2 with its main surface 1 a facing the upper surface 2 a of the multilayer wiring substrate 2 .
- the semiconductor chip 1 is electrically coupled to the multilayer wiring substrate 2 by soldering, in which they are flip-chip coupled through a plurality of solder bumps 8 .
- a plurality of bonding electrodes 2 c lie in a region where the semiconductor chip 1 is to be flip-chip mounted. More specifically, the electrode pads 1 c of the semiconductor chip 1 and the bonding electrodes 2 c for flip-chip coupling through the solder bumps 8 are located in the chip mounting area of the upper surface 2 a of the multilayer wiring substrate 2 .
- a plurality of bonding electrodes 2 c are arranged in two rows in first regions 2 y of the chip mounting area of the upper surface 2 a of the multilayer wiring substrate 2 which are opposite to the peripheral areas of the main surface 1 a of the semiconductor chip 1 .
- an array of power supply and GND bonding electrodes (bonding electrodes 2 m for core power supply and bonding electrodes 2 n for GND) are formed in a second region 2 z inside the first regions 2 y.
- power supply and GND refer to operating electric potentials supplied to the integrated circuit of the semiconductor chip 1 , in which power supply potential is, for example, 3.0 V for an external power supply and 1.5 V for an internal power supply (core power supply) and GND potential is 0 V (grounding potential).
- an array of power supply and GND bonding electrodes are arranged in the second region 2 z near the center of the chip mounting area of the upper surface 2 a of the multilayer wiring substrate 2 .
- the first regions 2 y are located around the second region 2 z, in which a plurality of bonding electrodes 2 c are arranged in two rows in each of the first regions 2 y.
- an array of lands 2 j are arranged on the lower surface 2 b of the multilayer wiring substrate 2 , with a solder ball 5 as an external terminal coupled to each land 2 j.
- the flip chip joints lying between the multilayer wiring substrate 2 and the semiconductor chip 1 , and their surroundings are filled with underfill resin 6 to solidify the flip chip joints for protection.
- a stiffener ring 7 is attached to the periphery of the upper surface 2 a of the multilayer wiring substrate 2 in a way to surround the semiconductor chip 1 .
- the stiffener ring 7 is bonded to the multilayer wiring substrate 2 with a ring-shaped tape 7 a.
- a heat spreader 4 is provided over the stiffener ring 7 .
- the heat spreader 4 is joined to the stiffener ring 7 and the back surface 1 b of the semiconductor chip 1 through heat-radiating resin 3 on the semiconductor chip 1 and an adhesive agent (for example, tape material) 7 b between the stiffener ring 7 and heat spreader 4 .
- heat generated from the semiconductor chip is transferred to the heat spreader 4 through the heat-radiating resin 3 and dissipated out from the heat spreader 4 and meanwhile the heat is also transferred to the multilayer wiring substrate 2 through the solder bumps 8 , then from the solder balls 5 to the mounting substrate. Also the heat is transferred from the heat spreader 4 through the adhesive agent 7 b and stiffener ring 7 to the multilayer wiring substrate 2 , from which it is transferred through the solder balls 5 to the mounting substrate and finally dissipated.
- the multilayer wiring substrate 2 of the BGA 9 is a coreless substrate without a core layer 2 h ( FIG. 19 ) as a base layer, in which it includes a buildup layer 2 f, a plurality of bonding electrodes 2 c formed on the front surface of the buildup layer 2 f (upper surface 2 a of the multilayer wiring substrate 2 ), a plurality of lands 2 j formed on the back surface of the buildup layer 2 f (lower surface 2 b of the multilayer wiring substrate 2 ), through holes (wirings) 2 d for electrically coupling the bonding electrodes 2 c on the front surface to the lands 2 j on the back surface, internal wirings 2 e in the buildup layer 2 f and so on.
- Solder resist film 2 g as insulator lies around the bonding electrodes 2 c and around the lands 2 j.
- the bonding electrodes 2 c on the upper surface 2 a and the corresponding lands 2 j on the lower surface 2 b are electrically coupled through the through holes (wirings) 2 d, via hole wirings 2 i ( FIG. 2 ) or internal wiring 2 e in the buildup layer 2 f.
- the semiconductor chip 1 is, for example, made of silicon with the electrode pads 1 c as surface electrodes formed on its main surface 1 a.
- the electrode pads 1 c are located along each side and arrays of electrode pads 1 c are arranged inside the rows of electrode pads in the peripheral areas.
- the underfill resin 6 coated between the chip and substrate is, for example, epoxy resin.
- the stiffener ring 7 and heat spreader 4 are made of metal with a high thermal conductivity and the solder bumps 8 for flip-chip coupling and the solder balls 5 as external terminals are, for example, made of a lead-free solder material.
- the bonding electrodes 2 c, via hole wirings 2 i, internal wiring 2 e, and through holes 2 d of the multilayer wiring substrate 2 are, for example, made of pure copper or copper alloy containing a low percentage (1% or less) of impurity such as aluminum or silicon (Si).
- the multilayer wiring substrate 2 of the BGA 9 according to the first embodiment is a thin coreless substrate without a core layer 2 h ( FIG. 19 ). Due to the absence of a core layer, through holes 2 d can be made by laser or photolithographic processing and as a consequence, the through hole pitch (interval between through holes) can be decreased and the bump pitch (interval between bumps) can also be decreased.
- the thickness of the coreless substrate should be 0.2 mm or less; in the first embodiment, it is, for example, between 0.03 mm and 0.05 mm.
- FIG. 14 shows the relation between pad arrangement type and substrate structure type as found by an investigation by the present inventors, based on which the structure of the multilayer wiring substrate 2 of the BGA 9 according to the first embodiment is determined.
- the present invention is intended to provide a multi-pin structure at lower cost; for a multi-pin structure, the through hole pitch and bump pitch must be decreased and for cost reduction, the number of wiring layers of the multilayer wiring substrate 2 must be decreased as far as possible.
- the number of wiring layers can be decreased to create a multi-pin structure by changing the signal pad pitch from 64 ⁇ m to 20 ⁇ m (in the direction of arrow B in FIG. 14 ), so it is necessary to find what conditions are required to realize a signal pad pitch of 20 ⁇ m or so.
- the signal pad pitch can be decreased from 64 ⁇ m to 21 ⁇ m but six wiring layers are required for the coreless substrate (multilayer wiring substrate 2 ).
- the signal pad pitch is 20 ⁇ m (C in FIG. 14 ) and in this case, if the coreless substrate is used , only four wiring layers are required (D in FIG. 14 ). By doing so, the cost of the multilayer wiring substrate 2 can be reduced.
- peripheral arrangement type and two rows are selected for the signal pad arrangement, it is possible to adopt a cored substrate with eight wiring layers; however, in that case, since the substrate has eight wiring layers, cost reduction cannot be achieved.
- the multilayer wiring substrate 2 can be thin and cost reduction can be achieved.
- the multilayer wiring substrate 2 can be thin, the through hole pitch can be as small as 150-200 ⁇ m and the bump pitch can be as small as 100-150 ⁇ m.
- FIG. 5 shows the wiring pattern of the uppermost wiring layer, or a first wiring layer L 1 , nearest to the upper surface 2 a of the multilayer wiring substrate 2 shown in FIG. 2 , in which this wiring layer faces the main surface 1 a of the semiconductor chip 1 where flip-chip coupling is made.
- a plurality of bonding electrodes 2 c are arranged in two rows in the first regions 2 y of the chip mounting area of the upper surface 2 a of the multilayer wiring substrate 2 which are opposite to the peripheral areas of the main surface 1 a of the semiconductor chip 1 .
- an array of power supply and GND bonding electrodes (bonding electrodes 2 m for core power supply and bonding electrodes 2 n for GND as shown in FIG. 9 ) are formed in the second region 2 z inside the first regions 2 y.
- an array of core power supply bonding electrode and GND bonding electrodes 2 n as shown in FIG. 9 are arranged in the second region 2 z near the center of the chip mounting area and in the first regions 2 y around the second region 2 z, a plurality of bonding electrodes 2 c are arranged in two rows.
- the bonding electrodes 2 c in each first region 2 y include a plurality of bonding electrodes 2 k for signals and the bonding electrodes 2 k for signals are separated into inner and outer ones.
- a plurality of signal wirings 2 u drawn inside from the signal bonding electrodes 2 k are each electrically coupled to wiring portions 2 ca ( FIG. 15 ) in another layer through the through holes 2 d and as shown in FIG. 5 , the through holes 2 d are located between each first region 2 y and the second region 2 z.
- the signal wirings 2 u electrically coupled to the outer row of signal bonding electrodes 2 k are drawn outside while the signal wirings 2 u electrically coupled to the inner row of signal bonding electrodes 2 k are drawn inside.
- the lead wirings for the bonding electrodes 2 c in the outer row are drawn outside while the lead wirings for the bonding electrodes 2 c in the inner row are drawn inside. Therefore, as shown in FIG. 9 , the signal wirings 2 u drawn inside from the signal bonding electrodes 2 k in the inner row are each electrically coupled to signal through holes 2 q and these signal through holes 2 q are located between each first region 2 y and the second region 2 z.
- the bonding electrodes 2 c arranged in two rows in each first region 2 y those in the outer row are all signal bonding electrodes 2 k.
- the bonding electrodes 2 c in each first region 2 y include a plurality of GND bonding electrodes 2 n and a plurality of IO power supply bonding electrodes 2 p as well as the signal bonding electrodes 2 k. These GND bonding electrodes 2 n and IO power supply bonding electrodes 2 p all lie in the inner row in the first region 2 y.
- a plurality of GND through holes 2 s electrically coupled to the GND bonding electrodes 2 n through GND wirings 2 w and a plurality of IO power supply through holes 2 t electrically coupled to the IO power supply bonding electrodes 2 p through IO power supply wirings 2 x.
- the GND through holes 2 s and IO power supply through holes 2 t are located between each first region 2 y and the second region 2 z.
- the signal through holes 2 q, GND through holes 2 s, and IO power supply through holes 2 t are located between the first regions 2 y and the second region 2 z.
- a plurality of power supply and GND bonding electrodes lie in the second region 2 z.
- the power supply bonding electrodes are bonding electrodes 2 m for core power supply.
- an array of core power supply bonding electrodes 2 m and GND bonding electrodes 2 n lie in the second region 2 z, in which each core power supply bonding electrode 2 m has a core power supply through hole 2 r through a core power supply wiring 2 v and each GND bonding electrode 2 n has a GND through hole 2 s through a GND wiring 2 w.
- an array of core power supply through holes 2 r and GND through holes 2 s are located in the second region 2 z.
- the through holes 2 d between the first regions 2 y and the second region 2 z (signal through holes 2 q, GND through holes 2 s, IO power supply through holes 2 t ) and the through holes 2 d in the second region 2 z (core power supply through holes 2 r , GND through holes 2 s ) are both spaced at a very small pitch of 150-200 ⁇ m.
- FIG. 6 shows the wiring pattern of a second wiring layer L 2 just under the first wiring layer L 1 of the multilayer wiring substrate 2 .
- it shows the wiring pattern of the second wiring layer from the upper surface 2 a (wiring layer next to the upper surface 2 a ) in the direction from the upper surface 2 a of the multilayer wiring substrate 2 to the lower surface 2 b.
- a large GND plane 2 wa is formed in the second wiring layer L 2 .
- the GND plane 2 wa is electrically coupled to the GND bonding electrodes 2 n in the first layer L 1 through the GND wirings 2 w and GND through holes 2 s.
- a plurality of signal through holes 2 q, IO power supply through holes 2 t, and core power supply through holes 2 r are disposed and isolated from the GND plane 2 wa.
- the reason that the GND plane 2 wa is provided in the second wiring layer L 2 is that the plane, located near the signal wirings 2 u in the first wiring layer L 1 , makes them less susceptible to noise and contributes to stabilization of signals.
- the signal wirings 2 u in the first wiring layer L 1 are less susceptible to noise and ensure stable signals because the GND wirings 2 w and IP power supply wirings 2 x in the first wiring layer L 1 are adjacent to them as shown in FIG. 13 and also the GND plane 2 wa as shown in FIG. 10 lies just under them, namely they are surrounded by power supply and GND members.
- FIG. 7 shows the wiring pattern of a third wiring layer L 3 just under the second wiring layer L 2 of the multilayer wiring substrate 2 .
- it shows the wiring pattern of the third wiring layer from the upper surface 2 a (wiring layer next to the second wiring layer L 2 ) in the direction from the upper surface 2 a of the multilayer wiring substrate 2 to the lower surface 2 b.
- a core power supply plane 2 va lies almost in the center of the third wiring layer L 3 and a plurality of oblong IO power supply planes 2 xa are formed around the plane 2 va .
- the core power supply plane 2 va and IO power supply planes 2 xa are located in the third wiring layer next to (under) the second wiring layer L 2 with the GND plane 2 wa formed thereon, in the direction from the upper surface 2 a of the multilayer wiring substrate 2 to the lower surface 2 b.
- the core power supply plane 2 va is electrically coupled to the core power supply bonding electrodes 2 m in the second region 2 z of the first wiring layer L 1 through the core power supply wirings 2 v and core power supply through holes 2 r .
- the IO power supply planes 2 xa are electrically coupled to the IO power supply bonding electrodes 2 p in the first regions 2 y of the first wiring layer L 1 through the IO power supply wirings 2 x and IO power supply through holes 2 t.
- the GND plane 2 wa electrically coupled to the GND bonding electrodes 2 n in the second region 2 z in the center of the first wiring layer L 1 lies in the second wiring layer L 2 and similarly the core power supply plane 2 va electrically coupled to the core power supply bonding electrodes 2 m in the second region 2 z of the first wiring layer L 1 lies in the third wiring layer L 3 .
- the GND electrodes and power supply electrodes in the first wiring layer L 1 are coupled to different wiring layers, namely the second wiring layer L 2 and third wiring layer L 3 respectively.
- each through hole 2 d and the through hole pitch are small; more specifically it is possible because through holes 2 d can be densely made in the second region 2 z of the first wiring layer L 1 by laser processing.
- a plurality of signal wirings 2 u are provided in the third wiring layer L 3 .
- the signal wirings 2 u in the third wiring layer L 3 are electrically coupled to the signal bonding electrodes 2 k in the first regions 2 y of the first wiring layer L 1 through the signal wirings 2 u and signal through holes 2 q in the first wiring layer L 1 .
- the signal wirings 2 u in the third wiring layer L 3 (another layer) electrically coupled to the signal wirings 2 u drawn inside through the signal through holes 2 q are drawn outside in the third wiring layer L 3 . Therefore, the signal through holes 2 q are all located outside the second region 2 z in the first wiring layer L 1 .
- the signal wirings 2 u are arranged in pairs and oblong IO power supply planes 2 xa are located on both sides of each pair of signal wirings 2 u.
- the BGA 9 according to the first embodiment is a multi-pin semiconductor device with not less than hundreds of pins.
- this semiconductor device in order to arrange, in a small number of wiring layers, signal wirings 2 u to be connected to a desired number of signal pins, signal through holes 2 q are also provided inside the first regions 2 y (between the first regions 2 y and second region 2 z ) so as to permit the signal wirings 2 u to be drawn outside in another wiring layer (in this case, the third wiring layer L 3 ), because the number of signal wirings 2 u arranged only outside the first regions 2 y in the first wiring layer L 1 is insufficient.
- This device structure permits not less than hundreds of pins to be arranged in a small number of wiring layers.
- the device uses a thin substrate such as a coreless substrate so that the diameter of through holes 2 d in the second region 2 z under the chip and the through hole pitch can be small enough to obtain space for the formation of signal through holes 2 q between the first regions 2 y and second region 2 z of the first wiring layer L 1 .
- the presence of signal through holes 2 q between the first regions 2 y and second region 2 z makes it possible to realize a semiconductor device in which not less than hundreds of pins are arranged in a small number of wiring layers as mentioned above.
- FIG. 8 shows the wiring pattern of a fourth wiring layer L 4 just under the third wiring layer L 3 of the multilayer wiring substrate 2 .
- it shows the wiring pattern of the fourth wiring layer from the upper surface 2 a (wiring layer next to the third wiring layer L 3 ) in the direction from the upper surface 2 a of the multilayer wiring substrate 2 to the lower surface 2 b.
- a GND plane 2 wa electrically coupled to the GND planes 2 wa in the second wiring layer L 2 through the GND through holes 2 s and a plurality of core power supply planes 2 va electrically coupled to the core power supply planes 2 va in the third wiring layer L 3 through the core power supply through holes 2 r are formed and lands 2 j for GND, those for power supply, and those for signals which are electrically coupled to the relevant planes are provided.
- Each land 2 j is coupled to a solder ball 5 which is an external terminal for the BGA 9 .
- the GND plane 2 wa in the fourth wiring layer L 4 is electrically coupled to the GND plane 2 wa in the second wiring layer L 2 only through the GND through holes 2 s. This stabilizes the GND potential of the multilayer wiring substrate 2 .
- FIGS. 15 and 16 show wiring portions 2 ca exposed in an opening 2 ga of the solder resist film 2 g and bonding electrodes 2 c, in which FIG. 15 illustrates bonding electrodes 2 c for peripheral pads in a first region 2 y of the upper surface 2 a and FIG. 16 illustrates bonding electrodes 2 c for area arrangement in the second region 2 z of the upper surface 2 a .
- a plating layer 2 cb overlying the bonding electrode 2 c is brought into contact with a solder bump 8 .
- solder bumps 8 are, for example, cylindrical to enable flip-chip coupling with a small signal pad pitch of 20 ⁇ m.
- FIGS. 17 and 18 show an example of the relation between bump size on the chip and minimum spacing between wirings on the substrate.
- solder bump size A and spacing B between wirings (bonding electrodes 2 C) as shown in FIG. 17 the relation of A ⁇ B (bump size ⁇ spacing) exists so that when a solder bump shifts as shown in FIG. 18 , gap C is produced between the solder bump 8 and the bonding electrode 2 c, thereby preventing an electric short circuit.
- the plural signal bonding electrodes 2 k in the regions (first regions 2 y ) of the upper surface 2 a of the multilayer wiring substrate 2 which are opposite to the peripheral areas of the chip are separated into inner and outer ones and the signal through holes 2 q coupled to the signal wirings 2 u drawn inside are located between the first regions 2 y with rows of signal bonding electrodes 2 k and the center second region 2 z with core power supply bonding electrodes 2 m and GND bonding electrodes 2 n, permitting chip pads to be arranged densely.
- the diameter of through holes 2 d in the second region 2 z under the chip and the through hole pitch can be small enough to obtain space for the formation of plural signal through holes 2 q between the first regions 2 y and second region 2 z of the upper surface 2 a (first wiring layer L 1 ).
- the signal bonding electrodes 2 k in the first regions 2 y can be separated into inner and outer ones and the chip pad pitch can be thus decreased and the signal bonding electrodes 2 k can be disposed for peripheral arrangement (in the first regions 2 y ) and the core power supply bonding electrodes 2 m and GND bonding electrodes 2 n can be disposed for area arrangement (in the second region 2 z ).
- chip size can be reduced without an increase in the number of layers in the multilayer wiring substrate 2 .
- the cost of the multi-pin BGA 9 can be decreased and the need for chip shrinkage can be met.
- a flip-chip semiconductor device is more costly than a wire-bonded semiconductor device. In this sense, it is very meaningful that the cost of the BGA 9 according to the first embodiment as a flip-chip semiconductor device is reduced.
- the core power supplies in the second region 2 z are coupled through the core power supply through holes 2 r to the core power supply lands 2 j in the fourth wiring layer L 4 , so more pins can be provided without an increase in the number of wiring layers to realize a multi-pin structure.
- a plurality of core power supply bonding electrodes 2 m can be arranged in the second region 2 z near the center of the semiconductor chip 1 , so power supply stabilization can be achieved in the multi-pin BGA 9 with a shrunk chip.
- FIG. 19 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a first variation of the first embodiment of the invention.
- the multilayer wiring substrate 2 of the first variation as shown in FIG. 19 is an wiring substrate with a core layer 2 h, in which the thickness of the substrate is thin since the core layer 2 h is thin.
- the thickness of the multilayer wiring substrate 2 with the core layer 2 h is about 0.4 mm to 0.6 mm or so; this substrate has an improved rigidity though its thickness is larger than the coreless substrate described above.
- a thin multilayer wiring substrate 2 with a core layer 2 h refers to a multilayer wiring substrate with a core layer 2 h having a thickness not less than 0.4 and not more than 1.0 mm.
- Such a thin multilayer wiring substrate 2 with a core layer 2 h is used, for example, as an in-vehicle semiconductor package substrate which is relatively large (20-35 mm square) and should be highly reliable.
- the abovementioned coreless substrate according to the first embodiment which has a relatively small package size (10-20 mm square) is used as a semiconductor package substrate for a mobile device such as a mobile phone.
- FIG. 20 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a second variation of the first embodiment of the invention.
- gap D between the semiconductor chip 1 and the solder resist film 2 g of the multilayer wiring substrate 2 is as small as 5 ⁇ m and underfill resin 6 ( FIG. 2 ) is not filled therein because it may be difficult to fill the underfill resin 6 therein.
- a plating layer 2 cb of nickel-gold or the like lies on the surface of a wiring portion 2 ca.
- FIG. 21 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a third variation of the first embodiment of the invention.
- the flip-chip structure of the semiconductor device of the third variation as shown in FIG. 21 has no solder resist film 2 g as shown in FIG. 20 in the multilayer wiring substrate 2 ; instead it has an insulating film 2 gb with a height equivalent to the height of the wiring portion 2 ca to planarize the substrate surface.
- the gap between the multilayer wiring substrate 2 and the main surface 1 a of the semiconductor chip 1 is as wide as 15 ⁇ m or so and this gap is filled with underfill resin 6 .
- the gap between the multilayer wiring substrate 2 and the main surface 1 a of the semiconductor chip 1 is wide enough to reduce the possibility of inhomogeneous filling of underfill resin 6 .
- FIG. 22 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fourth variation of the first embodiment of the invention.
- the solder resist film 2 g lies not all over the chip mounting area of the upper surface 2 a of the multilayer wiring substrate 2 , namely the solder resist film 2 g lies only outside the chip mounting area.
- a plating layer 2 cb of nickel-gold or the like is formed all over the exposed portion of each wiring portion 2 ca.
- the gap between the multilayer wiring substrate 2 and the main surface 1 a of the semiconductor chip 1 is wider, thereby reducing the possibility of inhomogeneous filling of the underfill resin 6 .
- FIG. 23 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fifth variation of the first embodiment of the invention.
- the flip-chip structure of the semiconductor device of the fifth variation shown in FIG. 23 is produced as follows: after a semiconductor chip 1 with solder bumps 8 is placed on bonding electrodes 2 c, the solder bumps are melted, then underfill resin 6 is filled there, and heat is applied to harden the underfill resin 6 .
- FIG. 24 is a plan view of the wiring substrate built in the semiconductor device according to a sixth variation of the first embodiment of the invention and FIG. 25 is a sectional view of an example of the semiconductor device using the wiring substrate shown in FIG. 24 .
- the semiconductor device of the sixth variation shown in FIG. 25 is a BGA 10 which uses gold bumps 11 for flip-chip coupling, with the surfaces of the bonding electrodes 2 c ( FIG. 24 ) tinned.
- the solder resist film 2 g lies on the upper surface 2 a of the multilayer wiring substrate 2 ( FIG. 25 ) except the chip mounting area, specifically the solder resist film 2 g is formed around the chip mounting area. Therefore, in the BGA 10 as well, the underfill resin is filled homogeneously as shown in FIG. 25 .
- An opening 2 ga in the solder resist film 2 g can stop a flow of underfill resin 6 .
- FIG. 26 is a plan view showing an example of the relation between the bonding electrode shape of the wiring substrate and the electrode pads of the semiconductor chip in the semiconductor device according to a seventh variation of the first embodiment of the invention.
- the shape of the solder bumps 8 of the multilayer wiring substrate 2 for flip-chip coupling is a rectangle along the direction in which the wiring portions 2 ca to be coupled to the solder bumps 8 extend.
- the solder bumps 8 can be adequately coupled to them for flip-chip coupling.
- FIG. 27 is a fragmentary enlarged sectional view of the semiconductor device according to an eighth variation of the first embodiment of the invention.
- the semiconductor device of the eighth variation shown in FIG. 27 is a BGA 13 in which the semiconductor chip 1 is thin and solder bumps 12 for stacking are laid around the semiconductor chip 1 on the upper surface 2 a of the multilayer wiring substrate 2 and coupled to the bonding electrodes 2 c.
- encapsulating resin can flow to the back surface 1 b of the semiconductor chip 1 so that the semiconductor chip 1 is buried in an encapsulant 15 , namely the multilayer wiring substrate 2 houses the chip.
- the upper surface 2 gc which connects the encapsulant 15 covering the semiconductor chip 1 and the solder resist film 2 g is planarized so that the solder bumps 12 for stacking protrude from the upper surface 2 gc.
- FIG. 28 is a fragmentary enlarged sectional view of the semiconductor device according to a ninth variation of the first embodiment of the invention.
- the semiconductor device of the ninth variation shown in FIG. 28 is a POP (Package On Package) 14 which has two units of the BGA 13 shown in FIG. 28 stacked one upon the other.
- POP Package On Package
- a BGA 13 which houses a thin semiconductor chip 1 is produced and two or more units of the BGA 13 are stacked to make up a POP 14 .
- FIG. 29 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L 1 ) of the wiring substrate built in the semiconductor device according to a second embodiment of the invention
- FIG. 30 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L 2 ) of the wiring substrate built in the semiconductor device according to the second embodiment
- FIG. 31 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L 3 ) of the wiring substrate built in the semiconductor device according to the second embodiment of the invention.
- FIG. 32 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L 4 ) of the wiring substrate built in the semiconductor device according to the second embodiment.
- FIG. 33 is a fragmentary enlarged plan view of part A of FIG. 29 ;
- FIG. 34 is a fragmentary enlarged plan view of part A of FIG. 30 ;
- FIG. 35 is a fragmentary enlarged plan view of part A of FIG. 31 ;
- FIG. 36 is a fragmentary enlarged plan view of part A of FIG. 32 ;
- FIG. 37 is a fragmentary enlarged plan view of part A of the wiring substrate built in the semiconductor device according to a variation of the second embodiment.
- the second embodiment concerns a semiconductor device having a multilayer wiring substrate 2 in which the number of pins is smaller than in the BGA 9 according to the first embodiment.
- the number of core power supply bonding electrodes 2 m and the number of GND bonding electrodes 2 n as shown in FIG. 33 are smaller than in the first embodiment, resulting in a decrease in the number of pins of the semiconductor device.
- the number of bonding electrodes 2 c (core power supply bonding electrodes 2 m and GND bonding electrodes 2 n ) in the second region 2 z of the first wiring layer L 1 is smaller than the number of bonding electrodes 2 c in the second region 2 z of the multilayer wiring substrate 2 of the BGA 9 according to the first embodiment.
- FIGS. 29 and 33 illustrate the wiring pattern of the first wiring layer L 1 ;
- FIGS. 30 and 34 illustrate that of the second wiring layer L 2 ;
- FIGS. 31 and 35 illustrate that of the third wiring layer L 3 ;
- FIGS. 32 and 36 illustrate that of the fourth wiring layer L 4 .
- the wiring pattern of each first region 2 y and that of the area between each first regions 2 y and the second region 2 z are the same as in the multilayer wiring substrate 2 according to the first embodiment.
- the difference from the first embodiment is that in the wiring pattern of the first wiring layer L 1 shown in FIG. 29 , the number of bonding electrodes 2 c in the second region 2 z is smaller than in the first embodiment, resulting in a decrease in the number of pins of the semiconductor device.
- the GND bonding electrodes 2 n in the second region 2 z are electrically coupled to a GND plane 2 wa in the second wiring layer L 2 shown in FIGS. 30 and 34 through GND wirings 2 w and GND through holes 2 s.
- the core power supply bonding electrodes 2 m in the second region 2 z of the first wiring layer L 1 are electrically coupled to core power supply planes 2 va in the third wiring layer L 3 shown in FIGS. 31 and 35 through core power supply wirings 2 v and core power supply through holes 2 r.
- the fourth wiring layer L 4 there are a GND plane 2 wa electrically coupled to the GND plane 2 wa in the second wiring layer L 2 through the GND through holes 2 s, and a plurality of core power supply planes 2 va ( 2 j ) coupled to the core power supply plane 2 va in the third wiring layer L 3 through the core power supply through holes 2 r , along with lands 2 j for GND, power supply and signals which are electrically coupled to the relevant planes.
- the signal wirings 2 u in the third wiring layer L 3 (another layer) electrically coupled to the signal wirings 2 u drawn inside through the signal through holes 2 q are drawn outside in the third wiring layer L 3 . Therefore, the signal through holes 2 q are all located outside the second region 2 z in the first wiring layer L 1 .
- the signal wirings 2 u are arranged in pairs and oblong IO power supply planes 2 xa are located on both sides of each pair of signal wirings 2 u.
- the semiconductor device according to the second embodiment is a multi-pin semiconductor device.
- this semiconductor device in order to arrange, in a small number of wiring layers, signal wirings 2 u to be connected to a desired number of signal pins, signal through holes 2 q are also provided inside the first regions 2 y (between the first regions 2 y and second region 2 z ) so as to permit the signal wirings 2 u to be drawn outside in another wiring layer (in this case, the third wiring layer L 3 ), because the number of signal wirings 2 u arranged only outside the first regions 2 y in the first wiring layer L 1 is insufficient.
- This device structure permits a lot of pins to be arranged in a small number of wiring layers.
- the device uses a thin substrate such as a coreless substrate so that the diameter of through holes 2 d in the second region 2 z under the chip and the through hole pitch can be small enough to obtain space for the formation of signal through holes 2 q between the first regions 2 y and second region 2 z of the first wiring layer L 1 .
- the presence of signal through holes 2 q between the first regions 2 y and second region 2 z makes it possible to realize a semiconductor device in which a lot of pins are arranged in a small number of wiring layers.
- the other details of the wiring patterns of the first wiring layer L 1 , second wiring layer L 2 , third wiring layer L 3 , and fourth wiring layer L 4 in the second embodiment are the same as those in the first embodiment and description thereof is omitted here.
- the advantageous effect achieved by the semiconductor device having the multilayer wiring substrate 2 according to the second embodiment is the same as that achieved by the semiconductor device (BGA 9 ) according to the first embodiment and description thereof is omitted here.
- FIG. 37 shows the structure of an wiring substrate as a variation of the second embodiment, in which a plurality of bonding electrodes 2 c in each first region 2 y of the first wiring layer L 1 are arranged in a staggered pattern. Specifically, the two rows of bonding electrodes 2 c in each first region 2 y of the first wiring layer L 1 are arranged in a staggered pattern. In this case, the two rows of electrode pads 1 c in the peripheral areas of the main surface 1 a of the semiconductor chip 1 are also arranged in a staggered pattern so as to permit flip-chip coupling.
- the pitch between bonding electrodes 2 c can be 20 ⁇ m at a line/space ratio of 20 ⁇ m/20 ⁇ m.
- the pad pitch can be decreased and the number of pins in the semiconductor device can be increased.
- the first embodiment has been described on the assumption that the bonding electrodes 2 c in the first regions 2 y in the peripheral areas of the upper surface 2 a of the multilayer wiring substrate 2 are arranged in parallel (not staggered)
- the bonding electrodes 2 c in the first regions 2 y (including the second region 2 z ) of the upper surface 2 a may also be arranged in a staggered pattern in the multilayer wiring substrate 2 of the BGA 9 according to the first embodiment.
- the bonding electrodes 2 c in the first regions 2 y of the upper surface 2 a of the multilayer wiring substrate 2 of the BGA 9 according to the first embodiment are arranged in a staggered pattern, in the BGA 9 the pad pitch can be further decreased and the number of pins can be further increased.
- the stiffener ring 7 is omissible. If the stiffener ring 7 is not attached, the heat spreader 4 is bonded only to the back surface 1 b of the semiconductor chip 1 through heat-radiating resin 3 or the like.
- the present invention is suitable for electronic devices which adopt a flip-chip coupling method.
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- Computer Hardware Design (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
Description
- The disclosure of Japanese Patent Application No. 2010-5403 filed on Jan. 14, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
- The present invention relates to semiconductor devices and more particularly to technology for a semiconductor device including a semiconductor chip flip-chip coupled to a wiring substrate.
- A semiconductor device having a multilayer substrate is disclosed in which a plurality of connecting terminals to which bumps for connection of an LSI chip are fixed are exposed on one outermost layer of the multilayer substrate and solder balls are fixed over metal pads on the other outermost layer to make up a ball grid array (BGA) structure for connection to a motherboard (for example, see Japanese Unexamined Patent Publication No. 2006-73622).
- In recent years, in the category of multi-pin semiconductor devices (semiconductor packages), demand for smaller semiconductor chips (shrinkage in size) has been growing for the purpose of cost reduction. This demand is based on the idea that the number of semiconductor chips obtained from a single wafer should be increased by shrinkage in the size of each semiconductor chip (hereinafter called simply “chip”) in order to reduce the cost of multi-pin semiconductor devices.
- When priority is given to the multi-pin structure or package size, the BGA (ball grid array) substrate type is selected rather than the lead frame type. In this case, the wiring substrate used here is often a multilayer substrate because of the multi-pin structure. In addition, in the case of multi-pin semiconductor devices, package size depends on the number of pins, so if the chip is shrunk and the number of pins remains unchanged, the interval between pads (pad pitch) should be smaller. This may raise a problem that wirings cannot pass between pads.
- In other words , for a multi-pin semiconductor device, chip shrinkage may pose a problem that the pad pitch is too small for wirings to pass between pads.
- On the other hand, if the number of pads is increased due to the multi-pin structure and the number of layers of the multilayer substrate is unchanged, the problem may be somewhat relieved by area arrangement (central arrangement) of pads. However, if that is the case, signal wirings to be coupled to signal pads located on the periphery of the main surface of the chip must be drawn inside (toward the center of the chip) and coupled via through holes to another layer and drawn out from the other layer.
- Generally, in a semiconductor chip with a larger number of pads, a multilayer wiring substrate is used and area arrangement of pads is adopted. For example, in some multilayer wiring substrates, a total of six wiring layers, three above the core layer and three below it, are formed by a build-up technique or the like and area arrangement of chip pads is also adopted.
- However, in the case of multi-pin semiconductor devices, since core power supply bonding electrodes are densely arranged near the chip center, it is not easy to provide space for through holes for electrical coupling to the signal wirings drawn inside in the multilayer wiring substrate.
- Therefore, for the multi-pin structure, the number of layers of the multilayer wiring substrate must be increased to arrange wirings properly. This would lead to rise in semiconductor device cost.
- Furthermore, when the chip size is reduced, the pad pitch should be decreased, maybe making it difficult for wirings to pass between pads as mentioned above. Thus the problem here is that area arrangement of pads is impossible. On the other hand, though the use of the redistribution technique makes it possible to adopt area arrangement of pads, it involves difficulty in design and necessitates a chip cost increase. Since a rise in the chip cost leads to a rise in the semiconductor device cost, it is not a good solution.
- The BGA semiconductor device described in the above patent document also has a problem that if the number of pins is to be increased, the number of wiring layers of the multilayer substrate must be increased, leading to a rise in the semiconductor device cost.
- The present invention has been made in view of the above problem and an object thereof is to provide a technique which reduces the cost of multi-pin semiconductor devices.
- Another object of the invention is to provide a technique which enables area arrangement of pads in a semiconductor device with a shrunk chip.
- The above and further objects and novel features of the invention will more fully appear from the following detailed description in this specification and the accompanying drawings.
- Typical aspects of the present invention which are disclosed herein are briefly outlined below.
- According to one aspect of the present invention, a semiconductor device which uses a multilayer wiring substrate having an upper surface and a lower surface opposite to the upper surface with a semiconductor chip flip-chip mounted on the upper surface includes the semiconductor chip having a main surface and a back surface opposite to the main surface with a plurality of electrode pads formed on the main surface, the multilayer wiring substrate in which a plurality of bonding electrodes are formed in a plurality of rows on the upper surface in a first region corresponding to a peripheral area of the main surface of the semiconductor chip and an array of fixed potential (power supply and GND) bonding electrodes are formed in a second region inside the first region, and a plurality of external terminals provided on the lower surface of the multilayer wiring substrate. Here, a plurality of signal bonding electrodes among the bonding electrodes in the first region of the upper surface of the multilayer wiring substrate are separated into inner and outer ones; each of a plurality of signal wirings drawn inside from the signal bonding electrodes is electrically coupled to an wiring portion in another wiring layer through a through hole; and the through holes are located between the first region and the second region.
- According to another aspect of the invention, a semiconductor device which uses a multilayer wiring substrate having an upper surface and a lower surface opposite to the upper surface with a semiconductor chip flip-chip mounted on the upper surface includes the semiconductor chip having a main surface and a back surface opposite to the main surface with a plurality of electrode pads formed on the main surface, the multilayer wiring substrate in which a plurality of bonding electrodes are formed in two rows on the upper surface in a first region corresponding to a peripheral area of the main surface of the semiconductor chip and an array of fixed potential (power supply and GND) bonding electrodes are formed in a second region inside the first region, and a plurality of external terminals provided on the lower surface of the multilayer wiring substrate. Here, a plurality of signal bonding electrodes among the bonding electrodes in the first region of the upper surface of the multilayer wiring substrate are separated into inner and outer ones; each of a plurality of signal wirings drawn inside from the signal bonding electrodes is electrically coupled to an wiring portion in another wiring layer through a through hole; and the through holes are located between the first region and the second region.
- The advantageous effect achieved by preferred embodiments of the invention is briefly outlined below.
- In a multi-pin semiconductor device, the chip can be shrunk without the need for an increase in the number of layers in its multilayer wiring substrate, so that the cost of the semiconductor device can be reduced.
- In a multi-pin semiconductor device with a shrunk chip, area arrangement of semiconductor chip pads is possible.
-
FIG. 1 is a partially broken perspective view of the structure of a semiconductor device according to a first embodiment of the invention; -
FIG. 2 is a sectional view of the semiconductor device shown inFIG. 1 ; -
FIG. 3 is a fragmentary enlarged sectional view of part A ofFIG. 2 ; -
FIG. 4 is a plan view of an example of the electrode pad arrangement of the semiconductor chip mounted in the semiconductor device shown inFIG. 1 ; -
FIG. 5 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L1) of the wiring substrate built in the semiconductor device shown inFIG. 1 ; -
FIG. 6 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L2) of the wiring substrate built in the semiconductor device shown inFIG. 1 ; -
FIG. 7 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L3) of the wiring substrate built in the semiconductor device shown inFIG. 1 ; -
FIG. 8 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L4) of the wiring substrate built in the semiconductor device shown inFIG. 1 ; -
FIG. 9 is a fragmentary enlarged plan view of part A ofFIG. 5 ; -
FIG. 10 is a fragmentary enlarged plan view of part A ofFIG. 6 ; -
FIG. 11 is a fragmentary enlarged plan view of part A ofFIG. 7 ; -
FIG. 12 is a fragmentary enlarged plan view of part A ofFIG. 8 ; -
FIG. 13 is a fragmentary enlarged plan view of part B ofFIG. 5 ; -
FIG. 14 shows data on the relation between pad arrangement type and substrate structure type in the semiconductor chip mounted in the semiconductor device shown inFIG. 1 ; -
FIG. 15 is a fragmentary enlarged sectional view combined with a fragmentary enlarged plan view, showing the positional relation between the bonding electrodes and bumps of the wiring substrate for peripheral pads and the electrode pads of the semiconductor chip in the semiconductor device according to the first embodiment; -
FIG. 16 is a fragmentary enlarged plan view showing the shape of bonding electrodes of the wiring substrate for central pads in the semiconductor device according to the first embodiment; -
FIG. 17 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment; -
FIG. 18 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment; -
FIG. 19 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a first variation of the first embodiment; -
FIG. 20 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a second variation of the first embodiment; -
FIG. 21 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a third variation of the first embodiment; -
FIG. 22 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fourth variation of the first embodiment; -
FIG. 23 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fifth variation of the first embodiment; -
FIG. 24 is a plan view of the wiring substrate built in the semiconductor device according to a sixth variation of the first embodiment; -
FIG. 25 is a sectional view of an example of the semiconductor device using the wiring substrate shown inFIG. 24 ; -
FIG. 26 is a plan view showing an example of the relation between the bonding electrode shape of the wiring substrate and the electrode pads of the semiconductor chip in the semiconductor device according to a seventh variation of the first embodiment; -
FIG. 27 is a fragmentary enlarged sectional view of the semiconductor device according to an eighth variation of the first embodiment; -
FIG. 28 is a fragmentary enlarged sectional view of the semiconductor device according to a ninth variation of the first embodiment; -
FIG. 29 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L1) of the wiring substrate built in the semiconductor device according to a second embodiment of the invention; -
FIG. 30 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L2) of the wiring substrate built in the semiconductor device according to the second embodiment; -
FIG. 31 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L3) of the wiring substrate built in the semiconductor device according to the second embodiment; -
FIG. 32 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L4) of the wiring substrate built in the semiconductor device according to the second embodiment; -
FIG. 33 is a fragmentary enlarged plan view of part A ofFIG. 29 ; -
FIG. 34 is a fragmentary enlarged plan view of part A ofFIG. 30 ; -
FIG. 35 is a fragmentary enlarged plan view of part A ofFIG. 31 ; -
FIG. 36 is a fragmentary enlarged plan view of part A ofFIG. 32 ; and -
FIG. 37 is a fragmentary enlarged plan view of part A of the wiring substrate built in the semiconductor device according to a variation of the second embodiment. - In connection with the preferred embodiments described below, the same or similar explanations will not be repeated except when necessary.
- Descriptions of the preferred embodiments will be made below separately or in different sections as necessary, but such descriptions are not irrelevant to each other unless otherwise specified. One description may be, in whole or in part, a variation or a detailed or supplementary form of another.
- Also, in the preferred embodiments described below, even when a numerical datum for an element (the number of pieces, numerical value, quantity, range, etc.) is indicated by a specific numerical value, it is not limited to the specific numerical value unless otherwise specified or theoretically limited to that numerical value; it may be larger or smaller than the specific numerical value.
- In the preferred embodiments described below, it is needles to say that their constituent elements (including constituent steps) are not necessarily essential unless otherwise specified or theoretically essential.
- In the preferred embodiments described below, when an element is described as “comprising A” or “having A” or “including A”, a component other than A is not excluded unless it is explicitly stated that the element only includes A or otherwise specified.
- Similarly, in the preferred embodiments described below, when a specific form or positional relation is indicated for an element, it should be interpreted to include a form or positional relation which is virtually equivalent or similar to the specific form or positional relation unless otherwise specified or unless it should be theoretically limited to the specific form or positional relation. The same can be said of numerical values or ranges as mentioned above.
- Next, the preferred embodiments will be described in detail referring to the accompanying drawings. Basically in all the drawings that illustrate the preferred embodiments, elements with like functions are designated by like reference numerals and repeated descriptions thereof are omitted.
-
FIG. 1 is a partially broken perspective view of the structure of a semiconductor device according to a first embodiment of the invention;FIG. 2 is a sectional view of the semiconductor device shown inFIG. 1 ;FIG. 3 is a fragmentary enlarged sectional view of part A ofFIG. 2 ; andFIG. 4 is a plan view of an example of the electrode pad arrangement of the semiconductor chip mounted in the semiconductor device shown inFIG. 1 .FIG. 5 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L1) of the wiring substrate built in the semiconductor device shown inFIG. 1 ;FIG. 6 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L2) of the wiring substrate built in the semiconductor device shown inFIG. 1 ;FIG. 7 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L3) of the wiring substrate built in the semiconductor device shown inFIG. 1 ; andFIG. 8 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L4) of the wiring substrate built in the semiconductor device shown inFIG. 1 .FIG. 9 is a fragmentary enlarged plan view of part A ofFIG. 5 ;FIG. 10 is a fragmentary enlarged plan view of part A ofFIG. 6 ;FIG. 11 is a fragmentary enlarged plan view of part A ofFIG. 7 ;FIG. 12 is a fragmentary enlarged plan view of part A ofFIG. 8 ; andFIG. 13 is a fragmentary enlarged plan view of part B ofFIG. 5 .FIG. 14 shows data on the relation between pad arrangement type and substrate structure type in the semiconductor chip mounted in the semiconductor device shown inFIG. 1 ;FIG. 15 is a fragmentary enlarged sectional view combined with a fragmentary enlarged plan view, showing the positional relation between the bonding electrodes and bumps of the wiring substrate for peripheral pads and the electrode pads of the semiconductor chip in the semiconductor device according to the first embodiment;FIG. 16 is a fragmentary enlarged plan view showing the shape of bonding electrodes of the wiring substrate for central pads in the semiconductor device according to the first embodiment;FIG. 17 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment; andFIG. 18 is a plan view showing an example of the relation between the bump size and the bonding electrode size of the substrate at a flip-chip joint in the semiconductor device according to the first embodiment. - The semiconductor device according to the first embodiment as shown in
FIGS. 1 and 2 is a semiconductor package in which asemiconductor chip 1 is flip-chip mounted over theupper surface 2 a of an wiring substrate by soldering. In this first embodiment , it is aBGA 9 in which a plurality ofsolder balls 5 as external terminals are arranged in a grid pattern on thelower surface 2 b of the wiring substrate. In other words, the semiconductor device according to the first embodiment is a flip-chip BGA 9; for example, it may be a multi-pin semiconductor package with not less than hundreds of pins as external terminals. - Details of the
BGA 9 are explained below. TheBGA 9 includes: amultilayer wiring substrate 2 having anupper surface 2 a and alower surface 2 b opposite to theupper surface 2 a; asemiconductor chip 1 which has amain surface 1 a and aback surface 1 b opposite to themain surface 1 a and is flip-chip mounted over theupper surface 2 a of themultilayer wiring substrate 2; and an array ofsolder balls 5 as external terminals disposed on thelower surface 2 b of themultilayer wiring substrate 2. - Here, the
semiconductor chip 1, having a plurality ofelectrode pads 1 c as surface electrodes formed on its main surface la, is flip-chip (face-down) mounted over theupper surface 2 a of themultilayer wiring substrate 2. In other words, thesemiconductor chip 1 is mounted over themultilayer wiring substrate 2 with itsmain surface 1 a facing theupper surface 2 a of themultilayer wiring substrate 2. Here, thesemiconductor chip 1 is electrically coupled to themultilayer wiring substrate 2 by soldering, in which they are flip-chip coupled through a plurality of solder bumps 8. - Also, as shown in
FIG. 5 , on theupper surface 2 a of the multilayer wiring substrate 2 (BGA substrate), a plurality ofbonding electrodes 2 c lie in a region where thesemiconductor chip 1 is to be flip-chip mounted. More specifically, theelectrode pads 1 c of thesemiconductor chip 1 and thebonding electrodes 2 c for flip-chip coupling through the solder bumps 8 are located in the chip mounting area of theupper surface 2 a of themultilayer wiring substrate 2. - A plurality of
bonding electrodes 2 c are arranged in two rows infirst regions 2 y of the chip mounting area of theupper surface 2 a of themultilayer wiring substrate 2 which are opposite to the peripheral areas of themain surface 1 a of thesemiconductor chip 1. Also, an array of power supply and GND bonding electrodes (bonding electrodes 2 m for core power supply andbonding electrodes 2 n for GND) are formed in asecond region 2 z inside thefirst regions 2 y. Here, power supply and GND refer to operating electric potentials supplied to the integrated circuit of thesemiconductor chip 1, in which power supply potential is, for example, 3.0 V for an external power supply and 1.5 V for an internal power supply (core power supply) and GND potential is 0 V (grounding potential). - More specifically, an array of power supply and GND bonding electrodes are arranged in the
second region 2 z near the center of the chip mounting area of theupper surface 2 a of themultilayer wiring substrate 2. Thefirst regions 2 y are located around thesecond region 2 z, in which a plurality ofbonding electrodes 2 c are arranged in two rows in each of thefirst regions 2 y. - On the other hand, as shown in
FIG. 2 , an array oflands 2 j are arranged on thelower surface 2 b of themultilayer wiring substrate 2 , with asolder ball 5 as an external terminal coupled to eachland 2 j. - The flip chip joints, lying between the
multilayer wiring substrate 2 and thesemiconductor chip 1, and their surroundings are filled withunderfill resin 6 to solidify the flip chip joints for protection. - Furthermore, a
stiffener ring 7 is attached to the periphery of theupper surface 2 a of themultilayer wiring substrate 2 in a way to surround thesemiconductor chip 1. Thestiffener ring 7 is bonded to themultilayer wiring substrate 2 with a ring-shaped tape 7 a. Aheat spreader 4 is provided over thestiffener ring 7. Theheat spreader 4 is joined to thestiffener ring 7 and theback surface 1 b of thesemiconductor chip 1 through heat-radiatingresin 3 on thesemiconductor chip 1 and an adhesive agent (for example, tape material) 7 b between thestiffener ring 7 andheat spreader 4. - Consequently, heat generated from the semiconductor chip is transferred to the
heat spreader 4 through the heat-radiatingresin 3 and dissipated out from theheat spreader 4 and meanwhile the heat is also transferred to themultilayer wiring substrate 2 through the solder bumps 8, then from thesolder balls 5 to the mounting substrate. Also the heat is transferred from theheat spreader 4 through theadhesive agent 7 b andstiffener ring 7 to themultilayer wiring substrate 2, from which it is transferred through thesolder balls 5 to the mounting substrate and finally dissipated. - As shown in
FIG. 3 , themultilayer wiring substrate 2 of theBGA 9 according to the first embodiment is a coreless substrate without acore layer 2 h (FIG. 19 ) as a base layer, in which it includes abuildup layer 2 f, a plurality ofbonding electrodes 2 c formed on the front surface of thebuildup layer 2 f (upper surface 2 a of the multilayer wiring substrate 2), a plurality oflands 2 j formed on the back surface of thebuildup layer 2 f (lower surface 2 b of the multilayer wiring substrate 2), through holes (wirings) 2 d for electrically coupling thebonding electrodes 2 c on the front surface to thelands 2 j on the back surface,internal wirings 2 e in thebuildup layer 2 f and so on. - Solder resist
film 2 g as insulator lies around thebonding electrodes 2 c and around thelands 2 j. - The
bonding electrodes 2 c on theupper surface 2 a and thecorresponding lands 2 j on thelower surface 2 b are electrically coupled through the through holes (wirings) 2 d, viahole wirings 2 i (FIG. 2 ) orinternal wiring 2 e in thebuildup layer 2 f. - As shown in
FIG. 4 , thesemiconductor chip 1 is, for example, made of silicon with theelectrode pads 1 c as surface electrodes formed on itsmain surface 1 a. In the peripheral areas of the main surface la, two rows ofelectrode pads 1 c are located along each side and arrays ofelectrode pads 1 c are arranged inside the rows of electrode pads in the peripheral areas. - As shown in
FIG. 2 , theunderfill resin 6 coated between the chip and substrate is, for example, epoxy resin. Thestiffener ring 7 andheat spreader 4 are made of metal with a high thermal conductivity and the solder bumps 8 for flip-chip coupling and thesolder balls 5 as external terminals are, for example, made of a lead-free solder material. - The
bonding electrodes 2 c, viahole wirings 2 i,internal wiring 2 e, and throughholes 2 d of themultilayer wiring substrate 2 are, for example, made of pure copper or copper alloy containing a low percentage (1% or less) of impurity such as aluminum or silicon (Si). - The
multilayer wiring substrate 2 of theBGA 9 according to the first embodiment is a thin coreless substrate without acore layer 2 h (FIG. 19 ). Due to the absence of a core layer, throughholes 2 d can be made by laser or photolithographic processing and as a consequence, the through hole pitch (interval between through holes) can be decreased and the bump pitch (interval between bumps) can also be decreased. The thickness of the coreless substrate should be 0.2 mm or less; in the first embodiment, it is, for example, between 0.03 mm and 0.05 mm. -
FIG. 14 shows the relation between pad arrangement type and substrate structure type as found by an investigation by the present inventors, based on which the structure of themultilayer wiring substrate 2 of theBGA 9 according to the first embodiment is determined. The present invention is intended to provide a multi-pin structure at lower cost; for a multi-pin structure, the through hole pitch and bump pitch must be decreased and for cost reduction, the number of wiring layers of themultilayer wiring substrate 2 must be decreased as far as possible. - If it is possible to make many wiring layers, it would be easy to decrease the through hole pitch or bump pitch; however, this approach cannot be adopted because it is costly.
- As shown in
FIG. 14 , it has been found that the number of wiring layers can be decreased to create a multi-pin structure by changing the signal pad pitch from 64 μm to 20 μm (in the direction of arrow B inFIG. 14 ), so it is necessary to find what conditions are required to realize a signal pad pitch of 20 μm or so. - As shown in
FIG. 14 , when the number of signal pad rows is increased from 4 to 12 (in the direction of arrow A inFIG. 14 ) in the case of area arrangement, the signal pad pitch can be decreased from 64 μm to 21 μm but six wiring layers are required for the coreless substrate (multilayer wiring substrate 2). - So, if peripheral arrangement type and two rows are selected for the signal pad arrangement instead, the signal pad pitch is 20 μm (C in
FIG. 14 ) and in this case, if the coreless substrate is used , only four wiring layers are required (D inFIG. 14 ). By doing so, the cost of themultilayer wiring substrate 2 can be reduced. On the other hand, if peripheral arrangement type and two rows are selected for the signal pad arrangement, it is possible to adopt a cored substrate with eight wiring layers; however, in that case, since the substrate has eight wiring layers, cost reduction cannot be achieved. - Therefore, by selecting peripheral arrangement type with two rows of signal pads and using a coreless substrate with four wiring layers for the
BGA 9 according to the first embodiment, themultilayer wiring substrate 2 can be thin and cost reduction can be achieved. In other words, due to the use of a coreless substrate, themultilayer wiring substrate 2 can be thin, the through hole pitch can be as small as 150-200 μm and the bump pitch can be as small as 100-150 μm. - Consequently it is possible to provide a multi-pin structure with a signal pad pitch of 20 μm or so and also since it uses only four wiring layers, the cost of the
multilayer wiring substrate 2 can be reduced. - Next, the wiring pattern of each of the four wiring layers of the
multilayer wiring substrate 2 according to the first embodiment will be described referring toFIGS. 5 to 13 . -
FIG. 5 shows the wiring pattern of the uppermost wiring layer, or a first wiring layer L1, nearest to theupper surface 2 a of themultilayer wiring substrate 2 shown inFIG. 2 , in which this wiring layer faces themain surface 1 a of thesemiconductor chip 1 where flip-chip coupling is made. In the first wiring layer L1, a plurality ofbonding electrodes 2 c are arranged in two rows in thefirst regions 2 y of the chip mounting area of theupper surface 2 a of themultilayer wiring substrate 2 which are opposite to the peripheral areas of themain surface 1 a of thesemiconductor chip 1. Also, an array of power supply and GND bonding electrodes (bonding electrodes 2 m for core power supply andbonding electrodes 2 n for GND as shown inFIG. 9 ) are formed in thesecond region 2 z inside thefirst regions 2 y. - More specifically, an array of core power supply bonding electrode and
GND bonding electrodes 2 n as shown inFIG. 9 are arranged in thesecond region 2 z near the center of the chip mounting area and in thefirst regions 2 y around thesecond region 2 z, a plurality ofbonding electrodes 2 c are arranged in two rows. - As shown in
FIGS. 9 and 13 , thebonding electrodes 2 c in eachfirst region 2 y include a plurality ofbonding electrodes 2 k for signals and thebonding electrodes 2 k for signals are separated into inner and outer ones. A plurality ofsignal wirings 2 u drawn inside from thesignal bonding electrodes 2 k are each electrically coupled towiring portions 2 ca (FIG. 15 ) in another layer through the throughholes 2 d and as shown inFIG. 5 , the throughholes 2 d are located between eachfirst region 2 y and thesecond region 2 z. - As shown in
FIG. 13 , looking at thesignal bonding electrodes 2 k among thebonding electrodes 2 c in eachfirst region 2 y, so far as the two (inner and outer) rows ofbonding electrodes 2 c are concerned, thesignal wirings 2 u electrically coupled to the outer row ofsignal bonding electrodes 2 k are drawn outside while thesignal wirings 2 u electrically coupled to the inner row ofsignal bonding electrodes 2 k are drawn inside. - In other words , the lead wirings for the
bonding electrodes 2 c in the outer row are drawn outside while the lead wirings for thebonding electrodes 2 c in the inner row are drawn inside. Therefore, as shown inFIG. 9 , thesignal wirings 2 u drawn inside from thesignal bonding electrodes 2 k in the inner row are each electrically coupled to signal throughholes 2 q and these signal throughholes 2 q are located between eachfirst region 2 y and thesecond region 2 z. In this first embodiment, among thebonding electrodes 2 c arranged in two rows in eachfirst region 2 y, those in the outer row are allsignal bonding electrodes 2 k. - As shown in
FIG. 13 , thebonding electrodes 2 c in eachfirst region 2 y include a plurality ofGND bonding electrodes 2 n and a plurality of IO powersupply bonding electrodes 2 p as well as thesignal bonding electrodes 2 k. TheseGND bonding electrodes 2 n and IO powersupply bonding electrodes 2 p all lie in the inner row in thefirst region 2 y. - Also, in a region on the inside of the
first region 2 y there are provided a plurality of GND throughholes 2 s electrically coupled to theGND bonding electrodes 2 n throughGND wirings 2 w and a plurality of IO power supply throughholes 2 t electrically coupled to the IO powersupply bonding electrodes 2 p through IOpower supply wirings 2 x. In other words, the GND throughholes 2 s and IO power supply throughholes 2 t are located between eachfirst region 2 y and thesecond region 2 z. - Therefore, as shown in
FIG. 5 , the signal throughholes 2 q, GND throughholes 2 s, and IO power supply throughholes 2 t are located between thefirst regions 2 y and thesecond region 2 z. - On the other hand, as shown in
FIGS. 5 and 9 , a plurality of power supply and GND bonding electrodes lie in thesecond region 2 z. The power supply bonding electrodes are bondingelectrodes 2 m for core power supply. Specifically, an array of core powersupply bonding electrodes 2 m andGND bonding electrodes 2 n lie in thesecond region 2 z, in which each core powersupply bonding electrode 2 m has a core power supply throughhole 2 r through a corepower supply wiring 2 v and eachGND bonding electrode 2 n has a GND throughhole 2 s through aGND wiring 2 w. - In other words , an array of core power supply through
holes 2 r and GND throughholes 2 s are located in thesecond region 2 z. - The through
holes 2 d between thefirst regions 2 y and thesecond region 2 z (signal throughholes 2 q, GND throughholes 2 s, IO power supply throughholes 2 t) and the throughholes 2 d in thesecond region 2 z (core power supply throughholes 2 r, GND throughholes 2 s) are both spaced at a very small pitch of 150-200 μm. -
FIG. 6 shows the wiring pattern of a second wiring layer L2 just under the first wiring layer L1 of themultilayer wiring substrate 2. In other words, it shows the wiring pattern of the second wiring layer from theupper surface 2 a (wiring layer next to theupper surface 2 a) in the direction from theupper surface 2 a of themultilayer wiring substrate 2 to thelower surface 2 b. - As shown in
FIG. 6 , alarge GND plane 2 wa is formed in the second wiring layer L2. TheGND plane 2 wa is electrically coupled to theGND bonding electrodes 2 n in the first layer L1 through the GND wirings 2 w and GND throughholes 2 s. - Furthermore, as shown in
FIG. 10 , in the second wiring layer L2 , a plurality of signal throughholes 2 q, IO power supply throughholes 2 t, and core power supply throughholes 2 r are disposed and isolated from theGND plane 2 wa. - The reason that the
GND plane 2 wa is provided in the second wiring layer L2 is that the plane, located near thesignal wirings 2 u in the first wiring layer L1, makes them less susceptible to noise and contributes to stabilization of signals. - More specifically, the
signal wirings 2 u in the first wiring layer L1 are less susceptible to noise and ensure stable signals because the GND wirings 2 w and IPpower supply wirings 2 x in the first wiring layer L1 are adjacent to them as shown inFIG. 13 and also theGND plane 2 wa as shown inFIG. 10 lies just under them, namely they are surrounded by power supply and GND members. - Next,
FIG. 7 shows the wiring pattern of a third wiring layer L3 just under the second wiring layer L2 of themultilayer wiring substrate 2. In other words, it shows the wiring pattern of the third wiring layer from theupper surface 2 a (wiring layer next to the second wiring layer L2) in the direction from theupper surface 2 a of themultilayer wiring substrate 2 to thelower surface 2 b. - As shown in
FIGS. 7 and 11 , a corepower supply plane 2 va lies almost in the center of the third wiring layer L3 and a plurality of oblong IOpower supply planes 2 xa are formed around theplane 2 va. In other words, the corepower supply plane 2 va and IOpower supply planes 2 xa are located in the third wiring layer next to (under) the second wiring layer L2 with theGND plane 2 wa formed thereon, in the direction from theupper surface 2 a of themultilayer wiring substrate 2 to thelower surface 2 b. - Here, the core
power supply plane 2 va is electrically coupled to the core powersupply bonding electrodes 2 m in thesecond region 2 z of the first wiring layer L1 through the corepower supply wirings 2 v and core power supply throughholes 2 r. On the other hand, the IOpower supply planes 2 xa are electrically coupled to the IO powersupply bonding electrodes 2 p in thefirst regions 2 y of the first wiring layer L1 through the IOpower supply wirings 2 x and IO power supply throughholes 2 t. - As described above, in the
multilayer wiring substrate 2, theGND plane 2 wa electrically coupled to theGND bonding electrodes 2 n in thesecond region 2 z in the center of the first wiring layer L1 lies in the second wiring layer L2 and similarly the corepower supply plane 2 va electrically coupled to the core powersupply bonding electrodes 2 m in thesecond region 2 z of the first wiring layer L1 lies in the third wiring layer L3. In other words, the GND electrodes and power supply electrodes in the first wiring layer L1 are coupled to different wiring layers, namely the second wiring layer L2 and third wiring layer L3 respectively. - This arrangement is possible because the diameter of each through
hole 2 d and the through hole pitch are small; more specifically it is possible because throughholes 2 d can be densely made in thesecond region 2 z of the first wiring layer L1 by laser processing. - Also a plurality of
signal wirings 2 u are provided in the third wiring layer L3. Thesignal wirings 2 u in the third wiring layer L3 are electrically coupled to thesignal bonding electrodes 2 k in thefirst regions 2 y of the first wiring layer L1 through thesignal wirings 2 u and signal throughholes 2 q in the first wiring layer L1. More specifically, thesignal wirings 2 u drawn inside, among those of thesignal bonding electrodes 2 k in thefirst regions 2 y of the first wiring layer L1, are electrically coupled to thesignal wirings 2 u in the third wiring layer L3 through the signal throughholes 2 q located between thefirst regions 2 y andsecond region 2 z , and thesignal wirings 2 u in the third wiring layer L3 are each drawn outside through the signal throughholes 2 q. - In other words , among the wirings for the
signal bonding electrodes 2 k in thefirst regions 2 y of the first wiring layer L1, thesignal wirings 2 u in the third wiring layer L3 (another layer) electrically coupled to thesignal wirings 2 u drawn inside through the signal throughholes 2 q are drawn outside in the third wiring layer L3. Therefore, the signal throughholes 2 q are all located outside thesecond region 2 z in the first wiring layer L1. - In the third wiring layer L3, the
signal wirings 2 u are arranged in pairs and oblong IOpower supply planes 2 xa are located on both sides of each pair ofsignal wirings 2 u. - The
BGA 9 according to the first embodiment is a multi-pin semiconductor device with not less than hundreds of pins. In this semiconductor device, in order to arrange, in a small number of wiring layers,signal wirings 2 u to be connected to a desired number of signal pins, signal throughholes 2 q are also provided inside thefirst regions 2 y (between thefirst regions 2 y andsecond region 2 z) so as to permit thesignal wirings 2 u to be drawn outside in another wiring layer (in this case, the third wiring layer L3), because the number ofsignal wirings 2 u arranged only outside thefirst regions 2 y in the first wiring layer L1 is insufficient. This device structure permits not less than hundreds of pins to be arranged in a small number of wiring layers. - For this purpose, the device uses a thin substrate such as a coreless substrate so that the diameter of through
holes 2 d in thesecond region 2 z under the chip and the through hole pitch can be small enough to obtain space for the formation of signal throughholes 2 q between thefirst regions 2 y andsecond region 2 z of the first wiring layer L1. The presence of signal throughholes 2 q between thefirst regions 2 y andsecond region 2 z makes it possible to realize a semiconductor device in which not less than hundreds of pins are arranged in a small number of wiring layers as mentioned above. - Next,
FIG. 8 shows the wiring pattern of a fourth wiring layer L4 just under the third wiring layer L3 of themultilayer wiring substrate 2. In other words, it shows the wiring pattern of the fourth wiring layer from theupper surface 2 a (wiring layer next to the third wiring layer L3) in the direction from theupper surface 2 a of themultilayer wiring substrate 2 to thelower surface 2 b. - As shown in
FIGS. 8 and 12 , in the fourth wiring layer L4, aGND plane 2 wa electrically coupled to the GND planes 2 wa in the second wiring layer L2 through the GND throughholes 2 s and a plurality of corepower supply planes 2 va electrically coupled to the corepower supply planes 2 va in the third wiring layer L3 through the core power supply throughholes 2 r are formed andlands 2 j for GND, those for power supply, and those for signals which are electrically coupled to the relevant planes are provided. Eachland 2 j is coupled to asolder ball 5 which is an external terminal for theBGA 9. - The
GND plane 2 wa in the fourth wiring layer L4 is electrically coupled to theGND plane 2 wa in the second wiring layer L2 only through the GND throughholes 2 s. This stabilizes the GND potential of themultilayer wiring substrate 2. -
FIGS. 15 and 16 show wiring portions 2 ca exposed in anopening 2 ga of the solder resistfilm 2 g andbonding electrodes 2 c, in whichFIG. 15 illustratesbonding electrodes 2 c for peripheral pads in afirst region 2 y of theupper surface 2 a andFIG. 16 illustratesbonding electrodes 2 c for area arrangement in thesecond region 2 z of theupper surface 2 a. In flip-chip coupling of either type ofbonding electrode 2 c, aplating layer 2 cb overlying thebonding electrode 2 c is brought into contact with asolder bump 8. In theBGA 9 according to the first embodiment, solder bumps 8 are, for example, cylindrical to enable flip-chip coupling with a small signal pad pitch of 20 μm. -
FIGS. 17 and 18 show an example of the relation between bump size on the chip and minimum spacing between wirings on the substrate. Regarding the relation between solder bump size A and spacing B between wirings (bonding electrodes 2C) as shown inFIG. 17 , the relation of A<B (bump size<spacing) exists so that when a solder bump shifts as shown inFIG. 18 , gap C is produced between thesolder bump 8 and thebonding electrode 2 c, thereby preventing an electric short circuit. - In the
multi-pin BGA 9 according to the first embodiment, the pluralsignal bonding electrodes 2 k in the regions (first regions 2 y) of theupper surface 2 a of themultilayer wiring substrate 2 which are opposite to the peripheral areas of the chip are separated into inner and outer ones and the signal throughholes 2 q coupled to thesignal wirings 2 u drawn inside are located between thefirst regions 2 y with rows ofsignal bonding electrodes 2 k and the centersecond region 2 z with core powersupply bonding electrodes 2 m andGND bonding electrodes 2 n, permitting chip pads to be arranged densely. - In other words, due to the adoption of a thin coreless substrate for the
multilayer wiring substrate 2, the diameter of throughholes 2 d in thesecond region 2 z under the chip and the through hole pitch can be small enough to obtain space for the formation of plural signal throughholes 2 q between thefirst regions 2 y andsecond region 2 z of theupper surface 2 a (first wiring layer L1). - As a consequence, the
signal bonding electrodes 2 k in thefirst regions 2 y can be separated into inner and outer ones and the chip pad pitch can be thus decreased and thesignal bonding electrodes 2 k can be disposed for peripheral arrangement (in thefirst regions 2 y) and the core powersupply bonding electrodes 2 m andGND bonding electrodes 2 n can be disposed for area arrangement (in thesecond region 2 z). - Consequently, chip size can be reduced without an increase in the number of layers in the
multilayer wiring substrate 2. - Since a multi-pin structure is realized without using a redistribution technique and increasing the number of layers in the
multilayer wiring substrate 2, the cost of themulti-pin BGA 9 can be decreased and the need for chip shrinkage can be met. Generally a flip-chip semiconductor device is more costly than a wire-bonded semiconductor device. In this sense, it is very meaningful that the cost of theBGA 9 according to the first embodiment as a flip-chip semiconductor device is reduced. - Furthermore, since area arrangement of electrode pads is can be made without using a redistribution technique, it is easy to design the chip.
- Furthermore, in the
multilayer wiring substrate 2, since the through hole diameter is decreased, the core power supplies in thesecond region 2 z are coupled through the core power supply throughholes 2 r to the core power supply lands 2 j in the fourth wiring layer L4, so more pins can be provided without an increase in the number of wiring layers to realize a multi-pin structure. - Since area arrangement of
electrode pads 1 c of thesemiconductor chip 1 is possible, area arrangement ofelectrode pads 1 c of thesemiconductor chip 1 can be made even in the multi-pin semiconductor device with a shrunk chip. - Furthermore, since area arrangement of
electrode pads 1 c of thesemiconductor chip 1 can be made even in the multi-pin semiconductor device with a shrunk chip, a plurality of core powersupply bonding electrodes 2 m can be arranged in thesecond region 2 z near the center of thesemiconductor chip 1, so power supply stabilization can be achieved in themulti-pin BGA 9 with a shrunk chip. - Particularly, if the
BGA 9 is intended for a high power device, such power supply stabilization is very advantageous. - Next, variations of the first embodiment will be described.
-
FIG. 19 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a first variation of the first embodiment of the invention. Themultilayer wiring substrate 2 of the first variation as shown inFIG. 19 is an wiring substrate with acore layer 2 h, in which the thickness of the substrate is thin since thecore layer 2 h is thin. - In the
multilayer wiring substrate 2 with athin core layer 2 h as shown inFIG. 19 , due to the thinness of thecore layer 2 h, small-diameter through holes can be made using a small-diameter drill, so it is possible to make throughholes 2 d whose diameter and pitch are almost as small as those of the through holes of a coreless substrate. - As a consequence, even the semiconductor device which uses the
multilayer wiring substrate 2 with acore layer 2 h can achieve almost the same advantageous effect as the semiconductor device which uses the corelessmultilayer wiring substrate 2. For example, the thickness of themultilayer wiring substrate 2 with thecore layer 2 h is about 0.4 mm to 0.6 mm or so; this substrate has an improved rigidity though its thickness is larger than the coreless substrate described above. It is assumed here that a thinmultilayer wiring substrate 2 with acore layer 2 h refers to a multilayer wiring substrate with acore layer 2 h having a thickness not less than 0.4 and not more than 1.0 mm. Such a thinmultilayer wiring substrate 2 with acore layer 2 h is used, for example, as an in-vehicle semiconductor package substrate which is relatively large (20-35 mm square) and should be highly reliable. - The abovementioned coreless substrate according to the first embodiment which has a relatively small package size (10-20 mm square) is used as a semiconductor package substrate for a mobile device such as a mobile phone.
- Next,
FIG. 20 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a second variation of the first embodiment of the invention. In the flip-chip structure of the semiconductor device of the second variation as shown inFIG. 20 , gap D between thesemiconductor chip 1 and the solder resistfilm 2 g of themultilayer wiring substrate 2 is as small as 5 μm and underfill resin 6 (FIG. 2 ) is not filled therein because it may be difficult to fill theunderfill resin 6 therein. - Since no
underfill resin 6 is used, the problem of inhomogeneous filling ofunderfill resin 6 is eliminated. Here, aplating layer 2 cb of nickel-gold or the like lies on the surface of awiring portion 2 ca. - Next,
FIG. 21 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a third variation of the first embodiment of the invention. The flip-chip structure of the semiconductor device of the third variation as shown inFIG. 21 has no solder resistfilm 2 g as shown inFIG. 20 in themultilayer wiring substrate 2; instead it has an insulatingfilm 2 gb with a height equivalent to the height of thewiring portion 2 ca to planarize the substrate surface. - Here, the gap between the
multilayer wiring substrate 2 and themain surface 1 a of thesemiconductor chip 1 is as wide as 15 μm or so and this gap is filled withunderfill resin 6. - The gap between the
multilayer wiring substrate 2 and themain surface 1 a of thesemiconductor chip 1 is wide enough to reduce the possibility of inhomogeneous filling ofunderfill resin 6. - Next,
FIG. 22 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fourth variation of the first embodiment of the invention. In the flip-chip structure of the semiconductor device of the fourth variation shown inFIG. 22 , the solder resistfilm 2 g lies not all over the chip mounting area of theupper surface 2 a of themultilayer wiring substrate 2, namely the solder resistfilm 2 g lies only outside the chip mounting area. In this case, aplating layer 2 cb of nickel-gold or the like is formed all over the exposed portion of eachwiring portion 2 ca. - As a consequence, the gap between the
multilayer wiring substrate 2 and themain surface 1 a of thesemiconductor chip 1 is wider, thereby reducing the possibility of inhomogeneous filling of theunderfill resin 6. - Next,
FIG. 23 is a fragmentary enlarged sectional view of the wiring substrate built in the semiconductor device according to a fifth variation of the first embodiment of the invention. The flip-chip structure of the semiconductor device of the fifth variation shown inFIG. 23 is produced as follows: after asemiconductor chip 1 withsolder bumps 8 is placed onbonding electrodes 2 c, the solder bumps are melted, then underfillresin 6 is filled there, and heat is applied to harden theunderfill resin 6. - This reduces the possibility of inhomogeneous filling of the
underfill resin 6. - Next,
FIG. 24 is a plan view of the wiring substrate built in the semiconductor device according to a sixth variation of the first embodiment of the invention andFIG. 25 is a sectional view of an example of the semiconductor device using the wiring substrate shown inFIG. 24 . The semiconductor device of the sixth variation shown inFIG. 25 is aBGA 10 which uses gold bumps 11 for flip-chip coupling, with the surfaces of thebonding electrodes 2 c (FIG. 24 ) tinned. - As shown in
FIG. 24 , like themultilayer wiring substrate 2 shown inFIG. 22 , the solder resistfilm 2 g lies on theupper surface 2 a of the multilayer wiring substrate 2 (FIG. 25 ) except the chip mounting area, specifically the solder resistfilm 2 g is formed around the chip mounting area. Therefore, in theBGA 10 as well, the underfill resin is filled homogeneously as shown inFIG. 25 . Anopening 2 ga in the solder resistfilm 2 g can stop a flow ofunderfill resin 6. - Next,
FIG. 26 is a plan view showing an example of the relation between the bonding electrode shape of the wiring substrate and the electrode pads of the semiconductor chip in the semiconductor device according to a seventh variation of the first embodiment of the invention. In the semiconductor device of the seventh variation shown inFIG. 26 , the shape of the solder bumps 8 of themultilayer wiring substrate 2 for flip-chip coupling is a rectangle along the direction in which thewiring portions 2 ca to be coupled to the solder bumps 8 extend. - As a consequence, even if the
wiring portions 2 ca are as thin as 20 μm, the solder bumps 8 can be adequately coupled to them for flip-chip coupling. - Next,
FIG. 27 is a fragmentary enlarged sectional view of the semiconductor device according to an eighth variation of the first embodiment of the invention. The semiconductor device of the eighth variation shown inFIG. 27 is aBGA 13 in which thesemiconductor chip 1 is thin and solder bumps 12 for stacking are laid around thesemiconductor chip 1 on theupper surface 2 a of themultilayer wiring substrate 2 and coupled to thebonding electrodes 2 c. - In the
BGA 13, due to the thinness of thesemiconductor chip 1, encapsulating resin can flow to theback surface 1 b of thesemiconductor chip 1 so that thesemiconductor chip 1 is buried in anencapsulant 15, namely themultilayer wiring substrate 2 houses the chip. Theupper surface 2 gc which connects theencapsulant 15 covering thesemiconductor chip 1 and the solder resistfilm 2 g is planarized so that the solder bumps 12 for stacking protrude from theupper surface 2 gc. -
FIG. 28 is a fragmentary enlarged sectional view of the semiconductor device according to a ninth variation of the first embodiment of the invention. The semiconductor device of the ninth variation shown inFIG. 28 is a POP (Package On Package) 14 which has two units of theBGA 13 shown inFIG. 28 stacked one upon the other. - In other words, a
BGA 13 which houses athin semiconductor chip 1 is produced and two or more units of theBGA 13 are stacked to make up aPOP 14. -
FIG. 29 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the first wiring layer (L1) of the wiring substrate built in the semiconductor device according to a second embodiment of the invention;FIG. 30 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the second wiring layer (L2) of the wiring substrate built in the semiconductor device according to the second embodiment;FIG. 31 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the third wiring layer (L3) of the wiring substrate built in the semiconductor device according to the second embodiment of the invention; andFIG. 32 is a plan view of an example of the wiring pattern of the area under the chip and its vicinity in the fourth wiring layer (L4) of the wiring substrate built in the semiconductor device according to the second embodiment.FIG. 33 is a fragmentary enlarged plan view of part A ofFIG. 29 ;FIG. 34 is a fragmentary enlarged plan view of part A ofFIG. 30 ;FIG. 35 is a fragmentary enlarged plan view of part A ofFIG. 31 ;FIG. 36 is a fragmentary enlarged plan view of part A ofFIG. 32 ; andFIG. 37 is a fragmentary enlarged plan view of part A of the wiring substrate built in the semiconductor device according to a variation of the second embodiment. - The second embodiment concerns a semiconductor device having a
multilayer wiring substrate 2 in which the number of pins is smaller than in theBGA 9 according to the first embodiment. In thesecond region 2 z of the first wiring layer L1 of themultilayer wiring substrate 2, the number of core powersupply bonding electrodes 2 m and the number ofGND bonding electrodes 2 n as shown inFIG. 33 are smaller than in the first embodiment, resulting in a decrease in the number of pins of the semiconductor device. Specifically, the number ofbonding electrodes 2 c (core powersupply bonding electrodes 2 m andGND bonding electrodes 2 n) in thesecond region 2 z of the first wiring layer L1 is smaller than the number ofbonding electrodes 2 c in thesecond region 2 z of themultilayer wiring substrate 2 of theBGA 9 according to the first embodiment. - Next, the four wiring layers of the
multilayer wiring substrate 2 in the second embodiment will be each described referring toFIGS. 29 to 36 . -
FIGS. 29 and 33 illustrate the wiring pattern of the first wiring layer L1;FIGS. 30 and 34 illustrate that of the second wiring layer L2;FIGS. 31 and 35 illustrate that of the third wiring layer L3 ; andFIGS. 32 and 36 illustrate that of the fourth wiring layer L4. In these figures, the wiring pattern of eachfirst region 2 y and that of the area between eachfirst regions 2 y and thesecond region 2 z are the same as in themultilayer wiring substrate 2 according to the first embodiment. - The difference from the first embodiment is that in the wiring pattern of the first wiring layer L1 shown in
FIG. 29 , the number ofbonding electrodes 2 c in thesecond region 2 z is smaller than in the first embodiment, resulting in a decrease in the number of pins of the semiconductor device. As shown inFIG. 33 , theGND bonding electrodes 2 n in thesecond region 2 z are electrically coupled to aGND plane 2 wa in the second wiring layer L2 shown inFIGS. 30 and 34 through GNDwirings 2 w and GND throughholes 2 s. - On the other hand, the core power
supply bonding electrodes 2 m in thesecond region 2 z of the first wiring layer L1 are electrically coupled to corepower supply planes 2 va in the third wiring layer L3 shown inFIGS. 31 and 35 through corepower supply wirings 2 v and core power supply throughholes 2 r. - Furthermore, as shown in
FIGS. 32 and 36 , in the fourth wiring layer L4, there are aGND plane 2 wa electrically coupled to theGND plane 2 wa in the second wiring layer L2 through the GND throughholes 2 s, and a plurality of corepower supply planes 2 va (2 j) coupled to the corepower supply plane 2 va in the third wiring layer L3 through the core power supply throughholes 2 r, along withlands 2 j for GND, power supply and signals which are electrically coupled to the relevant planes. - As in the
multilayer wiring substrate 2 according to the first embodiment, in themultilayer wiring substrate 2 according to the second embodiment as well, among the wirings for thesignal bonding electrodes 2 k in thefirst regions 2 y of the first wiring layer L1, thesignal wirings 2 u in the third wiring layer L3 (another layer) electrically coupled to thesignal wirings 2 u drawn inside through the signal throughholes 2 q are drawn outside in the third wiring layer L3. Therefore, the signal throughholes 2 q are all located outside thesecond region 2 z in the first wiring layer L1. - In the third wiring layer L3, the
signal wirings 2 u are arranged in pairs and oblong IOpower supply planes 2 xa are located on both sides of each pair ofsignal wirings 2 u. - Like the
BGA 9 according to the first embodiment, the semiconductor device according to the second embodiment is a multi-pin semiconductor device. In this semiconductor device, in order to arrange, in a small number of wiring layers,signal wirings 2 u to be connected to a desired number of signal pins, signal throughholes 2 q are also provided inside thefirst regions 2 y (between thefirst regions 2 y andsecond region 2 z) so as to permit thesignal wirings 2 u to be drawn outside in another wiring layer (in this case, the third wiring layer L3), because the number ofsignal wirings 2 u arranged only outside thefirst regions 2 y in the first wiring layer L1 is insufficient. This device structure permits a lot of pins to be arranged in a small number of wiring layers. - For this purpose, the device uses a thin substrate such as a coreless substrate so that the diameter of through
holes 2 d in thesecond region 2 z under the chip and the through hole pitch can be small enough to obtain space for the formation of signal throughholes 2 q between thefirst regions 2 y andsecond region 2 z of the first wiring layer L1. The presence of signal throughholes 2 q between thefirst regions 2 y andsecond region 2 z makes it possible to realize a semiconductor device in which a lot of pins are arranged in a small number of wiring layers. - The other details of the wiring patterns of the first wiring layer L1, second wiring layer L2, third wiring layer L3, and fourth wiring layer L4 in the second embodiment are the same as those in the first embodiment and description thereof is omitted here.
- The advantageous effect achieved by the semiconductor device having the
multilayer wiring substrate 2 according to the second embodiment is the same as that achieved by the semiconductor device (BGA 9) according to the first embodiment and description thereof is omitted here. - Next, a variation of the second embodiment will be described.
-
FIG. 37 shows the structure of an wiring substrate as a variation of the second embodiment, in which a plurality ofbonding electrodes 2 c in eachfirst region 2 y of the first wiring layer L1 are arranged in a staggered pattern. Specifically, the two rows ofbonding electrodes 2 c in eachfirst region 2 y of the first wiring layer L1 are arranged in a staggered pattern. In this case, the two rows ofelectrode pads 1 c in the peripheral areas of themain surface 1 a of thesemiconductor chip 1 are also arranged in a staggered pattern so as to permit flip-chip coupling. - This arrangement makes it possible that in the wiring pattern of the
multilayer wiring substrate 2, the pitch betweenbonding electrodes 2 c can be 20 μm at a line/space ratio of 20 μm/20 μm. As a consequence, the pad pitch can be decreased and the number of pins in the semiconductor device can be increased. - The invention made by the present inventors has been so far explained in reference to the preferred embodiments thereof . However, the invention is not limited thereto and it is obvious that these details may be modified in various ways without departing from the spirit and scope thereof.
- For example, although the first embodiment has been described on the assumption that the
bonding electrodes 2 c in thefirst regions 2 y in the peripheral areas of theupper surface 2 a of themultilayer wiring substrate 2 are arranged in parallel (not staggered) , thebonding electrodes 2 c in thefirst regions 2 y (including thesecond region 2 z) of theupper surface 2 a may also be arranged in a staggered pattern in themultilayer wiring substrate 2 of theBGA 9 according to the first embodiment. - If the
bonding electrodes 2 c in thefirst regions 2 y of theupper surface 2 a of themultilayer wiring substrate 2 of theBGA 9 according to the first embodiment are arranged in a staggered pattern, in theBGA 9 the pad pitch can be further decreased and the number of pins can be further increased. - Although the first embodiment has been described on the assumption that the
stiffener ring 7 is attached to theBGA 9, thestiffener ring 7 is omissible. If thestiffener ring 7 is not attached, theheat spreader 4 is bonded only to theback surface 1 b of thesemiconductor chip 1 through heat-radiatingresin 3 or the like. - The present invention is suitable for electronic devices which adopt a flip-chip coupling method.
Claims (16)
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US15/714,801 US10134663B2 (en) | 2010-01-14 | 2017-09-25 | Semiconductor device |
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US14/871,742 Active US9818679B2 (en) | 2010-01-14 | 2015-09-30 | Semiconductor device |
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Also Published As
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US20140217582A1 (en) | 2014-08-07 |
JP2011146489A (en) | 2011-07-28 |
US9818679B2 (en) | 2017-11-14 |
US10134663B2 (en) | 2018-11-20 |
JP5514560B2 (en) | 2014-06-04 |
US8729709B2 (en) | 2014-05-20 |
US20160027723A1 (en) | 2016-01-28 |
US20180012831A1 (en) | 2018-01-11 |
US9171791B2 (en) | 2015-10-27 |
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