US20110140711A1

US20110140711A1 - Measurement circuit and electronic device

Info

Publication number: US20110140711A1
Application number: US13/004,816
Authority: US
Inventors: Yasuo Furukawa
Original assignee: Advantest Corp
Current assignee: Advantest Corp
Priority date: 2009-09-16
Filing date: 2011-01-11
Publication date: 2011-06-16
Also published as: JPWO2011033691A1; WO2011033564A1; US8536887B2; US20110062977A1; WO2011033691A1; JPWO2011033564A1

Abstract

Provided is a measurement circuit that is provided in the same electronic device as a circuit under measurement, comprises a difference generating section and an integrating section, and performs a sigma-delta AD conversion on a signal under measurement output by the circuit under measurement, the measurement circuit further comprising a sampling section that is provided between an output end of the difference generating section and an input end of the integrating section, detects a level of a signal input thereto at predetermined sampling intervals, and outputs a sampled signal corresponding to the detected signal level. This measurement circuit is used to easily perform a sigma-delta AD conversion on a high-frequency signal under measurement.

Description

BACKGROUND

1. Technical Field
The present invention relates to a measurement circuit and an electronic device.
2. Related Art
An effective technique for checking the operation of a circuit inside an electronic device, such as an LSI, is to measure a signal output by the circuit. If the signal has a high frequency, however, the signal waveform is distorted when the signal is drawn outside the electronic device. Therefore, it is difficult to directly measure the change timing or the like of the signal itself. Furthermore, an EB (Electronic Beam) tester is known as a means for measuring operations, such as change timing, of a signal in a circuit in an electronic device.
The Non-Patent Document shown below is provided as related art. Non-Patent Document 1: Makoto Nagata, “On-Chip Measurements Complementary to Design Flow for Integrity on SoCs,” Proc. Design Automation Conference 2007, pp. 400-403, 2007.06.
When using an external device, such as an EB tester, to measure an internal signal of a circuit under test, it is necessary to purchase the external device equipment, and the measurement takes a long time. Another measurement method involves providing an additional circuit that converts the internal signal within the electronic device into a low-frequency signal, and then measuring the low-frequency signal on the outside. The frequency of the signal can be converted by a mixer or the like. However, since the additional circuit increases the overall circuit size, the cost of the electronic device also increases.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein to provide a measurement circuit and an electronic device, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. According to a first aspect related to the innovations herein, provided is a measurement circuit that is provided in the same electronic device as a circuit under measurement, comprises a difference generating section and an integrating section, and performs a sigma-delta AD conversion on a signal under measurement output by the circuit under measurement, the measurement circuit further comprising a sampling section that is provided between an output end of the difference generating section and an input end of the integrating section, detects a level of a signal input thereto at predetermined sampling intervals, and outputs a sampled signal corresponding to the detected signal level. Also provided is an electronic device including the measurement circuit.
The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary configuration of an electronic device 200.

FIG. 2 shows exemplary waveforms of each signal in the sampling section 20.

FIG. 3 shows another exemplary configuration of the measurement circuit 100.

FIG. 4 shows exemplary waveforms of each signal in the measurement circuit 100 described in relation to FIG. 3.

FIG. 5 shows another exemplary configuration of the measurement circuit 100.

FIG. 6 shows another exemplary configuration of the measurement circuit 100.

FIG. 7 shows another exemplary configuration of the measurement circuit 100.

FIG. 8 shows another exemplary configuration of the measurement circuit 100.

FIG. 9 shows exemplary frequency characteristics of the sampling section 20.

FIG. 10 shows frequency characteristics of the output from a final-stage sampling section 20-n with respect to the input to a first-stage sampling section 20-1.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, some embodiments of the present invention will be described. The embodiments do not limit the invention according to the claims, and all the combinations of the features described in the embodiments are not necessarily essential to means provided by aspects of the invention.
FIG. 1 shows an exemplary configuration of an electronic device 200. The electronic device 200 may be a semiconductor chip or the like. The electronic device 200 includes a circuit under measurement 108, a measurement circuit 100, an input terminal 102, an output terminal 104, and a measuring terminal 106.
The circuit under measurement 108 refers to an actual operation circuit that, when the electronic device 200 is implemented in an electric device or the like, performs at least a portion of the functions of the electric device. The circuit under measurement 108 operates according to an input signal to output a signal corresponding to the operation result.
The circuit under measurement 108 may receive a pattern from outside the electronic device 200, via the input terminal 102. The output terminal 104 outputs, to the outside of the electronic device 200, the signal output by the circuit under measurement 108. The circuit under measurement 108 receives an operational clock Tsck with a period of Tsck. The operational clock Tsck may be input from outside the electronic device 200, or may be generated within the electronic device 200. The circuit under measurement 108 outputs a signal in synchronization with the operational clock Tsck.
The measurement circuit 100 is provided within the same electronic device 200 as the circuit under measurement 108. The measurement circuit 100 measures a signal under measurement output by the circuit under measurement 108, and outputs the measurement results to the outside of the electronic device 200. When measuring the signal under measurement output by the circuit under measurement 108, the circuit under measurement 108 outputs the signal under measurement with a repeating prescribed signal pattern and a period Fout that is an integer multiple of the operational clock Tsck. The circuit under measurement 108 may receive, from an external device, an input pattern for outputting the signal under measurement.
The measurement circuit 100 outputs the measurement result as a signal whose frequency is lower than the Nyquist frequency of the signal under measurement. The Nyquist frequency of the signal under measurement is expressed as 1/(2×Fout). More specifically, the measurement circuit 100 measures the signal under measurement by performing a sigma-delta AD conversion, with a frequency lower than the Nyquist frequency of the signal under measurement, on the signal under measurement output from the circuit under measurement 108.
The sigma-delta AD conversion can aggregate, in a high frequency region, the noise components caused by the quantization error of the AD conversion. With a normal sigma-delta AD conversion, however, the AD conversion is performed by integrating the signal level of the signal under measurement and comparing the integrated value to a reference level at each pulse timing of a measurement clock. Therefore, in the sigma-delta AD conversion, the signal level of the signal under measurement must not change significantly between pulses of the measurement clock. In other words, with the sigma-delta AD conversion, the frequency of the measurement clock must be sufficiently higher than the frequency of the signal under measurement.
The measurement circuit 100 measures the signal under measurement by performing the sigma-delta AD conversion with a frequency lower than the Nyquist frequency of the signal under measurement. As a result, a high-frequency signal under measurement can be easily subjected to the sigma-delta AD conversion without generating a high-frequency measurement clock.
The measurement circuit 100 of the present embodiment includes a difference generating section 10, a sampling section 20, an integrating section 30, a quantizing section 40, and a feedback section 50. The difference generating section 10, the integrating section 30, the quantizing section 40, and the feedback section 50 form the so-called sigma-delta AD converter. The difference generating section 10 decreases the signal level of the signal under measurement from the circuit under measurement 108, according to a feedback signal FB received from the feedback section 50, and inputs the resulting signal to the sampling section 20.
The sampling section 20 is provided between the output end of the difference generating section 10 and the input end of the integrating section 30. The sampling section 20 detects, at predetermined sampling intervals, the level of the signal received from the difference generating section 10. The sampling section 20 outputs a sampled signal corresponding to the signal level detected in each sampling interval. In the present embodiment, the sampling section 20 includes a sample/hold circuit. The sampling section 20 of the present embodiment outputs, as the sampled signal, a hold signal HS that is obtained by holding the signal level detected in each sampling interval for a prescribed duration corresponding to the sampling interval. The sampling section 20 detects the signal level output by the difference generating section 10, with an operational period greater than the repeating period Fout of the signal under measurement.
For example, the sampling section 20 may detect the level of the received signal at a timing corresponding to each pulse of the measurement clock Tcck. The measurement clock Tcck may be received from outside the electronic device 200, or may be generated within the electronic device 200. The measurement clock Tcck has a frequency that is lower than the Nyquist frequency of the signal under measurement. The sampling section 20 outputs a hold signal HS obtained by holding the signal level detected according to each pulse of the measurement clock Tcck until the next pulse timing of the measurement clock Tcck.
The measurement clock Tcck and the repeating frequency Fout of the signal under measurement have the relationship shown below.
Tcck×m=Fout×n+Trck
Here, m and n are natural numbers. As a result, for every m cycles of the measurement clock Tcck, the relative phase between the measurement clock and the signal under measurement changes by Trck. In other words, the sampling section 20 can detect the signal level of the signal under measurement at a timing shifted by Trck for every m cycles of the measurement clock Tcck. Therefore, the signal under measurement can be equivalently sampled with the time resolution Trck, by arranging the sampled data of the signal under measurement for every m cycles of the measurement clock Tcck.
The integrating section 30 integrates, on the time axis, the signal level of the hold signal HS output from the sampling section 20. The integrating section 30 is a circuit that integrates the signal level of a received analog signal on the time axis.
The quantizing section 40 outputs a digital signal corresponding to the integrated value from the integrating section 30. The quantizing section 40 may detect the value of the integration result from the integrating section 30 with the same period as the operational period of the sampling section 20, and output a digital signal corresponding to the detected value. The quantizing section 40 performs quantization by AD converting the integrated value at a timing of each pulse of the measurement clock Tcck.
When the quantizing section 40 outputs the digital signal, the feedback section 50 inputs to the difference generating section 10 the feedback signal FB with a signal level corresponding to the digital signal. As a result, the noise caused by the quantization error of the quantizing section 40 is decreased. The feedback section 50 of the present embodiment includes a delaying section 52 and a DA converter 54.
The delaying section 52 is provided in parallel with the measuring terminal 106 and delays the digital signal output by the quantizing section 40. The delaying section 52 may delay the digital signal by one period of the measurement clock Tcck. The delaying section 52 may include a flip-flop that is supplied with the measurement clock Tcck as the operational clock. The DA converter 54 outputs the feedback signal FB obtained by DA converting the digital signal delayed by the delaying section 52.
The measurement circuit 100 may output the measurement result via the measuring terminal 106, or may output the measurement result via the output terminal 104. The measurement circuit 100 may output, as the measurement result, a digital signal obtained by performing the sigma-delta AD conversion on the signal under measurement, or an analog signal generated from this digital signal. The measurement circuit 100 may extract a component of this digital signal that is less than or equal to a predetermined frequency, and output this component. In this case, the measurement circuit 100 may include a low-pass filter for passing the digital signal.
FIG. 2 shows exemplary waveforms of each signal in the sampling section 20. In the present embodiment, the period of the measurement clock Tcck is greater than the repeating period Fout of the signal under measurement by Trck. In the example of FIG. 2, Tcck=Fout+(Fout/8).
As described above, the sampling section 20 outputs the hold signal HS obtained by holding the signal level of the signal under measurement according to the pulses of the measurement clock Tcck. As a result, the sampling section 20 outputs a digital waveform with a period obtained as the product of (i) the period of the signal under measurement and (ii) the ratio between Trck and Fout. In the example of FIG. 2, the sampling section 20 outputs a digital waveform with a period that is eight times the period of the signal under measurement.
Since the integrating section 30 integrates the hold signal HS, which is obtained by holding the signal level of the signal under measurement at the timing of the measurement clock, the integrated value corresponding to the signal level of the signal under measurement at the timing of the measurement clock can be output, even if the signal level of the signal under measurement changes. The quantizing section 40 quantizes this integrated value, and therefore the digital signal corresponding to the signal level of the signal under measurement at the timing of the measurement clock can be output.
Even if the sampling section 20 is provided between the circuit under measurement 108 and the difference generating section 10, the sigma-delta AD conversion can be performed on the signal under measurement with the low-frequency measurement clock Tcck. It should be noted that, in this case, the sampling section 20 directly receives the signal under measurement output by the circuit under measurement 108, and therefore it is preferable that the sampling section 20 be capable of operating across the entire voltage range of the signal under measurement.
On the other hand, when the sampling section 20 is provided between the difference generating section 10 and the integrating section 30 as shown in FIG. 1, the sampling section 20 is provided with a signal obtained by dividing the signal under measurement by the feedback signal FB, and therefore the necessary operational voltage range is decreased. As a result, the sampling section 20 is preferably provided between the difference generating section 10 and the integrating section 30.
FIG. 3 shows another exemplary configuration of the measurement circuit 100. Components in FIG. 3 having the same reference numerals as components in FIG. 1 may have the same function and configuration as these components. The measurement circuit 100 includes a resistor 12, a resistor 14, a difference generating section 10, a sampling section 20, an integrating section 30, a quantizing section 40, and a delaying section 52.
The difference generating section 10 receives the signal under measurement via the resistor 12 and receives the feedback signal FB via the resistor 14. The difference generating section 10 may be a connection line electrically connected to the resistor 12 and the resistor 14. In this case, the feedback signal FB has a negative sign and the difference generating section 10 adds the negative feedback signal FB to the signal under measurement.
The sampling section 20 includes a first transistor 22 and a second transistor 24, whose sources are connected in parallel relative to the difference generating section 10, and a pulse generating section 26. The first transistor 22 and the second transistor 24 have the same characteristics.
The pulse generating section 26 receives the measurement clock Tcck and adjusts the pulse width of each pulse of the measurement clock Tcck to be a predetermined pulse width. For example, the pulse generating section 26 may output an exclusive OR of the measurement clock and a delayed clock, which is obtained by delaying the measurement clock Tcck according to the pulse width to be generated. The pulse generating section 26 supplies the generated pulse to the gate of the second transistor 24 and supplies an inverse pulse, obtained by inverting the generated pulse, to the gate of the first transistor 22. In other words, the first transistor 22 and the second transistor 24 operate differentially.
Generally, a capacitor for holding an output voltage is provided in the sample/hold circuit, but in the measurement circuit 100 of the present embodiment, a capacitor 32 functioning as the integrating section 30 is provided downstream from the sampling section 20. The capacitor 32 has a function to hold the output of the sampling section 20, and therefore the sampling section 20 need not include a capacitor.
The integrating section 30 includes a capacitor 32 between the first transistor 22 and the second transistor 24. As a result, the integrating section 30 integrates the voltage output by the sampling circuit 20.
The quantizing section 40 outputs a digital signal corresponding to the voltage across the capacitor 32. The quantizing section 40 of the present embodiment compares the voltage across the capacitor 32 to a predetermined reference level, at the pulse timing of the measurement clock Tcck. The quantizing section 40 may be a 1-bit AD converter that outputs a pulse when the voltage across the capacitor 32 is greater than or equal to the reference level.
The delaying section 52 includes a flip-flop that receives the pulse output by the quantizing section 40 at a data input terminal D and receives the measurement clock Tcck at a clock input terminal. The delaying section 52 delays the pulse received from the quantizing section 40 according to the measurement clock Tcck, and outputs the delayed pulse from an output terminal Q. The delaying section 52 delays the pulse received from the quantizing section 40 according to the measurement clock Tcck, inverts the pulse, and outputs the resulting pulse from the inverted output terminal /Q.
The amplitude level of the pulse output from the inverted output terminal /Q may be the same as the reference level in the quantizing section 40. The inverted output terminal /Q inputs this inverted pulse to the difference generating section 10 as the feedback signal FB.
FIG. 4 shows exemplary waveforms of each signal in the measurement circuit 100 described in relation to FIG. 3. In FIG. 4, the signal under measurement is represented by the dashed-line triangular wave and the output of the integrating section 30 is represented by the solid straight line. The pulse generating section 26 outputs a signal with a predetermined pulse width having the same period as the measurement clock Tcck.
While the pulse received from the pulse generating section 26 is logic H, the second transistor 24 charges and discharges the capacitor 32 according to the signal under measurement. The integrating section 30 outputs the voltage across the capacitor 32.
The quantizing section 40 compares the voltage output by the integrating section 30 to a reference level. The quantizing section 40 may perform this comparison while the signal input to the gate of the second transistor 24 is logic L. With this operation, the pulses can be output according to the signal level of the signal under measurement at the timing of the measurement clock.
It should be noted that Trck, e.g. the difference between the repeating period Fout of the signal under measurement and the period of the measurement clock Tcck, is preferably sufficiently smaller than the repeating period Fout of the signal under measurement. For example, Trck may be 1/1000 or less of the repeating period Fout. The ratio between Trck and the repeating frequency Fout of the signal under measurement may be approximately equal to the ratio between the sampling period in the sigma-delta AD conversion and the repeating period Fout of the signal under measurement. The width of the pulses output by the pulse generating section 26 may be greater than or less than Trck.
FIG. 5 shows another exemplary configuration of the measurement circuit 100. The measurement circuit 100 of the present embodiment includes a difference generating section 10, a sampling section 20, an integrating section 30, a quantizing section 40, a feedback section 50, and an error calculating section 60. Components in FIG. 5 having the same reference numerals as components in FIG. 1 or FIG. 3 may have the same function and configuration as these components.
The difference generating section 10 is the same as the difference generating section 10 described in FIGS. 1 to 4. The quantizing section 40 outputs a pulse when the signal level of the signal output by the difference generating section 10 is greater than or equal to a predetermined reference level. In the same manner as the quantizing section 40 described in FIG. 1, the quantizing section 40 may output a multi-bit digital signal. In this case, the feedback section 50 may include a DA converter 54.
The sampling section 20 is provided in parallel with the quantizing section 40, and outputs a hold signal HS corresponding to the signal output by the difference generating section 10. The difference generating section 10 is electrically connected to the quantizing section 40 and the sampling section 20 via a branching path 70. The branching path 70 branches the signal output from the difference generating section 10 and inputs the resulting signals to the quantizing section 40 and the sampling section 20. The signal input to the sampling section 20 is then input to the error calculating section 60 through processing of the sampling section 20.
The operation of the sampling section 20 may be the same as that of the sampling section 20 described in relation to FIG. 2. The sampling section 20 and the quantizing section 40 receive the measurement clock Tcck with the same period.
The error calculating section 60 calculates a difference between a digital value corresponding to the pulse output by the quantizing section 40 and the signal level output by the difference generating section 10. The error calculating section 60 may calculate the voltage corresponding to the difference between the level of the signal output by the difference generating section 10 and a reference level of the quantizing section 40, according to the pulse output by the quantizing section 40.
The integrating section 30 integrates the error calculated by the error calculating section 60. The integrating section 30 integrates the voltage output by the error calculating section 60 on the time axis. The feedback section 50 inputs to the difference generating section 10 the feedback signal FB having a signal level corresponding to the integrated value from the integrating section 30.
The measurement circuit 100 of the present embodiment, which performs a sigma-delta AD conversion that involves the integrating section 30 integrating the quantization error, can easily perform the sigma-delta AD conversion on a high-frequency signal under measurement, in the same manner as the measurement circuit 100 described in relation to FIGS. 1 to 4, by including the sampling section 20 between the difference generating section 10 and the integrating section 30.
FIG. 6 shows another exemplary configuration of the measurement circuit 100. The measurement circuit 100 of the present embodiment differs from the measurement circuit 100 shown in FIG. 5 in that the location of the sampling section 20 is different. The remaining configuration may be the same as that of the measurement circuit 100 shown in FIG. 5.
The measurement circuit 100 of the present embodiment includes the sampling section 20 between the output end of the difference generating section 10 and the branching path 70. The sampling section 20 inputs the hold signal, corresponding to the signal output by the difference generating section 10, to both the quantizing section 40 and the error calculating section 60.
With this configuration as well, the sigma-delta AD conversion can be easily performed on a high-frequency signal under measurement. It should be noted that providing the sampling section 20 at the position shown in FIG. 6 causes the hold signal HS to be input to the quantizing section 40, and so the loop band in the sigma-delta AD conversion is determined by the frequency characteristics of the sampling section 20. Therefore, in the example of FIG. 6, the sampling section 20 preferably has frequency characteristics including a wider frequency band.
As shown in FIG. 5, when the sampling section 20 is provided in parallel with the quantizing section 40 between the output end of the difference generating section 10 and the input end of the error calculating section 60, the frequency characteristics of the sampling section 20 do not affect the loop band in the sigma-delta AD conversion. Therefore, when there is no limitation on the arrangement of the circuit elements, the sampling section 20 is preferably provided in parallel with the quantizing section 40 between the output end of the difference generating section 10 and the input end of the error calculating section 60.
FIG. 7 shows an exemplary configuration of another measurement circuit 100. The measurement circuit 100 of the present embodiment differs from the measurement circuit 100 shown in FIG. 5 in that the position of the sampling section 20 is different. The remaining configuration may be the same as that of the measurement circuit 100 shown in FIG. 5.
The measurement circuit 100 of the present embodiment includes the sampling section 20 between the output end of the error calculating section 60 and the input end of the integrating section 30. The sampling section 20 outputs a hold signal corresponding to the signal output by the error calculating section 60. The integrating section 30 integrates the hold signal output by the sampling section 20. With this configuration as well, the sigma-delta AD conversion can be easily performed on a high-frequency signal under measurement.
FIG. 8 shows another exemplary configuration of the measurement circuit 100. The measurement circuit 100 of the present embodiment differs from the measurement circuits 100 described in FIGS. 1 to 7 by including a plurality of sampling sections 20 connected in cascade instead of a single sampling section 20. The remaining configuration may be the same as that of any one of the measurement circuits 100 described in relation to FIGS. 1 to 7. FIG. 8 shows a measurement circuit 100 resulting from the inclusion of the plurality of sampling sections 20 connected in cascade in the configuration shown in FIG. 5.
Each sampling section 20 has a different aperture time for acquiring the level of the received signal. Each sampling section 20 may average or integrate the signal level of the signal under measurement over a time period from when the pulse of the measurement clock Tcck is received to when the aperture time has passed, and output the result. For example, in the example described in FIGS. 3 and 4, the aperture time corresponds to the width of the pulse output by the pulse generating section 26.
FIG. 9 shows exemplary frequency characteristics of the sampling section 20. In FIG. 9, the horizontal axis represents frequency and the vertical axis represents gain. When the sampling section 20 averages or integrates the signal level of the signal under measurement within an aperture time, as described above, a signal whose signal period is equal to one divided by an integer multiple of the aperture time receives a gain of 0 from the sample/hold section 20.
In other words, for a signal whose signal period is equal to one divided by an integer multiple of the aperture time, the sampling section 20 does not change the output value no matter which timing is used for the sampling. Therefore, as shown in FIG. 9, the output gain of the sample/hold section 20 is 0 at a frequency that is an integer multiple of the frequency fa corresponding to the aperture time Ta, where fa=1/Ta.
FIG. 10 shows frequency characteristics of the output from a final-stage sampling section 20-n with respect to the input to a first-stage sampling section 20-1. When a plurality of sampling sections 20 having slightly different aperture times are connected in cascade, a notched portion of the frequency characteristic is continuous, and therefore in the overall frequency characteristic, the output gain becomes substantially zero within a specific frequency range. The aperture times of the sampling sections 20 may be set such that the notch frequencies of the sampling sections 20 are uniformly distributed between predetermined frequencies fal and fan. The aperture time of each sampling section 20 may be changeable.
With this configuration, the sampling sections 20 can function as a band pass filter. Therefore, the loop band or the like in the sigma-delta AD conversion can be controlled, for example.
In the examples of FIGS. 1 to 10, the measurement circuit 100 is provided on the same electronic device 200 as the circuit under measurement 108, but as another example, the measurement circuit 100 may be provided in a different device than the circuit under measurement 108.
While the embodiments of the present invention have been described, the technical scope of the invention is not limited to the above described embodiments. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiments. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention.
The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams can be performed in any order as long as the order is not indicated by “prior to,” “before,” or the like and as long as the output from a previous process is not used in a later process. Even if the process flow is described using phrases such as “first” or “next” in the claims, embodiments, or diagrams, it does not necessarily mean that the process must be performed in this order.

Claims

1. A measurement circuit that is provided in the same electronic device as a circuit under measurement, comprises a difference generating section and an integrating section, and performs a sigma-delta AD conversion on a signal under measurement output by the circuit under measurement, the measurement circuit further comprising:

a sampling section that is provided between an output end of the difference generating section and an input end of the integrating section, detects a level of a signal input thereto at predetermined sampling intervals, and outputs a sampled signal corresponding to the detected signal level.

2. The measurement circuit according to claim 1, further comprising a quantizing section and a feedback section, wherein

the difference generating section decreases a signal level of the signal under measurement according to a feedback signal input thereto, and inputs the resulting signal to the sampling section,

the integrating section integrates the signal level of the sampled signal output by the sampling section,

the quantizing section outputs a digital signal corresponding to the integrated value from the integrating section, and

when the quantizing section outputs the digital signal, the feedback section inputs to the difference generating section the feedback signal with a signal level corresponding to a value of the digital signal.

3. The measurement circuit according to claim 1, further comprising a quantizing section, a feedback section, and an error calculating section, wherein

the difference generating section decreases a signal level of the signal under measurement according to a feedback signal input thereto, and outputs the resulting signal,

the quantizing section outputs a digital signal corresponding to a signal level of a signal output by the difference generating section,

the error calculating section calculates an error between the level of the signal output by the difference generating section and a value of the digital signal,

the integrating section integrates the error calculated by the error calculating section, and

the feedback section inputs to the difference generating section the feedback signal with a signal level corresponding to the integrated value from the integrating section.

4. The measurement circuit according to claim 3, wherein

the sampling section is provided between an output end of the difference generating section and an input end of the error calculating section.

5. The measurement circuit according to claim 3, further comprising a branching path that branches the signal output by the difference generating section and inputs the resulting signals to the quantizing section and the error calculating section, wherein

the sampling section is provided between the branching path and an input end of the error calculating section.

6. The measurement circuit according to claim 2, wherein

the sampling section detects the signal level output by the difference generating section, with an operational period that is greater than a period of the signal under measurement.

7. The measurement circuit according to claim 6, wherein

the quantizing section detects a value of the integration result from the integrating section, with a period equal to the operational period of the sampling section, and outputs a digital signal corresponding to the detected value.

8. The measurement circuit according to claim 2, comprising a plurality of the sampling sections that are connected in cascade and that each have a different aperture timing for acquiring a level of a signal input thereto.

9. The measurement circuit according to claim 1, wherein

the sampling section outputs a sampled signal obtained by holding the signal level detected at each sampling interval for a time period corresponding to the sampling interval.

10. An electronic device comprising:

the measurement circuit according to claim 1; and

the circuit under measurement.

11. A measurement circuit that comprises a difference generating section and an integrating section and that performs a sigma-delta AD conversion on a signal under measurement, the measurement circuit further comprising:

a sampling section that is provided between an output end of the difference generating section and an input end of the integrating section, detects a level of a signal input thereto at predetermined sampling intervals, and outputs a sampled signal obtained by holding the signal level detected at each sampling interval for a time period corresponding to the sampling interval.