US20110115080A1 - Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same - Google Patents

Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same Download PDF

Info

Publication number
US20110115080A1
US20110115080A1 US12/944,114 US94411410A US2011115080A1 US 20110115080 A1 US20110115080 A1 US 20110115080A1 US 94411410 A US94411410 A US 94411410A US 2011115080 A1 US2011115080 A1 US 2011115080A1
Authority
US
United States
Prior art keywords
semiconductor
sealing layer
base plate
semiconductor device
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/944,114
Inventor
Shinji Wakisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tera Probe Inc
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Assigned to CASIO COMPUTER CO., LTD. reassignment CASIO COMPUTER CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WAKISAKA, SHINJI
Publication of US20110115080A1 publication Critical patent/US20110115080A1/en
Assigned to TERAMIKROS, INC. reassignment TERAMIKROS, INC. CHANGE OF OWNERSHIP BY CORPORATE SEPARATION Assignors: CASIO COMPUTER CO., LTD.
Assigned to TERAMIKROS, INC. reassignment TERAMIKROS, INC. CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE'S ADDRESS ON REEL 027520/FRAME 0401 Assignors: CASIO COMPUTER CO., LTD.
Assigned to TERA PROBE, INC. reassignment TERA PROBE, INC. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: TERAMIKROS, INC.
Priority to US14/299,775 priority Critical patent/US9105580B2/en
Priority to US14/791,068 priority patent/US9343428B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1161—Physical or chemical etching
    • H01L2224/11612—Physical or chemical etching by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method of the same.
  • Jpn. Pat. Appln. KOKAI Publication No. 2008-60298 has disclosed a so-called water level package (WLP) and embedded water level package (EWLP) as IC chip packaging methods.
  • the WLP method includes sealing a wafer-state semiconductor wafer with a resin, forming a terminal in the semiconductor wafer, and then cutting the semiconductor wafer into a chip size (e.g., see FIG. 2 to FIG. 10 of Patent document 1). As a result, a small package equal in size to the built-in IC chip can be manufactured.
  • the EWLP method includes further packaging a chip manufactured by the WLP method to embed the chip in a substrate (e.g., see FIG. 11 to FIG. 16 of Patent document 1). More specifically, a plurality of semiconductor chips ( 2 ) packaged by the WLP method are arranged on a base plate ( 1 ). A lattice-like semi-cured resin sheet ( 14 a ) is laid on the base plate ( 1 ) around the semiconductor chips ( 2 ), and another semi-cured resin sheet ( 15 a ) is further laid on the semi-cured resin sheet ( 14 a ) and the semiconductor chips ( 2 ). These semi-cured resin sheets ( 14 a , 15 a ) are cured by heating and pressurization.
  • a via ( 16 ) is formed by laser in an insulating layer ( 15 ) which is formed by the curing of the semi-cured resin sheet ( 15 a ).
  • Wiring lines ( 17 , 18 ) are formed by a semi-additive process. The wiring lines ( 17 , 18 ) are connected to an electrode ( 12 ) of the semiconductor chip ( 2 ).
  • a solder ( 21 ) is then formed on the wiring lines ( 17 , 18 ), and the base plate ( 1 ), a sealing layer ( 14 ) and the insulating layer ( 15 ) are diced for each of the semiconductor chips ( 2 ).
  • Patent document 1 requires a step of forming a via ( 16 ) by laser to connect the wiring lines ( 17 , 18 ) to the electrode ( 12 ). To this end, equipment for laser processing is needed. Moreover, the number of manufacturing steps is increased, and the manufacturing costs rise.
  • It is therefore an object of the present invention is to enable the elimination of the step of forming the via by laser processing and to reduce the manufacturing steps, manufacturing time and manufacturing costs of a semiconductor device.
  • a semiconductor device comprising: a semiconductor construct including a semiconductor substrate, and a columnar electrode provided to protrude on the surface of the semiconductor substrate; a base plate on which the semiconductor construct is installed; and a sealing layer stacked on the semiconductor substrate except for the columnar electrode and on the base plate including the side surface of the semiconductor substrate.
  • a semiconductor device manufacturing method comprising: mounting a plurality of semiconductor constructs on a base plate, each of the semiconductor constructs including a columnar electrode provided to protrude on the surface of a semiconductor substrate; and stacking a sealing layer on the semiconductor substrate except for the columnar electrode and on the base plate including the side surface of the semiconductor substrate.
  • FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2A , 2 B, 2 C, and 2 D are process charts of a method of manufacturing the semiconductor device shown in FIG. 1 ;
  • FIGS. 3A , 3 B, and 3 C are process charts following steps in FIG. 2 ;
  • FIGS. 4A , and 4 B are process charts following steps in FIG. 3 ;
  • FIGS. 5A , and 5 B are process charts following steps in FIG. 4 ;
  • FIGS. 6A , and 6 B are process charts following steps in FIG. 5 ;
  • FIGS. 7A , and 7 B are process charts following steps in FIG. 6 .
  • FIG. 1 is a sectional view of a semiconductor device 1 .
  • This semiconductor device 1 comprises a base plate 31 , a semiconductor construct 10 , a sealing layer 32 , an upper wiring line 33 and a solder ball 35 .
  • the semiconductor construct 10 includes a semiconductor chip 11 , a passivation film 13 , a plurality of connection pads 12 , a protective film 25 , a rewiring line 21 and a columnar electrode (an external connection electrode) 22 .
  • the columnar electrode 22 in the shape of a circular cylinder, a prism or some other column is provided to protrude on the surface of the semiconductor chip 11 .
  • the semiconductor chip 11 is bonded onto the base plate 31 by an adhesive layer 30 .
  • the sealing layer 32 is stacked on the base plate 31 to cover the semiconductor chip 11 .
  • the columnar electrode 22 penetrates the sealing layer 32 .
  • the semiconductor chip 11 is a semiconductor substrate in the form of a piece.
  • the semiconductor chip 11 is made of, for example, silicon.
  • An LSI is formed on the surface of the semiconductor chip 11 .
  • the connection pads 12 are formed on the surface of the semiconductor chip 11 , and are connected to a wiring line of the LSI.
  • the passivation film 13 covers the LSI.
  • the passivation film 13 is made of, for example, silicon oxide or silicon nitride.
  • the passivation film 13 is provided with an opening 13 a that exposes the connection pad 12 .
  • the protective film 25 is stacked on the passivation film 13 .
  • the protective film 25 is made of a polyimide resin or some other resin.
  • a high-function plastic material such as polyimide (PI) or polybenzoxazole (PBO), an epoxy, phenol or silicon plastic material, or a composite material of the above materials.
  • the protective film 25 is provided with an opening 25 a that exposes the connection pad 12 .
  • the opening 25 a of the protective film 25 is smaller than the opening 13 a of the passivation film 13 .
  • the connection pad 12 and the protective film 25 are in close contact at the outer circumferential portion of the opening 25 a.
  • a foundation metal layer (not shown) is formed on the protective film 25 including the upper surface of the connection pad 12 .
  • the foundation metal layer is a copper (Cu) film, or a film in which copper is stacked on titanium (Ti). When viewed in plan, the foundation metal layer is patterned into a predetermined shape.
  • the foundation metal layer is partly stacked on the connection pad 12 , and is connected to the connection pad 12 via the openings 13 a , 25 a .
  • the rewiring line 21 is formed on the foundation metal layer.
  • the rewiring line 21 is a copper (Cu) film. When viewed in plan, the rewiring line 21 is patterned into a predetermined shape. The patterned shapes of the rewiring line 21 and the foundation metal layer are substantially the same.
  • no protective film 25 may be formed, and the rewiring line 21 may be formed on the passivation film 13 .
  • the columnar electrode 22 is formed on part of the rewiring line 21 .
  • the columnar electrode 22 is made of copper or some other metal.
  • Each rewiring line 21 electrically connects the corresponding connection pad 12 and columnar electrode 22 .
  • the semiconductor chip 11 is bonded to the base plate 31 by the adhesive layer 30 .
  • the bonding surface of the semiconductor chip 11 is opposite to the surface in which the passivation film 13 , the connection pad 12 and the columnar electrode 22 are formed.
  • the base plate 31 is made of a glass fiber reinforced epoxy resin (including a glass fabric epoxy resin), a carbon fiber reinforced epoxy resin (including a carbon fabric epoxy resin), a glass fiber reinforced polyimide resin (including a glass fabric polyimide resin), a carbon fiber reinforced polyimide resin (including a carbon fabric polyimide resin), or some other fiber reinforced resin.
  • a glass fiber reinforced epoxy resin including a glass fabric epoxy resin
  • a carbon fiber reinforced epoxy resin including a carbon fabric epoxy resin
  • a glass fiber reinforced polyimide resin including a glass fabric polyimide resin
  • a carbon fiber reinforced polyimide resin including a carbon fabric polyimide resin
  • the sealing layer 32 is stacked on the surface of the semiconductor chip 11 except for the columnar electrode 22 and on the base plate 31 including the side surface of the semiconductor chip 11 .
  • the sealing layer 32 is stacked on the base plate 31 around the semiconductor chip 11 .
  • the semiconductor chip 11 is covered with the sealing layer 32 .
  • Part of the sealing layer 32 is stacked on the semiconductor chip 11 .
  • the rewiring line 21 is covered with the sealing layer 32 except for the part where the columnar electrode 22 is formed.
  • the columnar electrode 22 penetrates the sealing layer 32 .
  • the surface of the sealing layer 32 is provided to be flush with the surface (top face) of the columnar electrode 22 .
  • the surface of the columnar electrode 22 is not covered with the sealing layer 32 .
  • the sealing layer 32 is formed by curing a sheet-like resin (prepreg) in a semi-cured condition (B-stage condition).
  • the sealing layer 32 is made of a fiber reinforced resin or a resin which is not fiber reinforced. More specifically, the sealing layer 32 is made of a glass fiber reinforced epoxy resin (including a glass fabric epoxy resin), a glass fiber reinforced polyimide resin (including a glass fabric polyimide resin), or some other fiber reinforced resin. Alternatively, the sealing layer 32 is made of a substrate material epoxy resin which is not fiber reinforced, a substrate material polyimide resin, or some other substrate material resin.
  • such materials include MEGTRON6 which is a multilayer printed circuit board material having a low dielectric constant and high heat resistance and which is manufactured by Panasonic Electric Works Co., Ltd., and MEGTRON3 which is a semiconductor package substrate material.
  • FR-4 multilayer material “MCL” manufactured by Hitachi Chemical Co., Ltd., a highly heat-resistant and highly reliable FR-4 multilayer material “MCL”, a halogen-free FR-4 multilayer material “MCL”, a high Tg epoxy multilayer material “MCL”, a highly elastic and low thermal expansion multilayer material “MCL”, a halogen-free highly elastic and low thermal expansion multilayer material “MCL”, a halogen-free highly elastic and low thermal expansion multilayer material “MCL” for a thin package, a low dielectric loss tangent and highly heat-resistant multilayer material “MCL”, a halogen-free low dielectric loss tangent and highly heat-resistant multilayer material “MCL” having a low dielectric constant, or a
  • the upper wiring line 33 is formed on the sealing layer 32 .
  • the upper wiring line 33 is a copper (Cu) film, a titanium (Ti) film, a film in which copper is stacked on titanium, or some other conductive film.
  • the upper wiring line 33 is patterned into a predetermined shape. Part of the upper wiring line 33 is stacked on the surface (top face) of the columnar electrode 22 , and the upper wiring line 33 is connected to the columnar electrode 22 .
  • An overcoat film 34 is stacked on the sealing layer 32 , and the upper wiring line 33 is covered with the overcoat film 34 .
  • the overcoat film 34 is made of a resin material.
  • the overcoat film 34 is a solder resist. That is, an opening 34 a is formed in the overcoat film 34 , and part of the upper wiring line 33 is exposed in the opening 34 a , on which the solder ball 35 is formed.
  • the solder ball 35 is coupled to the upper wiring line 33 so that the solder ball 35 and the upper wiring line 33 are electrically connected to each other. In addition, no solder ball 35 may be provided.
  • a conductive film 36 is stacked on the surface opposite to the surface on which the semiconductor chip 11 is installed.
  • An overcoat layer 37 is stacked on the conductive film 36 .
  • the conductive film 36 has the same composition as the upper wiring line 33 .
  • the overcoat layer 37 has the same composition as the overcoat film 34 .
  • one semiconductor chip 11 is installed on the base plate 31 , and this semiconductor chip 11 is embedded in the sealing layer 32 .
  • a plurality of semiconductor chips 11 may be installed on the base plate 31 , and these semiconductor chips 11 may be embedded in the sealing layer 32 .
  • FIG. 2 to FIG. 7 are diagrams showing the method of manufacturing the semiconductor device 1 .
  • the method of manufacturing the semiconductor device 1 is broadly divided into a preprocess shown in FIG. 2 and FIG. 3 and a post-process shown in FIG. 4 to FIG. 7 .
  • the preprocess is a process for manufacturing the semiconductor construct 10 .
  • the post-process is a process for packaging the manufactured semiconductor construct 10 .
  • FIG. 2A is a sectional view of a semiconductor wafer 110 before diced.
  • the semiconductor wafer 110 is a semiconductor substrate which is not divided into pieces. That is, the semiconductor wafer 110 is separated into a plurality of chip regions 111 by lattice-like dicing streets 112 that serve as scheduled dividing lines. These chip regions 111 are arranged in matrix form.
  • An LSI is formed on the surface of the semiconductor wafer 110 for each of the chip regions 111 .
  • a plurality of connection pads 12 are also formed on the surface of the semiconductor wafer 110 .
  • a passivation film 13 is formed on the surface of the semiconductor wafer 110 , and the LSI is covered with the passivation film 13 .
  • an insulating resin film is formed on the surface of the semiconductor wafer 110 .
  • This insulating resin film is patterned to form an opening 25 a and a trench 25 b in this film.
  • the insulating resin film is then divided into protective films 25 for the respective chip regions 111 .
  • the trenches 25 b are formed into a lattice shape along the dicing streets 112 .
  • a foundation metal layer and a rewiring line 21 are formed.
  • the semi-additive process is used as a method of forming the foundation metal layer and the rewiring line 21 .
  • the foundation metal layer is formed on the entire upper surface of the protective film 25 including the upper surface of the connection pad 12 exposed through the openings 13 a , 25 a of the passivation film 13 and the protective film 25 .
  • the foundation metal layer may only be a copper layer formed by electroless plating, may only be a copper layer formed by sputtering, or may be a copper layer formed by sputtering on a thin layer of, for example, titanium formed by sputtering.
  • a plating resist film is patterned/formed on the upper surface of the foundation metal layer.
  • an opening is formed in a part of the plating resist film corresponding to a region where the rewiring line 21 is to be formed.
  • the rewiring line 21 is formed on the foundation metal layer. More specifically, electrolytic plating with copper is carried out using the foundation metal layer as a plating current path, thereby forming the rewiring line 21 on the upper surface of the foundation metal layer within the opening of the plating resist film.
  • the plating resist film is released. At this moment, the foundation metal layer has not been patterned yet.
  • a dry film resist 122 thicker than the rewiring line 21 is affixed to one surface on the rewiring line 21 and the protective film 25 .
  • This dry film resist 122 is exposed and developed to form an opening 122 a in the dry film resist 122 .
  • the position to form the opening 122 a is the position of a columnar electrode 22 to be formed later.
  • the dry film resist 122 is left in the position where the columnar electrode 22 to be formed later is not formed.
  • the electrolytic plating method is carried out using the rewiring line 21 as an electrode so that the dry film resist 122 is used as a mask to cover part of the rewiring line 21 with the dry film resist 122 .
  • the columnar electrode 22 is grown on the rewiring line 21 within the opening 122 a .
  • the columnar electrode 22 is grown to be thicker than the rewiring line 21 .
  • the dry film resist 122 is removed after the formation of the columnar electrode 22 .
  • part of the foundation metal layer of the rewiring line 21 that does not overlap the patterned rewiring line 21 is removed by etching.
  • the upper layer of the rewiring line 21 and the surface of the columnar electrode 22 are partly etched.
  • the rewiring line 21 and the columnar electrode 22 are sufficiently thicker than the foundation metal layer, so that the rewiring line 21 and the columnar electrode 22 remain.
  • the semiconductor wafer 110 is diced along the dicing streets 112 , and the semiconductor wafer 110 is divided into a plurality of semiconductor chips 11 .
  • a semiconductor construct 10 provided with a plurality of columnar electrodes 22 erected on the surface of the semiconductor chip 11 is completed.
  • a mother base plate 131 is prepared.
  • An adhesive layer 30 is applied or affixed and thereby formed in a region on one surface of the mother base plate 131 where the semiconductor chip 11 is installed.
  • a plurality of semiconductor chips 11 are arranged on the mother base plate 131 in matrix form, and the semiconductor chips 11 are bonded to the mother base plate 131 by the adhesive layer 30 .
  • the semiconductor chips 11 are installed on the mother base plate 131 in matrix form.
  • the mother base plate 131 is the base plate 31 shown in FIG. 1 before cut.
  • a single layer sheet-like prepreg 132 is stacked on the mother base plate 131 from above the semiconductor chips 11 and the columnar electrodes 22 , and the prepreg 132 is pressurized and heated.
  • the prepreg 132 is pressurized toward the mother base plate 131 .
  • part of the prepreg 132 is stacked on the semiconductor chip 11 , and the semiconductor chips 11 are embedded in the prepreg 132 .
  • the columnar electrode 22 is put through the prepreg 132 .
  • the prepreg 132 is heated and thereby cured into a sealing layer 32 .
  • the prepreg 132 is a fiber reinforced prepreg.
  • the prepreg 132 is a prepreg which is not fiber reinforced.
  • the fiber reinforced prepreg is formed by impregnating a fiber (e.g., glass fiber, glass fabric, carbon fiber, carbon fabric) with a thermosetting resin (e.g., epoxy resin, polyimide resin) and semi-curing the resin into a sheet form.
  • a fiber e.g., glass fiber, glass fabric, carbon fiber, carbon fabric
  • a thermosetting resin e.g., epoxy resin, polyimide resin
  • thermosetting resin e.g., epoxy resin, polyimide resin
  • the fiber reinforced prepreg it is particularly preferable to use a semi-cured glass fiber reinforced epoxy resin or glass fiber reinforced polyimide resin.
  • the prepreg which is not fiber reinforced it is particularly preferable to use a semi-cured glass epoxy resin or polyimide resin which is not fiber reinforced.
  • the surface of the sealing layer 32 and the top face of the columnar electrode 22 are ground.
  • the surface of the sealing layer 32 and the top face of the columnar electrode 22 are planarized by grinding.
  • the top face of the columnar electrode 22 which is not exposed from the surface of the sealing layer 32 before grinding is exposed by grinding.
  • a conductive layer 133 is grown on the surface of the sealing layer 32 and the top face of the columnar electrode 22 by an electroless plating method, electrolytic plating method or vapor-phase growth method (e.g., a sputter method) or by a combination of these methods.
  • a conductive film 36 also grows on the opposite surface.
  • a resist (a dry film resist or liquid resist will also do) is applied to the conductive layer 133 .
  • the resist is exposed and developed.
  • the remaining resist is used as a mask to etch the conductive layer 133 .
  • the conductive layer 133 is formed/processed into an upper wiring line 33 , as shown in FIG. 6A . After the upper wiring line 33 is patterned, the resist is removed.
  • the overcoat film 34 is patterned, so that the upper wiring line 33 and the sealing layer 32 are covered with the overcoat film 34 , and part of the upper wiring line 33 is exposed through an opening 34 a of the overcoat film 34 .
  • an overcoat layer 37 is also formed on the opposite surface.
  • insulating layers and rewiring lines may be alternately formed to produce multilayer wiring lines.
  • a through-hole may be formed from the surface of the sealing layer 32 to the opposite surface of the mother base plate 131 .
  • solder ball 35 is formed on the upper wiring line 33 within each opening 34 a .
  • the formation of the solder ball 35 may be omitted, or the solder ball 35 may be formed after dicing processing described later.
  • the mother base plate 131 and the sealing layer 32 are diced into a lattice shape for each semiconductor chip 11 , and divided to form a plurality of semiconductor devices 1 .
  • the mother base plate 131 is divided by dicing into the base plates 31 for the respective semiconductor devices 1 , and the sealing layer 32 is also divided. In consequence, the semiconductor device 1 is completed.
  • the mother base plate 131 and the sealing layer 32 are not diced for each semiconductor chip 11 but are diced for each combination of semiconductor chips 11 .
  • the prepreg 132 is used (see FIG. 4B ) when the sealing layer 32 is formed.
  • the columnar electrode 22 formed on the semiconductor chip 11 in advance can be put through the prepreg 132 . That is, the prepreg 132 is stacked, heated and pressurized, and then ground to form the sealing layer 32 . Therefore, the step of forming the sealing layer 32 serves both as a step of forming an insulating layer (sealing layer) that covers the upper surface of the semiconductor chip 11 and a step of forming an insulating layer (sealing layer) that covers the circumferential side surface of the semiconductor construct 10 including the semiconductor chip 11 .
  • the steps of forming the insulating layers (sealing layers) can be reduced.
  • the upper surface of a sealing film ( 13 ) of a semiconductor construct ( 2 ) and the upper surface of an insulating layer ( 14 ) can be flat as far as the process is concerned.
  • steps are produced due to, for example, curing, contraction or thermal expansion, and wiring lines may be broken. Therefore, after the upper insulating layer ( 15 ) is formed on the semiconductor construct ( 2 ) and the upper surface of the insulating layer ( 14 ), the via ( 16 ) is formed by laser, and then the upper wiring line ( 18 ) is formed on the upper insulating layer ( 15 ).
  • the upper wiring line 33 can be directly formed on the sealing layer 32 . Therefore, there is no need for a step of forming a via in the sealing layer 32 by laser after the sealing layer 32 is formed and forming an electrode in the laser via. This makes it possible to reduce the steps, time and costs required for the manufacture of the semiconductor device 1 . Moreover, it is not necessary to form an upper insulating film, so that the semiconductor device 1 can be smaller in thickness.
  • the thick sealing layer 32 can be formed around the columnar electrode 22 even if the columnar electrode 22 is high.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A semiconductor device comprises a semiconductor construct including a semiconductor substrate, and an external connection electrode provided to protrude on the surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including the side surface of the semiconductor substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2009-259874, filed Nov. 13, 2009, the entire contents of which are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device and a manufacturing method of the same.
  • 2. Description of the Related Art
  • Jpn. Pat. Appln. KOKAI Publication No. 2008-60298 has disclosed a so-called water level package (WLP) and embedded water level package (EWLP) as IC chip packaging methods. The WLP method includes sealing a wafer-state semiconductor wafer with a resin, forming a terminal in the semiconductor wafer, and then cutting the semiconductor wafer into a chip size (e.g., see FIG. 2 to FIG. 10 of Patent document 1). As a result, a small package equal in size to the built-in IC chip can be manufactured.
  • The EWLP method includes further packaging a chip manufactured by the WLP method to embed the chip in a substrate (e.g., see FIG. 11 to FIG. 16 of Patent document 1). More specifically, a plurality of semiconductor chips (2) packaged by the WLP method are arranged on a base plate (1). A lattice-like semi-cured resin sheet (14 a) is laid on the base plate (1) around the semiconductor chips (2), and another semi-cured resin sheet (15 a) is further laid on the semi-cured resin sheet (14 a) and the semiconductor chips (2). These semi-cured resin sheets (14 a, 15 a) are cured by heating and pressurization. Further, a via (16) is formed by laser in an insulating layer (15) which is formed by the curing of the semi-cured resin sheet (15 a). Wiring lines (17, 18) are formed by a semi-additive process. The wiring lines (17, 18) are connected to an electrode (12) of the semiconductor chip (2). A solder (21) is then formed on the wiring lines (17, 18), and the base plate (1), a sealing layer (14) and the insulating layer (15) are diced for each of the semiconductor chips (2).
  • Meanwhile, the manufacturing method described in Patent document 1 requires a step of forming a via (16) by laser to connect the wiring lines (17, 18) to the electrode (12). To this end, equipment for laser processing is needed. Moreover, the number of manufacturing steps is increased, and the manufacturing costs rise.
  • It is therefore an object of the present invention is to enable the elimination of the step of forming the via by laser processing and to reduce the manufacturing steps, manufacturing time and manufacturing costs of a semiconductor device.
    • BRIEF SUMMARY OF THE INVENTION
  • To achieve to foregoing object, according to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor construct including a semiconductor substrate, and a columnar electrode provided to protrude on the surface of the semiconductor substrate; a base plate on which the semiconductor construct is installed; and a sealing layer stacked on the semiconductor substrate except for the columnar electrode and on the base plate including the side surface of the semiconductor substrate.
  • According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: mounting a plurality of semiconductor constructs on a base plate, each of the semiconductor constructs including a columnar electrode provided to protrude on the surface of a semiconductor substrate; and stacking a sealing layer on the semiconductor substrate except for the columnar electrode and on the base plate including the side surface of the semiconductor substrate.
  • Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.
  • FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
  • FIGS. 2A, 2B, 2C, and 2D are process charts of a method of manufacturing the semiconductor device shown in FIG. 1;
  • FIGS. 3A, 3B, and 3C are process charts following steps in FIG. 2;
  • FIGS. 4A, and 4B are process charts following steps in FIG. 3;
  • FIGS. 5A, and 5B are process charts following steps in FIG. 4;
  • FIGS. 6A, and 6B are process charts following steps in FIG. 5; and
  • FIGS. 7A, and 7B are process charts following steps in FIG. 6.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • An embodiment of the present invention will be described hereinafter with reference to the drawings. Although various restrictions which are technically preferable to carry out the present invention are imposed on the embodiment described below, the scope of the invention is not limited to the following embodiment and examples shown in the drawings.
  • FIG. 1 is a sectional view of a semiconductor device 1.
  • This semiconductor device 1 comprises a base plate 31, a semiconductor construct 10, a sealing layer 32, an upper wiring line 33 and a solder ball 35. The semiconductor construct 10 includes a semiconductor chip 11, a passivation film 13, a plurality of connection pads 12, a protective film 25, a rewiring line 21 and a columnar electrode (an external connection electrode) 22. Further, the columnar electrode 22 in the shape of a circular cylinder, a prism or some other column is provided to protrude on the surface of the semiconductor chip 11. The semiconductor chip 11 is bonded onto the base plate 31 by an adhesive layer 30. The sealing layer 32 is stacked on the base plate 31 to cover the semiconductor chip 11. The columnar electrode 22 penetrates the sealing layer 32.
  • The semiconductor chip 11 is a semiconductor substrate in the form of a piece. The semiconductor chip 11 is made of, for example, silicon. An LSI is formed on the surface of the semiconductor chip 11. The connection pads 12 are formed on the surface of the semiconductor chip 11, and are connected to a wiring line of the LSI. The passivation film 13 covers the LSI. The passivation film 13 is made of, for example, silicon oxide or silicon nitride. The passivation film 13 is provided with an opening 13 a that exposes the connection pad 12.
  • The protective film 25 is stacked on the passivation film 13. The protective film 25 is made of a polyimide resin or some other resin. For the protective film 25, it is possible to use, for example, a high-function plastic material such as polyimide (PI) or polybenzoxazole (PBO), an epoxy, phenol or silicon plastic material, or a composite material of the above materials.
  • The protective film 25 is provided with an opening 25 a that exposes the connection pad 12. The opening 25 a of the protective film 25 is smaller than the opening 13 a of the passivation film 13. The connection pad 12 and the protective film 25 are in close contact at the outer circumferential portion of the opening 25 a.
  • A foundation metal layer (not shown) is formed on the protective film 25 including the upper surface of the connection pad 12. The foundation metal layer is a copper (Cu) film, or a film in which copper is stacked on titanium (Ti). When viewed in plan, the foundation metal layer is patterned into a predetermined shape. The foundation metal layer is partly stacked on the connection pad 12, and is connected to the connection pad 12 via the openings 13 a, 25 a. The rewiring line 21 is formed on the foundation metal layer. The rewiring line 21 is a copper (Cu) film. When viewed in plan, the rewiring line 21 is patterned into a predetermined shape. The patterned shapes of the rewiring line 21 and the foundation metal layer are substantially the same. In addition, no protective film 25 may be formed, and the rewiring line 21 may be formed on the passivation film 13.
  • The columnar electrode 22 is formed on part of the rewiring line 21. The columnar electrode 22 is made of copper or some other metal. Each rewiring line 21 electrically connects the corresponding connection pad 12 and columnar electrode 22.
  • The semiconductor chip 11 is bonded to the base plate 31 by the adhesive layer 30. The bonding surface of the semiconductor chip 11 is opposite to the surface in which the passivation film 13, the connection pad 12 and the columnar electrode 22 are formed.
  • The base plate 31 is made of a glass fiber reinforced epoxy resin (including a glass fabric epoxy resin), a carbon fiber reinforced epoxy resin (including a carbon fabric epoxy resin), a glass fiber reinforced polyimide resin (including a glass fabric polyimide resin), a carbon fiber reinforced polyimide resin (including a carbon fabric polyimide resin), or some other fiber reinforced resin.
  • The sealing layer 32 is stacked on the surface of the semiconductor chip 11 except for the columnar electrode 22 and on the base plate 31 including the side surface of the semiconductor chip 11. Here, the sealing layer 32 is stacked on the base plate 31 around the semiconductor chip 11. The semiconductor chip 11 is covered with the sealing layer 32. Part of the sealing layer 32 is stacked on the semiconductor chip 11. The rewiring line 21 is covered with the sealing layer 32 except for the part where the columnar electrode 22 is formed. The columnar electrode 22 penetrates the sealing layer 32. The surface of the sealing layer 32 is provided to be flush with the surface (top face) of the columnar electrode 22. The surface of the columnar electrode 22 is not covered with the sealing layer 32.
  • The sealing layer 32 is formed by curing a sheet-like resin (prepreg) in a semi-cured condition (B-stage condition). The sealing layer 32 is made of a fiber reinforced resin or a resin which is not fiber reinforced. More specifically, the sealing layer 32 is made of a glass fiber reinforced epoxy resin (including a glass fabric epoxy resin), a glass fiber reinforced polyimide resin (including a glass fabric polyimide resin), or some other fiber reinforced resin. Alternatively, the sealing layer 32 is made of a substrate material epoxy resin which is not fiber reinforced, a substrate material polyimide resin, or some other substrate material resin. For example, such materials include MEGTRON6 which is a multilayer printed circuit board material having a low dielectric constant and high heat resistance and which is manufactured by Panasonic Electric Works Co., Ltd., and MEGTRON3 which is a semiconductor package substrate material. It is also possible to use an FR-4 multilayer material “MCL” manufactured by Hitachi Chemical Co., Ltd., a highly heat-resistant and highly reliable FR-4 multilayer material “MCL”, a halogen-free FR-4 multilayer material “MCL”, a high Tg epoxy multilayer material “MCL”, a highly elastic and low thermal expansion multilayer material “MCL”, a halogen-free highly elastic and low thermal expansion multilayer material “MCL”, a halogen-free highly elastic and low thermal expansion multilayer material “MCL” for a thin package, a low dielectric loss tangent and highly heat-resistant multilayer material “MCL”, a halogen-free low dielectric loss tangent and highly heat-resistant multilayer material “MCL” having a low dielectric constant, or a halogen-free highly heat-resistant multilayer material “MCL” having a low dielectric constant. The sealing layer 32 has light blocking properties.
  • The upper wiring line 33 is formed on the sealing layer 32. The upper wiring line 33 is a copper (Cu) film, a titanium (Ti) film, a film in which copper is stacked on titanium, or some other conductive film. When viewed in plan, the upper wiring line 33 is patterned into a predetermined shape. Part of the upper wiring line 33 is stacked on the surface (top face) of the columnar electrode 22, and the upper wiring line 33 is connected to the columnar electrode 22.
  • An overcoat film 34 is stacked on the sealing layer 32, and the upper wiring line 33 is covered with the overcoat film 34. The overcoat film 34 is made of a resin material. The overcoat film 34 is a solder resist. That is, an opening 34 a is formed in the overcoat film 34, and part of the upper wiring line 33 is exposed in the opening 34 a, on which the solder ball 35 is formed. The solder ball 35 is coupled to the upper wiring line 33 so that the solder ball 35 and the upper wiring line 33 are electrically connected to each other. In addition, no solder ball 35 may be provided.
  • A conductive film 36 is stacked on the surface opposite to the surface on which the semiconductor chip 11 is installed. An overcoat layer 37 is stacked on the conductive film 36. The conductive film 36 has the same composition as the upper wiring line 33. The overcoat layer 37 has the same composition as the overcoat film 34.
  • In FIG. 1, one semiconductor chip 11 is installed on the base plate 31, and this semiconductor chip 11 is embedded in the sealing layer 32. On the contrary, a plurality of semiconductor chips 11 may be installed on the base plate 31, and these semiconductor chips 11 may be embedded in the sealing layer 32.
  • A method of manufacturing the semiconductor device 1 is described with reference to FIG. 2 to FIG. 7. FIG. 2 to FIG. 7 are diagrams showing the method of manufacturing the semiconductor device 1. The method of manufacturing the semiconductor device 1 is broadly divided into a preprocess shown in FIG. 2 and FIG. 3 and a post-process shown in FIG. 4 to FIG. 7. The preprocess is a process for manufacturing the semiconductor construct 10. The post-process is a process for packaging the manufactured semiconductor construct 10.
  • First, the process for manufacturing the semiconductor construct 10 which is the preprocess is described.
  • FIG. 2A is a sectional view of a semiconductor wafer 110 before diced. As shown in FIG. 2A, the semiconductor wafer 110 is a semiconductor substrate which is not divided into pieces. That is, the semiconductor wafer 110 is separated into a plurality of chip regions 111 by lattice-like dicing streets 112 that serve as scheduled dividing lines. These chip regions 111 are arranged in matrix form.
  • An LSI is formed on the surface of the semiconductor wafer 110 for each of the chip regions 111. A plurality of connection pads 12 are also formed on the surface of the semiconductor wafer 110. A passivation film 13 is formed on the surface of the semiconductor wafer 110, and the LSI is covered with the passivation film 13.
  • First, as shown in FIG. 2B, an insulating resin film is formed on the surface of the semiconductor wafer 110. This insulating resin film is patterned to form an opening 25 a and a trench 25 b in this film. The insulating resin film is then divided into protective films 25 for the respective chip regions 111. Here, the trenches 25 b are formed into a lattice shape along the dicing streets 112.
  • A foundation metal layer and a rewiring line 21 are formed. The semi-additive process is used as a method of forming the foundation metal layer and the rewiring line 21.
  • More specifically, first, the foundation metal layer is formed on the entire upper surface of the protective film 25 including the upper surface of the connection pad 12 exposed through the openings 13 a, 25 a of the passivation film 13 and the protective film 25. In this case, the foundation metal layer may only be a copper layer formed by electroless plating, may only be a copper layer formed by sputtering, or may be a copper layer formed by sputtering on a thin layer of, for example, titanium formed by sputtering.
  • Then, a plating resist film is patterned/formed on the upper surface of the foundation metal layer. In this case, an opening is formed in a part of the plating resist film corresponding to a region where the rewiring line 21 is to be formed.
  • Then, as shown in FIG. 2C, the rewiring line 21 is formed on the foundation metal layer. More specifically, electrolytic plating with copper is carried out using the foundation metal layer as a plating current path, thereby forming the rewiring line 21 on the upper surface of the foundation metal layer within the opening of the plating resist film.
  • Then, the plating resist film is released. At this moment, the foundation metal layer has not been patterned yet.
  • As shown in FIG. 2D, after the formation of the rewiring line 21, a dry film resist 122 thicker than the rewiring line 21 is affixed to one surface on the rewiring line 21 and the protective film 25. This dry film resist 122 is exposed and developed to form an opening 122 a in the dry film resist 122. In the opening 122 a, part of the rewiring line 21 is exposed. The position to form the opening 122 a is the position of a columnar electrode 22 to be formed later. The dry film resist 122 is left in the position where the columnar electrode 22 to be formed later is not formed.
  • Then, the electrolytic plating method is carried out using the rewiring line 21 as an electrode so that the dry film resist 122 is used as a mask to cover part of the rewiring line 21 with the dry film resist 122. In this way, as shown in FIG. 3A, the columnar electrode 22 is grown on the rewiring line 21 within the opening 122 a. Here, the columnar electrode 22 is grown to be thicker than the rewiring line 21.
  • Then, as shown in FIG. 3B, the dry film resist 122 is removed after the formation of the columnar electrode 22.
  • Here, before the dry film resist 122 is affixed as described above or after the dry film resist 122 is removed as described above, part of the foundation metal layer of the rewiring line 21 that does not overlap the patterned rewiring line 21 is removed by etching. At the same time, the upper layer of the rewiring line 21 and the surface of the columnar electrode 22 are partly etched. However, the rewiring line 21 and the columnar electrode 22 are sufficiently thicker than the foundation metal layer, so that the rewiring line 21 and the columnar electrode 22 remain.
  • Then, as shown in FIG. 3C, the semiconductor wafer 110 is diced along the dicing streets 112, and the semiconductor wafer 110 is divided into a plurality of semiconductor chips 11. As a result, a semiconductor construct 10 provided with a plurality of columnar electrodes 22 erected on the surface of the semiconductor chip 11 is completed.
  • Now, the process for packaging the manufactured semiconductor construct 10 is described.
  • As shown in FIG. 4A, a mother base plate 131 is prepared. An adhesive layer 30 is applied or affixed and thereby formed in a region on one surface of the mother base plate 131 where the semiconductor chip 11 is installed. Further, a plurality of semiconductor chips 11 are arranged on the mother base plate 131 in matrix form, and the semiconductor chips 11 are bonded to the mother base plate 131 by the adhesive layer 30. In this way, the semiconductor chips 11 are installed on the mother base plate 131 in matrix form. When the semiconductor chips 11 are bonded to the mother base plate 131, the surface opposite to the surface in which the columnar electrode 22 is formed is bonded to the mother base plate 131. Here, the mother base plate 131 is the base plate 31 shown in FIG. 1 before cut.
  • Then, as shown in FIG. 4B, a single layer sheet-like prepreg 132 is stacked on the mother base plate 131 from above the semiconductor chips 11 and the columnar electrodes 22, and the prepreg 132 is pressurized and heated. Here, the prepreg 132 is pressurized toward the mother base plate 131. Thereby, part of the prepreg 132 is stacked on the semiconductor chip 11, and the semiconductor chips 11 are embedded in the prepreg 132. Further, the columnar electrode 22 is put through the prepreg 132. The prepreg 132 is heated and thereby cured into a sealing layer 32.
  • When a sealing layer 32 made of a fiber reinforced resin is to be formed, the prepreg 132 is a fiber reinforced prepreg. On the other hand, when a sealing layer 32 made of a resin which is not fiber reinforced is to be formed, the prepreg 132 is a prepreg which is not fiber reinforced. The fiber reinforced prepreg is formed by impregnating a fiber (e.g., glass fiber, glass fabric, carbon fiber, carbon fabric) with a thermosetting resin (e.g., epoxy resin, polyimide resin) and semi-curing the resin into a sheet form. As the prepreg which is not fiber reinforced, a thermosetting resin (e.g., epoxy resin, polyimide resin) which is semi-cured into a sheet form without impregnation of a fiber is used. As the fiber reinforced prepreg, it is particularly preferable to use a semi-cured glass fiber reinforced epoxy resin or glass fiber reinforced polyimide resin. As the prepreg which is not fiber reinforced, it is particularly preferable to use a semi-cured glass epoxy resin or polyimide resin which is not fiber reinforced.
  • Then, as shown in FIG. 5A, the surface of the sealing layer 32 and the top face of the columnar electrode 22 are ground. The surface of the sealing layer 32 and the top face of the columnar electrode 22 are planarized by grinding. The top face of the columnar electrode 22 which is not exposed from the surface of the sealing layer 32 before grinding is exposed by grinding.
  • Then, as shown in FIG. 5B, a conductive layer 133 is grown on the surface of the sealing layer 32 and the top face of the columnar electrode 22 by an electroless plating method, electrolytic plating method or vapor-phase growth method (e.g., a sputter method) or by a combination of these methods. At the same time, a conductive film 36 also grows on the opposite surface.
  • Then, a resist (a dry film resist or liquid resist will also do) is applied to the conductive layer 133. The resist is exposed and developed. The remaining resist is used as a mask to etch the conductive layer 133. Thereby, the conductive layer 133 is formed/processed into an upper wiring line 33, as shown in FIG. 6A. After the upper wiring line 33 is patterned, the resist is removed.
  • Then, as shown in FIG. 6B, the overcoat film 34 is patterned, so that the upper wiring line 33 and the sealing layer 32 are covered with the overcoat film 34, and part of the upper wiring line 33 is exposed through an opening 34 a of the overcoat film 34. When the overcoat film 34 is formed, an overcoat layer 37 is also formed on the opposite surface.
  • After the step shown in FIG. 6A and before the step shown in FIG. 6B, insulating layers and rewiring lines may be alternately formed to produce multilayer wiring lines. Moreover, after the step shown in FIG. 6A and before the step shown in FIG. 6B, a through-hole may be formed from the surface of the sealing layer 32 to the opposite surface of the mother base plate 131.
  • Then, as shown in FIG. 7A, a solder ball 35 is formed on the upper wiring line 33 within each opening 34 a. The formation of the solder ball 35 may be omitted, or the solder ball 35 may be formed after dicing processing described later.
  • Then, the mother base plate 131 and the sealing layer 32 are diced into a lattice shape for each semiconductor chip 11, and divided to form a plurality of semiconductor devices 1. Thus, as shown in FIG. 7B, the mother base plate 131 is divided by dicing into the base plates 31 for the respective semiconductor devices 1, and the sealing layer 32 is also divided. In consequence, the semiconductor device 1 is completed.
  • When a plurality of semiconductor chips 11 are included in one semiconductor device 1, the mother base plate 131 and the sealing layer 32 are not diced for each semiconductor chip 11 but are diced for each combination of semiconductor chips 11.
  • As described above, according to the embodiment, the prepreg 132 is used (see FIG. 4B) when the sealing layer 32 is formed. Thus, the columnar electrode 22 formed on the semiconductor chip 11 in advance can be put through the prepreg 132. That is, the prepreg 132 is stacked, heated and pressurized, and then ground to form the sealing layer 32. Therefore, the step of forming the sealing layer 32 serves both as a step of forming an insulating layer (sealing layer) that covers the upper surface of the semiconductor chip 11 and a step of forming an insulating layer (sealing layer) that covers the circumferential side surface of the semiconductor construct 10 including the semiconductor chip 11. Thus, in the method of manufacturing the semiconductor device 1, the steps of forming the insulating layers (sealing layers) can be reduced.
  • Furthermore, conventionally, in the EWLP method shown in Patent document 1, the upper surface of a sealing film (13) of a semiconductor construct (2) and the upper surface of an insulating layer (14) can be flat as far as the process is concerned. However, steps are produced due to, for example, curing, contraction or thermal expansion, and wiring lines may be broken. Therefore, after the upper insulating layer (15) is formed on the semiconductor construct (2) and the upper surface of the insulating layer (14), the via (16) is formed by laser, and then the upper wiring line (18) is formed on the upper insulating layer (15).
  • According to the embodiment, the upper wiring line 33 can be directly formed on the sealing layer 32. Therefore, there is no need for a step of forming a via in the sealing layer 32 by laser after the sealing layer 32 is formed and forming an electrode in the laser via. This makes it possible to reduce the steps, time and costs required for the manufacture of the semiconductor device 1. Moreover, it is not necessary to form an upper insulating film, so that the semiconductor device 1 can be smaller in thickness.
  • Furthermore, as the prepreg 132 is semi-cured, the thick sealing layer 32 can be formed around the columnar electrode 22 even if the columnar electrode 22 is high.
  • Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (15)

1. A semiconductor device comprising:
a semiconductor construct including a semiconductor substrate, and an external connection electrode provided to protrude on the surface of the semiconductor substrate;
a base plate on which the semiconductor construct is installed; and
a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including the side surface of the semiconductor substrate.
2. The semiconductor device according to claim 1, wherein
the sealing layer is formed by putting the external connection electrode through a prepreg and curing the prepreg.
3. The semiconductor device according to claim 2, wherein
the sealing layer is a single layer, and is made of a glass fiber reinforced epoxy resin, a glass fiber reinforced polyimide resin, or an epoxy resin or polyimide resin which is not fiber reinforced.
4. The semiconductor device according to claim 1, wherein
a connection pad and a wiring line which is provided to be connected to the connection pad are provided on the semiconductor substrate, and the external connection electrode is provided on a land of the wiring line.
5. The semiconductor device according to claim 1, wherein
the semiconductor substrate is bonded onto the base plate by an adhesive layer.
6. The semiconductor device according to claim 1, wherein
an upper wiring line is provided on the sealing layer to be directly connected to the external connection electrode without any insulating film in between.
7. The semiconductor device according to claim 1, wherein
the external connection electrode is a columnar electrode.
8. A semiconductor device manufacturing method comprising:
mounting a plurality of semiconductor constructs on a base plate, each of the semiconductor constructs including an external connection electrode provided to protrude on the surface of a semiconductor substrate; and
stacking a sealing layer on the semiconductor substrate except for the external connection electrode and on the base plate including the side surface of the semiconductor substrate.
9. The semiconductor device manufacturing method according to claim 8, wherein
to stack the sealing layer, a prepreg is laid on the semiconductor substrate and the base plate, the external connection electrode is put through the prepreg, and the prepreg is cured into the sealing layer.
10. The semiconductor device manufacturing method according to claim 8, wherein
the semiconductor substrate is a chipped semiconductor substrate,
the semiconductor substrates are installed on the base plate before the sealing layer is stacked,
to stack the sealing layer, a prepreg is laid on the base plate and a plurality of semiconductor substrates, the external connection electrode is put through the prepreg, and the prepreg is cured into the sealing layer, and
the base plate and the sealing layer are diced after the sealing layer is stacked.
11. The semiconductor device manufacturing method according to claim 9, wherein
the prepreg is a single layer, and is made of a glass fiber reinforced epoxy resin, a glass fiber reinforced polyimide resin, or an epoxy resin or polyimide resin which is not fiber reinforced.
12. The semiconductor device manufacturing method according to claim 8, wherein
a connection pad and a wiring line which is formed to be connected to the connection pad are formed on the semiconductor substrate, and the external connection electrode is provided on a land of the wiring line.
13. The semiconductor device manufacturing method according to claim 8, wherein
the semiconductor substrate is bonded onto the base plate by an adhesive layer.
14. The semiconductor device manufacturing method according to claim 8, wherein
an upper wiring line is formed on the sealing layer to be directly connected to the external connection electrode without any insulating film in between.
15. The semiconductor device manufacturing method according to claim 8, wherein
the external connection electrode is a columnar electrode.
US12/944,114 2009-11-13 2010-11-11 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same Abandoned US20110115080A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/299,775 US9105580B2 (en) 2009-11-13 2014-06-09 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same
US14/791,068 US9343428B2 (en) 2009-11-13 2015-07-02 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009259874A JP2011108733A (en) 2009-11-13 2009-11-13 Semiconductor device and method manufacturing the same
JP2009-259874 2009-11-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/299,775 Division US9105580B2 (en) 2009-11-13 2014-06-09 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same

Publications (1)

Publication Number Publication Date
US20110115080A1 true US20110115080A1 (en) 2011-05-19

Family

ID=44010690

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/944,114 Abandoned US20110115080A1 (en) 2009-11-13 2010-11-11 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same
US14/299,775 Active US9105580B2 (en) 2009-11-13 2014-06-09 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same
US14/791,068 Active - Reinstated US9343428B2 (en) 2009-11-13 2015-07-02 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same

Family Applications After (2)

Application Number Title Priority Date Filing Date
US14/299,775 Active US9105580B2 (en) 2009-11-13 2014-06-09 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same
US14/791,068 Active - Reinstated US9343428B2 (en) 2009-11-13 2015-07-02 Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same

Country Status (4)

Country Link
US (3) US20110115080A1 (en)
JP (1) JP2011108733A (en)
CN (1) CN102142417A (en)
TW (1) TW201126666A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8942006B2 (en) 2013-01-19 2015-01-27 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. PCB stackup having high- and low-frequency conductive layers and having insulating layers of different material types

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011108733A (en) * 2009-11-13 2011-06-02 Casio Computer Co Ltd Semiconductor device and method manufacturing the same
CN104269361B (en) * 2014-10-10 2017-04-19 禾邦电子(苏州)有限公司 Method for packaging semiconductor chip
CN109166807A (en) * 2018-07-24 2019-01-08 江阴芯智联电子科技有限公司 Manufacturing method of novel fan-out type packaging structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030219956A1 (en) * 2002-05-27 2003-11-27 Nec Corporation Thin film capacitor, method for manufacturing the same and printed circuit board incorporating the same
US20040232543A1 (en) * 2001-07-31 2004-11-25 Bernd Goller Electronic component with a plastic housing and method for production thereof
US20060022332A1 (en) * 2004-07-30 2006-02-02 Tetsuya Koyama Semiconductor chip-embedded substrate and method of manufacturing same
US20090095415A1 (en) * 2007-10-11 2009-04-16 Christophe Halope Reinforced radio frequency identification device support and its manufacturing method
US20100052142A1 (en) * 2008-09-03 2010-03-04 Kabushiki Kaisha Toshiba Semiconductor device and method for fabricating semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10200256A (en) * 1997-01-14 1998-07-31 Matsushita Electric Ind Co Ltd Manufacture of printed board
JP2002190672A (en) * 2000-12-19 2002-07-05 Hitachi Metals Ltd Build-up core board, build-up circuit board and its manufacturing method
JP2004349361A (en) 2003-05-21 2004-12-09 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP4119866B2 (en) * 2004-05-12 2008-07-16 富士通株式会社 Semiconductor device
JP2005353837A (en) 2004-06-10 2005-12-22 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
WO2007058005A1 (en) * 2005-11-16 2007-05-24 Ain Co., Ltd. Process for producing wiring board and wiring board
JP5137320B2 (en) * 2006-04-17 2013-02-06 株式会社テラミクロス Semiconductor device and manufacturing method thereof
JP4818005B2 (en) 2006-07-14 2011-11-16 Ｏｋｉセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
JP4726744B2 (en) 2006-08-29 2011-07-20 Ｏｋｉセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
JP2008060298A (en) 2006-08-31 2008-03-13 Casio Comput Co Ltd Semiconductor constitutional body and its manufacturing method, and semiconductor device and its manufacturing method
JP5028988B2 (en) 2006-12-13 2012-09-19 ヤマハ株式会社 Manufacturing method of semiconductor device
JP2011108733A (en) * 2009-11-13 2011-06-02 Casio Computer Co Ltd Semiconductor device and method manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232543A1 (en) * 2001-07-31 2004-11-25 Bernd Goller Electronic component with a plastic housing and method for production thereof
US20030219956A1 (en) * 2002-05-27 2003-11-27 Nec Corporation Thin film capacitor, method for manufacturing the same and printed circuit board incorporating the same
US20060022332A1 (en) * 2004-07-30 2006-02-02 Tetsuya Koyama Semiconductor chip-embedded substrate and method of manufacturing same
US20090095415A1 (en) * 2007-10-11 2009-04-16 Christophe Halope Reinforced radio frequency identification device support and its manufacturing method
US20100052142A1 (en) * 2008-09-03 2010-03-04 Kabushiki Kaisha Toshiba Semiconductor device and method for fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8942006B2 (en) 2013-01-19 2015-01-27 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. PCB stackup having high- and low-frequency conductive layers and having insulating layers of different material types

Also Published As

Publication number Publication date
US20150311181A1 (en) 2015-10-29
US9343428B2 (en) 2016-05-17
CN102142417A (en) 2011-08-03
TW201126666A (en) 2011-08-01
US9105580B2 (en) 2015-08-11
JP2011108733A (en) 2011-06-02
US20140287555A1 (en) 2014-09-25

Similar Documents

Publication Publication Date Title
US7112469B2 (en) Method of fabricating a semiconductor package utilizing a thermosetting resin base member
KR100880242B1 (en) Stacked Semiconductor Device Package and Method of Fabricating the Same
US9607861B2 (en) Semiconductor device and method of manufacturing the same
US7416918B2 (en) Direct build-up layer on an encapsulated die package having a moisture barrier structure
US8063490B2 (en) Semiconductor device including semiconductor constituent
EP2399288B1 (en) Integrated circuit micro-module
TW200527647A (en) A semiconductor device and its fabrication method
US9343428B2 (en) Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same
US20110001247A1 (en) Semiconductor device manufacturing method
KR102400764B1 (en) Semiconductor device and method of manufacture
TW200402126A (en) Semiconductor device and manufacturing method thereof
US8053807B2 (en) Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages
US20200303335A1 (en) Semiconductor device package and method for manufacturing the same
US20230178530A1 (en) Package structure and manufacturing method thereof
TWI485831B (en) Semiconductor device having multilayer wiring structure and method for manufacturing the same
US20110163459A1 (en) Method for manufacturing a stacked semiconductor package, and stacked semiconductor package
US7906833B2 (en) Semiconductor device and manufacturing method thereof
KR20090071444A (en) Method of manufacturing semiconductor device
US11393761B2 (en) Circuit board and its manufacturing method
JP7486934B2 (en) Circuit Board
CN109314064A (en) The batch micro operations of component load-bearing part
CN110265311B (en) Component carrier, method for producing the same, semi-finished product and electronic device
US11682628B2 (en) Semiconductor IC-embedded substrate having heat dissipation structure and its manufacturing method
US20240213135A1 (en) Semiconductor assembly comprising a 3d block and method of making the same
CN115083930A (en) Warpage preventing packaging method, chip packaging structure and electronic device

Legal Events

Date Code Title Description
AS Assignment

Owner name: CASIO COMPUTER CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WAKISAKA, SHINJI;REEL/FRAME:025348/0791

Effective date: 20101102

AS Assignment

Owner name: TERAMIKROS, INC., JAPAN

Free format text: CHANGE OF OWNERSHIP BY CORPORATE SEPARATION;ASSIGNOR:CASIO COMPUTER CO., LTD.;REEL/FRAME:027520/0401

Effective date: 20111212

AS Assignment

Owner name: TERAMIKROS, INC., JAPAN

Free format text: CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE'S ADDRESS ON REEL 027520/FRAME 0401;ASSIGNOR:CASIO COMPUTER CO., LTD.;REEL/FRAME:027546/0390

Effective date: 20111212

AS Assignment

Owner name: TERA PROBE, INC., JAPAN

Free format text: MERGER;ASSIGNOR:TERAMIKROS, INC.;REEL/FRAME:031664/0873

Effective date: 20131001

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION