US20110023741A1

US20110023741A1 - Fuse information detection circuit

Info

Publication number: US20110023741A1
Application number: US12/843,887
Authority: US
Inventors: Young Geun Choi
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2009-07-30
Filing date: 2010-07-27
Publication date: 2011-02-03
Also published as: KR20110012401A

Abstract

A fuse information detection circuit includes a fuse unit comprising a plurality of fuse sets and configured to output a plurality of fuse state signals, in parallel, at different levels according to whether fuses of the plurality of fuse sets are cut, a signal alignment unit configured to receive and store the plurality of fuse state signals and sequentially output the plurality of fuse state signals whenever a read pulse is inputted, and a fuse information signal generation unit configured to generate a fuse information signal by counting output of the signal alignment unit whenever the read pulse is inputted.

Description

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2009-0070113, filed on Jul. 30, 2009, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly to a fuse information detection circuit that detects whether a fuse provided in a semiconductor apparatus is cut.
2. Related Art
A semiconductor apparatus uses a great number of fuse options. The fuse options are used for analysis at the time of a design of the semiconductor apparatus. Particularly, in the case of a memory, the fuse options are also used for repairing a failed memory cell. A fuse option for selecting a redundancy memory cell in order to repair the failed memory cell will be described as an example. When a fuse provided in the fuse option has not been cut, a normal memory cell is selected. However, when the fuse provided in the fuse option has been cut, a redundancy memory cell is selected instead of the normal memory cell.
In general, the fuse of the fuse option is cut using laser equipment. That is, after a test is performed for a semiconductor apparatus, the fuse of the fuse option is cut in order to correct problematic parts. At this time, it is very important to check whether the fuse of the fuse option has been normally cut. This is because whether the fuse of the fuse option has been normally cut exerts significant influence on the yield of the semiconductor apparatus.
Many methods have been proposed to check whether the fuse of the fuse option has been normally cut. However, these to methods require much time for checking whether the fuse has been cut. Particularly, since a great number of fuse options are provided in a semiconductor apparatus, a large amount of time is required for checking whether fuses provided in the fuse options have been cut one by one.

SUMMARY

A fuse information detection circuit capable of quickly and simply checking cutting information of fuses of fuse options is described herein.
In one embodiment of the present invention, a fuse information detection circuit includes: a fuse unit including a plurality of fuse sets and configured to output a plurality of fuse state signals at different levels according to whether fuses of the plurality of fuse sets are cut; a signal alignment unit configured to receive and store the plurality of fuse state signals and sequentially output the plurality of fuse state signals whenever a read pulse is inputted; and a fuse information signal generation unit configured to generate a fuse information signal by counting output of the signal alignment unit whenever the read pulse is inputted.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a block diagram schematically illustrating the configuration of a fuse information detection circuit according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating the configuration of a fuse set shown in FIG. 1;

FIG. 3 is a diagram illustrating the configuration of a fuse information signal generation unit and a transmission unit of FIG. 1;

FIG. 4 is a diagram illustrating the configuration of a control signal generation unit of FIG. 1; and

FIG. 5 is a timing diagram illustrating the operation of a fuse information detection circuit according to one embodiment.

DETAILED DESCRIPTION

Hereinafter, a fuse information detection circuit according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments.
FIG. 1 is a block diagram schematically illustrating the configuration of a fuse information detection circuit according to one embodiment of the present invention. Referring to FIG. 1, the fuse information detection circuit includes a fuse unit 100, a signal alignment unit 200 and a fuse information signal generation unit 300. The fuse unit 100 is operatively coupled to the signal alignment unit 200. The signal alignment unit 200 is operatively coupled to the fuse information signal generation unit 300. The terminology “operatively coupled” as used herein refers to coupling that enables operational and/or functional communication and relationships there-between and may include any intervening items necessary to enable such communication such as, for example, data communication buses or any other necessary intervening items that one of ordinary skill would understand to be present. Also, it is to be understood that other intervening items may be present between “operatively coupled” items even though such other intervening items are not necessary to the functional communication facilitated by the operative coupling. For example, a data communication bus may provide data to several items along a pathway along which two or more items are operatively coupled, etc. Such operative coupling is shown generally in the figures described herein.
The fuse unit 100 includes a plurality of fuse sets 100-1 to 100-n. Each fuse set of the plurality of fuse sets 100-1 to 100-n has the same configuration. The plurality of fuse sets 100-1 to 100-n include fuses and are configured to output fuse state signals fuse<0:n-1> at different levels according to whether the fuses are cut. That is, the fuse unit 100 provides indication of cut fuses as its output. The output of the fuse unit 100 may be a parallel output which may indicate that various fuses of the plurality of fuse sets are cut. For example, when the fuses provided in the fuse sets 100-1 to 100-n have been cut, the fuse sets 100-1 to 100-n may output fuse state signals fuse<0:n-1> at a logic high level. However, when the fuses have not been cut, the fuse sets 100-1 to 100-n may output fuse state signals fuse<0:n-1> at a logic low level. “High level” and “low level” refers to, for example, voltage levels and/or voltage ranges that are predetermined to represent the high level or low level and not necessarily any specific values. It is to be understood that “high level” and “low level” may also be referred to as “logic levels” for example, a “high logic level” (or “logic high level”) and a “low logic level” (or “logic low level”), respectively. Such “logic levels” may also be understood to correspond to logical or binary bit values, for example, where a “logic low level” corresponds to a logical “0” (which may correspond to an “OFF” condition) and a “logic high level” corresponds to a logical “1” (which may correspond to and “ON” condition) or vice versa depending on specific implementations in the various embodiments. The configuration of the fuse sets 100-1 to 100-n will be described in detail below.
The signal alignment unit 200 is configured to receive the fuse state signals fuse<0:n-1> outputted from the fuse unit 100 and store them. The signal alignment unit 200 is configured to store the fuse state signals fuse<0:n-1> at the same time, and sequentially output the fuse state signals fuse<0:n-1> whenever a read pulse RD is inputted. That is, the signal alignment unit 200 may store the fuse state signals fuse<0:n-1> inputted in a parallel manner, and output serial signals FUSECUTB. For example, when a first fuse state signal fuse<0> is at a high level and a second fuse state signal fuse<1> is at a low level, after the signal alignment unit 200 stores the first fuse state signal fuse<0> and the second fuse state signal fuse<1> at the same time, the signal alignment unit 200 may output a high level signal, which is the first fuse state signal fuse<0>, when an initial to read pulse RD is inputted, and output a low level signal, which is the second fuse state signal fuse<1> when a subsequent read pulse RD is inputted. That is, the output of the signal alignment unit 200 is the high level signal when the initial read pulse RD is inputted, and is the low level signal when the subsequent read pulse RD is inputted.
The read pulse RD may use a clock signal used for a semiconductor memory apparatus. However, the read pulse RD is not limited thereto. For example, pulse signals inputted at a predetermined time interval may be used as the read pulse RD. Furthermore, a pulse generation unit 400, may be operatively coupled to the signal alignment unit 200, and may be further provided in order to adjust a time interval at which the read pulse RD is inputted. That is, in order such that the fuse state signals fuse<0:n-1> stored in the signal alignment unit 200 may be sequentially outputted as the serial signals (FUSECUTB) without redundancy, the pulse generation unit 400 may be further provided to adjust the time interval at which the read pulse RD is inputted. The pulse generation unit 400 may include a general pulse generator.
The signal alignment unit 200 uses a parallel-to-serial converter capable of storing signals inputted in a parallel manner and sequentially outputting the signals in a serial manner in synchronization with an inputted clock.
The fuse information signal generation unit 300 is configured to receive the output of the signal alignment unit 200, that is, receive the output FUSECUTB of the signal alignment unit 200, whenever the read pulse RD is generated, and perform a counting operation in response to the output FUSECUTB to generate fuse information signals FUSEINFORM. The fuse information signal generation unit 300 may be initialized by a reset signal RST.
When the read pulse RD is inputted, the fuse information signal generation unit 300 performs the counting operation according to the levels of the output FUSECUTB of the signal alignment unit 200. The fuse information signal generation unit 300 may also be operatively coupled to the pulse generation unit 400 and may receive the read pulse RD therefrom. In the case in which the read pulse RD is inputted, the fuse information signal generation unit 300 does not perform the counting operation when the output FUSECUTB of the signal alignment unit 200 is a high level signal, and performs the counting operation if the output FUSECUTB of the signal alignment unit 200 is a low level signal. For example, when the first fuse state signal fuse<0> is at a high level and the second fuse state signal fuse<1> is at a low level, the output FUSECUTB of the signal alignment unit 200 becomes the high level signal when the initial read pulse RD is inputted, and becomes the low level signal when the subsequent read pulse RD is inputted. Accordingly, when the initial read pulse RD is inputted, the fuse information signal generation unit 300 does not perform the counting operation because the output FUSECUTB at the high level is received from the signal alignment unit 200. When the subsequent read pulse RD is inputted, the fuse information signal generation unit 300 performs the counting operation because the output FUSECUTB becomes the low level signal. The fuse information signal generation unit 300 is configured to output a counting result as the fuse information signals FUSEINFORM. The fuse information signals FUSEINFORM may include code signals having plural bit numbers or code signals with different bits according is to the number of countings. Accordingly, the fuse information signal generation unit 300 is configured to sequentially receive the fuse state signals at different levels according to whether the fuses of the fuse unit 100 are cut and perform the counting operation, thereby generating the fuse information signals FUSEINFORM for checking the number of cut fuses in the fuse sets. In other words, the fuse information signal generation unit 300 determines the number of cut fuses by performing a counting operation on the FUSECUTB output.
The fuse information detection circuit according to one embodiment may further include a transmission unit 500, which is operatively coupled to the signal alignment unit 200 and to the fuse information signal generation unit 300. The transmission unit 500 is configured to transmit the output FUSECUTB of the signal alignment unit 200 in response to a test start signal TEST_START. When the test start signal TEST_START is activated, the transmission unit 500 transmits the output FUSECUTB of the signal alignment unit 200 to the fuse information signal generation unit 300. When the test start signal TEST_START is deactivated, the transmission unit 500 does not transmit the output FUSECUTB of the signal alignment unit 200 to the fuse information signal generation unit 300.
Furthermore, the fuse information detection circuit according to one embodiment may further include a control signal generation unit 600 which is configured to generate the reset signal RST and the test start signal TEST_START. The control signal generation unit may be operatively coupled to the fuse unit 100 and to the fuse information signal generation unit 300 to provide the reset signal RST, and may be operatively coupled to the transmission unit 500 to provide the test start signal TEST_START. The control signal generation unit 600 is configured to generate the reset signal RST and the test start signal TEST_START in response to a signal giving instructions for the operation of the fuse information detection circuit, for example, a test mode signal TM. The reset signal RST may be directly activated for initialization of the fuse unit 100 and the fuse information signal generation unit 300 when the test mode signal TM is inputted. The test start signal TEST_START may be activated immediately after the reset signal RST is deactivated.
FIG. 2 is a diagram illustrating the configuration of one of the plurality of fuse sets shown in FIG. 1 according to one embodiment. As described above, each fuse set of the plurality of fuse sets 100-1 to 100-n have the same configuration. Hereinafter, the configuration of the first fuse set 100-1 will be representatively described with reference to FIG. 2. Referring to FIG. 2, the first fuse set 100-1 is initialized in response to the reset signal RST and is configured to output the first fuse state signal fuse<0> at the high or low level according to whether the fuse is cut.
Referring to FIG. 2, the first fuse set 100-1 may include a first NMOS transistor N1, a second NMOS transistor N2, a fuse FUSE1, a first inverter IV1, and a second inverter IV2. FIG. 2 provides details and a circuit diagram of one exemplary embodiment implementing the fuse sets illustrated in FIG. 1, however, other is embodiments may utilize different arrangements and therefore it is to be understood that FIG. 2 is exemplary and to facilitate understanding by those of ordinary skill how to make and use the various embodiments but is therefore not to be construed as imposing limitations on implementation of the embodiments illustrated by FIG. 1. In FIG. 2, a fuse, FUSE1 is operatively coupled to a voltage VDD and a node A. A first and second NMOS transistor, N1 and N2 are operatively coupled, in parallel to node A and a ground voltage VSS. The N1 gate terminal is operatively coupled to the reset signal RST. A first and second inverter, IV1 and IV2, are operatively coupled in series to node A, and provide a fuse state signal as output. The gate terminal of N2 is operatively coupled to the output of the first inverter IV1. The first NMOS transistor N1 is turned on in response to the reset signal RST to apply the ground voltage VSS to node A. When the fuse FUSE1 has not been cut, the external voltage VDD is applied to the node A. When the fuse FUSE1 has been cut, the external voltage VDD is not applied to the node A. The first inverter IV1 and the second inverter IV2 are configured to output a signal, which is obtained by sequentially inverting the level of the voltage applied to the node A, as the first fuse state signal fuse<0>. The second NMOS transistor N2 has a gate terminal operatively coupled to an output terminal of the first inverter IV1 and is configured to latch the voltage level of the node A together with the first inverter IV1 when the output of the first inverter IV1 is at a low level. Consequently, when the fuse FUSE1 has not been cut, the first is fuse set 100-1 may output the first fuse state signal fuse<0> at the high level. However, when the fuse FUSE1 has been cut, the first fuse set 100-1 may output the first fuse state signal fuse<0> at the low level.
FIG. 3 is a diagram illustrating the configuration of the transmission unit 500 and the fuse information signal generation unit 300 of FIG. 1 according to one embodiment. FIG. 3 provides details and a circuit diagram of one exemplary embodiment implementing the transmission unit 500 and fuse information signal generation unit 300 illustrated in FIG. 1, however, other embodiments may utilize different arrangements and therefore it is to be understood that FIG. 3 is exemplary and to facilitate understanding by those of ordinary skill how to make and use the various embodiments but is therefore not to be construed as imposing limitations on implementation of the embodiments illustrated by FIG. 1. Referring to FIG. 3, the transmission unit 500 includes a third inverter IV3, which is operatively coupled to receive TEST_START at its input, and a pass gate PG which is operatively coupled to the third inverter IV3 output and input. The third inverter IV3 is configured to invert the test start signal TEST_START. When the test start signal TEST_START is activated, the pass gate PG is turned on in response to the test start signal TEST_START and the output of the third inverter IV3 and transmits the output FUSECUTB of the signal alignment unit 200.
Referring to FIG. 3, the fuse information signal generation unit 300 includes a latch section 310, which is operatively coupled to the pass gate PG of the transmission unit 500, an input section 320 which is operatively coupled to the latch section 310, and a counting section 330 which is operatively coupled to the input section 320. The latch section 310 is configured to invert and output the output FUSECUTB of the signal alignment unit 200, which is transmitted from the transmission unit 500, and simultaneously latch the output FUSECUTB of the signal alignment unit 200. The latch section 310 may include a fourth inverter IV4 and a fifth inverter IV5, wherein an input terminal of the fourth inverter IV4 is operatively coupled to an output terminal of the fifth inverter IV5 and an output terminal of the fourth inverter IV4 is operatively coupled to an input terminal of the fifth inverter IV5.
Whenever the read pulse RD is inputted, the input section 320 inverts the output of the latch section 310 to generate a counting signal CNTB. The input section 320 may include a NAND gate ND in some embodiments. The NAND gate ND is configured to receive the output of the latch section 310 and the read pulse RD. Consequently, when the read pulse RD is inputted, the NAND gate ND may output the output of the latch section 310, which has a level the same as that of the output FUSECUTB of the signal alignment unit 200, as the counting signal CNTB. That is, when the output FUSECUTB of the signal alignment unit 200 is at the high level, the counting signal CNTB generated by the NAND gate ND may maintain a high level. When the output FUSECUTB of the signal alignment unit 200 is at the low level, the counting signal CNTB may change to a low level with a pulse width corresponding to the width of the read pulse RD.
The counting section 330 is configured to receive the counting signal CNTB and count the number of times by which the counting signal CNTB changes to the low level. The counting section 330 may count the number of times by which the counting signal CNTB changes to the low level, and output a code signal with increased bits as the fuse information signal FUSEINFORM whenever the number of times by which the counting signal CNTB changes to the low level is increased. It is to be understood however that in other embodiments having different implementation configurations the counting section 330 may count the number of times by which the counting signal CNTB changes to the high level. Returning to the embodiment exemplified by FIG. 3, the counting section 330 may be initialized in response to the reset signal RST. The counting section 330 may include a general counter. For example, when the counting section 330 is a 3-bit counter, if the reset signal RST is activated, the counting section 330 initializes the bit value of the code signal into ‘0, 0, 0’, and increases the bit value of the code signal into ‘0, 0, 1’, ‘0, 1, 1’ and the like whenever the counting signal CNTB changes to the low level. Since the code signal is outputted as the fuse information signal FUSEINFORM, it is possible to determine the number of cut fuses by checking the bit value of the fuse information signal FUSEINFORM.
FIG. 4 is a diagram illustrating the configuration of the control signal generation unit 600 according to one embodiment. FIG. 4 provides details and a circuit diagram of one exemplary embodiment implementing the control signal generation unit 600 illustrated in FIG. 1, however, other embodiments may utilize different arrangements and therefore it is to be understood that FIG. 4 is exemplary and to facilitate understanding by those of ordinary skill how to make and use the various embodiments but is therefore not to be construed as imposing limitations on implementation of the embodiments illustrated by FIG. 1. Referring to FIG. 4, the control signal generation unit 600 may include a first inverter chain 610, an AND gate AND having an input operatively coupled to the output of the first inverter chain 610, and a second inverter chain 620, having its input operatively coupled to the output of the first inverter chain 610. The first inverter chain 610 includes an odd number of inverters and is configured to delay the test mode signal TM for a predetermined time. The AND gate AND is configured to receive the test mode signal TM and the output of the first inverter chain 610 and generate the reset signal RST. Consequently, the control signal generation unit 600 may generate the reset signal RST with a pulse width corresponding to the predetermined time for which the test mode signal TM is delayed by the first inverter chain 610. The second inverter chain 620 may include an odd number of inverters which are configured to receive and invert the output of the first inverter chain 610 and output the inversion result as the test start signal TEST_START.
FIG. 5 is a timing diagram illustrating the operation of the is fuse information detection circuit according to one embodiment. Hereinafter, the operation of the fuse information detection circuit according to one embodiment will be described with reference to FIGS. 1 to 5. When the test mode signal TM is activated in order to detect fuse information, the control signal generation unit 600 generates the reset signal RST and the test start signal TEST_START. When the reset signal RST is activated, the plurality of fuse sets 100-1 to 100-n of the fuse unit 100 and the counting section 330 are initialized.
When the reset signal RST is deactivated, the plurality of fuse sets 100-1 to 100-n of the fuse unit 100 output the fuse state signals fuse<0:n-1> at the high or low level according to whether the fuses are cut. Next, the case in which fuses of six of the fuse sets 100-1 to 100-n have been cut will be described as an example. The signal alignment unit 200 is configured to receive the fuse state signals fuse<0:n-1> from the fuse unit 100 and store them.
Whenever the read pulse RD is inputted, the signal alignment unit 200 sequentially outputs the stored fuse state signals fuse<0:n-1>. Furthermore, since the pass gate PG of the transmission unit 500 is turned on in response to the test start signal TEST_START, the transmission unit 500 transmits the output FUSECUTB of the signal alignment unit 200 to the fuse information signal generation unit 300. As shown in FIG. 5, in the case in which a fuse of the third fuse set 100-3 (not shown) has been cut, the output FUSECUTB of the signal alignment unit 200 maintains the high level when a first read pulse RD and a second read pulse RD are inputted, and change to the low level when a third read pulse RD is inputted. Similarly to this, when an (n-5)^thread pulse RD, an (n-3)^thread pulse RD, . . . , an n^thread pulse RD, are inputted, the signal alignment unit 200 outputs the signal FUSECUTB at the low level.
When the read pulse RD is inputted, if the output FUSECUTB of the signal alignment unit 200 is at the low level, the input section 320 generates a pulse of a low level as the counting signal CNTB. Referring to FIG. 5, it may be understood that the counting signal CNTB becomes the pulse of the low level when fuse state signals fuse<2>, fuse<n-6> and fuse<n-4:n-1> of the fuse sets having cut fuses are transmitted.
The counting section 330 is configured to count the number of times by which the counting signal CNTB changes to the low level. As the third read pulse RD is inputted, if the counting signal CNTB changes to the low level once, the counting section 330 increases a bit value once and outputs the fuse information signal FUSEINFORM of ‘0, 0, 1’. Since the counting signal CNTB changes to the low level six times, the bit value is increased by 6, so that the fuse information signal FUSEINFORM of ‘1, 1, 0’ is finally outputted. Accordingly, it is possible to understand that the fuses of six of the fuse sets 100-1 to 100-n have been cut based on the fuse information signal FUSEINFORM.
Consequently, according to one embodiment, it is possible to easily understand the number of fuse sets having cut fuses among is the plurality of fuse sets. Thus, as compared with the conventional art, time for checking whether fuses have been cut is reduced, resulting in the reduction of the manufacturing cost of a semiconductor memory apparatus. In addition, since it is possible to easily check whether fuse sets have been cut, it is possible to test the accuracy of laser equipment that cuts fuses of the fuse sets.
While certain embodiments have been described above, it will be understood by those skilled in the art that the embodiments described are by way of example only. Accordingly, the fuse information detection circuit described herein should not be limited based on the described embodiments. Rather, the fuse information detection circuit described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.

Claims

1. A fuse information detection circuit comprising:

a fuse unit comprising a plurality of fuse sets and configured to output a plurality of fuse state signals to indicate that fuses of the plurality of fuse sets are cut;

a signal alignment unit, operatively coupled to the fuse unit, configured to receive and store the plurality of fuse state signals and sequentially output the plurality of fuse state signals in response to a to read pulse; and

a fuse information signal generation unit, operatively coupled to the signal alignment unit, configured to generate a fuse information signal by counting output of the signal alignment unit in response to the read pulse.

2. The fuse information detection circuit according to claim 1, wherein the fuse information signal generation unit comprises:

a latch section configured to latch the output of the signal alignment unit;

an input section, operatively coupled to the latch section, configured to obtain the latch section output and generate a counting signal in response to the read pulse; and

a counting section, operatively coupled to the input section, configured to generate the fuse information signal by performing a counting operation in response to the counting signal.

3. The fuse information detection circuit according to claim 2, further comprising:

a transmission unit, operatively coupled to the signal alignment unit and the fuse information signal generation unit, configured to transmit the output of the signal alignment unit to the fuse information signal generation unit in response to a test start signal.

4. The fuse information detection circuit according to claim 3, wherein the fuse unit and the fuse information signal generation unit are initialized in response to a reset signal.

5. The fuse information detection circuit according to claim 4, further comprising:

a control signal generation unit, operatively coupled to the fuse unit, the fuse information signal generation unit and the transmission unit, and configured to receive a test mode signal and generate the reset signal and the test start signal.

6. The fuse information detection circuit according to claim 5, wherein the reset signal is activated when the test mode signal is activated, and the test start signal is activated when the reset signal is deactivated.

7. The fuse information detection circuit according to claim 1, further comprising:

a pulse generation unit, operatively coupled to at least one of the signal alignment unit and the fuse information signal generation unit, and configured to adjust an input time interval of the read pulse.

8. The fuse information detection circuit according to claim 1, wherein the signal alignment unit is configured to receive the plurality of fuse state signals inputted in a parallel manner, and to sequentially output the plurality of fuse state signals in a serial manner in response to the read pulse.

9. A fuse information detection circuit comprising:

a signal alignment unit, configured to receive, in parallel, a plurality of fuse state signals indicating cut fuses, from a plurality of fuse sets, and provide the plurality of fuse state signals as a serial output; and

a fuse information signal generation unit, operatively coupled to the signal alignment unit, configured to obtain the serial output and determine therefrom how many fuses of said plurality of fuses sets are cut.