US20100283095A1 - Flash Memory Device - Google Patents
Flash Memory Device Download PDFInfo
- Publication number
- US20100283095A1 US20100283095A1 US12/840,090 US84009010A US2010283095A1 US 20100283095 A1 US20100283095 A1 US 20100283095A1 US 84009010 A US84009010 A US 84009010A US 2010283095 A1 US2010283095 A1 US 2010283095A1
- Authority
- US
- United States
- Prior art keywords
- layer
- insulating layer
- region
- select transistor
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
Definitions
- the invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a flash memory device that reduces an undesirable interference phenomenon.
- Semiconductor memory devices for storing data can be largely classified into volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their data when the supply of power thereto is stopped, whereas nonvolatile memory devices retain their data in the absence of power.
- Each nonvolatile memory device includes a flash memory device.
- a unit cell of the flash memory device generally includes an active region defined on a specific region of a semiconductor substrate, a tunnel insulating layer formed on the active region, a floating gate formed on the tunnel insulating layer, a gate interlayer insulating layer formed on the floating gate, and a control gate electrode formed on the gate interlayer insulating layer.
- the flash memory device has been widely used for MP3 players, digital cameras, memory for computer BIOS storage, mobile phones, portable data storage devices and so on.
- the flash memory cell can store data as voltage externally applied to the control gate electrode is coupled to the floating gate. Accordingly, when storing data for a short period of time and at a low program voltage, the ratio of voltage applied to the control gate electrode to voltage applied to the floating gate must be high. The ratio of voltage applied to the control gate electrode to voltage applied to the floating gate is called the coupling ratio (“CR”). Furthermore, the coupling ratio can be expressed by the ratio of the capacitance of the gate interlayer insulating layer to the sum of the capacitance of the tunnel insulating layer and the gate interlayer insulating layer.
- the space where a unit active region and a unit field region will be formed narrows as devices become more highly integrated.
- a dielectric layer, a control gate and a floating gate are formed within a narrow active space, the distance between the gates is narrowed, so that the interference phenomenon becomes increasingly problematic.
- MLC Multi-Level Cell
- ASA-STI Advanced Self-Aligned Shallow Trench Isolation
- a conventional method of manufacturing a flash memory device is briefly described below.
- a buffer insulating layer is formed on the semiconductor substrate.
- the buffer insulating layer is formed from an oxide layer.
- the buffer insulating layer is removed.
- an annealing process is performed.
- the tunnel insulating layer is formed by performing a wet or dry oxidization process at a temperature ranging from 750° C. to 850° C. using H 2 or O 2 .
- the annealing process is performed in order to eliminate the trap phenomenon occurring at the interface between the semiconductor substrate and the tunnel insulating layer and to increase the data storage ability of the transistor.
- the annealing process includes a post-anneal process at a temperature ranging from 750° C. to 1100° C. using N 2 , N 2 O, or NO.
- a first conductive layer for a floating gate is formed on the tunnel insulating layer.
- the first conductive layer is formed by in-situ implanting a P or B dopant into a source gas of SiH 4 , Si 2 H 6 , or SiH 2 Cl 2 .
- a first hard mask layer having a stack structure of an oxide layer and a nitride layer is formed on the first conductive layer.
- the first hard mask layer, the first conductive layer, the tunnel insulating layer, and the semiconductor substrate are partially etched by a photo and development processes, thereby forming trenches and also a floating gate consisting of the first conductive layer.
- a first insulating layer is formed over the semiconductor substrate including the trenches so that the trenches are filled.
- the first insulating layer is polished to form isolation layers.
- the first insulating layer is polished using a High Density Plasma (HDP) oxide layer or Spin on Glass (SOG).
- HDP High Density Plasma
- SOG Spin on Glass
- a wet etch process i.e., a cleaning process is performed to partially remove the top surface of the isolation layers.
- a dielectric layer is formed over the semiconductor substrate including the isolation layers and the first conductive layer.
- An annealing process and an oxidization process are carried out at a temperature ranging from 600° C. to 900° C. using O 2 or H 2 .
- a second conductive layer for a control gate and a second hard mask layer are formed over the dielectric layer.
- the second conductive layer has a stacked structure including a polysilicon layer and a tungsten silicide (WSi x ) layer or tungsten (W).
- the second hard mask layer is formed from an oxide layer or a silicon oxynitride (SiON) layer.
- the second hard mask layer, the second conductive layer, the dielectric layer and the first conductive layer are etched through photo and development processes, thereby forming gates.
- Spacers for separating the gates are formed on the sides of the gates.
- a second insulating layer is formed over the semiconductor substrate including the spacers and the gates.
- the second insulating layer is formed from an oxide layer or a nitride layer.
- a first insulating layer having a source contact plug formed therein is formed on the second insulating layer.
- a second insulating layer having a drain contact plug formed therein is formed over the semiconductor substrate including the source contact plug and the first insulating layer.
- the source contact plug and the drain contact plug are formed from polysilicon or tungsten.
- metal lines are formed on the second insulating layer.
- the invention addresses the above problems and discloses a method of manufacturing a flash memory device that reduces the interference phenomenon between a select transistor and a cell gate in such a manner that a cell region and a select transistor region have a step created by partially etching the select transistor region of a semiconductor substrate (i.e., a region where a Source Select Line (SSL) and a Drain Select Line (DSL) are formed).
- a semiconductor substrate i.e., a region where a Source Select Line (SSL) and a Drain Select Line (DSL) are formed.
- a method of manufacturing a flash memory device including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.
- a flash memory device including a semiconductor substrate having a step between a cell region and a select transistor region, a transistor formed in the select transistor region, and a memory cell formed in the cell region.
- FIGS. 1A to 1E are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the invention.
- a first insulating layer (not shown) is formed on a semiconductor substrate 100 in order to minimize damage to the semiconductor substrate resulting from an ion implant process.
- the first insulating layer can be formed at a thickness of 50 ⁇ to 200 ⁇ using an oxide layer or a nitride layer.
- an N-type or P-type impurity is implanted into the semiconductor substrate 100 , and the first insulating layer is then removed.
- a select transistor region (i.e., a region of the semiconductor substrate 100 in which a SSL and a DSL will be formed) is partially etched to form first trenches 102 .
- the width of the first trenches 102 can be set to 4 to 6 times larger than that of the SSL or the DSL, and the depth of the first trenches 102 can range from 300 ⁇ to 1000 ⁇ .
- the side of the first trenches 102 is sloped, not vertical. The angle of the slope can be controlled depending on the polymer formation method and the corresponding amount of polymer used when etching the semiconductor substrate 100 .
- the side of the first trenches 102 is sloped so that it can provide good etching selectivity when etching steps are performed subsequent to the deposition of several additional layers.
- the first trenches 102 formed in the select transistor region define a step formed between the cell region and the select transistor region.
- a tunnel insulating layer 104 is formed over the semiconductor substrate 100 including the first trenches 102 .
- an annealing process is performed.
- the tunnel insulating layer 104 can be formed by performing a wet or dry oxidization process at a temperature ranging from 750° C. to 850° C. using H 2 or O 2 .
- the annealing process can be performed as a post annealing process at a temperature ranging from 750° C. to 1100° C. using N 2 , N 2 O, or NO.
- a first conductive layer 106 for a floating gate and a first hard mask layer are formed on the tunnel insulating layer 104 .
- the first conductive layer 106 can be formed from a polysilicon layer by in-situ implantation of a Phosphorous(P) or Boron(B) dopant into a source gas, such as SiH 4 , Si 2 H 6 , or SiH 2 Cl 2 .
- the first hard mask layer can be formed using a single pad oxide layer, a single nitride layer, or a stacked layer including a pad oxide layer and a nitride layer.
- the first hard mask layer, the first conductive layer 106 , the tunnel insulating layer 104 and the semiconductor substrate 100 are partially etched through photo and development processes, thereby forming second trenches (not shown) for isolation layers (not shown) and also a floating gate pattern (not shown) comprising the first conductive layer 106 .
- a second insulating layer is formed over the semiconductor substrate 100 including the second trenches so that the second trenches are filled.
- the second insulating layer is then polished to form the isolation layers.
- the second insulating layer can be formed from an HDP oxide layer or SOG.
- a wet etch process i.e., a cleaning process is performed to partially remove the top surface of the isolation layer.
- a dielectric layer 108 is formed over the semiconductor substrate 100 including the isolation layer and the first conductive layer 106 .
- An annealing process and an oxidization process are then performed.
- the annealing process can be performed at a temperature ranging from 600° C. to 900° C. using O 2 or H 2 .
- a second conductive layer 110 for a control gate and a second hard mask layer 112 are formed over the dielectric layer 108 .
- the second conductive layer 110 can have a structure in which a polysilicon layer is stacked with a tungsten silicide (WSi x ) layer or a tungsten (W) layer.
- the second hard mask layer 112 can be formed from an oxide layer or a silicon oxynitride (SiON) layer.
- the second hard mask layer 112 , the second conductive layer 110 , the dielectric layer 108 , the first conductive layer 106 and the tunnel insulating layer 104 are sequentially etched through photo and development processes, thereby forming gates 114 in which the tunnel insulating layer 104 , the first conductive layer 106 , the dielectric layer 108 , the second conductive layer 110 and the second hard mask layer 112 are stacked.
- a SSL and a DSL are also formed at the same time in the select transistor region (i.e., the region in which the first trenches 102 are formed).
- a step is formed between the cell gates 114 in the cell region, and the SSL or the DSL formed in the select transistor region due to the first trenches 102 .
- a re-oxidation process is performed in order to eliminate damage occurring in the etch process for forming the gate 114 .
- spacers 116 are formed on the sides of the gates 114 .
- a third insulating layer 118 is formed over the semiconductor substrate 100 including the spacer 116 and the gates 114 .
- the third insulating layer 118 can be formed from an oxide layer or a nitride layer.
- a first insulating layer 120 is formed on the third insulating layer 118 .
- the first insulating layer 120 can be polished using a Chemical Mechanical Polishing (CMP) process to remove the step.
- CMP Chemical Mechanical Polishing
- the first insulating layer 120 is etched to form a source contact hole in a source retion between the SSLs of the select transistor region.
- the source contact hole is filled with a third conductive layer to form a source contact plug 122 .
- the third conductive layer can be formed from polysilicon or tungsten (W).
- a second insulating layer 124 is formed over the semiconductor substrate 100 including the source contact plug 122 and the first insulating layer 120 .
- a CMP process is then performed to polish the second insulating layer 124 .
- the second insulating layer 124 is formed, there is a step in the select transistor region. In this case, if a photoresist pattern for forming a drain contact hole is formed without first removing the step, the photoresist pattern will also have a step, preventing the etch process from being properly performed. Furthermore, if the etch process is not properly performed, metal material partially remains, thereby degrading the cell properties.
- the second insulating layer 124 and the first insulating layer 120 are etched by means of photo and development processes, thereby forming a drain contact hole in a drain region between the DSLs of the select transistor region.
- a fourth conductive layer is then formed over the semiconductor substrate 100 including the drain contact hole so that the drain contact hole is filled.
- the fourth conductive layer can be formed from polysilicon or tungsten (W).
- a polishing process is then performed until the top surface of the second insulating layer 124 is exposed, thereby forming a drain contact plug 126 .
- the invention has the following advantages.
- the cell region and the select transistor region are formed to have a step by partially etching the select transistor region of a semiconductor substrate (i.e., the region in which the SSL and the DSL are formed). Accordingly, the interference phenomenon between the select transistor and the cell gate nearest to the select transistor can be improved.
- the width between the select transistor and the cell gate nearest to the select transistor can be reduced significantly.
- the cell properties can be prevented from becoming defective since a large amount or a small amount of voltage flows due to changed current properties of a cell gate near a select transistor.
Abstract
A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.
Description
- This is a division of U.S. application Ser. No. 11/758,509 filed Jun. 5, 2007, which claims the priority benefit under USC 119 of Korean patent application number 10-2006-121518, filed on Dec. 4, 2006, the respective disclosures of which are incorporated by reference.
- The invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a flash memory device that reduces an undesirable interference phenomenon.
- Semiconductor memory devices for storing data can be largely classified into volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their data when the supply of power thereto is stopped, whereas nonvolatile memory devices retain their data in the absence of power.
- Each nonvolatile memory device includes a flash memory device. A unit cell of the flash memory device generally includes an active region defined on a specific region of a semiconductor substrate, a tunnel insulating layer formed on the active region, a floating gate formed on the tunnel insulating layer, a gate interlayer insulating layer formed on the floating gate, and a control gate electrode formed on the gate interlayer insulating layer. In particular, the flash memory device has been widely used for MP3 players, digital cameras, memory for computer BIOS storage, mobile phones, portable data storage devices and so on.
- The flash memory cell can store data as voltage externally applied to the control gate electrode is coupled to the floating gate. Accordingly, when storing data for a short period of time and at a low program voltage, the ratio of voltage applied to the control gate electrode to voltage applied to the floating gate must be high. The ratio of voltage applied to the control gate electrode to voltage applied to the floating gate is called the coupling ratio (“CR”). Furthermore, the coupling ratio can be expressed by the ratio of the capacitance of the gate interlayer insulating layer to the sum of the capacitance of the tunnel insulating layer and the gate interlayer insulating layer.
- In current flash memory manufacturing methods, the space where a unit active region and a unit field region will be formed narrows as devices become more highly integrated. When a dielectric layer, a control gate and a floating gate are formed within a narrow active space, the distance between the gates is narrowed, so that the interference phenomenon becomes increasingly problematic. In particular, in order to develop a Multi-Level Cell (MLC) in a general NAND flash memory device employing an Advanced Self-Aligned Shallow Trench Isolation (ASA-STI) method, interference charges between the floating gates must be reduced.
- A conventional method of manufacturing a flash memory device is briefly described below.
- In order to minimize the damage to a semiconductor substrate resulting from an ion implant process, a buffer insulating layer is formed on the semiconductor substrate. The buffer insulating layer is formed from an oxide layer. After the ion implant process is performed, the buffer insulating layer is removed. After a tunnel insulating layer is formed over the semiconductor substrate, an annealing process is performed. The tunnel insulating layer is formed by performing a wet or dry oxidization process at a temperature ranging from 750° C. to 850° C. using H2 or O2. The annealing process is performed in order to eliminate the trap phenomenon occurring at the interface between the semiconductor substrate and the tunnel insulating layer and to increase the data storage ability of the transistor. The annealing process includes a post-anneal process at a temperature ranging from 750° C. to 1100° C. using N2, N2O, or NO.
- A first conductive layer for a floating gate is formed on the tunnel insulating layer. The first conductive layer is formed by in-situ implanting a P or B dopant into a source gas of SiH4, Si2H6, or SiH2Cl2. A first hard mask layer having a stack structure of an oxide layer and a nitride layer is formed on the first conductive layer. The first hard mask layer, the first conductive layer, the tunnel insulating layer, and the semiconductor substrate are partially etched by a photo and development processes, thereby forming trenches and also a floating gate consisting of the first conductive layer.
- A first insulating layer is formed over the semiconductor substrate including the trenches so that the trenches are filled. The first insulating layer is polished to form isolation layers. The first insulating layer is polished using a High Density Plasma (HDP) oxide layer or Spin on Glass (SOG). In order to control the Effective Field Height (EFH) of the isolation layers, a wet etch process (i.e., a cleaning process) is performed to partially remove the top surface of the isolation layers.
- A dielectric layer is formed over the semiconductor substrate including the isolation layers and the first conductive layer. An annealing process and an oxidization process are carried out at a temperature ranging from 600° C. to 900° C. using O2 or H2. A second conductive layer for a control gate and a second hard mask layer are formed over the dielectric layer. The second conductive layer has a stacked structure including a polysilicon layer and a tungsten silicide (WSix) layer or tungsten (W). The second hard mask layer is formed from an oxide layer or a silicon oxynitride (SiON) layer. The second hard mask layer, the second conductive layer, the dielectric layer and the first conductive layer are etched through photo and development processes, thereby forming gates.
- Spacers for separating the gates are formed on the sides of the gates. In order to protect a cell gate, a second insulating layer is formed over the semiconductor substrate including the spacers and the gates. The second insulating layer is formed from an oxide layer or a nitride layer.
- A first insulating layer having a source contact plug formed therein is formed on the second insulating layer. A second insulating layer having a drain contact plug formed therein is formed over the semiconductor substrate including the source contact plug and the first insulating layer. The source contact plug and the drain contact plug are formed from polysilicon or tungsten. In order to store data in the cell gate and transfer external voltage to the source contact plug and the drain contact plug formed so as to read stored data, metal lines are formed on the second insulating layer.
- Today, in a flash memory device, in order to select a specific cell gate, voltage is applied to the SSL and the metal line, and current flows through the cell gate due to a difference between applied voltages. In order for the current to flow through only the cell gate, the select transistor, such as the Source Select Line (SSL) or the drain select line (DSL), are used. However, an interference phenomenon occurs between the select transistor and the cell gate that is the nearest to the select transistor due to voltage applied to turn on/off the select transistor. Accordingly, the current properties of the gate around the select transistor are changed, causing a large amount or small amount of current to flow. This results in defective cell properties.
- Accordingly, the invention addresses the above problems and discloses a method of manufacturing a flash memory device that reduces the interference phenomenon between a select transistor and a cell gate in such a manner that a cell region and a select transistor region have a step created by partially etching the select transistor region of a semiconductor substrate (i.e., a region where a Source Select Line (SSL) and a Drain Select Line (DSL) are formed).
- According to an aspect of the invention, there is provided a method of manufacturing a flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.
- According to another aspect of the invention, there is provided a flash memory device, including a semiconductor substrate having a step between a cell region and a select transistor region, a transistor formed in the select transistor region, and a memory cell formed in the cell region.
-
FIGS. 1A to 1E are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the invention. - Now, a specific embodiment according to the invention is described with reference to the accompanying drawings.
- Referring to
FIG. 1A , a first insulating layer (not shown) is formed on asemiconductor substrate 100 in order to minimize damage to the semiconductor substrate resulting from an ion implant process. The first insulating layer can be formed at a thickness of 50 Å to 200 Å using an oxide layer or a nitride layer. In order to define a cell region and a peri region, an N-type or P-type impurity is implanted into thesemiconductor substrate 100, and the first insulating layer is then removed. - A select transistor region (i.e., a region of the
semiconductor substrate 100 in which a SSL and a DSL will be formed) is partially etched to formfirst trenches 102. The width of thefirst trenches 102 can be set to 4 to 6 times larger than that of the SSL or the DSL, and the depth of thefirst trenches 102 can range from 300 Å to 1000 Å. When forming thefirst trenches 102, the side of thefirst trenches 102 is sloped, not vertical. The angle of the slope can be controlled depending on the polymer formation method and the corresponding amount of polymer used when etching thesemiconductor substrate 100. The side of thefirst trenches 102 is sloped so that it can provide good etching selectivity when etching steps are performed subsequent to the deposition of several additional layers. Thefirst trenches 102 formed in the select transistor region define a step formed between the cell region and the select transistor region. - Referring to
FIG. 1B , atunnel insulating layer 104 is formed over thesemiconductor substrate 100 including thefirst trenches 102. In order to prevent a trap phenomenon from occurring at the interface of thesemiconductor substrate 100 and thetunnel insulating layer 104 and to increase the data storage ability of the transistor, an annealing process is performed. Thetunnel insulating layer 104 can be formed by performing a wet or dry oxidization process at a temperature ranging from 750° C. to 850° C. using H2 or O2. The annealing process can be performed as a post annealing process at a temperature ranging from 750° C. to 1100° C. using N2, N2O, or NO. - A first
conductive layer 106 for a floating gate and a first hard mask layer (not shown) are formed on thetunnel insulating layer 104. The firstconductive layer 106 can be formed from a polysilicon layer by in-situ implantation of a Phosphorous(P) or Boron(B) dopant into a source gas, such as SiH4, Si2H6, or SiH2Cl2. The first hard mask layer can be formed using a single pad oxide layer, a single nitride layer, or a stacked layer including a pad oxide layer and a nitride layer. - The first hard mask layer, the first
conductive layer 106, thetunnel insulating layer 104 and thesemiconductor substrate 100 are partially etched through photo and development processes, thereby forming second trenches (not shown) for isolation layers (not shown) and also a floating gate pattern (not shown) comprising the firstconductive layer 106. - A second insulating layer is formed over the
semiconductor substrate 100 including the second trenches so that the second trenches are filled. The second insulating layer is then polished to form the isolation layers. The second insulating layer can be formed from an HDP oxide layer or SOG. In order to control the EFH of the isolation layer, a wet etch process (i.e., a cleaning process) is performed to partially remove the top surface of the isolation layer. - A
dielectric layer 108 is formed over thesemiconductor substrate 100 including the isolation layer and the firstconductive layer 106. An annealing process and an oxidization process are then performed. The annealing process can be performed at a temperature ranging from 600° C. to 900° C. using O2 or H2. - A second
conductive layer 110 for a control gate and a secondhard mask layer 112 are formed over thedielectric layer 108. The secondconductive layer 110 can have a structure in which a polysilicon layer is stacked with a tungsten silicide (WSix) layer or a tungsten (W) layer. The secondhard mask layer 112 can be formed from an oxide layer or a silicon oxynitride (SiON) layer. - Referring to
FIG. 1C , the secondhard mask layer 112, the secondconductive layer 110, thedielectric layer 108, the firstconductive layer 106 and thetunnel insulating layer 104 are sequentially etched through photo and development processes, thereby forminggates 114 in which thetunnel insulating layer 104, the firstconductive layer 106, thedielectric layer 108, the secondconductive layer 110 and the secondhard mask layer 112 are stacked. - When cell gates 114 (i.e., the
gates 114 in the cell region) are formed, a SSL and a DSL (which have the same stacked structure as the cell gates 114) are also formed at the same time in the select transistor region (i.e., the region in which thefirst trenches 102 are formed). A step is formed between thecell gates 114 in the cell region, and the SSL or the DSL formed in the select transistor region due to thefirst trenches 102. - Referring to
FIG. 1D , a re-oxidation process is performed in order to eliminate damage occurring in the etch process for forming thegate 114. In order to separate thegates 114,spacers 116 are formed on the sides of thegates 114. In order to protect thecell gates 114, a thirdinsulating layer 118 is formed over thesemiconductor substrate 100 including thespacer 116 and thegates 114. The thirdinsulating layer 118 can be formed from an oxide layer or a nitride layer. - Referring to
FIG. 1E , a first insulatinglayer 120 is formed on the third insulatinglayer 118. When the first insulatinglayer 120 is formed, there is a step in the select transistor region. The first insulatinglayer 120 can be polished using a Chemical Mechanical Polishing (CMP) process to remove the step. - The first insulating
layer 120 is etched to form a source contact hole in a source retion between the SSLs of the select transistor region. The source contact hole is filled with a third conductive layer to form asource contact plug 122. The third conductive layer can be formed from polysilicon or tungsten (W). - Thereafter, a second insulating
layer 124 is formed over thesemiconductor substrate 100 including thesource contact plug 122 and the first insulatinglayer 120. A CMP process is then performed to polish the second insulatinglayer 124. When the second insulatinglayer 124 is formed, there is a step in the select transistor region. In this case, if a photoresist pattern for forming a drain contact hole is formed without first removing the step, the photoresist pattern will also have a step, preventing the etch process from being properly performed. Furthermore, if the etch process is not properly performed, metal material partially remains, thereby degrading the cell properties. - The second
insulating layer 124 and the first insulatinglayer 120 are etched by means of photo and development processes, thereby forming a drain contact hole in a drain region between the DSLs of the select transistor region. A fourth conductive layer is then formed over thesemiconductor substrate 100 including the drain contact hole so that the drain contact hole is filled. The fourth conductive layer can be formed from polysilicon or tungsten (W). - A polishing process is then performed until the top surface of the second insulating
layer 124 is exposed, thereby forming adrain contact plug 126. - As described above, the invention has the following advantages.
- First, the cell region and the select transistor region are formed to have a step by partially etching the select transistor region of a semiconductor substrate (i.e., the region in which the SSL and the DSL are formed). Accordingly, the interference phenomenon between the select transistor and the cell gate nearest to the select transistor can be improved.
- Second, by reducing the interference phenomenon, the width between the select transistor and the cell gate nearest to the select transistor can be reduced significantly.
- Third, by reducing the interference phenomenon, the cell properties can be prevented from becoming defective since a large amount or a small amount of voltage flows due to changed current properties of a cell gate near a select transistor.
- Fourth, a retention characteristic of the select transistor and the cell gate nearest to the select transistor can be improved.
- Fifth, by improving the interference phenomenon, a program characteristic of the cell gate can become uniform.
- Although the foregoing description has been made with reference to the various embodiments, it is to be understood that changes and modifications of the disclosure may be made by the skilled artisan without departing from the spirit and scope of the disclosure and appended claims.
Claims (4)
1. A flash memory device, comprising:
a semiconductor substrate having a step between a cell region and a select transistor region;
a transistor formed in the select transistor region; and
a memory cell formed in the cell region.
2. The flash memory device of claim 1 , wherein a width of the select transistor region has 4 to 6 times larger than that of the transistor.
3. The flash memory device of claim 1 , wherein the step has a height ranging from about 300 Å to about 1000 Å.
4. The flash memory device of claim 1 , wherein a source contact plug and a drain contact plug are formed in the select transistor region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/840,090 US20100283095A1 (en) | 2006-12-04 | 2010-07-20 | Flash Memory Device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060121518A KR100880338B1 (en) | 2006-12-04 | 2006-12-04 | Method of manufacturing a flash memory device |
KR10-2006-121518 | 2006-12-04 | ||
US11/758,509 US7781275B2 (en) | 2006-12-04 | 2007-06-05 | Method of manufacturing a flash memory device |
US12/840,090 US20100283095A1 (en) | 2006-12-04 | 2010-07-20 | Flash Memory Device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/758,509 Division US7781275B2 (en) | 2006-12-04 | 2007-06-05 | Method of manufacturing a flash memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20100283095A1 true US20100283095A1 (en) | 2010-11-11 |
Family
ID=39474709
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/758,509 Expired - Fee Related US7781275B2 (en) | 2006-12-04 | 2007-06-05 | Method of manufacturing a flash memory device |
US12/840,090 Abandoned US20100283095A1 (en) | 2006-12-04 | 2010-07-20 | Flash Memory Device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/758,509 Expired - Fee Related US7781275B2 (en) | 2006-12-04 | 2007-06-05 | Method of manufacturing a flash memory device |
Country Status (4)
Country | Link |
---|---|
US (2) | US7781275B2 (en) |
JP (1) | JP2008141159A (en) |
KR (1) | KR100880338B1 (en) |
CN (1) | CN100539084C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100308395A1 (en) * | 2009-06-08 | 2010-12-09 | Hynix Semiconductor Inc. | Nonvolatile Memory Device and Method of Manufacturing the Same |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009277847A (en) * | 2008-05-14 | 2009-11-26 | Toshiba Corp | Nonvolatile semiconductor storage device |
JP2010114380A (en) * | 2008-11-10 | 2010-05-20 | Toshiba Corp | Semiconductor device |
KR20130139610A (en) * | 2012-06-13 | 2013-12-23 | 에스케이하이닉스 주식회사 | Semiconductor memory device, memory system comprising the same and method of manufacturing the same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5024961A (en) * | 1990-07-09 | 1991-06-18 | Micron Technology, Inc. | Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices |
US20020192887A1 (en) * | 1997-03-28 | 2002-12-19 | Tetsuo Adachi | Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device |
US20040178470A1 (en) * | 2003-03-14 | 2004-09-16 | Katsuhiko Hieda | Semiconductor memory device and method of manufacturing the same |
US20040261111A1 (en) * | 2003-06-20 | 2004-12-23 | Aboulgasem Abulgasem Hassan | Interactive mulitmedia communications at low bit rates |
US20060220098A1 (en) * | 2005-04-04 | 2006-10-05 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices and methods of making the same |
US20070059945A1 (en) * | 2005-09-12 | 2007-03-15 | Nima Mohklesi | Atomic layer deposition with nitridation and oxidation |
US20070109848A1 (en) * | 2005-11-15 | 2007-05-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and fabrication method for the same |
US7446038B2 (en) * | 2006-01-27 | 2008-11-04 | Industrial Technology Research Institute | Interlayer interconnect of three-dimensional memory and method for manufacturing the same |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2877463B2 (en) * | 1990-07-23 | 1999-03-31 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP3271090B2 (en) * | 1992-12-01 | 2002-04-02 | ソニー株式会社 | Semiconductor device manufacturing method |
JPH07254651A (en) * | 1994-03-16 | 1995-10-03 | Toshiba Corp | Semiconductor integrated circuit device |
KR19980072838A (en) * | 1997-03-08 | 1998-11-05 | 김광호 | Manufacturing method of nonvolatile semiconductor memory device with enhanced device isolation characteristics |
KR19990015794A (en) * | 1997-08-09 | 1999-03-05 | 윤종용 | Nonvolatile Memory Device and Manufacturing Method Thereof |
JP3556491B2 (en) | 1998-12-04 | 2004-08-18 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
KR100323140B1 (en) * | 2000-01-17 | 2002-02-06 | 윤종용 | NAND-type flash memory device and method of fabricating the same |
KR100426482B1 (en) * | 2001-12-22 | 2004-04-14 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory cell |
KR100490288B1 (en) * | 2003-06-30 | 2005-05-18 | 주식회사 하이닉스반도체 | Method of manufacturing flash memory device |
CN100386883C (en) | 2004-12-15 | 2008-05-07 | 旺宏电子股份有限公司 | Non-volatile memory unit and its operating method and non-volatile internal memory |
KR20060111221A (en) | 2005-04-22 | 2006-10-26 | 주식회사 하이닉스반도체 | Method of forming a gate pattern in flash memory device |
KR100672140B1 (en) | 2005-05-03 | 2007-01-19 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR20060120977A (en) | 2005-05-23 | 2006-11-28 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory device |
KR100673229B1 (en) | 2005-07-04 | 2007-01-22 | 주식회사 하이닉스반도체 | NAND-type flash memory device and method for manufacturing the same |
KR100864992B1 (en) | 2006-01-02 | 2008-10-23 | 주식회사 하이닉스반도체 | Method of manufacturing a Nand flash memory device |
-
2006
- 2006-12-04 KR KR1020060121518A patent/KR100880338B1/en not_active IP Right Cessation
-
2007
- 2007-06-05 US US11/758,509 patent/US7781275B2/en not_active Expired - Fee Related
- 2007-06-20 CN CNB2007101114438A patent/CN100539084C/en not_active Expired - Fee Related
- 2007-06-21 JP JP2007163670A patent/JP2008141159A/en active Pending
-
2010
- 2010-07-20 US US12/840,090 patent/US20100283095A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5024961A (en) * | 1990-07-09 | 1991-06-18 | Micron Technology, Inc. | Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices |
US20020192887A1 (en) * | 1997-03-28 | 2002-12-19 | Tetsuo Adachi | Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device |
US20040178470A1 (en) * | 2003-03-14 | 2004-09-16 | Katsuhiko Hieda | Semiconductor memory device and method of manufacturing the same |
US20040261111A1 (en) * | 2003-06-20 | 2004-12-23 | Aboulgasem Abulgasem Hassan | Interactive mulitmedia communications at low bit rates |
US20060220098A1 (en) * | 2005-04-04 | 2006-10-05 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices and methods of making the same |
US20070059945A1 (en) * | 2005-09-12 | 2007-03-15 | Nima Mohklesi | Atomic layer deposition with nitridation and oxidation |
US20070109848A1 (en) * | 2005-11-15 | 2007-05-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and fabrication method for the same |
US7446038B2 (en) * | 2006-01-27 | 2008-11-04 | Industrial Technology Research Institute | Interlayer interconnect of three-dimensional memory and method for manufacturing the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100308395A1 (en) * | 2009-06-08 | 2010-12-09 | Hynix Semiconductor Inc. | Nonvolatile Memory Device and Method of Manufacturing the Same |
US9331087B2 (en) | 2009-06-08 | 2016-05-03 | SK Hynix Inc. | Method of manufacturing a nonvolatile memory device |
Also Published As
Publication number | Publication date |
---|---|
CN101197330A (en) | 2008-06-11 |
CN100539084C (en) | 2009-09-09 |
US7781275B2 (en) | 2010-08-24 |
KR20080050788A (en) | 2008-06-10 |
US20080128778A1 (en) | 2008-06-05 |
JP2008141159A (en) | 2008-06-19 |
KR100880338B1 (en) | 2009-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8492224B2 (en) | Metal control gate structures and air gap isolation in non-volatile memory | |
US20050285219A1 (en) | Nonvolatile semiconductor memory and method of fabricating the same | |
CN108022930B (en) | Method of forming a semiconductor device structure and semiconductor device structure | |
US7773403B2 (en) | Spacer patterns using assist layer for high density semiconductor devices | |
TWI433304B (en) | Eeprom cell | |
KR100587396B1 (en) | Non-volatile memory device and Method for the same | |
US20120326220A1 (en) | Integrated Circuits With Sidewall Nitridation | |
US7592225B2 (en) | Methods of forming spacer patterns using assist layer for high density semiconductor devices | |
US7560340B2 (en) | Method of manufacturing flash memory device | |
KR100771805B1 (en) | Method of manufacturing a flash memory device | |
WO2013096564A1 (en) | Non-volatile storage system with three layer floating gate | |
US7741179B2 (en) | Method of manufacturing flash semiconductor device | |
US7781275B2 (en) | Method of manufacturing a flash memory device | |
US20080012063A1 (en) | Flash Memory and Method for Manufacturing the Same | |
US7923327B2 (en) | Method of fabricating non-volatile memory device with concavely depressed electron injection region | |
KR20120031257A (en) | Dielectric stack | |
US7525148B2 (en) | Nonvolatile memory device | |
US20100304557A1 (en) | Method of forming flash memory device having inter-gate plug | |
KR100771553B1 (en) | Buried type non-volatile memory device having charge trapping layer and method for fabricating the same | |
US20100167480A1 (en) | Method for Manufacturing Flash Memory Device | |
US20080254584A1 (en) | Method of manufacturing flash memory device | |
KR100559996B1 (en) | Method for manufacturing flash memory | |
US20080160692A1 (en) | Method for Manufacturing Flash Memory Device | |
US20050153511A1 (en) | Methods of fabricating nonvolatile memory device | |
JP2011124321A (en) | Method for manufacturing semiconductor and semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |