US20100025777A1 - Method for suppressing lattice defects in a semiconductor substrate - Google Patents
Method for suppressing lattice defects in a semiconductor substrate Download PDFInfo
- Publication number
- US20100025777A1 US20100025777A1 US12/577,022 US57702209A US2010025777A1 US 20100025777 A1 US20100025777 A1 US 20100025777A1 US 57702209 A US57702209 A US 57702209A US 2010025777 A1 US2010025777 A1 US 2010025777A1
- Authority
- US
- United States
- Prior art keywords
- atoms
- lattice
- layer
- compressive
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000007547 defect Effects 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 title abstract description 11
- 239000002019 doping agent Substances 0.000 claims abstract description 13
- 238000002513 implantation Methods 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 230000007935 neutral effect Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Definitions
- the present invention relates to the field of semiconductor fabrication.
- it relates to the fabrication of field effect transistors (FETs), involving the formation of semiconductor materials of selected conductivity, carried on by implantation of dopants.
- FETs field effect transistors
- MOS FETs metal oxide semiconductor FETs require the formation of source and drain regions in a substrate of generally pure silicon (Si).
- Si is provided in the form of a wafer, grown as a single crystal. Zones of the Si lattice are converted into regions of N or P conductivity by the addition of donor-type dopants, such as arsenic, for N regions, and acceptor-type dopants, such as boron, for P regions.
- donor-type dopants such as arsenic, for N regions
- acceptor-type dopants such as boron
- An aspect of the claimed invention is a method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice.
- the process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms.
- the lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
- FIG. 1 illustrates manner in which the problem of stress-induced defect formation occurs in a semiconductor substrate.
- FIG. 2 schematically depicts the solution of the claimed invention.
- FIG. 3 illustrates the mechanism by which the method of the presently claimed invention suppresses defects in a semiconductor substrate.
- FIG. 4 depicts an embodiment of a semiconductor formed in accordance with the claimed invention.
- FIG. 5 depicts an alternate embodiment of a semiconductor formed in accordance with the claimed invention.
- FIG. 6 depicts a further alternate embodiment of a semiconductor formed in accordance with the claimed invention.
- FIG. 1 depicts a typical MOSFET 100 after undergoing ion implantation.
- the transistor is formed on a silicon substrate 101 and includes source 102 , drain 104 and gate 106 .
- the depletion layer 108 adjacent each electrode and extending across the channel between the source and drain, is well known in the art.
- the depicted cell is one member of an array that can encompass millions of cells, as known in the art, and the cell is separated from other members of the array by Shallow Trench Isolators (STI) 109 , filled with dielectric fill material.
- STI Shallow Trench Isolators
- the source and drain are formed in the silicon substrate by the implantation of dopants, as known in the art, and the implantation process produces defects in the lattice, which defects are addressed by annealing the substrate after implantation. While most defects are removed by annealing, some will coalesce into larger defects 112 , often in the form of dislocation loops or area defects. These defects are generally collections of interstitial silicon atoms, knocked out of their lattice positions by dopant atoms. It has been found that large defects 112 tend to form more readily in portions of the substrate that either have no mechanical stress on the lattice, or preferably, where the lattice is subjected to tensile stress.
- locations where the lattice passes around a convex point in an underlying strained structure such as around comers in the SiGe source, SiGe drain and STI's, tend to favor the accumulation of defects, resulting in the situation seen in FIG. 1 , where defects 112 are seen at the corners of the source and drain as well as the corners of the STI's.
- FIG. 2 illustrates an analogy to the mechanism at work in this situation.
- the lattice 200 is represented as having lattice sites, corresponding to the peaks in the figure, where an interstitial atom 201 can come to rest in between the lattice atoms, requiring some expenditure of energy to move to another interstitial position.
- the energy required to move to either side is identical, corresponding to the situation in an unstressed lattice. Probabilities of moving either left or right in the drawing are equal.
- the bottom portion of the drawing shows one end of the line is higher than the other, analogous to the situation in which one portion of the lattice is subjected to compressive stress and the other is relaxed.
- movement “uphill” toward the compressive stress clearly requires more energy than movement “downhill” toward the relaxed portion of the lattice.
- movement toward relaxed portions of the lattice such as locations where the lattice is stressed by bending around a corner, are energetically favorable and will tend to collect more defects than compressively stressed areas.
- FIG. 3 A conceptual view of the operation of the claimed invention is seen in FIG. 3 .
- the structure formed by this process contains a number of large defects 112 , in the form of area, line or dislocation loop defects, but all such defects occur outside the compressive layer.
- FIG. 4 illustrates an embodiment of the presently claimed invention in a transistor 100 , with elements as set out above in connection with FIG. 1 .
- a compressive layer 103 of germanium is formed along with the dopant atoms.
- the germanium can be co-implanted—implanted at the same time—along with the dopants, or a layer of Ge can be epitaxially grown during formation of the substrate. Both of these techniques are effective in the illustrated context, and both are well-known in the art. Neither is particularly preferred, and thus the user can choose which process to employ based on other factors.
- defects 112 are all located outside the compressive layer, and thus away from the depletion layer 108 . Confined to portions of the substrate where they cannot form a leakage path, these defects are rendered entirely harmless.
- An alternative embodiment locates the compressive layer at least partially within the depletion layer, as seen in FIG. 4 .
- the exact position can lie entirely within the layer, or overlapping it.
- the primary goal of the compressive layer is to protect the depletion layer from defect formation, so having the compressive layer within the depletion layer altogether prevents the formation of defects there.
- the optimum solution calls for the compressive layer 103 to lie entirely outside the depletion layer, between the depletion layer and the defects 112 , as shown in FIG. 5 .
- the compressive layer is positioned to prevent the movement of intersitials toward or into the depletion layer, completely precluding defect formation there.
- FIG. 6 positions the compressive layer 103 at a level shallower than that of the depletion layer 108 .
- the compressive layer would lie wholly within the source and drain regions, as shown.
- the shape of the compressive layer will have substantially the same profile as does the source or drain region containing that layer, a fact that may not be clear from the drawing. Here, defects would form in the source and drain regions.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
Description
- The present invention relates to the field of semiconductor fabrication. In particular, it relates to the fabrication of field effect transistors (FETs), involving the formation of semiconductor materials of selected conductivity, carried on by implantation of dopants.
- Fabrication of metal oxide semiconductor (MOS) FETs requires the formation of source and drain regions in a substrate of generally pure silicon (Si). The Si is provided in the form of a wafer, grown as a single crystal. Zones of the Si lattice are converted into regions of N or P conductivity by the addition of donor-type dopants, such as arsenic, for N regions, and acceptor-type dopants, such as boron, for P regions. These dopants are generally introduced by ion bombardment, in which ionized dopant atoms are energized and fired at the lattice, penetrating the crystal structure to a depth largely dependent on the bombardment energy and the ion mass.
- It can be immediately gathered that such bombardment introduces crystal damage, in which lattice atoms are knocked out of lattice sites, while at the same time a certain number of the newly-introduced atoms will likewise come to rest in positions outside the lattice positions. Such out-of-position phenomena are termed defects. A vacant lattice site is termed a vacancy defect, while an atom located at a non-lattice site is referred to as an interstitial defect. The restorative method generally employed in the art consists of annealing the crystal, applying heat to the lattice to mildly energize the atoms, allowing them to work themselves back into the lattice structure, which provides the arrangement having the lowest overall energy level.
- An aspect of the claimed invention is a method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
-
FIG. 1 illustrates manner in which the problem of stress-induced defect formation occurs in a semiconductor substrate. -
FIG. 2 schematically depicts the solution of the claimed invention. -
FIG. 3 illustrates the mechanism by which the method of the presently claimed invention suppresses defects in a semiconductor substrate. -
FIG. 4 depicts an embodiment of a semiconductor formed in accordance with the claimed invention. -
FIG. 5 depicts an alternate embodiment of a semiconductor formed in accordance with the claimed invention. -
FIG. 6 depicts a further alternate embodiment of a semiconductor formed in accordance with the claimed invention. - The following detailed description is made with reference to the figures. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.
- The problem addressed by the present disclosure is seen in
FIG. 1 , which depicts atypical MOSFET 100 after undergoing ion implantation. The transistor is formed on asilicon substrate 101 and includessource 102,drain 104 andgate 106. Thedepletion layer 108 adjacent each electrode and extending across the channel between the source and drain, is well known in the art. The depicted cell is one member of an array that can encompass millions of cells, as known in the art, and the cell is separated from other members of the array by Shallow Trench Isolators (STI) 109, filled with dielectric fill material. - The source and drain are formed in the silicon substrate by the implantation of dopants, as known in the art, and the implantation process produces defects in the lattice, which defects are addressed by annealing the substrate after implantation. While most defects are removed by annealing, some will coalesce into
larger defects 112, often in the form of dislocation loops or area defects. These defects are generally collections of interstitial silicon atoms, knocked out of their lattice positions by dopant atoms. It has been found thatlarge defects 112 tend to form more readily in portions of the substrate that either have no mechanical stress on the lattice, or preferably, where the lattice is subjected to tensile stress. For example, locations where the lattice passes around a convex point in an underlying strained structure, such as around comers in the SiGe source, SiGe drain and STI's, tend to favor the accumulation of defects, resulting in the situation seen inFIG. 1 , wheredefects 112 are seen at the corners of the source and drain as well as the corners of the STI's. -
FIG. 2 illustrates an analogy to the mechanism at work in this situation. In each portion of the drawing, thelattice 200 is represented as having lattice sites, corresponding to the peaks in the figure, where aninterstitial atom 201 can come to rest in between the lattice atoms, requiring some expenditure of energy to move to another interstitial position. In the upper portion of the drawing, the energy required to move to either side is identical, corresponding to the situation in an unstressed lattice. Probabilities of moving either left or right in the drawing are equal. The bottom portion of the drawing, however, shows one end of the line is higher than the other, analogous to the situation in which one portion of the lattice is subjected to compressive stress and the other is relaxed. Here, movement “uphill” toward the compressive stress clearly requires more energy than movement “downhill” toward the relaxed portion of the lattice. Thus, movement toward relaxed portions of the lattice, such as locations where the lattice is stressed by bending around a corner, are energetically favorable and will tend to collect more defects than compressively stressed areas. - A conceptual view of the operation of the claimed invention is seen in
FIG. 3 . There, along with the implantation of dopants, acompressive layer 103 of atoms having a larger size than silicon, being higher on the periodic table, is implanted in the substrate. Germanium, lying directly below silicon in the periodic table, is a preferred element for this purpose. That layer produces an area of higher compression, causing a net migration of defects away from the compressive layer, indicated byarrows 105. After annealing, the structure formed by this process contains a number oflarge defects 112, in the form of area, line or dislocation loop defects, but all such defects occur outside the compressive layer. -
FIG. 4 illustrates an embodiment of the presently claimed invention in atransistor 100, with elements as set out above in connection withFIG. 1 . Here, however, acompressive layer 103 of germanium is formed along with the dopant atoms. The germanium can be co-implanted—implanted at the same time—along with the dopants, or a layer of Ge can be epitaxially grown during formation of the substrate. Both of these techniques are effective in the illustrated context, and both are well-known in the art. Neither is particularly preferred, and thus the user can choose which process to employ based on other factors. - Most importantly,
defects 112 are all located outside the compressive layer, and thus away from thedepletion layer 108. Confined to portions of the substrate where they cannot form a leakage path, these defects are rendered entirely harmless. - An alternative embodiment locates the compressive layer at least partially within the depletion layer, as seen in
FIG. 4 . The exact position can lie entirely within the layer, or overlapping it. The primary goal of the compressive layer is to protect the depletion layer from defect formation, so having the compressive layer within the depletion layer altogether prevents the formation of defects there. - The optimum solution calls for the
compressive layer 103 to lie entirely outside the depletion layer, between the depletion layer and thedefects 112, as shown inFIG. 5 . There, the compressive layer is positioned to prevent the movement of intersitials toward or into the depletion layer, completely precluding defect formation there. - Another embodiment, shown in
FIG. 6 , positions thecompressive layer 103 at a level shallower than that of thedepletion layer 108. Here, those in the art will understand that it would not be desirable to have the compressive layer extend into channel, and thus the compressive layer would be implanted after implantation of the source anddrain regions - While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
Claims (9)
1. A semiconductor formed on a crystal substrate, having N-type and P-type regions, with a channel between the source and drain regions and a gate positioned above the channel, and having a depletion layer adjacent each region, comprising a compressive layer of atoms, such atoms being selected to impose a compressive stress on the crystal lattice, wherein any existing energetically stable lattice defects, lie outside the compressive layer.
2. The semiconductor of claim 1 , wherein the compressive layer atoms are larger than the lattice member atoms.
3. The semiconductor of claim 1 , wherein the compressive layer atoms are electrically neutral
4. The semiconductor of claim 1 , wherein the compressive layer is provided by co-implantation of compressive atoms with dopant atoms.
5. The semiconductor of claim 1 , wherein the compressive layer is provided by epitaxially growing the compressive layer.
6. The semiconductor of claim 1 , wherein the lattice-member atoms are silicon, and the compressive layer atoms are germanium.
7. The semiconductor of claim 1 , wherein the compressive layer lies at least partially within the depletion layer.
8. The semiconductor of claim 1 , wherein the compressive layer lies outside the depletion layer, between the depletion layer and the defects.
9. The semiconductor of claim 1 , wherein the compressive layer lies at a level shallower than that of the depletion layer, such that the defects lie in the source and drain regions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/577,022 US20100025777A1 (en) | 2007-10-30 | 2009-10-09 | Method for suppressing lattice defects in a semiconductor substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/928,142 US9472423B2 (en) | 2007-10-30 | 2007-10-30 | Method for suppressing lattice defects in a semiconductor substrate |
US12/577,022 US20100025777A1 (en) | 2007-10-30 | 2009-10-09 | Method for suppressing lattice defects in a semiconductor substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/928,142 Division US9472423B2 (en) | 2007-10-30 | 2007-10-30 | Method for suppressing lattice defects in a semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
US20100025777A1 true US20100025777A1 (en) | 2010-02-04 |
Family
ID=40581686
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/928,142 Active 2030-07-07 US9472423B2 (en) | 2007-10-30 | 2007-10-30 | Method for suppressing lattice defects in a semiconductor substrate |
US12/577,022 Abandoned US20100025777A1 (en) | 2007-10-30 | 2009-10-09 | Method for suppressing lattice defects in a semiconductor substrate |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/928,142 Active 2030-07-07 US9472423B2 (en) | 2007-10-30 | 2007-10-30 | Method for suppressing lattice defects in a semiconductor substrate |
Country Status (6)
Country | Link |
---|---|
US (2) | US9472423B2 (en) |
EP (1) | EP2210269A4 (en) |
JP (1) | JP5227412B2 (en) |
CN (1) | CN101681838B (en) |
TW (1) | TWI396236B (en) |
WO (1) | WO2009058449A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9276113B2 (en) * | 2014-03-10 | 2016-03-01 | International Business Corporation | Structure and method to make strained FinFET with improved junction capacitance and low leakage |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112271137B (en) * | 2020-11-02 | 2024-04-09 | 中国工程物理研究院电子工程研究所 | Passivation method based on high electron mobility transistor |
Citations (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4769686A (en) * | 1983-04-01 | 1988-09-06 | Hitachi, Ltd. | Semiconductor device |
US5098852A (en) * | 1989-07-05 | 1992-03-24 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device by mega-electron volt ion implantation |
US5592012A (en) * | 1993-04-06 | 1997-01-07 | Sharp Kabushiki Kaisha | Multivalued semiconductor read only storage device and method of driving the device and method of manufacturing the device |
US5966622A (en) * | 1997-10-08 | 1999-10-12 | Lucent Technologies Inc. | Process for bonding crystalline substrates with different crystal lattices |
US5985726A (en) * | 1998-11-06 | 1999-11-16 | Advanced Micro Devices, Inc. | Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET |
US6180476B1 (en) * | 1998-11-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Dual amorphization implant process for ultra-shallow drain and source extensions |
US6200869B1 (en) * | 1998-11-06 | 2001-03-13 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions |
US6225173B1 (en) * | 1998-11-06 | 2001-05-01 | Advanced Micro Devices, Inc. | Recessed channel structure for manufacturing shallow source/drain extensions |
US20010011362A1 (en) * | 2000-01-27 | 2001-08-02 | Nec Corporation | Semiconductor layout design method and apparatus |
US20020022326A1 (en) * | 1999-11-11 | 2002-02-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US6437406B1 (en) * | 2000-10-19 | 2002-08-20 | International Business Machines Corporation | Super-halo formation in FETs |
US20020138817A1 (en) * | 2001-03-26 | 2002-09-26 | Kuo-Chun Lee | Method for inserting antenna diodes into an integrated circuit design |
US6590230B1 (en) * | 1996-10-15 | 2003-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6594809B2 (en) * | 2000-11-29 | 2003-07-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low leakage antenna diode insertion for integrated circuits |
US6618847B1 (en) * | 1998-11-13 | 2003-09-09 | Stmicroelectronics, Inc. | Power stabilizer using under-utilized standard cells |
US6682965B1 (en) * | 1997-03-27 | 2004-01-27 | Sony Corporation | Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect |
US6685772B2 (en) * | 2001-03-28 | 2004-02-03 | California Institute Of Technology | De novo processing of electronic materials |
US6689671B1 (en) * | 2002-05-22 | 2004-02-10 | Advanced Micro Devices, Inc. | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate |
US20050029601A1 (en) * | 2003-08-04 | 2005-02-10 | International Business Machines Corporation | Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions |
US20050035409A1 (en) * | 2003-08-15 | 2005-02-17 | Chih-Hsin Ko | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US20050044522A1 (en) * | 2003-08-21 | 2005-02-24 | Kawasaki Microelectronics, Inc. | Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure |
US20050076320A1 (en) * | 2003-10-02 | 2005-04-07 | Kawasaki Microelectronics, Inc. | Layout structure of semiconductor integrated circuit and method for forming the same |
US20050106824A1 (en) * | 2001-12-04 | 2005-05-19 | Carnera Alberto | Method for suppressing transient enhanced diffusion of dopants in silicon |
US20050151181A1 (en) * | 2004-01-09 | 2005-07-14 | International Business Machines Corporation | Nitrided sti liner oxide for reduced corner device impact on vertical device performance |
US20050216877A1 (en) * | 2002-07-12 | 2005-09-29 | Cadence Design Systems, Inc. | Method and system for context-specific mask writing |
US20060017138A1 (en) * | 2004-07-13 | 2006-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain enhanced ultra shallow junction formation |
US20060046415A1 (en) * | 2004-08-25 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method for the same |
US7032194B1 (en) * | 2003-02-19 | 2006-04-18 | Xilinx, Inc. | Layout correction algorithms for removing stress and other physical effect induced process deviation |
US20060107243A1 (en) * | 2004-11-18 | 2006-05-18 | Agere Systems Inc. | Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects |
US20060160338A1 (en) * | 2004-12-17 | 2006-07-20 | Applied Materials, Inc. | Method of ion implantation to reduce transient enhanced diffusion |
US7084051B2 (en) * | 2002-06-07 | 2006-08-01 | Sharp Kabushiki Kaisha | Manufacturing method for semiconductor substrate and manufacturing method for semiconductor device |
US20060199398A1 (en) * | 2003-05-30 | 2006-09-07 | Tokyo Electron Limited | Method of modifying insulating film |
US20070045610A1 (en) * | 2005-08-24 | 2007-03-01 | Industrial Technology Research Institute | Transistor device with strained germanium (Ge) layer by selectively growth and fabricating method thereof |
US20070123010A1 (en) * | 2005-11-30 | 2007-05-31 | Jan Hoentschel | Technique for reducing crystal defects in strained transistors by tilted preamorphization |
US20070130553A1 (en) * | 2005-12-06 | 2007-06-07 | Cadence Design Systems, Inc. | Analog layout module generator and method |
US20070173022A1 (en) * | 2006-01-20 | 2007-07-26 | Chih-Hao Wang | Defect-free SiGe source/drain formation by epitaxy-free process |
US7259079B2 (en) * | 2003-07-11 | 2007-08-21 | Micron Technology, Inc. | Methods for filling high aspect ratio trenches in semiconductor layers |
US20070204250A1 (en) * | 2006-02-27 | 2007-08-30 | Synopsys, Inc. | Stress-managed revision of integrated circuit layouts |
US20070202663A1 (en) * | 2006-02-27 | 2007-08-30 | Synopsys, Inc. | Managing integrated circuit stress using stress adjustment trenches |
US20080005712A1 (en) * | 2006-06-29 | 2008-01-03 | Charlebois Steven E | Method of optimizing customizable filler cells in an integrated circuit physical design process |
US7404174B2 (en) * | 2004-07-27 | 2008-07-22 | International Business Machines Corporation | method for generating a set of test patterns for an optical proximity correction algorithm |
US20080265361A1 (en) * | 2007-04-26 | 2008-10-30 | Martin Krauss | Method for generating a layout, use of a transistor layout, and semiconductor circuit |
US20090007043A1 (en) * | 2006-02-27 | 2009-01-01 | Synopsys, Inc. | Managing Integrated Circuit Stress Using Dummy Diffusion Regions |
US20090047772A1 (en) * | 2006-07-28 | 2009-02-19 | Central Research Institute Of Electric Power Industry | Method for Improving the Quality of a SiC Crystal |
US20090055793A1 (en) * | 2007-08-22 | 2009-02-26 | Hanno Melzner | Method of making an integrated circuit having fill structures |
US7514366B2 (en) * | 2004-08-24 | 2009-04-07 | Micron Technology, Inc. | Methods for forming shallow trench isolation |
US7521763B2 (en) * | 2007-01-03 | 2009-04-21 | International Business Machines Corporation | Dual stress STI |
US7538351B2 (en) * | 2005-03-23 | 2009-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an SOI structure with improved carrier mobility and ESD protection |
US7605407B2 (en) * | 2006-09-06 | 2009-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite stressors with variable element atomic concentrations in MOS devices |
US20090302349A1 (en) * | 2005-06-15 | 2009-12-10 | Industrial Technology Research Institute | Strained germanium field effect transistor and method of fabricating the same |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878682A (en) | 1994-07-08 | 1996-03-22 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
TW429478B (en) * | 1997-08-29 | 2001-04-11 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
JPH11168069A (en) | 1997-12-03 | 1999-06-22 | Nec Corp | Manufacture of semiconductor device |
JP2002524845A (en) | 1998-09-02 | 2002-08-06 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | Silicon-on-insulator structure obtained from single crystal silicon with low defect density |
TW533508B (en) * | 1999-05-05 | 2003-05-21 | Taiwan Semiconductor Mfg | Structure and method for preventing inter-metal dielectric layer of semiconductor from cracking |
JP2001237322A (en) * | 2000-02-25 | 2001-08-31 | Nec Microsystems Ltd | Semiconductor integrated circuit layout method |
JP2003128494A (en) * | 2001-10-22 | 2003-05-08 | Sharp Corp | Method for producing semiconductor device and semiconductor device |
CN1444264A (en) * | 2002-03-08 | 2003-09-24 | 矽统科技股份有限公司 | Microshallow insulating groove structure preparation method |
CN1259703C (en) * | 2002-08-29 | 2006-06-14 | 上海宏力半导体制造有限公司 | Manufacturing method of semiconductor assembly part capable of improving lattice defectin silicon build up crystal layer |
JP2004214440A (en) * | 2003-01-06 | 2004-07-29 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
DE10310740A1 (en) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Method for producing a stress-relaxed layer structure on a non-lattice-matched substrate, and use of such a layer system in electronic and / or optoelectronic components |
JP2004281591A (en) * | 2003-03-14 | 2004-10-07 | Hitachi Ltd | Semiconductor epitaxial wafer, its manufacturing method, semiconductor device, and its manufacturing method |
US7169675B2 (en) * | 2004-07-07 | 2007-01-30 | Chartered Semiconductor Manufacturing, Ltd | Material architecture for the fabrication of low temperature transistor |
JP2006093658A (en) * | 2004-08-25 | 2006-04-06 | Toshiba Corp | Semiconductor apparatus and manufacturing method thereof |
JP2006196872A (en) * | 2004-12-17 | 2006-07-27 | Matsushita Electric Ind Co Ltd | Standard cell, standard cell library, semiconductor device, and layout method of them |
JP4455441B2 (en) * | 2005-07-27 | 2010-04-21 | 株式会社東芝 | Manufacturing method of semiconductor device |
US7514752B2 (en) * | 2005-08-26 | 2009-04-07 | Toshiba America Electronic Components, Inc. | Reduction of short-circuiting between contacts at or near a tensile-compressive boundary |
JP2007141971A (en) * | 2005-11-15 | 2007-06-07 | Matsushita Electric Ind Co Ltd | Designing method of semiconductor integrated circuit |
US20070160100A1 (en) * | 2006-01-11 | 2007-07-12 | Huffaker Diana L | Misfit dislocation forming interfacial self-assembly for growth of highly-mismatched III-Sb alloys |
-
2007
- 2007-10-30 US US11/928,142 patent/US9472423B2/en active Active
-
2008
- 2008-07-30 JP JP2010529994A patent/JP5227412B2/en not_active Expired - Fee Related
- 2008-07-30 WO PCT/US2008/071572 patent/WO2009058449A1/en active Application Filing
- 2008-07-30 TW TW097128820A patent/TWI396236B/en not_active IP Right Cessation
- 2008-07-30 CN CN2008800141375A patent/CN101681838B/en active Active
- 2008-07-30 EP EP08782517A patent/EP2210269A4/en not_active Withdrawn
-
2009
- 2009-10-09 US US12/577,022 patent/US20100025777A1/en not_active Abandoned
Patent Citations (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4769686A (en) * | 1983-04-01 | 1988-09-06 | Hitachi, Ltd. | Semiconductor device |
US5098852A (en) * | 1989-07-05 | 1992-03-24 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device by mega-electron volt ion implantation |
US5592012A (en) * | 1993-04-06 | 1997-01-07 | Sharp Kabushiki Kaisha | Multivalued semiconductor read only storage device and method of driving the device and method of manufacturing the device |
US6590230B1 (en) * | 1996-10-15 | 2003-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6682965B1 (en) * | 1997-03-27 | 2004-01-27 | Sony Corporation | Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect |
US5966622A (en) * | 1997-10-08 | 1999-10-12 | Lucent Technologies Inc. | Process for bonding crystalline substrates with different crystal lattices |
US5985726A (en) * | 1998-11-06 | 1999-11-16 | Advanced Micro Devices, Inc. | Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET |
US6180476B1 (en) * | 1998-11-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Dual amorphization implant process for ultra-shallow drain and source extensions |
US6200869B1 (en) * | 1998-11-06 | 2001-03-13 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions |
US6225173B1 (en) * | 1998-11-06 | 2001-05-01 | Advanced Micro Devices, Inc. | Recessed channel structure for manufacturing shallow source/drain extensions |
US6618847B1 (en) * | 1998-11-13 | 2003-09-09 | Stmicroelectronics, Inc. | Power stabilizer using under-utilized standard cells |
US20020022326A1 (en) * | 1999-11-11 | 2002-02-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US20010011362A1 (en) * | 2000-01-27 | 2001-08-02 | Nec Corporation | Semiconductor layout design method and apparatus |
US6437406B1 (en) * | 2000-10-19 | 2002-08-20 | International Business Machines Corporation | Super-halo formation in FETs |
US6594809B2 (en) * | 2000-11-29 | 2003-07-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low leakage antenna diode insertion for integrated circuits |
US20020138817A1 (en) * | 2001-03-26 | 2002-09-26 | Kuo-Chun Lee | Method for inserting antenna diodes into an integrated circuit design |
US6685772B2 (en) * | 2001-03-28 | 2004-02-03 | California Institute Of Technology | De novo processing of electronic materials |
US20050106824A1 (en) * | 2001-12-04 | 2005-05-19 | Carnera Alberto | Method for suppressing transient enhanced diffusion of dopants in silicon |
US6689671B1 (en) * | 2002-05-22 | 2004-02-10 | Advanced Micro Devices, Inc. | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate |
US7084051B2 (en) * | 2002-06-07 | 2006-08-01 | Sharp Kabushiki Kaisha | Manufacturing method for semiconductor substrate and manufacturing method for semiconductor device |
US20050216877A1 (en) * | 2002-07-12 | 2005-09-29 | Cadence Design Systems, Inc. | Method and system for context-specific mask writing |
US7032194B1 (en) * | 2003-02-19 | 2006-04-18 | Xilinx, Inc. | Layout correction algorithms for removing stress and other physical effect induced process deviation |
US20060199398A1 (en) * | 2003-05-30 | 2006-09-07 | Tokyo Electron Limited | Method of modifying insulating film |
US7259079B2 (en) * | 2003-07-11 | 2007-08-21 | Micron Technology, Inc. | Methods for filling high aspect ratio trenches in semiconductor layers |
US20050029601A1 (en) * | 2003-08-04 | 2005-02-10 | International Business Machines Corporation | Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions |
US20050035409A1 (en) * | 2003-08-15 | 2005-02-17 | Chih-Hsin Ko | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US20050044522A1 (en) * | 2003-08-21 | 2005-02-24 | Kawasaki Microelectronics, Inc. | Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure |
US20050076320A1 (en) * | 2003-10-02 | 2005-04-07 | Kawasaki Microelectronics, Inc. | Layout structure of semiconductor integrated circuit and method for forming the same |
US20050151181A1 (en) * | 2004-01-09 | 2005-07-14 | International Business Machines Corporation | Nitrided sti liner oxide for reduced corner device impact on vertical device performance |
US20060017138A1 (en) * | 2004-07-13 | 2006-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain enhanced ultra shallow junction formation |
US7404174B2 (en) * | 2004-07-27 | 2008-07-22 | International Business Machines Corporation | method for generating a set of test patterns for an optical proximity correction algorithm |
US7514366B2 (en) * | 2004-08-24 | 2009-04-07 | Micron Technology, Inc. | Methods for forming shallow trench isolation |
US20060046415A1 (en) * | 2004-08-25 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method for the same |
US20060107243A1 (en) * | 2004-11-18 | 2006-05-18 | Agere Systems Inc. | Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects |
US7174532B2 (en) * | 2004-11-18 | 2007-02-06 | Agere Systems, Inc. | Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects |
US20060160338A1 (en) * | 2004-12-17 | 2006-07-20 | Applied Materials, Inc. | Method of ion implantation to reduce transient enhanced diffusion |
US7538351B2 (en) * | 2005-03-23 | 2009-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an SOI structure with improved carrier mobility and ESD protection |
US20090302349A1 (en) * | 2005-06-15 | 2009-12-10 | Industrial Technology Research Institute | Strained germanium field effect transistor and method of fabricating the same |
US20070045610A1 (en) * | 2005-08-24 | 2007-03-01 | Industrial Technology Research Institute | Transistor device with strained germanium (Ge) layer by selectively growth and fabricating method thereof |
US20070123010A1 (en) * | 2005-11-30 | 2007-05-31 | Jan Hoentschel | Technique for reducing crystal defects in strained transistors by tilted preamorphization |
US20070130553A1 (en) * | 2005-12-06 | 2007-06-07 | Cadence Design Systems, Inc. | Analog layout module generator and method |
US20070173022A1 (en) * | 2006-01-20 | 2007-07-26 | Chih-Hao Wang | Defect-free SiGe source/drain formation by epitaxy-free process |
US20070204250A1 (en) * | 2006-02-27 | 2007-08-30 | Synopsys, Inc. | Stress-managed revision of integrated circuit layouts |
US20090007043A1 (en) * | 2006-02-27 | 2009-01-01 | Synopsys, Inc. | Managing Integrated Circuit Stress Using Dummy Diffusion Regions |
US7484198B2 (en) * | 2006-02-27 | 2009-01-27 | Synopsys, Inc. | Managing integrated circuit stress using dummy diffusion regions |
US20090313595A1 (en) * | 2006-02-27 | 2009-12-17 | Synopsys, Inc. | Stress-managed revision of integrated circuit layouts |
US20070202663A1 (en) * | 2006-02-27 | 2007-08-30 | Synopsys, Inc. | Managing integrated circuit stress using stress adjustment trenches |
US20080005712A1 (en) * | 2006-06-29 | 2008-01-03 | Charlebois Steven E | Method of optimizing customizable filler cells in an integrated circuit physical design process |
US20090047772A1 (en) * | 2006-07-28 | 2009-02-19 | Central Research Institute Of Electric Power Industry | Method for Improving the Quality of a SiC Crystal |
US7605407B2 (en) * | 2006-09-06 | 2009-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite stressors with variable element atomic concentrations in MOS devices |
US7521763B2 (en) * | 2007-01-03 | 2009-04-21 | International Business Machines Corporation | Dual stress STI |
US20080265361A1 (en) * | 2007-04-26 | 2008-10-30 | Martin Krauss | Method for generating a layout, use of a transistor layout, and semiconductor circuit |
US20090055793A1 (en) * | 2007-08-22 | 2009-02-26 | Hanno Melzner | Method of making an integrated circuit having fill structures |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9276113B2 (en) * | 2014-03-10 | 2016-03-01 | International Business Corporation | Structure and method to make strained FinFET with improved junction capacitance and low leakage |
Also Published As
Publication number | Publication date |
---|---|
US9472423B2 (en) | 2016-10-18 |
EP2210269A1 (en) | 2010-07-28 |
TWI396236B (en) | 2013-05-11 |
US20090108293A1 (en) | 2009-04-30 |
JP5227412B2 (en) | 2013-07-03 |
JP2011501437A (en) | 2011-01-06 |
WO2009058449A1 (en) | 2009-05-07 |
EP2210269A4 (en) | 2012-05-30 |
TW200926301A (en) | 2009-06-16 |
CN101681838B (en) | 2011-09-14 |
CN101681838A (en) | 2010-03-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7947546B2 (en) | Implant damage control by in-situ C doping during SiGe epitaxy for device applications | |
TWI459557B (en) | N-channel mosfets comprising dual stressors, and methods for forming the same | |
KR101605150B1 (en) | In situ formed drain and source regions including a strain inducing alloy and a graded dopant profile | |
US7851291B2 (en) | Epitaxial silicon germanium for reduced contact resistance in field-effect transistors | |
US8557692B2 (en) | FinFET LDD and source drain implant technique | |
US9034741B2 (en) | Halo region formation by epitaxial growth | |
US8598006B2 (en) | Strain preserving ion implantation methods | |
JP2005521265A5 (en) | ||
US9153662B2 (en) | MOSFET with selective dopant deactivation underneath gate | |
CN103094207A (en) | Method of manufacturing semiconductor device using stress memorization technique | |
US20090057678A1 (en) | Method of Forming an Integrated Circuit and Integrated Circuit | |
US8273642B2 (en) | Method of fabricating an NMOS transistor | |
US7071069B2 (en) | Shallow amorphizing implant for gettering of deep secondary end of range defects | |
DE112011101488T5 (en) | Transistor with longitudinal stress in the channel induced by a buried stressor relaxed by implantation | |
US9472423B2 (en) | Method for suppressing lattice defects in a semiconductor substrate | |
US8154077B2 (en) | Semiconductor device | |
CN102468166A (en) | Transistor and manufacturing method thereof | |
US8507993B2 (en) | Buried layer of an integrated circuit | |
US7410846B2 (en) | Method for reduced N+ diffusion in strained Si on SiGe substrate | |
US20090108408A1 (en) | Method for Trapping Implant Damage in a Semiconductor Substrate | |
JP2007184535A (en) | Method of manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |