US20090305615A1 - Carrier for double-side polishing apparatus, double-side polishing apparatus using the same, and double-side polishing method - Google Patents

Carrier for double-side polishing apparatus, double-side polishing apparatus using the same, and double-side polishing method Download PDF

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Publication number
US20090305615A1
US20090305615A1 US12/308,991 US30899107A US2009305615A1 US 20090305615 A1 US20090305615 A1 US 20090305615A1 US 30899107 A US30899107 A US 30899107A US 2009305615 A1 US2009305615 A1 US 2009305615A1
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US
United States
Prior art keywords
carrier
double
side polishing
semiconductor wafer
polishing apparatus
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Abandoned
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US12/308,991
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English (en)
Inventor
Isao Uchiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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Assigned to SHIN-ETSU HANDOTAI CO., LTD. reassignment SHIN-ETSU HANDOTAI CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: UCHIYAMA, ISAO
Publication of US20090305615A1 publication Critical patent/US20090305615A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/28—Work carriers for double side lapping of plane surfaces

Definitions

  • the present invention relates to a carrier for double-side polishing apparatus that holds a semiconductor wafer when polishing the semiconductor wafer in a double-side polishing apparatus.
  • the semiconductor wafer When, e.g., polishing both surfaces of a semiconductor wafer, the semiconductor wafer is held by a carrier in conventional examples.
  • This carrier is formed with a thickness thinner than that of the semiconductor wafer and has a wafer holding hole through which the wafer is held at a predetermined position between an upper turn table and a lower turn table of a double-side polishing apparatus.
  • the semiconductor wafer is inserted into and held in this wafer holding hole, upper and lower surfaces of the semiconductor wafer are sandwiched by polishing jig, e.g., polishing pads provided on opposed surfaces of the upper turn table and the lower turn table, and polishing is carried out while supplying a polishing agent to the polishing target surfaces.
  • this method has a defect that the number of steps is increased when the secondary double-side polishing step that remedies the peripheral sag is performed, and a double-side polishing method that can more readily reduce the peripheral sag has been demanded.
  • dressing of polishing pad surfaces is performed by using, e.g., a ceramic plate in order to obtain stable polishing characteristics.
  • a ceramic plate in order to obtain stable polishing characteristics.
  • an effect of dressing of the polishing pad surfaces does not last long, and there is a problem that dressing of the polishing pad surfaces must be frequently carried out by using, e.g., a ceramic plate.
  • a carrier for double-side polishing apparatus which is set between upper and lower turn tables having polishing pads attached thereto and has a holding hole in which a semiconductor wafer sandwiched between the upper and lower turn tables is held at the time of polishing in a double-side polishing apparatus, wherein a material of the carrier is titanium, and surface roughness of the titanium carrier is 0.14 ⁇ m or above in terms of Ra.
  • the material of the carrier is titanium
  • a hardness is higher and abrasion at the time of polishing is smaller than those of a resin
  • a carrier life can be improved.
  • titanium itself has a small diffusion coefficient in the semiconductor wafer, e.g., silicon, it hardly becomes a problem as an impurity, and a metal impurity having a large diffusion coefficient like Fe is not present in titanium, thereby suppressing contamination of the metal impurity with respect to the semiconductor wafer.
  • the high-quality wafer having reduced peripheral sag and a high flatness can be stably efficiently produced.
  • dressing of the polishing pads can be performed by using the carrier surface during polishing, a frequency of dressing of the polishing pads using, e.g., ceramic plate can be reduced, thus efficient polishing can be performed.
  • the surface roughness it is preferable for the surface roughness to be 0.32 ⁇ m or above in terms of Ra.
  • the surface roughness of the carrier is 0.32 ⁇ m or above in terms of Ra, the high-quality wafer having reduced peripheral sag and a high flatness can be produced.
  • the carrier prefferably to have grooves each reaching the holding hole from a carrier outer peripheral side on front and back surfaces thereof.
  • the carrier has the grooves each reaching the holding hole from the carrier outer peripheral side on front and back surfaces thereof in this manner, since the polishing liquid is supplied to the semiconductor wafer through the grooves at the time of polishing, a resistance undergone by the wafer outer peripheral portion at the time of polishing can be alleviated, and the peripheral sag can be reduced. Additionally, dressing of the polishing pads can be also performed by the groove during polishing, a frequency of dressing of the polishing pads using, e.g., ceramic plate can be further decreased.
  • a pattern of the grooves can be a grid-like pattern or a radial pattern.
  • the polishing liquid can be easily and assuredly supplied to the semiconductor wafer at the time of polishing.
  • a double-side polishing apparatus comprising at least the carrier for double-side polishing apparatus according to the present invention
  • the material of the carrier is titanium
  • a life can be increased, and contamination of a metal impurity with respect to a semiconductor wafer can be suppressed, thereby producing the high-quality wafer having reduced peripheral sag and a high flatness.
  • dressing of polishing pads can be performed by carrier surfaces during polishing, a frequency of dressing of the polishing pads using, e.g., ceramic plate can be reduced, thus considerably improving an operating rate of the apparatus.
  • a double-side polishing method for a semiconductor wafer comprising: arranging the carrier between upper and lower turn tables holding the semiconductor wafer in a holding hole formed in the carrier; and sandwiching the semiconductor wafer between the upper and lower turn tables to perform double-side polishing.
  • the carrier for double-side polishing apparatus that has an improved life and hardly occurs contamination due to a metal impurity can be provided, and the high-quality wafer having reduced contamination due to the metal impurity, and decreased peripheral sag, and a high flatness can be stably efficiently produced by using this carrier.
  • dressing of the polishing pads can be performed by using the carrier surfaces during polishing, a frequency of dressing of the polishing pads using, e.g., a ceramic plate can be reduced. Therefore, a cost can be reduced, and the semiconductor wafer can be efficiently subjected to double-side polishing.
  • FIG. 1 is a vertical cross-sectional view showing an example of a double-side polishing apparatus including a carrier for double-side apparatus according to the present invention
  • FIG. 2 is an internal structural view of the double-side polishing apparatus as seen from a plane;
  • FIG. 3 is a schematic view showing a measurement position for a peripheral sag amount
  • FIG. 4 shows measurement results of experiments
  • FIG. 5 shows measurement results of experiments
  • FIG. 6 show an example of a pattern of grooves on front and back surfaces of the carrier for double-side polishing apparatus according to the present invention, (a) grid-like pattern, (b) radial pattern;
  • FIG. 7 shows measurement results of Examples 1 and 2 and Comparative Examples 1 and 2;
  • FIG. 8 shows measurement results of Examples 3 to 7.
  • FIG. 9 shows measurement results of Example 8 and Comparative Example 3.
  • a carrier for double-side polishing apparatus there is one formed of a metal, e.g., stainless or one having ceramic abrasive grains deposited on a surface of a metal plate, for example.
  • a metal e.g., stainless or one having ceramic abrasive grains deposited on a surface of a metal plate, for example.
  • an outer peripheral portion alone of a held semiconductor wafer is excessively polished at the time of polishing to cause peripheral sag, or deposited abrasive grains fall off to produce scratches on a wafer surface, resulting in a problem that a quality of the semiconductor wafer is reduced.
  • a carrier for double-side polishing apparatus in which a material of the carrier is titanium and surface roughness of the titanium carrier is 0.14 ⁇ m or above in terms of Ra can solve the above-explained problem, thereby bringing the present invention to completion.
  • a carrier for double-side polishing apparatus when such a carrier for double-side polishing apparatus is used to perform double-side polishing, a high-quality wafer having reduced peripheral sag and a high flatness can be produced. Furthermore, since dressing of the polishing pads can be performed by using carrier surfaces during polishing, a frequency of dressing of the polishing pads using, e.g., ceramic plate can be reduced, and polishing can be efficiently carried out. Moreover, this carrier has a structure where each carrier surface itself is roughened without depositing abrasive grains, the abrasive grains do not fall off to produce scratches on the wafer surfaces. Additionally, since titanium is adopted as the material, a life becomes long, and contamination of, e.g., iron that affects a wafer quality does not occur.
  • FIG. 1 is a vertical cross-sectional view showing an example of a double-side polishing apparatus including a double-side polishing apparatus according to the present invention
  • FIG. 2 is an internal structural view of the double-side polishing apparatus as seen from a plane.
  • the present invention relates to an improvement in a carrier that holds a semiconductor wafer in a double-side polishing apparatus that simultaneously polishes both surfaces of the semiconductor wafer, and an outline of the double-side polishing apparatus will be first explained with reference to FIGS. 1 and 2 .
  • a double-side polishing apparatus 11 provided with a carrier 10 for double-side polishing apparatus includes a lower turn table 12 and an upper turn table 13 vertically provided to face each other, and polishing pads 14 are attached to opposed surfaces sides of the respective turn tables 12 and 13 . Further, a sun gear 15 is provided at a central portion between the upper turntable 13 and the lower turntable 12 , and an internal gear 16 is provided at a rim portion. A semiconductor wafer W is held in a holding hole 17 of the carrier 10 and sandwiched between the upper turntable 13 and the lower turn table 12 .
  • each carrier 10 meshes with respective tooth portions of the sun gear 15 and the internal gear 16 , and each carrier 10 rotates around the sun gear 15 while rotating on its axis when the upper turn table 13 and the lower turn table 12 are rotated by a non-illustrated driving source.
  • each semiconductor wafer W is held in the holding hole 17 of the carrier 10 , and both surfaces thereof are simultaneously polished by the upper and lower polishing pads 14 .
  • a polishing liquid is supplied from a non-illustrated nozzle.
  • each carrier holds one wafer to perform polishing in FIG. 2 , but carriers each having a number of holding holes may be used and a number of wafers may be held in each carrier to perform polishing.
  • the carrier 10 for double-side polishing apparatus according to the present invention set in the double-side polishing apparatus 11 will now be explained hereinafter.
  • a material of the carrier 10 according to the present invention is titanium, and this material has a higher hardness than that a SUS material coated with resin and does not have an impurity with a large diffusion coefficient like Fe or Ni contained therein. Therefore, scratches or damages can be reduced to increase a carrier life, and a cost can be reduced. Furthermore, contamination of a metal that becomes a problem of the semiconductor wafer W can be suppressed.
  • a hardness of SUS as a conventional carrier material is 420 Hv
  • a hardness of Ti as a material of the carrier 10 according to the present invention is 220 Hv. Therefore, it has been conventionally considered that Ti has the hardness lower than that of SUS and cannot be used as a material of the carrier.
  • a carrier having the exposed SUS material causes occurrence of crucial metal contamination with respect to the semiconductor wafer W, and the SUS material must be actually coated with a resin in order to suppress the metal contamination. Therefore, each surface of the carrier 10 according to the present invention is titanium, as its material is harder than each surface of the conventional carrier coated with a resin. Therefore, its life becomes long.
  • the carrier 10 according to the present invention is featured in that its surface roughness is 0.14 ⁇ m or above in terms of Ra.
  • the present inventor has discovered that the surface roughness of the carrier must be 0.14 ⁇ m or above in terms of Ra in order to obtain a wafer having reduced peripheral sag.
  • the carrier for double-side polishing apparatus a number of carriers which are formed of titanium and have different surface roughness degrees obtained by roughening front and back surfaces thereof by diamond pellets having different sizes were prepared.
  • the surface roughness of each carrier surface was measured by using Surf Test SJ-201P manufactured by Mitutoyo, and evaluation was carried out based on JIS B0601-1994.
  • Each of the carriers was set in a double-side polishing apparatus, dressing of polishing pads was performed, and then double-side polishing of each silicon wafer having a diameter of 300 mm was performed. That is, the etched silicon wafer was set in each of five titanium carriers each having one holding hole, an upper turn table was rotated in a clockwise direction whilst a lower turn table was rotated in a counterclockwise direction with a number of revolutions of 20 rpm and a load of 250 g/cm 2 , and an alkaline solution containing colloidal silica was used as a polishing liquid to perform polishing.
  • a peripheral sag amount of each polished wafer was measured.
  • a wafer shape evaluation apparatus manufactured by Kuroda Precision Industries Ltd. was used to measure a difference in wafer shape between a position that is 1 mm away from a wafer edge and a position that is 3 mm away from the same as a peripheral sag amount with a section between a position that is 30 mm away from the wafer edge and a position where peripheral sag starts being determined as a reference plane as shown in FIG. 3 .
  • the following Table 1 and FIGS. 4 and 5 show measurement results.
  • the carrier in this experiment, deformation or damages of each carrier do not occur even if the front and back surfaces of the carrier are roughened, the carrier can be used to reach its life equivalent to that of a titanium carrier that is not subjected to processing of roughening the front and back surfaces of the carrier, and any difference in wafer quality other than a flatness from the non-processed carrier was not recognized.
  • dressing of the polishing pads can be performed during polishing by roughening the front and back surfaces of the carrier. Although dressing is performed once in 10 batches in conventional examples, the same effect can be obtained by carrying out dressing once in 40 batches.
  • the titanium carrier having surface roughness of 0.14 ⁇ m or above in terms of Ra or more preferably the titanium carrier having surface roughness of 0.32 ⁇ m or above in terms of Ra has a long carrier life, and performing double-side polishing by using this carrier enables stably and efficiently producing a high-quality wafer having reduced metal contamination, decreased peripheral sag, and a high flatness at a low cost. Further, since dressing of the polishing pads can be performed by using carrier surfaces during polishing, a frequency of dressing of the polishing pads using, e.g., ceramic plate can be reduced, and an operating rate of the apparatus can be considerably improved.
  • the carrier according to the present invention it is preferable for the carrier according to the present invention to have grooves each reaching the holding hole from the carrier outer peripheral side on the front and back surfaces thereof.
  • the carrier has such grooves, since the polishing liquid is supplied to the semiconductor wafer through the grooves at the time of polishing, a resistance undergone by the wafer outer peripheral portion at the time of polishing can be alleviated, thereby reducing the peripheral sag. Further, since dressing of the polishing pads can be carried out by using the grooves during polishing, a frequency of dressing of the polishing pads using, e.g., ceramic plate can be further reduced.
  • a pattern of the grooves is not restricted in particular, it may be, e.g., a grid-like pattern described in FIG. 6( a ), a radial pattern grooves 18 shown in FIG. 6( b ), or a pattern of horizontal stripes or vertical stripes.
  • each groove 18 may have, e.g., a width of 1 to 2 mm and a depth of 2 to 6 ⁇ m.
  • the carrier for double-side polishing apparatus has been taken as an example and explained, the carrier for double-side polishing apparatus according to the present invention is not restricted to the planetary type, and it is also effective to adopt a carrier for swinging type double-side polishing apparatus.
  • the double-side polishing apparatus 11 provided with the carrier 10 for the double-side polishing apparatus according to the present invention When the double-side polishing apparatus 11 provided with the carrier 10 for the double-side polishing apparatus according to the present invention is adopted, a wafer having reduced metal contamination, decreased peripheral sag, and a high flatness can be obtained. Furthermore, since dressing of the polishing pads can be performed by using the carrier surfaces during polishing, a frequency of dressing of the polishing pads can be reduced, and an operating rate of the apparatus can be considerably improved. Moreover, since a carrier life is long, a cost can be reduced.
  • the carrier 10 for the double-side polishing apparatus can be set between the upper and lower turn tables 12 and 13 having the polishing pads 14 of the double-side polishing apparatus 11 attached thereto, the semiconductor wafer W is held in the holding hole 17 to be sandwiched between the upper and lower turn tables 12 and 13 , and the wafer W can be subjected to double-side polishing while supplying the polishing liquid.
  • double-side polishing of each silicon wafer having a diameter of 300 mm was performed. That is, one etched silicon wafer W was set in each of five titanium carriers each having a holding hole 17 , an upper turn table 13 was rotated in a clockwise direction whilst a lower turn table 12 was rotated in a counterclockwise direction with a number of revolutions of 20 rpm and a load of 250 g/cm 2 , and an alkaline solution containing colloidal silica was used as a polishing liquid. This polishing was repeatedly performed for four times.
  • a peripheral sag amount of each wafer after polishing was measured.
  • a wafer shape evaluation apparatus manufactured by Kuroda Precision Industries Ltd. was used to measure a difference in wafer shape between a position that is 1 mm away from a wafer edge and a position that is 3 mm away from the same as a peripheral sag amount with a section from a position that is 30 mm apart form the wafer edge to a position where peripheral sag starts being determined as a reference plane.
  • FIG. 7 shows obtained measurement results.
  • FIG. 7 shows obtained measurement results.
  • each wafer having reduced peripheral sag and a high flatness can be obtained in each of the four polishing operations.
  • a groove width was 1 mm
  • a groove depth was 2 ⁇ m
  • a groove interval was 2 mm. Double-side polishing was performed under the same conditions as those of Examples 1 and 2 except that each carrier having such grooves was used.
  • FIG. 8 shows obtained measurement results.
  • each wafer according to Examples 3, 4, and 5 has a higher flatness than each wafer according to Examples 6 and 7.
  • the peripheral sag amount according to each of Examples 3, 4, and 5 is far smaller than that according to Examples 6 and 7 and the peripheral sag can be further improved by forming the grooves on the carrier.
  • Double-side polishing was performed under the same conditions as those of Examples 1 and 2.
  • the carrier having abrasive grains deposited thereon When the carrier having abrasive grains deposited thereon is used in this manner, a quality of a wafer may be possibly degraded, but using the carrier according to the present invention enables obtaining a high-quality wafer.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
US12/308,991 2006-07-18 2007-06-05 Carrier for double-side polishing apparatus, double-side polishing apparatus using the same, and double-side polishing method Abandoned US20090305615A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006-195967 2006-07-18
JP2006195967A JP4904960B2 (ja) 2006-07-18 2006-07-18 両面研磨装置用キャリア及びこれを用いた両面研磨装置並びに両面研磨方法
PCT/JP2007/061339 WO2008010357A1 (fr) 2006-07-18 2007-06-05 Support pour dispositif de polissage recto verso et dispositif de polissage recto verso et procédé de polissage recto verso utilisant le support

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US (1) US20090305615A1 (fr)
EP (1) EP2042267B1 (fr)
JP (1) JP4904960B2 (fr)
KR (1) KR101493709B1 (fr)
CN (1) CN101489722B (fr)
TW (1) TWI418439B (fr)
WO (1) WO2008010357A1 (fr)

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US20110045748A1 (en) * 2009-08-21 2011-02-24 Siltron Inc. Double side polishing apparatus and carrier therefor
US20110104995A1 (en) * 2008-02-27 2011-05-05 Shin-Etsu Handotai Co., Ltd. Carrier for a double-side polishing apparatus, double-side polishing apparatus using this carrier, and double-side polishing method
US20120028546A1 (en) * 2010-07-28 2012-02-02 Siltronic Ag Method and apparatus for trimming the working layers of a double-side grinding apparatus
CN103493184A (zh) * 2011-04-26 2014-01-01 信越半导体股份有限公司 半导体晶片及其制造方法
DE102013200756A1 (de) 2013-01-18 2014-08-07 Siltronic Ag Läuferscheibe für die beidseitige Politur von Scheiben aus Halbleitermaterial
US20140273760A1 (en) * 2013-03-15 2014-09-18 Ii-Vi Incorporated Double-Sided Polishing of Hard Substrate Materials
US20140308878A1 (en) * 2013-04-12 2014-10-16 Siltronic Ag Method for polishing semiconductor wafers by means of simultaneous double-side polishing
US20150321311A1 (en) * 2013-01-29 2015-11-12 Shin-Etsu Handotai Co., Ltd. Carrier for use in double-side polishing apparatus and method of double-side polishing wafer
US20180099377A1 (en) * 2016-10-12 2018-04-12 Disco Corporation Processing apparatus and processing method for workpiece
US11052506B2 (en) * 2015-10-09 2021-07-06 Sumco Corporation Carrier ring, grinding device, and grinding method
US20220061162A1 (en) * 2020-08-24 2022-02-24 At&S (China) Co. Ltd. Component Carrier With Well-Defined Outline Sidewall Cut by Short Laser Pulse and/or Green Laser
US11772231B2 (en) 2016-07-29 2023-10-03 Sumco Corporation Double-sided wafer polishing method

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JP2012111001A (ja) * 2010-11-25 2012-06-14 Nikon Corp ワークキャリア及び該ワークキャリアを備えた研磨装置
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JP6197580B2 (ja) * 2013-10-29 2017-09-20 株式会社Sumco キャリアプレート及びワークの両面研磨装置
JP6128198B1 (ja) 2015-12-22 2017-05-17 株式会社Sumco ウェーハの両面研磨方法及びこれを用いたエピタキシャルウェーハの製造方法
CN109551311A (zh) * 2018-12-12 2019-04-02 大连理工大学 一种机械研磨或抛光过程中减小塌边现象的方法
JP7200898B2 (ja) * 2019-09-27 2023-01-10 株式会社Sumco ワークの両面研磨方法
CN111230630B (zh) * 2020-03-14 2022-04-22 李广超 一种扁钢双面打磨器
CN113496870B (zh) * 2020-04-03 2022-07-26 重庆超硅半导体有限公司 一种集成电路用硅片边缘形貌控制方法
JP7168113B1 (ja) * 2022-04-20 2022-11-09 信越半導体株式会社 ウェーハの両面研磨方法

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JP4904960B2 (ja) 2012-03-28
CN101489722A (zh) 2009-07-22
JP2008023617A (ja) 2008-02-07
TWI418439B (zh) 2013-12-11
KR20090029270A (ko) 2009-03-20
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TW200819242A (en) 2008-05-01
KR101493709B1 (ko) 2015-02-16

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