US20090124483A1 - Metal compound dots dielectric piece - Google Patents

Metal compound dots dielectric piece Download PDF

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Publication number
US20090124483A1
US20090124483A1 US12/356,064 US35606409A US2009124483A1 US 20090124483 A1 US20090124483 A1 US 20090124483A1 US 35606409 A US35606409 A US 35606409A US 2009124483 A1 US2009124483 A1 US 2009124483A1
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Prior art keywords
dots
metal compound
energy barrier
layer
dielectric piece
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US12/356,064
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Cha-Hsin Lin
Pei-Jer Tzeng
Maikap Siddheswar
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/405—Oxides of refractory metals or yttrium
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • This invention relates to a dielectric material layer, and more particularly to a dielectric piece including metal compound dots.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • NVRAM non-volatile memory
  • Nano-dots non-volatile memory devices at present draw a great attention.
  • Nano-dots non-volatile memory device includes a charge storage layers having a great number of nano-dots form therein, each of which serves as an independent charge storage center.
  • a tunneling oxide layer includes pathways for leakage currents
  • nano-dots non-volatile memory still has superior charge retention capability.
  • the nano-dots non-volatile memory is well characterized in storing charges into nano-dots layers so as to perform a charge storage function of the memory.
  • silicon nanocrystal dots, germanium nanocrystal dots, or metal nano-dots dielectric layer serving as a charge storage layer to instead of the traditional silicon nitride charge storage layer are studied.
  • the present invention is to provide a dielectric piece including metal compound dots to store charges.
  • One embodiment of the present invention is to provide a method of fabricating a dielectric piece including metal compound dots.
  • a stack layer including a metal nitride layer and an energy barrier layer is formed over a substrate.
  • a treatment process is performed to transform the metal nitride layer into a plurality of crystalline metal compound dots distributed in the energy barrier layer.
  • One embodiment of the present invention is to provide a method of fabricating a dielectric piece including metal compound dots.
  • a stack layer including a metal nitride layer and an energy barrier layer is formed over a substrate.
  • an annealing process is performed to transform the metal compound layer in the stack layer into a plurality of crystalline metal compound dots distributed in the energy barrier layer.
  • One embodiment of the invention is to provide a dielectric piece.
  • the dielectric piece includes an energy barrier layer and a plurality of crystalline metal compound dots distributed in the energy barrier layer.
  • the material of the energy barrier layer is different from that of the crystalline metal compound dots.
  • the method of fabricating the dielectric piece including metal compound dots in accordance with the present invention is simple, and can be used for mass production of semiconductors devices.
  • the dielectric piece of the present invention meets the requirements of semiconductor devices in this and the next generation so as to be applied to complementary metal oxide semiconductors (CMOS), non-volatile memory devices, or capacitors as inter-gate dielectric layers, charge storage layers, or dielectric layers of capacitors.
  • CMOS complementary metal oxide semiconductors
  • capacitors as inter-gate dielectric layers, charge storage layers, or dielectric layers of capacitors.
  • FIGS. 1A through 1B are schematic cross-sectional views showing a method of fabricating a dielectric piece including metal compound dots according to one embodiment of the present invention.
  • FIGS. 2A through 2B are schematic cross-sectional views showing a method for fabricating the dielectric piece including metal compound dots according to another embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional diagram showing the dielectric piece according to an embodiment of the present invention.
  • FIG. 4 schematically illustrates an application of the dielectric piece of the present invention to a CMOS.
  • FIG. 5 schematically illustrates an application of the dielectric piece of the present invention to a flash memory device.
  • FIG. 6 schematically illustrates an application of the dielectric piece of the present invention to a flash memory device.
  • FIG. 7 schematically illustrates an application of the dielectric piece of the present invention to a capacitor.
  • a method of fabricating a dielectric piece includes metal compound dots is illustrated in the following embodiments.
  • a stack layer including an energy barrier layer and a metal nitride layer or a metal oxide layer is formed over a substrate. Afterward, a process is performed to transform the metal nitride layer or the metal oxide layer in the stack layer into a plurality of crystalline metal compound dots distributed in the energy barrier layer.
  • FIGS. 1A through 1B are schematic cross-sectional views showing a method of fabricating a dielectric piece including metal compound dots according to one embodiment of the present invention.
  • a stack layer 102 is formed over a substrate 100 .
  • the stack layer 102 includes a metal nitride layer 104 and an energy barrier layer 106 .
  • the stack layer 102 shown in the FIG. 1A includes two metal nitride layers 104 and two energy barrier layers 106 alternately.
  • the metal nitride layers 104 and the energy barrier layers 106 are alternately stacked.
  • the stack layer 102 includes one metal nitride layer 104 sandwiched in between two energy barrier layers 106 , for example.
  • the stack layer 102 in another embodiment of the present invention includes one energy barrier layer 106 sandwiched in between two metal nitride layers 104 .
  • the material of the metal nitride layer 104 includes refractory metal nitride, such as titanium nitride, zirconium nitride, or hafnium nitride, which can be formed through an atomic layer chemical vapor deposition (ALD) process.
  • the thickness of the metal nitride layer 104 is determined in accordance with the requirements of design. For example, in order to form the metal compound nanocrystal dots, the thickness of the metal nitride layer 104 is less than or equal to 10 angstroms. In one embodiment of the present invention, the thickness of the metal nitride layer 104 is approximately 3-6 angstroms.
  • the material of the energy barrier 106 is different from that of the crystalline metal compound dots transformed from the metal nitride layer 104 . While applied to semiconductor devices, the selection of the material of the energy barrier 106 can consider a material whose conductive band and valence band are relative to those of semiconductor, such as silicon. Usually, the conductive band the energy barrier 106 is 1 eV higher than that of semiconductors, while the valence band the energy barrier 106 is 1 eV lower than that of semiconductors. Thus, the potential energy barrier can be higher enough to prevent electrons or holes passing through the energy barrier 106 , which can achieve insulation properties.
  • the material of the energy barrier 106 can be selected from a group consisting of Al 2 O 3 , Ta 2 O 5 , BaO, ZrO 2 , LaAlO 3 , La 2 O 3 , SrO, Y 2 O 3 , Si 3 N 4 , Si x N y , HfSiO x , ZrSiO x , MgO, SiO x , and SiO 2 , and combinations thereof.
  • the thickness of the energy barrier layer 106 is determined in accordance with the requirements of design. In one embodiment of the present invention, the thickness of the energy barrier 106 is about 5-20 angstroms, for example.
  • a process is performed to transform the metal nitride layer 104 in the stack layer 102 into a plurality of crystalline metal compound dots 108 distributed in the energy barrier layer 106 .
  • the crystalline metal compound dots 108 are, for example, crystalline metal oxide dots, such as crystalline titanium oxide dots, crystalline zirconium oxide dots, or crystalline hafnium oxide dots.
  • the process is to perform an annealing operation in oxygen-free ambience, such as nitrogen, argon, hydrogen, or ammonia ambience, to transform the metal nitride layer 104 in the stack layer 102 into a plurality of metal nitride dots distributed in the energy barrier layer 106 .
  • the metal nitride dots are transformed into a plurality of crystalline metal oxide dots 108 .
  • the treatment process includes an oxidation annealing operation in air, oxygen, nitric oxide, or nitrogen dioxide ambience, for example, to directly transform the metal nitride layer 104 into crystalline metal oxide dots 108 .
  • the crystalline metal compound dots 108 are crystalline metal oxide dots which are made during the conveying process after the stack layer 102 is formed. The stack layer 102 may be exposed to the oxygen in the air during the conveying process. The oxygen carried by the stack layer 102 can directly transforms the metal nitride layer 104 into the crystalline metal oxide dots 108 , though the annealing operation is in an oxygen-free or a micro-oxygen ambience.
  • FIGS. 2A through 2C are schematic cross-sectional views showing a method of fabricating the dielectric piece including metal compound dots according to another embodiment of the present invention.
  • a stack layer 202 is formed over a substrate 200 .
  • the stack layer 202 includes a metal compound layer 204 and an energy barrier layer 206 .
  • the stack layer 202 shown in the FIG. 2A includes two metal compound layers 204 and two energy barrier layers 206 .
  • the metal compound layers 204 and the energy barrier layers 206 are alternately stacked.
  • the stack layer 202 includes one metal compound layer 204 sandwiched in between two energy barrier layers 206 .
  • the stack layer 202 in another embodiment of the present invention includes one energy barrier layer 206 sandwiched in between two metal compound layers 204 .
  • the material of the metal compound layer 204 includes a refractory metal oxide, such as titanium oxide, zirconium oxide, or hafnium oxide.
  • the material is formed through an atomic layer chemical vapor deposition (ALD) process.
  • ALD atomic layer chemical vapor deposition
  • the thickness of the metal compound layer 204 is determined in accordance with the requirements of design. For example, in order to form metal compound nano-dots, the thickness of the metal compound layer 204 is less than or equal to 10 angstroms. In one embodiment of the present invention, the thickness of the metal compound layer 204 is about 3 angstroms.
  • the material of the energy barrier 206 is selected from a group consisting of Al 2 O 3 , Ta 2 O 5 , BaO, ZrO 2 , LaAlO 3 , La 2 O 3 , SrO, Y 2 O 3 , Si 3 N y , Si x N y , HfSiO x , ZrSiO x , MgO, SiO x , and SiO 2 , and combinations thereof.
  • the thickness of the energy barrier layer 206 is determined in accordance with the requirements of design. In one embodiment of the present invention, the thickness of each energy barrier layer 206 is about 5-20 angstroms, for example.
  • a process is performed to transform the metal compound layer 204 in the stack layer 202 into a plurality of crystalline metal compound dots 208 distributed in the energy barrier layer 206 .
  • the crystalline metal compound dots 208 are, for example, refractory metal compound dots, such as crystalline titanium oxide dots, crystalline zirconium oxide dots, or crystalline hafnium oxide dots.
  • the process is to perform an annealing operation in oxygen-free ambience such as a nitrogen, argon, hydrogen, or ammonia ambience to transform the metal compound layer in the stack layer 202 into a plurality of crystalline metal compound dots 208 distributed in the energy barrier layer 206 .
  • the process includes an oxidation annealing operation in an oxygen, nitric oxide, or nitrogen dioxide ambience, for example, to transform the metal nitride layer 204 into the crystalline metal oxide dots 208 .
  • a dielectric piece 300 can be formed through the aforesaid methods.
  • the dielectric piece 300 includes an energy barrier 306 and a plurality of crystalline metal compound dots 308 distributed in the energy barrier 306 .
  • the crystalline metal compound dots 308 include crystalline titanium oxide dots, crystalline zirconium oxide dots, or crystalline hafnium oxide dots.
  • the material of the energy barrier 306 is selected from a group consisting of Al 2 O 3 , Ta 2 O 5 , BaO, ZrO 2 , LaAlO 3 , La 2 O 3 , SrO, Y 2 O 3 , Si 3 N 4 , Si x N y , HfSiO x , ZrSiO x , MgO, SiO x , and SiO 2 , and combinations thereof.
  • the crystalline metal compound dots 308 in the dielectric piece 300 can be as small as nano-dots and be limited within the energy barrier layer 306 . Accordingly, the charges in the dielectric piece 300 are well retained. This dielectric piece can be extensively applied to fabricate integrated circuits.
  • the dielectric piece of the present invention can also be applied to fabricate semiconductor devices.
  • the dielectric piece of the present invention can be applied to a CMOS 402 as a gate dielectric layer 406 of a gate structure 404 .
  • the dielectric piece of the present invention can be applied to non-volatile memory devices.
  • the dielectric piece of the present invention can be applied to a flash memory device 501 as a replacement of a floating gate 504 for charge storage.
  • FIG. 4 the dielectric piece of the present invention can be applied to a CMOS 402 as a gate dielectric layer 406 of a gate structure 404 .
  • the dielectric piece of the present invention can be applied to non-volatile memory devices.
  • the dielectric piece of the present invention can be applied to a flash memory device 501 as a replacement of a floating gate 504 for charge storage.
  • FIG. 5 for example, the dielectric piece of the present invention can be applied to a flash memory device 501 as a replacement of a floating gate 504 for
  • the dielectric piece can be applied to a silicon nitride read-only-memory device 602 as a charge storage layer 604 between a control gate 606 and a substrate 600 , replacing traditional oxide/nitride/oxide (ONO) layer.
  • the dielectric piece can as well be applied to a capacitor 702 as a dielectric material 706 between two electrodes 704 and 708 . In application, the dielectric piece can certainly be utilized alone or together with other dielectric materials.

Abstract

A dielectric piece includes an energy barrier layer and a plurality of crystalline metal compound dots distributed in the energy barrier layer. The material of the crystalline metal compound dots is different from that of the energy barrier layer. Due to its capability of retaining charges, the dielectric piece of the present invention meets the requirements of semiconductor devices in this and the next generation so as to be applied to complementary metal oxide semiconductors (CMOS), non-volatile memory devices, or capacitors as inter-gate dielectric layers, charge storage layers, or dielectric layers of capacitors.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional of and claims priority benefit of an application Ser. No. 11/466,773, filed on Aug. 24, 2006, which claims the priority benefit of Taiwan application serial no. 95125405, filed on Jul. 12, 2006. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention relates to a dielectric material layer, and more particularly to a dielectric piece including metal compound dots.
  • 2. Description of Related Art
  • Derived from semiconductor technologies, a variety of memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory (NVRAM) nowadays play a significant role in the semiconductor industry. With the development and advancement of the semiconductor technology, these memory devices have been extensively applied to personal computers, mobile phones, internet, and so forth. These electronic products have become, little by little, indispensable to human life.
  • Owing to size reduction of semiconductor devices, the industry is facing a number of challenges, such as power consumption arisen from current leakage through DRAM, excessive area accounted by SRAM, high voltage requirement for performing reading/writing function in flash memory, and so on. Accordingly, it is urgent to develop new memory devices possessing advantages such as high density, non-volatilization, high-speed reading/writing capacity, unlimited numbers of reading/writing, low operational voltage, low power consumption, compatibility with current CMOS processes, and so forth.
  • Among the newly developed memory devices, nano-dots non-volatile memory devices at present draw a great attention. Nano-dots non-volatile memory device includes a charge storage layers having a great number of nano-dots form therein, each of which serves as an independent charge storage center. Hence, even if a tunneling oxide layer includes pathways for leakage currents, nano-dots non-volatile memory still has superior charge retention capability. Despite the shrink in size, the nano-dots non-volatile memory is well characterized in storing charges into nano-dots layers so as to perform a charge storage function of the memory. Nowadays, silicon nanocrystal dots, germanium nanocrystal dots, or metal nano-dots dielectric layer serving as a charge storage layer to instead of the traditional silicon nitride charge storage layer are studied.
    • SUMMARY OF THE INVENTION
  • The present invention is to provide a dielectric piece including metal compound dots to store charges.
  • One embodiment of the present invention is to provide a method of fabricating a dielectric piece including metal compound dots. A stack layer including a metal nitride layer and an energy barrier layer is formed over a substrate. Afterward, a treatment process is performed to transform the metal nitride layer into a plurality of crystalline metal compound dots distributed in the energy barrier layer.
  • One embodiment of the present invention is to provide a method of fabricating a dielectric piece including metal compound dots. A stack layer including a metal nitride layer and an energy barrier layer is formed over a substrate. Afterward, an annealing process is performed to transform the metal compound layer in the stack layer into a plurality of crystalline metal compound dots distributed in the energy barrier layer.
  • One embodiment of the invention is to provide a dielectric piece. The dielectric piece includes an energy barrier layer and a plurality of crystalline metal compound dots distributed in the energy barrier layer. The material of the energy barrier layer is different from that of the crystalline metal compound dots.
  • The method of fabricating the dielectric piece including metal compound dots in accordance with the present invention is simple, and can be used for mass production of semiconductors devices.
  • Due to its capability of retaining charges, the dielectric piece of the present invention meets the requirements of semiconductor devices in this and the next generation so as to be applied to complementary metal oxide semiconductors (CMOS), non-volatile memory devices, or capacitors as inter-gate dielectric layers, charge storage layers, or dielectric layers of capacitors. Various specific embodiments of the present invention are disclosed below, illustrating examples of various possible implementations of the concepts of the present invention. The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A through 1B are schematic cross-sectional views showing a method of fabricating a dielectric piece including metal compound dots according to one embodiment of the present invention.
  • FIGS. 2A through 2B are schematic cross-sectional views showing a method for fabricating the dielectric piece including metal compound dots according to another embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional diagram showing the dielectric piece according to an embodiment of the present invention.
  • FIG. 4 schematically illustrates an application of the dielectric piece of the present invention to a CMOS.
  • FIG. 5 schematically illustrates an application of the dielectric piece of the present invention to a flash memory device.
  • FIG. 6 schematically illustrates an application of the dielectric piece of the present invention to a flash memory device.
  • FIG. 7 schematically illustrates an application of the dielectric piece of the present invention to a capacitor.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A method of fabricating a dielectric piece includes metal compound dots is illustrated in the following embodiments. A stack layer including an energy barrier layer and a metal nitride layer or a metal oxide layer is formed over a substrate. Afterward, a process is performed to transform the metal nitride layer or the metal oxide layer in the stack layer into a plurality of crystalline metal compound dots distributed in the energy barrier layer.
  • The following takes several embodiments to describe the present invention, but not limited to.
    • First Embodiment
  • FIGS. 1A through 1B are schematic cross-sectional views showing a method of fabricating a dielectric piece including metal compound dots according to one embodiment of the present invention.
  • Referring to FIG. 1A, a stack layer 102 is formed over a substrate 100. The stack layer 102 includes a metal nitride layer 104 and an energy barrier layer 106. The stack layer 102 shown in the FIG. 1A includes two metal nitride layers 104 and two energy barrier layers 106 alternately. The metal nitride layers 104 and the energy barrier layers 106 are alternately stacked. In one embodiment of the present invention, the stack layer 102 includes one metal nitride layer 104 sandwiched in between two energy barrier layers 106, for example. Moreover, the stack layer 102 in another embodiment of the present invention includes one energy barrier layer 106 sandwiched in between two metal nitride layers 104. The material of the metal nitride layer 104 includes refractory metal nitride, such as titanium nitride, zirconium nitride, or hafnium nitride, which can be formed through an atomic layer chemical vapor deposition (ALD) process. The thickness of the metal nitride layer 104 is determined in accordance with the requirements of design. For example, in order to form the metal compound nanocrystal dots, the thickness of the metal nitride layer 104 is less than or equal to 10 angstroms. In one embodiment of the present invention, the thickness of the metal nitride layer 104 is approximately 3-6 angstroms. The material of the energy barrier 106 is different from that of the crystalline metal compound dots transformed from the metal nitride layer 104. While applied to semiconductor devices, the selection of the material of the energy barrier 106 can consider a material whose conductive band and valence band are relative to those of semiconductor, such as silicon. Mostly, the conductive band the energy barrier 106 is 1 eV higher than that of semiconductors, while the valence band the energy barrier 106 is 1 eV lower than that of semiconductors. Thus, the potential energy barrier can be higher enough to prevent electrons or holes passing through the energy barrier 106, which can achieve insulation properties. The material of the energy barrier 106 can be selected from a group consisting of Al2O3, Ta2O5, BaO, ZrO2, LaAlO3, La2O3, SrO, Y2O3, Si3N4, SixNy, HfSiOx, ZrSiOx, MgO, SiOx, and SiO2, and combinations thereof. The thickness of the energy barrier layer 106 is determined in accordance with the requirements of design. In one embodiment of the present invention, the thickness of the energy barrier 106 is about 5-20 angstroms, for example.
  • Afterward, referring to FIG. 1B, a process is performed to transform the metal nitride layer 104 in the stack layer 102 into a plurality of crystalline metal compound dots 108 distributed in the energy barrier layer 106. The crystalline metal compound dots 108 are, for example, crystalline metal oxide dots, such as crystalline titanium oxide dots, crystalline zirconium oxide dots, or crystalline hafnium oxide dots. In one embodiment of the present invention, the process is to perform an annealing operation in oxygen-free ambiance, such as nitrogen, argon, hydrogen, or ammonia ambiance, to transform the metal nitride layer 104 in the stack layer 102 into a plurality of metal nitride dots distributed in the energy barrier layer 106. Afterward, in oxygen ambiance, the metal nitride dots are transformed into a plurality of crystalline metal oxide dots 108. In another embodiment of the present invention, the treatment process includes an oxidation annealing operation in air, oxygen, nitric oxide, or nitrogen dioxide ambiance, for example, to directly transform the metal nitride layer 104 into crystalline metal oxide dots 108. In another embodiment of the present invention, the crystalline metal compound dots 108 are crystalline metal oxide dots which are made during the conveying process after the stack layer 102 is formed. The stack layer 102 may be exposed to the oxygen in the air during the conveying process. The oxygen carried by the stack layer 102 can directly transforms the metal nitride layer 104 into the crystalline metal oxide dots 108, though the annealing operation is in an oxygen-free or a micro-oxygen ambiance.
    • Second Embodiment
  • FIGS. 2A through 2C are schematic cross-sectional views showing a method of fabricating the dielectric piece including metal compound dots according to another embodiment of the present invention.
  • Referring to FIG. 2A, a stack layer 202 is formed over a substrate 200. The stack layer 202 includes a metal compound layer 204 and an energy barrier layer 206. The stack layer 202 shown in the FIG. 2A includes two metal compound layers 204 and two energy barrier layers 206. The metal compound layers 204 and the energy barrier layers 206 are alternately stacked. In one embodiment of the present invention, the stack layer 202 includes one metal compound layer 204 sandwiched in between two energy barrier layers 206. Moreover, the stack layer 202 in another embodiment of the present invention includes one energy barrier layer 206 sandwiched in between two metal compound layers 204. The material of the metal compound layer 204 includes a refractory metal oxide, such as titanium oxide, zirconium oxide, or hafnium oxide. The material is formed through an atomic layer chemical vapor deposition (ALD) process. The thickness of the metal compound layer 204 is determined in accordance with the requirements of design. For example, in order to form metal compound nano-dots, the thickness of the metal compound layer 204 is less than or equal to 10 angstroms. In one embodiment of the present invention, the thickness of the metal compound layer 204 is about 3 angstroms. The material of the energy barrier 206, different from that of the metal compound layer 204, is selected from a group consisting of Al2O3, Ta2O5, BaO, ZrO2, LaAlO3, La2O3, SrO, Y2O3, Si3Ny, SixNy, HfSiOx, ZrSiOx, MgO, SiOx, and SiO2, and combinations thereof. The thickness of the energy barrier layer 206 is determined in accordance with the requirements of design. In one embodiment of the present invention, the thickness of each energy barrier layer 206 is about 5-20 angstroms, for example.
  • Afterward, referring to FIG. 2B, a process is performed to transform the metal compound layer 204 in the stack layer 202 into a plurality of crystalline metal compound dots 208 distributed in the energy barrier layer 206. The crystalline metal compound dots 208 are, for example, refractory metal compound dots, such as crystalline titanium oxide dots, crystalline zirconium oxide dots, or crystalline hafnium oxide dots. In one embodiment of the present invention, the process is to perform an annealing operation in oxygen-free ambiance such as a nitrogen, argon, hydrogen, or ammonia ambiance to transform the metal compound layer in the stack layer 202 into a plurality of crystalline metal compound dots 208 distributed in the energy barrier layer 206. In another embodiment of the present invention, the process includes an oxidation annealing operation in an oxygen, nitric oxide, or nitrogen dioxide ambiance, for example, to transform the metal nitride layer 204 into the crystalline metal oxide dots 208.
  • Referring to FIG. 3, a dielectric piece 300 can be formed through the aforesaid methods. The dielectric piece 300 includes an energy barrier 306 and a plurality of crystalline metal compound dots 308 distributed in the energy barrier 306. The crystalline metal compound dots 308 include crystalline titanium oxide dots, crystalline zirconium oxide dots, or crystalline hafnium oxide dots. The material of the energy barrier 306, different from that of the crystalline metal compound dots 308, is selected from a group consisting of Al2O3, Ta2O5, BaO, ZrO2, LaAlO3, La2O3, SrO, Y2O3, Si3N4, SixNy, HfSiOx, ZrSiOx, MgO, SiOx, and SiO2, and combinations thereof. The crystalline metal compound dots 308 in the dielectric piece 300 can be as small as nano-dots and be limited within the energy barrier layer 306. Accordingly, the charges in the dielectric piece 300 are well retained. This dielectric piece can be extensively applied to fabricate integrated circuits.
  • The dielectric piece of the present invention can also be applied to fabricate semiconductor devices. For example, as shown in FIG. 4, the dielectric piece of the present invention can be applied to a CMOS 402 as a gate dielectric layer 406 of a gate structure 404. The dielectric piece of the present invention can be applied to non-volatile memory devices. Referring to FIG. 5, for example, the dielectric piece of the present invention can be applied to a flash memory device 501 as a replacement of a floating gate 504 for charge storage. Moreover, referring to FIG. 6, the dielectric piece can be applied to a silicon nitride read-only-memory device 602 as a charge storage layer 604 between a control gate 606 and a substrate 600, replacing traditional oxide/nitride/oxide (ONO) layer. Furthermore, referring to FIG. 7, the dielectric piece can as well be applied to a capacitor 702 as a dielectric material 706 between two electrodes 704 and 708. In application, the dielectric piece can certainly be utilized alone or together with other dielectric materials.
  • The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.

Claims (5)

1. A dielectric piece, comprising:
an energy barrier layer; and
a plurality of crystalline metal compound dots distributed in the energy barrier layer, with the material of the crystalline metal compound dots being different from that of the energy barrier layer.
2. The dielectric piece of claim 1, wherein the crystalline metal compound dots comprises crystalline titanium oxide dots, crystalline zirconium oxide dots, or crystalline hafnium oxide dots.
3. The dielectric piece of claim 1, wherein the crystalline metal compound dots are nano-dots.
4. The dielectric piece of claim 1, wherein the material of the energy barrier layer is selected from a group consisting of Al2O3, Ta2O5, BaO, ZrO2, LaAlO3, La2O3, SrO, Y2O3, Si3N4, SixNy, HfSiOx, ZrSiOx, MgO, SiOx and SiO2, and the combinations thereof.
5. The dielectric piece of claim 1, wherein the dielectric piece serves as a inter-gate dielectric layer, a charge storage layer or a dielectric material in a capacitor.
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