US20090085667A1 - Inverted doherty amplifier with increased off-state impedence - Google Patents
Inverted doherty amplifier with increased off-state impedence Download PDFInfo
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- US20090085667A1 US20090085667A1 US11/863,429 US86342907A US2009085667A1 US 20090085667 A1 US20090085667 A1 US 20090085667A1 US 86342907 A US86342907 A US 86342907A US 2009085667 A1 US2009085667 A1 US 2009085667A1
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- phase delay
- impedance value
- peaking
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Definitions
- the technical field relates generally to power amplifiers and more particularly to an inverted Doherty amplifier configuration providing increased off-state impedance.
- Some electronic systems such as base transceiver stations (“BTS”) are designed using a Doherty type linear amplifier configuration for increased linearity and efficiency in a linear amplifier topology.
- the Doherty amplifier uses at least two amplifier paths, a carrier amplifier path and a peaking amplifier path, and combines the output of these two paths at a summing junction (or node) in such a way as to provide for the increased linearity and efficiency.
- a carrier amplifier receives an undelayed input signal for amplification
- a peaking amplifier receives a phase delayed input signal for amplification.
- electronic systems such as BTSs and mobile devices are designed using a so called “inverted” Doherty amplifier configuration. In this Doherty type configuration, the carrier amplifier receives the delayed input signal for amplification, and the peaking amplifier receives the undelayed input signal for amplification.
- peaking amplifier off-state impedance is the impedance looking back into the peaking amplifier, including the output match, while the peaking amplifier is in an OFF state.
- Peaking amplifier off-state impedance should be relatively high so as not to load the carrier amplifier during a low RF IN drive condition when the peaking amplifier is off.
- Known Doherty type amplifier topologies maintain a high enough peaking amplifier off-state impedance for some applications, but not for others.
- FIG. 1 is a block diagram of a Doherty type amplifier in accordance with some embodiments.
- an inverted Doherty amplifier configuration provides for improved peaking amplifier off-state impedance over known conventional and inverted Doherty amplifier configurations.
- a phase delay element that is coupled in the peaking amplifier path between an output match network and a summing node provides a degree of phase delay and has a designed characteristic impedance value that is larger than the impedance value of a load coupled to the summing node. Designing the amplifier in this manner with the phase delay element having a characteristic impedance that is larger than the load impedance effectively increases the off-state impedance of the peaking amplifier.
- This novel inverted Doherty amplifier configuration provides for improved linearity and efficiency by decreasing the load on the carrier amplifier when the peaking amplifier is in an OFF state. Another advantage is an improved phase difference between the peaking amplifier and the carrier amplifier, whereby, a wider bandwidth is achieved. Yet another advantage is that this novel Doherty configuration enables further tuning optimization because the load line for the peaking and carrier amplifiers can be optimized.
- Inverted Doherty amplifier 100 may be used as part of a BTS or a mobile device, for example.
- Inverted Doherty amplifier 100 comprises a splitter network 102 that receives an input signal (RF IN ) and provides therefrom a phase delayed signal and an undelayed signal, respectively, to a first amplifier path (the top path) and a second amplifier path (the bottom path).
- the first amplifier path comprises an input match network 104 , an amplifier network 106 and an output match network 108 .
- the second amplifier path comprises an input match network 116 , an amplifier network 118 and an output match network 120 .
- the first and second amplifiers paths each amplify their respective signals, wherein the amplified signals are combined into a combined signal by a combiner network, which includes an impedance transforming element 112 and a phase delay element 122 .
- the combined signal is combined at a summing node 110 and is provided via the impedance transforming element 112 to a load 114 having a real impedance of Z L .
- amplifier network 100 receives RF IN (typically a linear modulated radio frequency (RF) signal) at the splitter 102 , which splits the input signal into at least two parts that are provided to separate paths, such as a carrier amplifier path (the top path) and a peaking amplifier path (the bottom path).
- the splitter is a hybrid coupler that phase shifts one of the resulting two signals by ⁇ 90 degrees (termed herein a delayed signal) with respect to the other signal (termed herein an undelayed signal).
- the splitter network 102 comprises a single piece of hardware that provides for all of the necessary phase delay at the input of the Doherty amplifier 100 (i.e., prior to amplifier networks 106 , 118 ).
- the splitter network comprises a splitter device that provides a portion of the phase delay and one or more separate phase delay elements in the first and/or second amplifier paths before the amplifier networks 106 , 118 that provide the remaining portion of phase delay required at the input. It should be noted that in any such embodiment, the total phase delay at the input is substantially equal to the phase delay provide by the phase delay element 122 .
- Each amplifier network 106 , 118 comprises a single amplifier, which in an embodiment is a laterally diffused metal oxide field effect transistor (or LDMOS FET as is referred to in the art). In other embodiments, a different type of transistor can be used and/or two or more suitable transistors in cascade may be used depending on the particular implementation and design requirements.
- Amplifier 106 operates in a linear mode and conducts between 180° to 360° of the input signal, and amplifier 118 conducts when the input signal is above a pre-selected threshold.
- amplifier 106 is referred to as a carrier amplifier and amplifier 118 is referred to as a peaking amplifier.
- the outputs of the amplifiers 106 , 118 are provided, respectively, to output match networks 108 , 120 .
- the combiner network is used to combine the outputs of the carrier amplifier 106 and the peaking amplifier 118 , and includes the impedance transforming element 112 and phase delay element 122 , which in this embodiment are each quarter wavelength (or “quarter wave”) elements.
- the quarter wave elements 112 and 122 are arranged such that the output of the carrier amplifier 106 is provided to the summing node 110 , and the output of the peaking amplifier 118 is first phase shifted and then provided to the summing node 110 to generate a summed signal from the two amplifier paths.
- the summed signal is provided to the load 114 through the quarter wavelength element 112 .
- the quarter wave elements are substantially quarter wave elements, but not necessarily an exact quarter wave element.
- variations in the processing of the quarter wave element may lead to phase shifting of signals amount that is not exactly the amount desired.
- the function of any quarter wave elements may be implemented with lumped components such as inductors and capacitors instead of with transmission lines as in this described embodiment.
- the quarter wave element 112 is disposed between the summing node and the load.
- This quarter wave element 112 has a characteristic impedance lower than the real impedance (resistance) of the load of R L .
- the characteristic impedance e.g., of a transmission line
- the phase delay element 122 has a dual role. First, it provides a high impedance path when the peaking amplifier is not conducting so as not to load the summing node and carrier amplifier while it is off.
- phase correction (of substantially 90 degrees) for the signal in the peaking amplifier path such that, at the summing node, the signal from the carrier amplifier path and the peaking amplifier path(s) are substantially in phase and can, thereby, be properly combined.
- the amplifier network will be used over a limited frequency range, there may be small phase differences, but not such that the substantial benefit of the invention is lost.
- the quarter wavelength element 122 has a characteristic impedance that is substantially equal to the real impedance of the load, in order to achieve various stated benefits.
- the phase delay element 122 is designed to have a characteristic impedance Z O that is greater than Z L in order to increase the peaking amplifier off-state impedance.
- output match network 120 is also configured and optimized based on the designed characteristic impedance of the phase delay element 122 . This further eliminates the need for additional transmission line elements in either the carrier amplifier path or the peaking amplifier path.
- Z L be substantially 50 Ohms.
- Z O can be designed to be substantially 75 Ohms.
- the peaking amplifier off-state impedance is shown to be doubled compared to when the characteristic impedance of phase delay element 122 is substantially equal to the impedance of the load.
- phase differential between the carrier and peaking amplifier paths was improved during the peaking amplifier ON state or high RF IN drive condition, which led to a broader Doherty design over frequency (i.e., a wider bandwidth of operation of the amplifier network).
- a further added benefit is that modifying the delay line impedance provides an additional degree of freedom in tuning in the increasingly complex Doherty amplifier designs.
- phase delay element 122 could provide a phase delay of greater than or less than a 90 degree phase delay to generate the required peaking amplifier off-state impedance.
- additional phase delay elements or delay lines can be placed before the carrier and/or peaking amplifies to achieve optimal phase balance in the Doherty architecture. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings.
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Abstract
Description
- The technical field relates generally to power amplifiers and more particularly to an inverted Doherty amplifier configuration providing increased off-state impedance.
- Some electronic systems such as base transceiver stations (“BTS”) are designed using a Doherty type linear amplifier configuration for increased linearity and efficiency in a linear amplifier topology. In general, the Doherty amplifier uses at least two amplifier paths, a carrier amplifier path and a peaking amplifier path, and combines the output of these two paths at a summing junction (or node) in such a way as to provide for the increased linearity and efficiency. In the traditional Doherty amplifier topology, a carrier amplifier receives an undelayed input signal for amplification, and a peaking amplifier receives a phase delayed input signal for amplification. More recently, electronic systems such as BTSs and mobile devices are designed using a so called “inverted” Doherty amplifier configuration. In this Doherty type configuration, the carrier amplifier receives the delayed input signal for amplification, and the peaking amplifier receives the undelayed input signal for amplification.
- One parameter of a Doherty type amplifier that can affect linearity and operational efficiency of the amplifier is peaking amplifier off-state impedance. More particularly, the peaking amplifier off-state impedance is the impedance looking back into the peaking amplifier, including the output match, while the peaking amplifier is in an OFF state. Peaking amplifier off-state impedance should be relatively high so as not to load the carrier amplifier during a low RFIN drive condition when the peaking amplifier is off. Known Doherty type amplifier topologies maintain a high enough peaking amplifier off-state impedance for some applications, but not for others. For example, due to a lower than desired peaking amplifier off-state impedance, efficiency and linearity are compromised for applications utilizing a Doherty amplifier configuration that includes laterally diffused metal oxide field effect transistors as the carrier and peaking amplifiers and that operate at higher frequencies (e.g., around 2 GHz).
- Thus, there exists a need for a Doherty type linear amplifier configuration that addresses at least some of the shortcomings of some known Doherty type amplifier configurations.
- The accompanying figure, which together with the detailed description below are incorporated in and form part of the specification and serve to further illustrate various embodiments of concepts that include the claimed invention, and to explain various principles and advantages of those embodiments.
-
FIG. 1 is a block diagram of a Doherty type amplifier in accordance with some embodiments. - Skilled artisans will appreciate that elements in the figure are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help improve understanding of various embodiments. In addition, the description and drawing do not necessarily require the order illustrated. Apparatus and method components have been represented where appropriate by conventional symbols in the drawing, showing only those specific details that are pertinent to understanding the various embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Thus, it will be appreciated that for simplicity and clarity of illustration, common and well-understood elements that are useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of these various embodiments.
- Generally speaking, pursuant to the various embodiments, an inverted Doherty amplifier configuration provides for improved peaking amplifier off-state impedance over known conventional and inverted Doherty amplifier configurations. In an embodiment, a phase delay element that is coupled in the peaking amplifier path between an output match network and a summing node provides a degree of phase delay and has a designed characteristic impedance value that is larger than the impedance value of a load coupled to the summing node. Designing the amplifier in this manner with the phase delay element having a characteristic impedance that is larger than the load impedance effectively increases the off-state impedance of the peaking amplifier.
- This novel inverted Doherty amplifier configuration provides for improved linearity and efficiency by decreasing the load on the carrier amplifier when the peaking amplifier is in an OFF state. Another advantage is an improved phase difference between the peaking amplifier and the carrier amplifier, whereby, a wider bandwidth is achieved. Yet another advantage is that this novel Doherty configuration enables further tuning optimization because the load line for the peaking and carrier amplifiers can be optimized. Those skilled in the art will realize that the above recognized advantages and other advantages described herein are merely illustrative and are not meant to be a complete rendering of all of the advantages of the various embodiments.
- Referring now to
FIG. 1 , there is shown a block schematic diagram of an inverted Dohertyamplifier 100 in accordance with some embodiments.Amplifier 100 may be used as part of a BTS or a mobile device, for example. Inverted Dohertyamplifier 100 comprises asplitter network 102 that receives an input signal (RFIN) and provides therefrom a phase delayed signal and an undelayed signal, respectively, to a first amplifier path (the top path) and a second amplifier path (the bottom path). The first amplifier path comprises aninput match network 104, anamplifier network 106 and anoutput match network 108. The second amplifier path comprises aninput match network 116, anamplifier network 118 and anoutput match network 120. The first and second amplifiers paths each amplify their respective signals, wherein the amplified signals are combined into a combined signal by a combiner network, which includes animpedance transforming element 112 and aphase delay element 122. The combined signal is combined at asumming node 110 and is provided via theimpedance transforming element 112 to aload 114 having a real impedance of ZL. - In operation in an embodiment,
amplifier network 100 receives RFIN (typically a linear modulated radio frequency (RF) signal) at thesplitter 102, which splits the input signal into at least two parts that are provided to separate paths, such as a carrier amplifier path (the top path) and a peaking amplifier path (the bottom path). In an embodiment, the splitter is a hybrid coupler that phase shifts one of the resulting two signals by −90 degrees (termed herein a delayed signal) with respect to the other signal (termed herein an undelayed signal). In this embodiment, thesplitter network 102 comprises a single piece of hardware that provides for all of the necessary phase delay at the input of the Doherty amplifier 100 (i.e., prior toamplifier networks 106, 118). However, other embodiments are envisioned and contemplated within the scope of the teachings herein, wherein the splitter network comprises a splitter device that provides a portion of the phase delay and one or more separate phase delay elements in the first and/or second amplifier paths before theamplifier networks phase delay element 122. - The signals are provided, respectively, to the
input match networks amplifier networks amplifier network Amplifier 106 operates in a linear mode and conducts between 180° to 360° of the input signal, andamplifier 118 conducts when the input signal is above a pre-selected threshold. In the vernacular of the art,amplifier 106 is referred to as a carrier amplifier andamplifier 118 is referred to as a peaking amplifier. The outputs of theamplifiers match networks - The combiner network is used to combine the outputs of the
carrier amplifier 106 and thepeaking amplifier 118, and includes theimpedance transforming element 112 andphase delay element 122, which in this embodiment are each quarter wavelength (or “quarter wave”) elements. Thequarter wave elements carrier amplifier 106 is provided to thesumming node 110, and the output of thepeaking amplifier 118 is first phase shifted and then provided to thesumming node 110 to generate a summed signal from the two amplifier paths. - Finally, the summed signal is provided to the
load 114 through thequarter wavelength element 112. It will be appreciated by those skilled in the art that, although referred to as quarter wave elements, since it is intended that the amplifier system amplify signals over a given range of frequencies, the quarter wave elements are substantially quarter wave elements, but not necessarily an exact quarter wave element. Moreover, variations in the processing of the quarter wave element may lead to phase shifting of signals amount that is not exactly the amount desired. Furthermore, it will be appreciated by those skilled in the art that the function of any quarter wave elements may be implemented with lumped components such as inductors and capacitors instead of with transmission lines as in this described embodiment. - As in the prior art, the
quarter wave element 112 is disposed between the summing node and the load. Thisquarter wave element 112 has a characteristic impedance lower than the real impedance (resistance) of the load of RL. The characteristic impedance (e.g., of a transmission line) is the ratio of amplitudes of a single pair of voltage and current waves propagating along the line in the absence of reflections. Thephase delay element 122 has a dual role. First, it provides a high impedance path when the peaking amplifier is not conducting so as not to load the summing node and carrier amplifier while it is off. Second, it provides phase correction (of substantially 90 degrees) for the signal in the peaking amplifier path such that, at the summing node, the signal from the carrier amplifier path and the peaking amplifier path(s) are substantially in phase and can, thereby, be properly combined. Practically speaking, since it is contemplated that the amplifier network will be used over a limited frequency range, there may be small phase differences, but not such that the substantial benefit of the invention is lost. - It is taught in the prior art that the
quarter wavelength element 122 has a characteristic impedance that is substantially equal to the real impedance of the load, in order to achieve various stated benefits. However, in accordance with the teachings herein (and contrary to conventional Doherty amplifier configurations), thephase delay element 122 is designed to have a characteristic impedance ZO that is greater than ZL in order to increase the peaking amplifier off-state impedance. In an embodiment, to facilitate peaking amplifier off-state impedance optimization using the teachings herein,output match network 120 is also configured and optimized based on the designed characteristic impedance of thephase delay element 122. This further eliminates the need for additional transmission line elements in either the carrier amplifier path or the peaking amplifier path. - In one illustrative implementation, let ZL be substantially 50 Ohms. In such a case, it has been found that for a device operating at around 2.0 GHz, ZO can be designed to be substantially 75 Ohms. For such a scenario, the peaking amplifier off-state impedance is shown to be doubled compared to when the characteristic impedance of
phase delay element 122 is substantially equal to the impedance of the load. Moreover, for the condition as described above of ZO>ZL, substantial efficiency and linearity improvement can be realized over the Doherty configuration having a condition of ZO=ZL. Another benefit that was evident but not expected was that the phase differential between the carrier and peaking amplifier paths was improved during the peaking amplifier ON state or high RFIN drive condition, which led to a broader Doherty design over frequency (i.e., a wider bandwidth of operation of the amplifier network). A further added benefit is that modifying the delay line impedance provides an additional degree of freedom in tuning in the increasingly complex Doherty amplifier designs. - In the foregoing specification, specific embodiments have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. For example, the
phase delay element 122 could provide a phase delay of greater than or less than a 90 degree phase delay to generate the required peaking amplifier off-state impedance. For such embodiments, additional phase delay elements or delay lines can be placed before the carrier and/or peaking amplifies to achieve optimal phase balance in the Doherty architecture. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued. - Moreover in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “has”, “having,” “includes”, “including,” “contains”, “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a”, “has . . . a”, “includes . . . a”, “contains . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms “a” and “an” are defined as one or more unless explicitly stated otherwise herein. The terms “substantially”, “essentially”, “approximately”, “about” or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non-limiting embodiment the term is defined to be within 10%, in another embodiment within 5%, in another embodiment within 1% and in another embodiment within 0.5%. Moreover, substantially is defined as a range based on manufacturing variations and variations over time and temperature. The term “coupled” as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is “configured” in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
- The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
Claims (9)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US11/863,429 US7521995B1 (en) | 2007-09-28 | 2007-09-28 | Inverted doherty amplifier with increased off-state impedence |
PCT/US2008/075744 WO2009045686A2 (en) | 2007-09-28 | 2008-09-10 | Inverted doherty amplifier with increased off-state impedence |
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US11/863,429 US7521995B1 (en) | 2007-09-28 | 2007-09-28 | Inverted doherty amplifier with increased off-state impedence |
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US20090085667A1 true US20090085667A1 (en) | 2009-04-02 |
US7521995B1 US7521995B1 (en) | 2009-04-21 |
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US11/863,429 Expired - Fee Related US7521995B1 (en) | 2007-09-28 | 2007-09-28 | Inverted doherty amplifier with increased off-state impedence |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012146016A1 (en) * | 2011-04-29 | 2012-11-01 | 中兴通讯股份有限公司 | Power amplifier device and power amplifier circuit |
WO2013048936A1 (en) * | 2011-09-27 | 2013-04-04 | Harris Corporation | Amplifying system |
US8717099B2 (en) | 2012-03-16 | 2014-05-06 | Infineon Technologies Ag | Wideband doherty amplifier circuit with peaking impedance absorption |
WO2015085742A1 (en) * | 2013-12-13 | 2015-06-18 | 中兴通讯股份有限公司 | Radio-frequency power amplifier, base station, and impedance adjustment method |
US9948246B1 (en) * | 2016-10-18 | 2018-04-17 | Mitsubishi Electric Research Laboratories, Inc. | Impedance flattening network for high efficiency wideband doherty power amplifier |
US10491165B2 (en) | 2018-03-12 | 2019-11-26 | Psemi Corporation | Doherty amplifier with adjustable alpha factor |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101678132B1 (en) * | 2009-06-11 | 2016-11-23 | 사브 에이비 | Distributed power amplifier with active matching |
US9209511B2 (en) | 2011-10-14 | 2015-12-08 | Anaren, Inc. | Doherty power amplifier network |
US8975955B2 (en) * | 2012-12-11 | 2015-03-10 | Alcatel Lucent | Analysis of Doherty amplifiers |
US9071202B2 (en) | 2013-10-18 | 2015-06-30 | Alcatel Lucent | Doherty amplifier with peak branch RF conditioning |
US9252722B2 (en) | 2013-12-20 | 2016-02-02 | Telefonaktiebolaget L M Ericsson (Publ) | Enhanced and versatile N-way doherty power amplifier |
US9531328B2 (en) | 2014-12-16 | 2016-12-27 | Nxp Usa, Inc. | Amplifiers with a short phase path, packaged RF devices for use therein, and methods of manufacture thereof |
US9748902B2 (en) | 2015-05-15 | 2017-08-29 | Nxp Usa, Inc. | Phase correction in a Doherty power amplifier |
US9667199B1 (en) | 2016-06-09 | 2017-05-30 | Nxp Usa, Inc. | Doherty amplifiers with minimum phase output networks |
WO2019084911A1 (en) * | 2017-11-03 | 2019-05-09 | Telefonaktiebolaget Lm Ericsson (Publ) | Doherty power amplifier and radio frequency device comprising the same |
US11411540B2 (en) | 2017-12-19 | 2022-08-09 | Telefonaktiebolaget Lm Ericsson (Publ) | Power amplifier and radio frequency device comprising the same |
US11784610B2 (en) | 2020-03-03 | 2023-10-10 | Nxp Usa, Inc. | Doherty amplifier module with compact wideband impedance inverter |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5420541A (en) * | 1993-06-04 | 1995-05-30 | Raytheon Company | Microwave doherty amplifier |
US5568086A (en) * | 1995-05-25 | 1996-10-22 | Motorola, Inc. | Linear power amplifier for high efficiency multi-carrier performance |
US6262629B1 (en) * | 1999-07-06 | 2001-07-17 | Motorola, Inc. | High efficiency power amplifier having reduced output matching networks for use in portable devices |
US6320462B1 (en) * | 2000-04-12 | 2001-11-20 | Raytheon Company | Amplifier circuit |
US6791417B2 (en) * | 2002-01-28 | 2004-09-14 | Cree Microwave, Inc. | N-way RF power amplifier circuit with increased back-off capability and power added efficiency using selected phase lengths and output impedances |
US7345537B2 (en) * | 2002-09-20 | 2008-03-18 | Triquint Semiconductor, Inc. | Linear power amplifier with multiple output power levels |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100749870B1 (en) * | 2006-06-07 | 2007-08-17 | (주) 와이팜 | Doherty amplifier |
-
2007
- 2007-09-28 US US11/863,429 patent/US7521995B1/en not_active Expired - Fee Related
-
2008
- 2008-09-10 WO PCT/US2008/075744 patent/WO2009045686A2/en active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5420541A (en) * | 1993-06-04 | 1995-05-30 | Raytheon Company | Microwave doherty amplifier |
US5568086A (en) * | 1995-05-25 | 1996-10-22 | Motorola, Inc. | Linear power amplifier for high efficiency multi-carrier performance |
US6262629B1 (en) * | 1999-07-06 | 2001-07-17 | Motorola, Inc. | High efficiency power amplifier having reduced output matching networks for use in portable devices |
US6320462B1 (en) * | 2000-04-12 | 2001-11-20 | Raytheon Company | Amplifier circuit |
US6791417B2 (en) * | 2002-01-28 | 2004-09-14 | Cree Microwave, Inc. | N-way RF power amplifier circuit with increased back-off capability and power added efficiency using selected phase lengths and output impedances |
US7345537B2 (en) * | 2002-09-20 | 2008-03-18 | Triquint Semiconductor, Inc. | Linear power amplifier with multiple output power levels |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012146016A1 (en) * | 2011-04-29 | 2012-11-01 | 中兴通讯股份有限公司 | Power amplifier device and power amplifier circuit |
US8797099B2 (en) | 2011-04-29 | 2014-08-05 | Zte Corporation | Power amplifier device and power amplifier circuit thereof |
WO2013048936A1 (en) * | 2011-09-27 | 2013-04-04 | Harris Corporation | Amplifying system |
US8717099B2 (en) | 2012-03-16 | 2014-05-06 | Infineon Technologies Ag | Wideband doherty amplifier circuit with peaking impedance absorption |
WO2015085742A1 (en) * | 2013-12-13 | 2015-06-18 | 中兴通讯股份有限公司 | Radio-frequency power amplifier, base station, and impedance adjustment method |
US9948246B1 (en) * | 2016-10-18 | 2018-04-17 | Mitsubishi Electric Research Laboratories, Inc. | Impedance flattening network for high efficiency wideband doherty power amplifier |
US20180109229A1 (en) * | 2016-10-18 | 2018-04-19 | Mitsubishi Electric Research Laboratories, Inc. | Impedance Flattening Network for High Efficiency Wideband Doherty Power Amplifier |
US10491165B2 (en) | 2018-03-12 | 2019-11-26 | Psemi Corporation | Doherty amplifier with adjustable alpha factor |
US11190144B2 (en) | 2018-03-12 | 2021-11-30 | Psemi Corporation | Doherty amplifier with adjustable alpha factor |
Also Published As
Publication number | Publication date |
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WO2009045686A3 (en) | 2010-07-22 |
US7521995B1 (en) | 2009-04-21 |
WO2009045686A2 (en) | 2009-04-09 |
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