US20080237880A1 - Integrated circuit package system with protected conductive layers - Google Patents
Integrated circuit package system with protected conductive layers Download PDFInfo
- Publication number
- US20080237880A1 US20080237880A1 US11/694,907 US69490707A US2008237880A1 US 20080237880 A1 US20080237880 A1 US 20080237880A1 US 69490707 A US69490707 A US 69490707A US 2008237880 A1 US2008237880 A1 US 2008237880A1
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- conductive layer
- protection cover
- over
- layer
- forming
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Definitions
- the present invention relates generally to integrated circuit package system, and more particularly to integrated circuit package system having protected conductive layers.
- Modern consumer electronics such as smart phones, personal digital assistants, and location based services devices, as well as enterprise electronics, such as servers and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost.
- enterprise electronics such as servers and storage arrays
- analog circuitry integration and processing support the miniaturization trend, other problems arise from this integration.
- semiconductor or integrated circuit devices have pads exposed for connecting, such as wire bonding, to the package terminals, such as leads.
- analog circuitry integration or any additional device processing after the pad development damages the pad resulting in poor electrical contact, contact reliability, reduced yield, and increased cost.
- the present invention provides an integrated circuit package system including providing an integrated circuit die having a contact pad, forming a protection cover over the contact pad, forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover, developing a conductive layer over the passivation layer, and forming a pad opening in the protection cover for exposing the contact pad.
- FIG. 1 is a cross-sectional view of an integrated circuit package system in an embodiment of the present invention
- FIG. 2 is a cross-sectional view of an integrated circuit package system in an alternative embodiment of the present invention.
- FIG. 3 is a cross-sectional view of a wafer structure in forming the first conductive layer in an embodiment of the present invention
- FIG. 4 is the structure of FIG. 3 in forming the resistive layer
- FIG. 5 is the structure of FIG. 4 in forming the insulator layer
- FIG. 6 is the structure of FIG. 5 in forming the second conductive layer
- FIG. 7 is the structure of FIG. 6 in forming the first passivation layer
- FIG. 8 is the structure of FIG. 7 in forming the fourth conductive layer
- FIG. 9 is the structure of FIG. 8 in forming the second passivation layer
- FIG. 10 is the structure of FIG. 9 in forming the sixth conductive layer
- FIG. 11 is the structure of FIG. 10 in forming the first interconnect
- FIG. 12 is the structure of FIG. 11 in forming the second interconnect.
- FIG. 13 is a flow chart of an integrated circuit package system for manufacture of the integrated circuit package system in an embodiment of the present invention.
- the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation.
- the term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side”(as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
- the term “on” means there is direct contact among elements.
- processing as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure.
- system as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.
- FIG. 1 therein is shown a cross-sectional view of an integrated circuit package system 100 in an embodiment of the present invention.
- the cross-sectional view depicts an integrated circuit die 102 having contact pads 104 , a first circuit element 106 , a second circuit element 108 , and a third circuit element 110 provided thereover.
- the contact pads 104 may function as input/output (IO) pads for the integrated circuit die 102 .
- the first circuit element 106 is depicted as capacitor.
- the second circuit element 108 is depicted as a resistor.
- the third circuit element 110 is depicted as conductive trace or a redistribution trace.
- the contact pads 104 , the first circuit element 106 , the second circuit element 108 , and the third circuit element 110 are preferably over an active side 112 of the integrated circuit die 102 .
- the contact pads 104 may be preferably formed with a first conductive layer 114 , such as aluminum (Al), copper (Cu), gold (Au), or a metal alloy.
- the first conductive layer 114 is preferably not the first conducting layer of the semiconductor process used to manufacture the integrated circuit die 102 .
- the first conductive layer 114 may be the last conducting layer of the semiconductor process used to manufacture the integrated circuit die 102 .
- a protection cover 116 preferably partially covers the contact pads 104 and exposes the contact pads 104 through pad openings 118 .
- the protection cover 116 is preferably formed from a resistive layer 120 .
- the protection cover 116 shields the contact pads 104 from further corrosive processing, such as wet etching, and prevents galvanic corrosion of the contact pads 104 . Galvanic corrosion adversely affects the contact pads 104 causing pin holes.
- the resistive layer 120 may be formed by a number of high resistivity materials, such as nickel chromium (NiCr) or poly-silicon crystalline (poly-Si).
- the first circuit element 106 preferably includes the first conductive layer 114 , the resistive layer 120 , an insulator layer 122 , and a second conductive layer 124 .
- the insulator layer 122 is preferably a dielectric layer or film, such as silicon nitride (SiN), tantalum pentoxide (Ta 2 O 5 ), or hafnium oxide (HfO 2 ).
- the second conductive layer 124 is preferably aluminum (Al), copper (Cu), a metal alloy, or other conductive film.
- the first circuit element 106 preferably has the resistive layer 120 over the first conductive layer 114 which is over the integrated circuit die 102 .
- the insulator layer 122 partially covers the resistive layer 120 and the first conductive layer 114 of the first circuit element 106 and exposes the resistive layer 120 with an insulator opening 126 .
- the second conductive layer 124 is preferably patterned over the insulator layer 122 not over the insulator opening 126 and over the insulator opening 126 connecting with the resistive layer 120 .
- the second circuit element 108 preferably includes the resistive layer 120 , the insulator layer 122 , and the second conductive layer 124 .
- the second circuit element 108 preferably has the insulator layer 122 over the resistive layer 120 which is over the integrated circuit die 102 .
- the second conductive layer 124 is patterned over the resistive layer 120 not covered by the insulator layer 122 .
- the second conductive layer 124 is adjacent with and does not cover the insulator layer 122 .
- the third circuit element 110 preferably includes the second conductive layer 124 .
- the third circuit element 110 is shown not contacting the second circuit element 108 or the resistive layer 120 over the contact pads 104 . Also, the first circuit element 106 is shown not contacting the second circuit element 108 .
- a first passivation layer 128 such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), covers the active side 112 including the second circuit element 108 .
- the first passivation layer 128 partially covers the first circuit element 106 , the third circuit element 110 , and the contact pads 104 .
- the first passivation layer 128 also provides first openings 130 exposing the contact pads 104 , the second conductive layer 124 of the first circuit element 106 , and the third circuit element 1 10 .
- the first passivation layer 128 is used to protect the underlying devices, such as the first circuit element 106 and the second circuit element 108 , from penetration of mobile ions, moisture, transition metal (such as gold or silver), and other contaminations.
- a third conductive layer 132 is preferably patterned over the first passivation layer 128 .
- the third conductive layer 132 is preferably adjacent to and lining predetermined locations of the first openings 130 .
- the third conductive layer 132 lines the first openings 130 over the first circuit element 106 and the third circuit element 110 .
- the third conductive layer 132 is shown not over the contact pads 104 .
- the third conductive layer 132 also covers predetermined locations over the first passivation layer 128 not adjacent the first openings 130 .
- the third conductive layer 132 is shown not completely covering the first passivation layer 128 .
- the third conductive layer 132 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).
- a fourth conductive layer 134 is preferably patterned over the third conductive layer 132 .
- the fourth conductive layer 134 and the third conductive layer 132 may preferably provide a number of functions.
- the first openings 130 lined with the third conductive layer 132 provide electrical vias connecting the fourth conductive layer 134 with the first circuit element 106 and the third circuit element 110 .
- the fourth conductive layer 134 over the third circuit element 110 and between the contact pads 104 and the third circuit element 110 may form a fourth circuit element 136 , such as an inductor.
- the third conductive layer 132 and the fourth conductive layer 134 between the first circuit element 106 and the third circuit element 110 may function as redistribution layer.
- the first passivation layer 128 serves as a stress buffer or protective coat for the integrated circuit die 102 .
- the first passivation layer 128 also separates the fourth circuit element 136 from the substrate of the integrated circuit die 102 resulting in an increase in the Q value of the inductor.
- a second passivation layer 138 such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), partially covers the first passivation layer 128 and the fourth conductive layer 134 with a second opening 140 exposing a portion of the fourth conductive layer 134 over the second circuit element 108 .
- the second passivation layer 138 does not cover the pad openings 118 exposing the contact pads 104 .
- a fifth conductive layer 142 is preferably patterned over the second passivation layer 138 adjacent to and line the second opening 140 .
- the fifth conductive layer 142 is over the fourth conductive layer 134 exposed in the second opening 140 and not completely covering the second passivation layer 138 .
- the fifth conductive layer 142 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).
- a sixth conductive layer 144 is preferably patterned over the fifth conductive layer 142 .
- the sixth conductive layer 144 may be formed from a number of different materials, such as nickel vanadium (NiV), Cu, Cu/NiV, Au/Ni, or CrCu.
- the fifth conductive layer 142 and the sixth conductive layer 144 may preferably form the under bump metallization (UBM) for a first interconnect 146 , such as sold bump, gold bump, or copper pillar.
- a second interconnect 148 such as a bond wire or a conductive pillar, is preferably attached to the contact pads 104 through the pad openings 118 in the first passivation layer 128 and the resistive layer 120 .
- the integrated circuit package system 100 may connect to the next system level (not shown), such as a printed circuit board or another integrated circuit device (not shown). Alternatively, the integrated circuit package system 100 may be further packaged.
- the cross-sectional view depicts an integrated circuit die 202 having contact pads 204 , a first circuit element 206 , a second circuit element 208 , and a third circuit element 210 provided thereover.
- the contact pads 204 may function as input/output (IO) pads for the integrated circuit die 202 .
- the first circuit element 206 is depicted as capacitor.
- the second circuit element 208 is depicted as a resistor.
- the third circuit element 210 is depicted as conductive trace or a redistribution trace.
- the contact pads 204 , the first circuit element 206 , the second circuit element 208 , and the third circuit element 210 are preferably over an active side 212 of the integrated circuit die 202 .
- the contact pads 204 may be preferably formed with a first conductive layer 214 , such as aluminum (Al), copper (Cu), gold (Au), or a metal alloy.
- the first conductive layer 214 is preferably not the first conducting layer of the semiconductor process used to manufacture the integrated circuit die 202 .
- the first conductive layer 214 may be the last conducting layer of the semiconductor process used to manufacture the integrated circuit die 202 .
- a protection cover 216 preferably partially covers the contact pads 204 and exposes the contact pads 204 through pad openings 218 .
- the protection cover 216 is preferably formed from an insulator layer 222 .
- the protection cover 216 shields the contact pads 204 from further corrosive processing, such as wet etching, and prevents galvanic corrosion of the contact pads 204 . Galvanic corrosion adversely affects the contact pads 204 causing pin holes.
- the insulator layer 222 may be formed by a number of a dielectric layer or film, such as silicon nitride (SiN), tantalum pentoxide (Ta 2 O 5 ), or hafnium oxide (HfO 2 ).
- the first circuit element 206 preferably includes the first conductive layer 214 , a resistive layer 220 , the insulator layer 222 , and a second conductive layer 224 .
- the resistive layer 220 is preferably a high resistivity material, such as nickel chromium (NiCr) or poly-silicon crystalline (poly-Si).
- the second conductive layer 224 is preferably aluminum (Al), copper (Cu), a metal alloy, or other conductive film.
- the first circuit element 206 preferably has the resistive layer 220 over the first conductive layer 214 which is over the integrated circuit die 202 .
- the insulator layer 222 partially covers the resistive layer 220 and the first conductive layer 214 of the first circuit element 206 and exposes the resistive layer 220 with an insulator opening 226 .
- the second conductive layer 224 is preferably patterned over the insulator layer 222 not over the insulator opening 226 and over the insulator opening 226 connecting with the resistive layer 220 .
- the second circuit element 208 preferably includes the resistive layer 220 , the insulator layer 222 , and the second conductive layer 224 .
- the second circuit element 208 preferably has the insulator layer 222 over the resistive layer 220 which is over the integrated circuit die 202 .
- the second conductive layer 224 is patterned over the resistive layer 220 not covered by the insulator layer 222 .
- the second conductive layer 224 is adjacent with and does not cover the insulator layer 222 .
- the third circuit element 210 preferably includes the second conductive layer 224 .
- the third circuit element 210 is shown not contacting the second circuit element 208 or the resistive layer 220 over the contact pads 204 .
- the first circuit element 206 is shown not contacting the second circuit element 208 .
- a third conductive layer 232 is preferably patterned over the first passivation layer 228 .
- the third conductive layer 232 is preferably adjacent to and lining predetermined locations of the first openings 230 .
- the third conductive layer 232 lines the first openings 230 over the first circuit element 206 and the third circuit element 210 .
- the third conductive layer 232 is shown not over the contact pads 204 .
- the third conductive layer 232 also covers predetermined locations over the first passivation layer 228 not adjacent the first openings 230 .
- the third conductive layer 232 is shown not completely covering the first passivation layer 228 .
- the third conductive layer 232 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).
- a fourth conductive layer 234 is preferably patterned over the third conductive layer 232 .
- the fourth conductive layer 234 and the third conductive layer 232 may preferably provide a number of functions.
- the first openings 230 lined with the third conductive layer 232 provide electrical vias connecting the fourth conductive layer 234 with the first circuit element 206 and the third circuit element 210 .
- the fourth conductive layer 234 over the third circuit element 210 and between the contact pads 204 and the third circuit element 210 may form a fourth circuit element 236 , such as an inductor.
- the third conductive layer 232 and the fourth conductive layer 234 between the first circuit element 206 and the third circuit element 210 may function as redistribution layer.
- the first passivation layer 228 serves as a stress buffer or protective coat for the integrated circuit die 202 .
- the first passivation layer 228 also separates the fourth circuit element 236 from the substrate of the integrated circuit die 202 resulting in an increase in the Q value of the inductor.
- a fifth conductive layer 242 is preferably patterned over the second passivation layer 238 adjacent to and line the second opening 240 .
- the fifth conductive layer 242 is over the fourth conductive layer 234 exposed in the second opening 240 and not completely covering the second passivation layer 238 .
- the fifth conductive layer 242 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).
- a sixth conductive layer 244 is preferably patterned over the fifth conductive layer 242 .
- the sixth conductive layer 244 may be formed from a number of different materials, such as nickel vanadium (NiV), Cu, Cu/NiV, Au/Ni, or CrCu.
- the fifth conductive layer 242 and the sixth conductive layer 244 may preferably form the under bump metallization (UBM) for a first interconnect 246 , such as sold bump, gold bump, or copper pillar.
- a second interconnect 248 such as a bond wire or a conductive pillar, is preferably attached to the contact pads 204 through the pad openings 218 in the first passivation layer 228 and the resistive layer 220 .
- the integrated circuit package system 200 may connect to the next system level (not shown), such as a printed circuit board or another integrated circuit device (not shown). Alternatively, the integrated circuit package system 200 may be further packaged.
- FIG. 3 therein is shown a cross-sectional view of a wafer structure 300 in forming the first conductive layer 114 in an embodiment of the present invention.
- the wafer structure 300 includes a wafer 302 having the first conductive layer 114 formed thereover.
- the first conductive layer 114 is patterned over the active side 112 forming the contact pads 104 and one of the electrodes, such as the metal cap, for the first circuit element 106 of FIG. 1 .
- the first conductive layer 114 is applied over the wafer 302 with a number of different processes, such as depositing, sputtering, or plating.
- the first conductive layer 114 may be patterned using a number of different processes.
- the patterning process may preferably be a development process utilizing patterned photoresist structures (not shown) over the first conductive layer 114 and etching.
- the photoresist is preferably removed for further processing the wafer structure 300 .
- the resistive layer 120 is preferably deposited over the first conductive layer 114 and the wafer 302 .
- the resistive layer 120 may be patterned using a number of different processes, such as the development process described above utilizing patterned photoresist structures and etching.
- the patterning process forms the resistive layer 120 over the first conductive layer 114 of the first circuit element 106 of FIG. 1 , the resistive layer 120 of the second circuit element 108 of FIG. 1 over the wafer 302 , and the protection cover 116 over the contact pads 104 .
- the resistive layer 120 over the contact pads 104 preferably functions to protect the contact pads 104 from further development, such as wet etching, of the wafer 302 that would be damaging to the contact pads 104 .
- the insulator layer 122 is preferably deposited over the first conductive layer 114 , the resistive layer 120 , and the wafer 302 .
- the insulator layer 122 may be patterned using a number of different processes, such as the development process utilizing patterned photoresist structures and etching.
- the patterning process forms the insulator layer 122 covering the first conductive layer 114 and partially covering the resistive layer 120 of the first circuit element of FIG. 1 .
- the insulator opening 126 in the insulator layer 122 exposes the resistive layer 120 .
- the patterning process also forms the insulator layer 122 over and not completely covering the resistive layer 120 of the second circuit element 108 of FIG. 1 .
- the protection cover 116 protects the contact pads 104 during the development of the insulator layer 122 .
- the second conductive layer 124 is preferably deposited over the insulator layer 122 , the resistive layer 120 , the first conductive layer 114 , and the wafer 302 .
- the second conductive layer 124 may be patterned using a number a different processes, such as a development process utilizing patterned photoresist structures and etching.
- the patterning process of the second conductive layer 124 forms the first circuit element 106 , the second circuit element 108 , and the third circuit element 110 .
- the protection cover 116 exposed in the pad openings 118 of FIG. 1 protects the contact pads 104 during the development of the second conductive layer 124 .
- the first passivation layer 128 is preferably deposited over the second conductive layer 124 , the insulator layer 122 , the resistive layer 120 , the first conductive layer 114 , and the wafer 302 .
- the first passivation layer 128 may be applied with a number of different processes, such as spin coating.
- the first passivation layer 128 may be patterned using a number of different processes, such as dry etch, wet etch, or dry etch with laser ablation.
- the patterning process of the first passivation layer 128 exposes the second conductive layer 124 of the first circuit element 106 , the third circuit element 110 and the resistive layer 120 over the contact pads 104 .
- the patterning process forms the first openings 130 and the pad openings 118 in the first passivation layer 128 .
- the protection cover 116 exposed in the pad openings 118 protects the contact pads 104 during the development of the first passivation layer 128 .
- the third conductive layer 132 is preferably deposited over the first passivation layer 128 and the second conductive layer 124 exposed by the first openings 130 .
- the third conductive layer 132 is preferably patterned adjacent to and lining predetermined locations of the first openings 130 .
- the third conductive layer 132 lines the first openings 130 over the first circuit element 106 and the third circuit element 110 .
- the third conductive layer 132 is shown not over the contact pads 104 .
- the third conductive layer 132 may be applied over the first passivation layer 128 and the first openings 130 exposing the second conductive layer 124 with a number of different processes, such as depositing, sputtering, or plating.
- the third conductive layer 132 is also preferably patterned over predetermined locations over the first passivation layer 128 not adjacent the first openings 130 .
- the third conductive layer 132 is shown not completely covering the first passivation layer 128 .
- the third conductive layer 132 may be patterned using a number of different processes.
- the patterning process may preferably be a development process utilizing patterned photoresist structures (not shown) over the third conductive layer 132 and wet etching.
- the fourth conductive layer 134 may be applied over the third conductive layer 132 and the first passivation layer 128 and with a number of different processes, such as depositing, sputtering, or plating.
- the fourth conductive layer 134 is also preferably patterned over predetermined locations over the third conductive layer 132 .
- the protection cover 116 exposed in the pad openings 118 protects the contact pads 104 during the development of the third conductive layer 132 and the fourth conductive layer 134 .
- the second passivation layer 138 is preferably deposited over the fourth conductive layer 134 , the third conductive layer 132 , and the wafer 302 .
- the second passivation layer 138 may be applied with a number of different processes, such as depositing or spin coating.
- the second passivation layer 138 may be patterned using a number of different processes, such as dry etch, wet etch, or dry etch with laser ablation.
- the patterning process of the second passivation layer 138 exposes the fourth conductive layer 134 with the second opening 140 over the second circuit element 108 .
- the second passivation layer 138 may optionally partially fill the pad openings 118 or may not occupy the pad openings 118 .
- the protection cover 116 exposed in the pad openings 118 protects the contact pads 104 during the development of the second passivation layer 138 .
- the protection cover 116 exposed in the pad openings 118 may be optionally removed for connecting the second interconnect 148 of FIG. 1 , such as bond wire, to both the contact pads 104 and to the fourth conductive layer 134 exposed by the second passivation layer 138 .
- the fifth conductive layer 142 may be applied over the second passivation layer 138 and the fourth conductive layer 134 exposed in the second opening 140 with a number of different processes, such as depositing, sputtering, or plating.
- the fifth conductive layer 142 is preferably patterned over the second passivation layer 138 adjacent to and line the second opening 140 .
- the fifth conductive layer 142 is over the fourth conductive layer 134 exposed in the second opening 140 and not completely covering the second passivation layer 138 .
- the sixth conductive layer 144 may be applied over the second passivation layer 138 and the fifth conductive layer 142 .
- the sixth conductive layer 144 is preferably patterned over the fifth conductive layer 142 and not completely covering the second passivation layer 138 .
- the protection cover 116 exposed in the pad openings 118 protects the contact pads 104 during the development of the fifth conductive layer 142 and the sixth conductive layer 144 .
- the development of the fifth conductive layer 142 and the sixth conductive layer 144 are described individually, although it is understood that both the fifth conductive layer 142 and the sixth conductive layer 144 may be applied over the wafer 302 and may be patterned in a single development step.
- FIG. 11 therein is shown the structure of FIG. 10 in forming the first interconnect 146 .
- the fifth conductive layer 142 and the sixth conductive layer 144 preferably form the under bump metallization (UBM) for the first interconnect 146 .
- UBM under bump metallization
- the protection cover 116 exposed in the pad openings 118 protects the contact pads 104 from contamination, such as during the reflow and the flux stripping for the first interconnect 146 .
- the protection cover 116 exposed in the pad openings 118 is preferably removed exposing the contact pads 104 .
- the protection cover 116 in the pad openings 118 may be removed in a number of different ways.
- the protection cover 116 possesses a good etch selectivity compared to the first passivation layer 128 with reactive ion etch (RIE).
- RIE reactive ion etch
- the protection cover 116 covering the contact pads 104 that are not exposed in the pad openings 118 continue to cover the contact pads 104 .
- the formation of the first interconnect 146 is described with the protection cover 116 exposed in the pad openings 118 , although it is understood that the protection cover 116 in the pad openings 118 may be removed and the first interconnect 146 may be formed over both the sixth conductive layer 144 and the contact pads 104 .
- FIG. 12 therein is shown the structure of FIG. 11 in forming the second interconnect 148 .
- the integrated circuit die 102 may be singulated from the wafer 302 .
- the second interconnect 148 preferably attaches to the contact pads 104 exposed in the pad openings 118 forming the integrated circuit package system 100 .
- the protection cover 116 over the contact pads 104 prevents contamination and Galvanic corrosion of the contact pads 104 from the processes described above.
- the protection cover 116 exposed in the pad openings 118 is described as removed, although it is understood that the protection cover 116 exposed in the pad openings 118 may not be removed. Also for illustrative purposes, the protection cover 116 exposed in the pad openings 118 is described as removed, although it is understood that a predetermined number and locations of the contact pads 104 may be exposed with the protection cover 116 removed. For example, a predetermined number and locations of the contact pads 104 may be connected for programming purpose or bonding option.
- the wafer 302 is described as singulated for forming the integrated circuit package system 100 , although it is understood that the wafer 302 may represent a wafer scale chip.
- the structure described in FIG. 8 , FIG. 10 , or FIG. 11 may represent the integrated circuit package system 100 .
- the system 1300 includes providing an integrated circuit die having a contact pad in a block 1302 ; forming a protection cover over the contact pad in a block 1304 ; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover in a block 1306 ; developing a conductive layer over the passivation layer in a block 1308 ; and forming a pad opening in the protection cover for exposing the contact pad in a block 1310 .
- Yet other important aspects of the embodiments include that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
- the integrated circuit package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving reliability in systems.
- the resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit package system.
Abstract
Description
- The present invention relates generally to integrated circuit package system, and more particularly to integrated circuit package system having protected conductive layers.
- Modern consumer electronics, such as smart phones, personal digital assistants, and location based services devices, as well as enterprise electronics, such as servers and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Every new generation of integrated circuits with increased operating frequency, performance and the higher level of large-scale integration have underscored the need for back-end integrated circuit manufacturing to provide more solutions involving the integrated circuit itself.
- Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing and mature package technologies. Both approaches may include additional processing of the integrated circuits to better match the targeted package.
- The continued emphasis in the integrated circuit technology is to create improved performance integrated circuit devices at competitive prices. This emphasis over the years has resulted in increasing miniaturization of integrated circuit devices, made possible by continued advances of integrated circuit processes and materials in combination with new and sophisticated device designs.
- Numerous integrated circuit designs are aimed for mixed-signal designs by incorporating analog functions. One of the major challenges in the creation of analog processing circuitry (using digital processing procedures and equipment) is that a number of the components that are used for analog circuitry are large in size and are therefore not readily integrated into integrated circuits. The main components that offer a challenge in this respect are capacitors and inductors, since both these components are, for typical analog processing circuits, of considerable size. In response to the demands for improved package performance and analog circuitry integration, packaging manufacturers may prepare the integrated circuit for packaging as well as provide analog circuitry integration onto the integrated circuit.
- Although analog circuitry integration and processing support the miniaturization trend, other problems arise from this integration. For example, semiconductor or integrated circuit devices have pads exposed for connecting, such as wire bonding, to the package terminals, such as leads. Typically, analog circuitry integration or any additional device processing after the pad development damages the pad resulting in poor electrical contact, contact reliability, reduced yield, and increased cost.
- Still thinner, smaller, and lighter package designs and mounting/connecting configurations have been adopted in response to continuing requirements for further miniaturization. At the same time, users are demanding integrated circuit packages that are more reliable under increasingly severe operating conditions.
- Thus, a need still remains for an integrated circuit package system providing low cost manufacturing and improved yield for the integrated circuits. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
- Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
- The present invention provides an integrated circuit package system including providing an integrated circuit die having a contact pad, forming a protection cover over the contact pad, forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover, developing a conductive layer over the passivation layer, and forming a pad opening in the protection cover for exposing the contact pad.
- Certain embodiments of the invention have other aspects in addition to or in place of those mentioned or obvious from the above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
-
FIG. 1 is a cross-sectional view of an integrated circuit package system in an embodiment of the present invention; -
FIG. 2 is a cross-sectional view of an integrated circuit package system in an alternative embodiment of the present invention; -
FIG. 3 is a cross-sectional view of a wafer structure in forming the first conductive layer in an embodiment of the present invention; -
FIG. 4 is the structure ofFIG. 3 in forming the resistive layer; -
FIG. 5 is the structure ofFIG. 4 in forming the insulator layer; -
FIG. 6 is the structure ofFIG. 5 in forming the second conductive layer; -
FIG. 7 is the structure ofFIG. 6 in forming the first passivation layer; -
FIG. 8 is the structure ofFIG. 7 in forming the fourth conductive layer; -
FIG. 9 is the structure ofFIG. 8 in forming the second passivation layer; -
FIG. 10 is the structure ofFIG. 9 in forming the sixth conductive layer; -
FIG. 11 is the structure ofFIG. 10 in forming the first interconnect; -
FIG. 12 is the structure ofFIG. 11 in forming the second interconnect; and -
FIG. 13 is a flow chart of an integrated circuit package system for manufacture of the integrated circuit package system in an embodiment of the present invention. - The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.
- In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.
- For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side”(as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements. The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure. The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.
- Referring now to
FIG. 1 , therein is shown a cross-sectional view of an integratedcircuit package system 100 in an embodiment of the present invention. The cross-sectional view depicts anintegrated circuit die 102 havingcontact pads 104, afirst circuit element 106, asecond circuit element 108, and athird circuit element 110 provided thereover. - For example, the
contact pads 104 may function as input/output (IO) pads for theintegrated circuit die 102. Thefirst circuit element 106 is depicted as capacitor. Thesecond circuit element 108 is depicted as a resistor. Thethird circuit element 110 is depicted as conductive trace or a redistribution trace. Thecontact pads 104, thefirst circuit element 106, thesecond circuit element 108, and thethird circuit element 110 are preferably over anactive side 112 of the integrated circuit die 102. - The
contact pads 104 may be preferably formed with a firstconductive layer 114, such as aluminum (Al), copper (Cu), gold (Au), or a metal alloy. The firstconductive layer 114 is preferably not the first conducting layer of the semiconductor process used to manufacture theintegrated circuit die 102. The firstconductive layer 114 may be the last conducting layer of the semiconductor process used to manufacture theintegrated circuit die 102. - A
protection cover 116 preferably partially covers thecontact pads 104 and exposes thecontact pads 104 throughpad openings 118. Theprotection cover 116 is preferably formed from aresistive layer 120. Theprotection cover 116 shields thecontact pads 104 from further corrosive processing, such as wet etching, and prevents galvanic corrosion of thecontact pads 104. Galvanic corrosion adversely affects thecontact pads 104 causing pin holes. Theresistive layer 120 may be formed by a number of high resistivity materials, such as nickel chromium (NiCr) or poly-silicon crystalline (poly-Si). - The
first circuit element 106 preferably includes the firstconductive layer 114, theresistive layer 120, aninsulator layer 122, and a secondconductive layer 124. Theinsulator layer 122 is preferably a dielectric layer or film, such as silicon nitride (SiN), tantalum pentoxide (Ta2O5), or hafnium oxide (HfO2). The secondconductive layer 124 is preferably aluminum (Al), copper (Cu), a metal alloy, or other conductive film. - The
first circuit element 106 preferably has theresistive layer 120 over the firstconductive layer 114 which is over the integrated circuit die 102. Theinsulator layer 122 partially covers theresistive layer 120 and the firstconductive layer 114 of thefirst circuit element 106 and exposes theresistive layer 120 with aninsulator opening 126. The secondconductive layer 124 is preferably patterned over theinsulator layer 122 not over theinsulator opening 126 and over theinsulator opening 126 connecting with theresistive layer 120. - The
second circuit element 108 preferably includes theresistive layer 120, theinsulator layer 122, and the secondconductive layer 124. Thesecond circuit element 108 preferably has theinsulator layer 122 over theresistive layer 120 which is over the integrated circuit die 102. The secondconductive layer 124 is patterned over theresistive layer 120 not covered by theinsulator layer 122. The secondconductive layer 124 is adjacent with and does not cover theinsulator layer 122. - The
third circuit element 110 preferably includes the secondconductive layer 124. Thethird circuit element 110 is shown not contacting thesecond circuit element 108 or theresistive layer 120 over thecontact pads 104. Also, thefirst circuit element 106 is shown not contacting thesecond circuit element 108. - A
first passivation layer 128, such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), covers theactive side 112 including thesecond circuit element 108. Thefirst passivation layer 128 partially covers thefirst circuit element 106, thethird circuit element 110, and thecontact pads 104. Thefirst passivation layer 128 also providesfirst openings 130 exposing thecontact pads 104, the secondconductive layer 124 of thefirst circuit element 106, and the third circuit element 1 10. Thefirst passivation layer 128 is used to protect the underlying devices, such as thefirst circuit element 106 and thesecond circuit element 108, from penetration of mobile ions, moisture, transition metal (such as gold or silver), and other contaminations. - A third
conductive layer 132 is preferably patterned over thefirst passivation layer 128. The thirdconductive layer 132 is preferably adjacent to and lining predetermined locations of thefirst openings 130. The thirdconductive layer 132 lines thefirst openings 130 over thefirst circuit element 106 and thethird circuit element 110. The thirdconductive layer 132 is shown not over thecontact pads 104. - The third
conductive layer 132 also covers predetermined locations over thefirst passivation layer 128 not adjacent thefirst openings 130. The thirdconductive layer 132 is shown not completely covering thefirst passivation layer 128. The thirdconductive layer 132 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). - A fourth
conductive layer 134 is preferably patterned over the thirdconductive layer 132. The fourthconductive layer 134 and the thirdconductive layer 132 may preferably provide a number of functions. For example, thefirst openings 130 lined with the thirdconductive layer 132 provide electrical vias connecting the fourthconductive layer 134 with thefirst circuit element 106 and thethird circuit element 110. - Another example, the fourth
conductive layer 134 over thethird circuit element 110 and between thecontact pads 104 and thethird circuit element 110 may form afourth circuit element 136, such as an inductor. The thirdconductive layer 132 and the fourthconductive layer 134 between thefirst circuit element 106 and thethird circuit element 110 may function as redistribution layer. - The
first passivation layer 128 serves as a stress buffer or protective coat for the integrated circuit die 102. Thefirst passivation layer 128 also separates thefourth circuit element 136 from the substrate of the integrated circuit die 102 resulting in an increase in the Q value of the inductor. - A
second passivation layer 138, such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), partially covers thefirst passivation layer 128 and the fourthconductive layer 134 with asecond opening 140 exposing a portion of the fourthconductive layer 134 over thesecond circuit element 108. Thesecond passivation layer 138 does not cover thepad openings 118 exposing thecontact pads 104. - A fifth
conductive layer 142 is preferably patterned over thesecond passivation layer 138 adjacent to and line thesecond opening 140. The fifthconductive layer 142 is over the fourthconductive layer 134 exposed in thesecond opening 140 and not completely covering thesecond passivation layer 138. The fifthconductive layer 142 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). - A sixth
conductive layer 144 is preferably patterned over the fifthconductive layer 142. The sixthconductive layer 144 may be formed from a number of different materials, such as nickel vanadium (NiV), Cu, Cu/NiV, Au/Ni, or CrCu. The fifthconductive layer 142 and the sixthconductive layer 144 may preferably form the under bump metallization (UBM) for afirst interconnect 146, such as sold bump, gold bump, or copper pillar. Asecond interconnect 148, such as a bond wire or a conductive pillar, is preferably attached to thecontact pads 104 through thepad openings 118 in thefirst passivation layer 128 and theresistive layer 120. - The integrated
circuit package system 100 may connect to the next system level (not shown), such as a printed circuit board or another integrated circuit device (not shown). Alternatively, the integratedcircuit package system 100 may be further packaged. - Referring now to
FIG. 2 , therein is shown a cross-sectional view of an integratedcircuit package system 200 in an alternative embodiment of the present invention. The cross-sectional view of the integratedcircuit package system 200 includes structural similarities with the integratedcircuit package system 100 ofFIG. 1 . - The cross-sectional view depicts an integrated circuit die 202 having
contact pads 204, afirst circuit element 206, asecond circuit element 208, and athird circuit element 210 provided thereover. For example, thecontact pads 204 may function as input/output (IO) pads for the integrated circuit die 202. Thefirst circuit element 206 is depicted as capacitor. Thesecond circuit element 208 is depicted as a resistor. Thethird circuit element 210 is depicted as conductive trace or a redistribution trace. Thecontact pads 204, thefirst circuit element 206, thesecond circuit element 208, and thethird circuit element 210 are preferably over anactive side 212 of the integrated circuit die 202. - The
contact pads 204 may be preferably formed with a firstconductive layer 214, such as aluminum (Al), copper (Cu), gold (Au), or a metal alloy. The firstconductive layer 214 is preferably not the first conducting layer of the semiconductor process used to manufacture the integrated circuit die 202. The firstconductive layer 214 may be the last conducting layer of the semiconductor process used to manufacture the integrated circuit die 202. - A
protection cover 216 preferably partially covers thecontact pads 204 and exposes thecontact pads 204 throughpad openings 218. Theprotection cover 216 is preferably formed from aninsulator layer 222. Theprotection cover 216 shields thecontact pads 204 from further corrosive processing, such as wet etching, and prevents galvanic corrosion of thecontact pads 204. Galvanic corrosion adversely affects thecontact pads 204 causing pin holes. Theinsulator layer 222 may be formed by a number of a dielectric layer or film, such as silicon nitride (SiN), tantalum pentoxide (Ta2O5), or hafnium oxide (HfO2). - The
first circuit element 206 preferably includes the firstconductive layer 214, aresistive layer 220, theinsulator layer 222, and a secondconductive layer 224. Theresistive layer 220 is preferably a high resistivity material, such as nickel chromium (NiCr) or poly-silicon crystalline (poly-Si). The secondconductive layer 224 is preferably aluminum (Al), copper (Cu), a metal alloy, or other conductive film. - The
first circuit element 206 preferably has theresistive layer 220 over the firstconductive layer 214 which is over the integrated circuit die 202. Theinsulator layer 222 partially covers theresistive layer 220 and the firstconductive layer 214 of thefirst circuit element 206 and exposes theresistive layer 220 with aninsulator opening 226. The secondconductive layer 224 is preferably patterned over theinsulator layer 222 not over theinsulator opening 226 and over theinsulator opening 226 connecting with theresistive layer 220. - The
second circuit element 208 preferably includes theresistive layer 220, theinsulator layer 222, and the secondconductive layer 224. Thesecond circuit element 208 preferably has theinsulator layer 222 over theresistive layer 220 which is over the integrated circuit die 202. The secondconductive layer 224 is patterned over theresistive layer 220 not covered by theinsulator layer 222. The secondconductive layer 224 is adjacent with and does not cover theinsulator layer 222. - The
third circuit element 210 preferably includes the secondconductive layer 224. Thethird circuit element 210 is shown not contacting thesecond circuit element 208 or theresistive layer 220 over thecontact pads 204. Also, thefirst circuit element 206 is shown not contacting thesecond circuit element 208. - A
first passivation layer 228, such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), covers theactive side 212 including thesecond circuit element 208. Thefirst passivation layer 228 partially covers thefirst circuit element 206, thethird circuit element 210, and thecontact pads 204. Thefirst passivation layer 228 also providesfirst openings 230 exposing thecontact pads 204, the secondconductive layer 224 of thefirst circuit element 206, and thethird circuit element 210. Thefirst passivation layer 228 is used to protect the underlying devices, such as thefirst circuit element 206 and thesecond circuit element 208, from penetration of mobile ions, moisture, transition metal (such as gold or silver), and other contaminations. - A third
conductive layer 232 is preferably patterned over thefirst passivation layer 228. The thirdconductive layer 232 is preferably adjacent to and lining predetermined locations of thefirst openings 230. The thirdconductive layer 232 lines thefirst openings 230 over thefirst circuit element 206 and thethird circuit element 210. The thirdconductive layer 232 is shown not over thecontact pads 204. - The third
conductive layer 232 also covers predetermined locations over thefirst passivation layer 228 not adjacent thefirst openings 230. The thirdconductive layer 232 is shown not completely covering thefirst passivation layer 228. The thirdconductive layer 232 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). - A fourth conductive layer 234 is preferably patterned over the third
conductive layer 232. The fourth conductive layer 234 and the thirdconductive layer 232 may preferably provide a number of functions. For example, thefirst openings 230 lined with the thirdconductive layer 232 provide electrical vias connecting the fourth conductive layer 234 with thefirst circuit element 206 and thethird circuit element 210. - Another example, the fourth conductive layer 234 over the
third circuit element 210 and between thecontact pads 204 and thethird circuit element 210 may form afourth circuit element 236, such as an inductor. The thirdconductive layer 232 and the fourth conductive layer 234 between thefirst circuit element 206 and thethird circuit element 210 may function as redistribution layer. - The
first passivation layer 228 serves as a stress buffer or protective coat for the integrated circuit die 202. Thefirst passivation layer 228 also separates thefourth circuit element 236 from the substrate of the integrated circuit die 202 resulting in an increase in the Q value of the inductor. - A
second passivation layer 238, such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), partially covers thefirst passivation layer 228 and the fourth conductive layer 234 with a second opening 240 exposing a portion of the fourth conductive layer 234 over thesecond circuit element 208. Thesecond passivation layer 238 does not cover thepad openings 218 exposing thecontact pads 204. - A fifth conductive layer 242 is preferably patterned over the
second passivation layer 238 adjacent to and line the second opening 240. The fifth conductive layer 242 is over the fourth conductive layer 234 exposed in the second opening 240 and not completely covering thesecond passivation layer 238. The fifth conductive layer 242 may be formed from a number of different materials, such as chromium (Cr), tin (Ti), tin tungsten (TiW), tin nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). - A sixth
conductive layer 244 is preferably patterned over the fifth conductive layer 242. The sixthconductive layer 244 may be formed from a number of different materials, such as nickel vanadium (NiV), Cu, Cu/NiV, Au/Ni, or CrCu. The fifth conductive layer 242 and the sixthconductive layer 244 may preferably form the under bump metallization (UBM) for afirst interconnect 246, such as sold bump, gold bump, or copper pillar. Asecond interconnect 248, such as a bond wire or a conductive pillar, is preferably attached to thecontact pads 204 through thepad openings 218 in thefirst passivation layer 228 and theresistive layer 220. - The integrated
circuit package system 200 may connect to the next system level (not shown), such as a printed circuit board or another integrated circuit device (not shown). Alternatively, the integratedcircuit package system 200 may be further packaged. - Referring now to
FIG. 3 , therein is shown a cross-sectional view of awafer structure 300 in forming the firstconductive layer 114 in an embodiment of the present invention. Thewafer structure 300 includes awafer 302 having the firstconductive layer 114 formed thereover. The firstconductive layer 114 is patterned over theactive side 112 forming thecontact pads 104 and one of the electrodes, such as the metal cap, for thefirst circuit element 106 ofFIG. 1 . - The first
conductive layer 114 is applied over thewafer 302 with a number of different processes, such as depositing, sputtering, or plating. The firstconductive layer 114 may be patterned using a number of different processes. For example, the patterning process may preferably be a development process utilizing patterned photoresist structures (not shown) over the firstconductive layer 114 and etching. The photoresist is preferably removed for further processing thewafer structure 300. - Referring now to
FIG. 4 , therein is shown the structure ofFIG. 3 in forming theresistive layer 120. Theresistive layer 120 is preferably deposited over the firstconductive layer 114 and thewafer 302. Theresistive layer 120 may be patterned using a number of different processes, such as the development process described above utilizing patterned photoresist structures and etching. - The patterning process forms the
resistive layer 120 over the firstconductive layer 114 of thefirst circuit element 106 ofFIG. 1 , theresistive layer 120 of thesecond circuit element 108 ofFIG. 1 over thewafer 302, and theprotection cover 116 over thecontact pads 104. Theresistive layer 120 over thecontact pads 104 preferably functions to protect thecontact pads 104 from further development, such as wet etching, of thewafer 302 that would be damaging to thecontact pads 104. - Referring now to
FIG. 5 , therein is shown the structure ofFIG. 4 in forming theinsulator layer 122. Theinsulator layer 122 is preferably deposited over the firstconductive layer 114, theresistive layer 120, and thewafer 302. Theinsulator layer 122 may be patterned using a number of different processes, such as the development process utilizing patterned photoresist structures and etching. - The patterning process forms the
insulator layer 122 covering the firstconductive layer 114 and partially covering theresistive layer 120 of the first circuit element ofFIG. 1 . Theinsulator opening 126 in theinsulator layer 122 exposes theresistive layer 120. The patterning process also forms theinsulator layer 122 over and not completely covering theresistive layer 120 of thesecond circuit element 108 ofFIG. 1 . Theprotection cover 116 protects thecontact pads 104 during the development of theinsulator layer 122. - Referring now to
FIG. 6 , therein is shown the structure ofFIG. 5 in forming the secondconductive layer 124. The secondconductive layer 124 is preferably deposited over theinsulator layer 122, theresistive layer 120, the firstconductive layer 114, and thewafer 302. The secondconductive layer 124 may be patterned using a number a different processes, such as a development process utilizing patterned photoresist structures and etching. - The patterning process of the second
conductive layer 124 forms thefirst circuit element 106, thesecond circuit element 108, and thethird circuit element 110. Theprotection cover 116 exposed in thepad openings 118 ofFIG. 1 protects thecontact pads 104 during the development of the secondconductive layer 124. - Referring now to
FIG. 7 , therein is shown the structure ofFIG. 6 in forming thefirst passivation layer 128. Thefirst passivation layer 128 is preferably deposited over the secondconductive layer 124, theinsulator layer 122, theresistive layer 120, the firstconductive layer 114, and thewafer 302. Thefirst passivation layer 128 may be applied with a number of different processes, such as spin coating. Thefirst passivation layer 128 may be patterned using a number of different processes, such as dry etch, wet etch, or dry etch with laser ablation. - The patterning process of the
first passivation layer 128 exposes the secondconductive layer 124 of thefirst circuit element 106, thethird circuit element 110 and theresistive layer 120 over thecontact pads 104. The patterning process forms thefirst openings 130 and thepad openings 118 in thefirst passivation layer 128. Theprotection cover 116 exposed in thepad openings 118 protects thecontact pads 104 during the development of thefirst passivation layer 128. - Referring now to
FIG. 8 , therein is shown the structure ofFIG. 7 in forming the fourthconductive layer 134. The thirdconductive layer 132 is preferably deposited over thefirst passivation layer 128 and the secondconductive layer 124 exposed by thefirst openings 130. - The third
conductive layer 132 is preferably patterned adjacent to and lining predetermined locations of thefirst openings 130. The thirdconductive layer 132 lines thefirst openings 130 over thefirst circuit element 106 and thethird circuit element 110. The thirdconductive layer 132 is shown not over thecontact pads 104. - The third
conductive layer 132 may be applied over thefirst passivation layer 128 and thefirst openings 130 exposing the secondconductive layer 124 with a number of different processes, such as depositing, sputtering, or plating. The thirdconductive layer 132 is also preferably patterned over predetermined locations over thefirst passivation layer 128 not adjacent thefirst openings 130. The thirdconductive layer 132 is shown not completely covering thefirst passivation layer 128. - The third
conductive layer 132 may be patterned using a number of different processes. For example, the patterning process may preferably be a development process utilizing patterned photoresist structures (not shown) over the thirdconductive layer 132 and wet etching. - The fourth
conductive layer 134 may be applied over the thirdconductive layer 132 and thefirst passivation layer 128 and with a number of different processes, such as depositing, sputtering, or plating. The fourthconductive layer 134 is also preferably patterned over predetermined locations over the thirdconductive layer 132. Theprotection cover 116 exposed in thepad openings 118 protects thecontact pads 104 during the development of the thirdconductive layer 132 and the fourthconductive layer 134. - Referring now to
FIG. 9 , therein is shown the structure ofFIG. 8 in forming thesecond passivation layer 138. Thesecond passivation layer 138 is preferably deposited over the fourthconductive layer 134, the thirdconductive layer 132, and thewafer 302. Thesecond passivation layer 138 may be applied with a number of different processes, such as depositing or spin coating. Thesecond passivation layer 138 may be patterned using a number of different processes, such as dry etch, wet etch, or dry etch with laser ablation. - The patterning process of the
second passivation layer 138 exposes the fourthconductive layer 134 with thesecond opening 140 over thesecond circuit element 108. Thesecond passivation layer 138 may optionally partially fill thepad openings 118 or may not occupy thepad openings 118. Theprotection cover 116 exposed in thepad openings 118 protects thecontact pads 104 during the development of thesecond passivation layer 138. Theprotection cover 116 exposed in thepad openings 118 may be optionally removed for connecting thesecond interconnect 148 ofFIG. 1 , such as bond wire, to both thecontact pads 104 and to the fourthconductive layer 134 exposed by thesecond passivation layer 138. - Referring now to
FIG. 10 , therein is shown the structure ofFIG. 9 in forming the sixthconductive layer 144. The fifthconductive layer 142 may be applied over thesecond passivation layer 138 and the fourthconductive layer 134 exposed in thesecond opening 140 with a number of different processes, such as depositing, sputtering, or plating. The fifthconductive layer 142 is preferably patterned over thesecond passivation layer 138 adjacent to and line thesecond opening 140. The fifthconductive layer 142 is over the fourthconductive layer 134 exposed in thesecond opening 140 and not completely covering thesecond passivation layer 138. - The sixth
conductive layer 144 may be applied over thesecond passivation layer 138 and the fifthconductive layer 142. The sixthconductive layer 144 is preferably patterned over the fifthconductive layer 142 and not completely covering thesecond passivation layer 138. Theprotection cover 116 exposed in thepad openings 118 protects thecontact pads 104 during the development of the fifthconductive layer 142 and the sixthconductive layer 144. For illustrative purposes, the development of the fifthconductive layer 142 and the sixthconductive layer 144 are described individually, although it is understood that both the fifthconductive layer 142 and the sixthconductive layer 144 may be applied over thewafer 302 and may be patterned in a single development step. - Referring now to
FIG. 11 , therein is shown the structure ofFIG. 10 in forming thefirst interconnect 146. The fifthconductive layer 142 and the sixthconductive layer 144 preferably form the under bump metallization (UBM) for thefirst interconnect 146. Theprotection cover 116 exposed in thepad openings 118 protects thecontact pads 104 from contamination, such as during the reflow and the flux stripping for thefirst interconnect 146. - The
protection cover 116 exposed in thepad openings 118 is preferably removed exposing thecontact pads 104. Theprotection cover 116 in thepad openings 118 may be removed in a number of different ways. For example, theprotection cover 116 possesses a good etch selectivity compared to thefirst passivation layer 128 with reactive ion etch (RIE). - The
protection cover 116 covering thecontact pads 104 that are not exposed in thepad openings 118 continue to cover thecontact pads 104. For illustrative purposes, the formation of thefirst interconnect 146 is described with theprotection cover 116 exposed in thepad openings 118, although it is understood that theprotection cover 116 in thepad openings 118 may be removed and thefirst interconnect 146 may be formed over both the sixthconductive layer 144 and thecontact pads 104. - Referring now to
FIG. 12 , therein is shown the structure ofFIG. 11 in forming thesecond interconnect 148. The integrated circuit die 102 may be singulated from thewafer 302. Thesecond interconnect 148 preferably attaches to thecontact pads 104 exposed in thepad openings 118 forming the integratedcircuit package system 100. Theprotection cover 116 over thecontact pads 104 prevents contamination and Galvanic corrosion of thecontact pads 104 from the processes described above. - For illustrative purposes, the
protection cover 116 exposed in thepad openings 118 is described as removed, although it is understood that theprotection cover 116 exposed in thepad openings 118 may not be removed. Also for illustrative purposes, theprotection cover 116 exposed in thepad openings 118 is described as removed, although it is understood that a predetermined number and locations of thecontact pads 104 may be exposed with theprotection cover 116 removed. For example, a predetermined number and locations of thecontact pads 104 may be connected for programming purpose or bonding option. - Further for illustrative purposes, the
wafer 302 is described as singulated for forming the integratedcircuit package system 100, although it is understood that thewafer 302 may represent a wafer scale chip. For example, the structure described inFIG. 8 ,FIG. 10 , orFIG. 11 may represent the integratedcircuit package system 100. - Referring now to
FIG. 13 , therein is shown a flow chart of an integratedcircuit package system 1300 for manufacture of the integratedcircuit package system 100 in an embodiment of the present invention. Thesystem 1300 includes providing an integrated circuit die having a contact pad in ablock 1302; forming a protection cover over the contact pad in ablock 1304; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover in ablock 1306; developing a conductive layer over the passivation layer in ablock 1308; and forming a pad opening in the protection cover for exposing the contact pad in ablock 1310. - Yet other important aspects of the embodiments include that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
- These and other valuable aspects of the embodiments consequently further the state of the technology to at least the next level.
- Thus, it has been discovered that the integrated circuit package system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving reliability in systems. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit package system.
- While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Claims (20)
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US11/694,907 US8026593B2 (en) | 2007-03-30 | 2007-03-30 | Integrated circuit package system with protected conductive layers for pads and method of manufacturing thereof |
US13/233,402 US8389396B2 (en) | 2007-03-30 | 2011-09-15 | Method for manufacture of integrated circuit package system with protected conductive layers for pads |
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US11/694,907 US8026593B2 (en) | 2007-03-30 | 2007-03-30 | Integrated circuit package system with protected conductive layers for pads and method of manufacturing thereof |
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US13/233,402 Active US8389396B2 (en) | 2007-03-30 | 2011-09-15 | Method for manufacture of integrated circuit package system with protected conductive layers for pads |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110024887A1 (en) * | 2009-07-31 | 2011-02-03 | Chi Heejo | Integrated circuit packaging system with through silicon via base and method of manufacture thereof |
US20110163413A1 (en) * | 2010-01-07 | 2011-07-07 | Samsung Electro-Mechanics Co., Ltd. | Rf semiconductor device and fabrication method thereof |
CN108091630A (en) * | 2016-11-23 | 2018-05-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
US11251146B2 (en) * | 2019-04-08 | 2022-02-15 | Infineon Technologies Ag | Semiconductor devices having a non-galvanic connection |
US20220157750A1 (en) * | 2020-11-17 | 2022-05-19 | Pep Innovation Pte. Ltd. | Semiconductor structures with via openings and methods of making the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7772106B2 (en) | 2007-11-07 | 2010-08-10 | Stats Chippac, Ltd. | Method of forming an inductor on a semiconductor wafer |
EP3732710A4 (en) * | 2017-12-30 | 2021-11-17 | INTEL Corporation | Galvanic corrosion protection for semiconductor packages |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5736791A (en) * | 1995-02-07 | 1998-04-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and bonding pad structure therefor |
US6232238B1 (en) * | 1999-02-08 | 2001-05-15 | United Microelectronics Corp. | Method for preventing corrosion of bonding pad on a surface of a semiconductor wafer |
US6278191B1 (en) * | 1999-05-28 | 2001-08-21 | National Semiconductor Corporation | Bond pad sealing using wire bonding |
US6682659B1 (en) * | 1999-11-08 | 2004-01-27 | Taiwan Semiconductor Manufacturing Company | Method for forming corrosion inhibited conductor layer |
US20040115934A1 (en) * | 2002-12-13 | 2004-06-17 | Jerry Broz | Method of improving contact resistance |
US6779711B2 (en) * | 1999-05-14 | 2004-08-24 | International Business Machines Corporation | Self-aligned corrosion stop for copper C4 and wirebond |
US7105379B2 (en) * | 2004-04-28 | 2006-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Implementation of protection layer for bond pad protection |
-
2007
- 2007-03-30 US US11/694,907 patent/US8026593B2/en active Active
-
2011
- 2011-09-15 US US13/233,402 patent/US8389396B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5736791A (en) * | 1995-02-07 | 1998-04-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and bonding pad structure therefor |
US6232238B1 (en) * | 1999-02-08 | 2001-05-15 | United Microelectronics Corp. | Method for preventing corrosion of bonding pad on a surface of a semiconductor wafer |
US6779711B2 (en) * | 1999-05-14 | 2004-08-24 | International Business Machines Corporation | Self-aligned corrosion stop for copper C4 and wirebond |
US6278191B1 (en) * | 1999-05-28 | 2001-08-21 | National Semiconductor Corporation | Bond pad sealing using wire bonding |
US6682659B1 (en) * | 1999-11-08 | 2004-01-27 | Taiwan Semiconductor Manufacturing Company | Method for forming corrosion inhibited conductor layer |
US20040115934A1 (en) * | 2002-12-13 | 2004-06-17 | Jerry Broz | Method of improving contact resistance |
US7105379B2 (en) * | 2004-04-28 | 2006-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Implementation of protection layer for bond pad protection |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110024887A1 (en) * | 2009-07-31 | 2011-02-03 | Chi Heejo | Integrated circuit packaging system with through silicon via base and method of manufacture thereof |
US8587129B2 (en) | 2009-07-31 | 2013-11-19 | Stats Chippac Ltd. | Integrated circuit packaging system with through silicon via base and method of manufacture thereof |
US20110163413A1 (en) * | 2010-01-07 | 2011-07-07 | Samsung Electro-Mechanics Co., Ltd. | Rf semiconductor device and fabrication method thereof |
CN102157514A (en) * | 2010-01-07 | 2011-08-17 | 三星电机株式会社 | RF semiconductor device and fabrication method thereof |
CN108091630A (en) * | 2016-11-23 | 2018-05-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
US11251146B2 (en) * | 2019-04-08 | 2022-02-15 | Infineon Technologies Ag | Semiconductor devices having a non-galvanic connection |
US20220157750A1 (en) * | 2020-11-17 | 2022-05-19 | Pep Innovation Pte. Ltd. | Semiconductor structures with via openings and methods of making the same |
Also Published As
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US8026593B2 (en) | 2011-09-27 |
US8389396B2 (en) | 2013-03-05 |
US20120003830A1 (en) | 2012-01-05 |
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