US20080116611A1 - Method of Manufacturing Multilayer Wiring Board - Google Patents

Method of Manufacturing Multilayer Wiring Board Download PDF

Info

Publication number
US20080116611A1
US20080116611A1 US11/943,410 US94341007A US2008116611A1 US 20080116611 A1 US20080116611 A1 US 20080116611A1 US 94341007 A US94341007 A US 94341007A US 2008116611 A1 US2008116611 A1 US 2008116611A1
Authority
US
United States
Prior art keywords
insulating substrate
resin
temperature
wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/943,410
Inventor
Minoru Ogawa
Masahiro Izumi
Shigeyasu Itoh
Shingetsu Yamada
Shuuji Suzuki
Hiroo Kurosaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Plastics Inc
Sony Corp
Original Assignee
Mitsubishi Plastics Inc
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Plastics Inc, Sony Corp filed Critical Mitsubishi Plastics Inc
Priority to US11/943,410 priority Critical patent/US20080116611A1/en
Publication of US20080116611A1 publication Critical patent/US20080116611A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4632Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/041Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by using a die for cutting the conductive material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1258Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0129Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0154Polyimide
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0209Inorganic, non-metallic particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0352Differences between the conductors of different layers of a multilayer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0388Other aspects of conductors
    • H05K2201/0391Using different types of conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108Male die used for patterning, punching or transferring
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06Lamination
    • H05K2203/065Binding insulating layers without adhesive, e.g. by local heating or welding, before lamination of the whole PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/045Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P20/00Technologies relating to chemical industry
    • Y02P20/50Improvements relating to the production of bulk chemicals
    • Y02P20/582Recycling of unreacted starting or intermediate materials
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00Stock material or miscellaneous articles
    • Y10S428/901Printed circuit
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49158Manufacturing circuit on or in base with molding of insulated base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49169Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49169Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/249921Web or sheet containing structurally defined element or component
    • Y10T428/249994Composite having a component wherein a constituent is liquid or is contained within preformed walls [e.g., impregnant-filled, previously void containing component, etc.]

Definitions

  • the present invention relates to a multilayer wiring board, a semiconductor device mounting board using such a wiring board, and a method of manufacturing such a multilayer wiring board.
  • thermoplastic resins which are used as these substrate materials include liquid crystal polymers and thermoplastic polyamides.
  • a predetermined wiring circuit is formed on top of the printed wiring board in a similar manner to a conventional general purpose printed wiring board, namely using a so-called wet process in which copper foil is laminated on top of the printed wiring board and the copper foil is then subjected to etching treatment using wet etching or the like to form the wiring pattern.
  • Other methods of forming the wiring circuit on the printed wiring board include methods in which the wiring circuit is formed by a dry process.
  • screen printing techniques or dispensing techniques are used to print a conductive paste onto the printed wiring board in a predetermined wiring pattern, and this conductive paste is then subjected to heat treatment to complete the formation of a predetermined wiring circuit on the printed wiring board.
  • This method of printing on a conductive paste does not require the wet etching process used in conventional copper foil etching methods, and consequently the manufacturing process can be converted to a dry process, which offers the advantage of being even gentler on the environment.
  • thermoplastic resin enables a shortening of the process tact, and also offers the advantages pf superior moldability and plasticity, and is consequently considered a very favorable material as a board substrate material.
  • thermoplastic resins offer advantages as highly heat resistant substrate materials
  • the resin when the thermoplastic resin is laminated and integrated into a single unit, the resin must be heated to a temperature close to the resin melting point to ensure thermal fusion, and a problem arises during this heating and thermal fusion in that a resin flow, resulting from the large reduction in the modulus of elasticity at temperatures near the melting point, may cause distortions in the conducting material which forms the wiring circuit.
  • examples of methods for wiring formation using dry processes include screen printing methods and dispensing methods using a conductive paste, although in both of these methods, there is a limit to the improvements in detail and precision of the conductive wiring which can be achieved in order to try and meet the ever increasing demands for higher density mounting.
  • the resin in a laminated product of a thermoplastic resin on which a wiring circuit has been formed using a conductive paste, the resin must be heated to a temperature close to the melting point and subjected to pressure to fuse the thermoplastic resin layers together to create a single integrated unit, and as the pitch of the wiring becomes finer, distortion of the wiring resulting from resin flow during lamination is increasingly becoming a factor which cannot be ignored in substrate design.
  • the present invention aims to resolve the problems described above. with an object of providing a multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, can be ideally applied to low volume high mix manufacturing configurations, and also has little impact on the environment. as well as providing a semiconductor device mounting board using such a multilayer wiring board, and a method of manufacturing such a multilayer wiring board.
  • the inventors of the present invention realized that if a substrate formed from a thermoplastic resin could be combined with a wiring pattern formed from a conductive paste to produce a wiring board, then a high performance, environmentally friendly multilayer wiring board could be produced, and were hence able to complete the present invention.
  • a wiring circuit is formed by embedding conductive wiring within an insulating substrate, formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C.
  • amorphous polyetherimide resin as the primary constituents, so that the surface of the wiring protrudes to the surface of the resin, and a plurality of wiring substrates, formed by smoothing the surface of an insulating substrate comprising embedded conductive wiring are laminated together, and wiring is provided which electrically connects the wiring substrates ( 1 , 2 , 3 , 4 ) to one another, and the insulating substrates of these wiring substrates are bonded together by thermal fusion and crystallized, and the conductive wiring of the wiring circuit of each wiring substrate and the wiring used for electrically connecting each of the wiring substrates together, is formed from a conductive material produced by curing a conductive paste.
  • the insulating substrate which forms an essential component of the wiring substrate utilizes a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, and conductive wiring is embedded within the insulating substrate formed from this thermoplastic resin composition so that the surface of the wiring protrudes to the surface of the resin composition.
  • a multilayer wiring board with excellent heat resistance, a high degree of mechanical strength and excellent electrical insulation can be achieved, and in addition, low temperature fusion is possible without the occurrence of resin flow, meaning the problem of wiring distortions resulting from such resin flow can be resolved, making high precisian, finely detailed conductive wiring possible.
  • a multilayer wiring board with excellent electrical characteristics and reliability can be provided.
  • thermoplastic resin composition and the type and shape of the conductive wiring
  • a variety of different wiring substrates can be formed, and as a result, by combining wiring substrates with different specifications.
  • the present invention can be applied to multilayer wiring boards with a wide variety of specifications.
  • the combination of a variety of wiring substrates of different specifications makes the invention ideally suited to low volume high mix type manufacturing configurations. Furthermore, by using a conductive paste for the electrical connections, wiring formation using wet processes becomes unnecessary, meaning the environmental impact can be reduced.
  • the aforementioned insulating substrate should preferably utilize an amorphous film produced by molten mixing and then rapid cooling of a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260 PC and an amorphous polyetherimide resin as the primary constituents.
  • the conductive wiring of the present invention preferably comprises a conductive material formed by curing a conductive paste and a metallic foil, with at least the surface of the metallic foil protruding to the surface of the substrate.
  • a semiconductor device mounting board of the present invention comprises a multilayer wiring board of the present invention with a semiconductor device mounted thereon.
  • a semiconductor device mounting board of the present invention because the semiconductor device is mounted on a multilayer wiring board of the present invention, a high precision, finely detailed and high density semiconductor device mounting board can be produced with relative ease.
  • a method of manufacturing a multilayer wiring board according to the present invention comprises the steps of performing thermal molding on either one surface or both surfaces of an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C.
  • amorphous polyetherimide resin as the primary constituents, at a temperature which is higher than the glass transition temperature of the thermoplastic resin composition but lower than the crystallization start temperature, thereby forming a conductive region comprising grooves, via holes, or a combination of grooves and via holes on the aforementioned one surface or both surfaces, subsequently filling the conductive region with a conductive paste and forming a wiring circuit in which the conductive paste functions as conductive wiring, thereby forming a wiring substrate comprising the insulating substrate and the wiring circuit, and subsequently laminating a plurality of these wiring substrates together, bonding and crystallizing the insulating substrates of these wiring substrates by thermal fusion at a temperature higher than the aforementioned crystallization start temperature, and electrically connecting the plurality of wiring substrates with conductive paste.
  • a wiring substrate is generated by forming a wiring circuit comprising conductive wiring formed from a conductive paste on an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, and a plurality of these wiring substrates are then laminated together, and the insulating substrates of these wiring substrates are then bonded together and crystallized by thermal fusion at a temperature higher than the aforementioned crystallization start temperature, while each of the wiring substrates are electrically connected together with conductive paste.
  • the insulating substrate should preferably utilize an amorphous film produced by molten mixing and then rapid cooling of a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents.
  • Another method of manufacturing a multilayer wiring board according to the present invention comprises the steps of positioning an impressing jig on one surface of an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystal line melting peak temperature of at feast 260° C.
  • an impressing jig is positioned on one surface of the insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, with a metallic foil disposed therebetween, and an elastic film, which displays a lower modulus of elasticity than the insulating substrate at temperatures lower than the glass transition temperature of the insulating substrate, is positioned on the other surface of the insulating substrate.
  • insulating substrates and the wiring circuits formed thereon by appropriate selection of the number of insulating substrates and the wiring circuits formed thereon, a variety of different insulating substrates and conductive wiring can be formed, and by combining these substrates and wiring, multilayer wiring boards with a wide variety of specifications can be produced with relative ease, meaning low volume high mix multilayer wiring boards can be prepared easily, and within a relatively short time period. Furthermore, in the manufacturing process, by employing a dry process in which electrical connection is achieved via a conductive paste, wiring formation processes relying on wet processes become unnecessary, meaning the environmental impact of the manufacturing process is lessened considerably.
  • FIG. 1 is a cross-sectional diagram showing a multilayer wiring board of a first embodiment of the present invention.
  • FIGS. 2A , 2 B, 2 C, and 2 D are process diagrams showing a method of manufacturing a multi layer wiring board of the first embodiment of the present invention.
  • FIGS. 3A , 3 B, 3 C, 3 D and 3 E are process diagrams showing a method of manufacturing a multilayer wiring board of the first embodiment of the present invention.
  • FIG. 4 is a graph showing the temperature dependency of the modulus of elasticity of an insulating substrate and an elastic film.
  • FIGS. 5A , 5 B, 5 C, 5 D, 5 E, and 5 F are process diagrams showing a method of manufacturing a multilayer wiring board of the first embodiment of the present invention.
  • FIGS. 6A and 6B are process diagrams showing a method of manufacturing a multilayer wiring board of the first embodiment of the present invention.
  • FIG. 7 is a cross-sectional diagram showing an IC package board of a second embodiment of the present invention.
  • FIGS. 8A , 8 B, and 8 C are process diagrams showing a method of manufacturing an IC package board of the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional diagram showing an IC package board of a third embodiment of the present invention.
  • FIGS. 10A and 10B are process diagrams showing a method of manufacturing an IC package board of the third embodiment of the present invention.
  • FIG. 1 is a cross-sectional diagram showing a multilayer wiring board according to a first embodiment of the present invention.
  • symbol 1 represents an uppermost layer substrate (a wiring substrate of the uppermost layer)
  • symbol 2 represents a lowest layer substrate (a wiring substrate of the lowest layer)
  • symbols 3 and 4 represent inner layer substrates (wiring substrates) sandwiched between the uppermost layer substrate 1 and the lowest layer substrate 4 .
  • the uppermost layer substrate 1 is typically a film, a thin plate or a sheet of a thickness of no more than 100 ⁇ m, wherein grooves 12 for forming a wiring circuit are. formed in one surface (the upper surface in the figure) of an insulating substrate 11 formed from a film, a thin plate or a sheet of a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C.
  • via holes (through holes) 13 are formed which pass through the insulating substrate 11 , a metallic foil 14 is embedded within the grooves 12 so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material 15 formed by curing a conductive paste is used to fill the via holes 13 .
  • the upper and lower surfaces of the insulating substrate 11 including the metallic foil 14 , have been smoothed and flattened.
  • the lowest layer substrate 2 is of exactly the same construction as the uppermost layer substrate 1 , and differs only in the fact that the grooves 12 for forming the wiring circuit are formed in the lower surface of the insulating substrate 11 .
  • the inner layer substrate 3 is typically a film, a thin plate or a sheet of a thickness of no more than 100 ⁇ m, wherein grooves 12 for forming a wiring circuit are formed in one surface (the upper surface in the figure) of an insulating substrate 11 formed from a film, a thin plate or a sheet of an identical thermoplastic resin composition to the uppermost layer substrate 1 , via holes 13 which pass through the insulating substrate 11 are formed in a portion of the grooves 12 , and a conductive material 15 formed by curing a conductive paste is used to, fill the grooves 12 and the via holes 13 .
  • the upper and lower surfaces of the conductive paste 15 including the metallic foil 14 , have been smoothed and flattened.
  • the inner layer substrate 4 is of exactly the same construction as the inner layer substrate 3 described above, and differs only in the fact that the grooves 12 for forming the wiring circuit are formed in the lower surface of the insulating substrate 11 .
  • the lowest layer substrate 2 , the inner layer substrates 4 and 3 , and the uppermost layer substrate 1 are laminated together in that sequence, and then bonded together and integrated into a single unit by thermal fusion, and the wiring circuits of each of the substrates 1 to 4 , and the wiring for establishing the electrical connections between each set of adjacent substrates 1 to 4 is formed from the conductive material 15 produced by curing a conductive paste.
  • the polyarylketone resin with a crystalline melting peak temperature of at least 260° C. which represents one of the primary constituents of the thermoplastic resin composition used for forming the insulating substrate 11 , is a thermoplastic resin comprising an aromatic linkage, an ether linkage and a ketone linkage within the structural unit, and representative examples include polyetherketones, polyetheretherketones and polyetherketoneketones.
  • Examples of commercially available polyetheretherketones include PEEK151G, PEEK381G, and PEEK450G (all of which are manufactured by Victrex Co., Ltd.)
  • the amorphous polyetherimide resin is an amorphous thermoplastic resin comprising an aromatic linkage. an ether linkage and an imide linkage within the structural unit, and there are no other particular restrictions on the structure.
  • Examples of commercially available polyetherimides include Ultem CRS5001 and Ultem 1000 (both manufactured by General Electric Company).
  • the actual resin composition of the thermoplastic resin composition described above is preferably produced by mixing 20 to 50 parts by weight of an inorganic filler with 100 parts by weight of a thermoplastic resin composition formed from 70 to 25% by weight of the polyarylketone resin and 30 to 75% by weight of the amorphous polyetherimide resin.
  • the reason that the content of the polyarylketone resin is restricted to within a range from 70 to 25% by weight is because if the content exceeds 70% by weight, then the crystallinity becomes very high, making lamination more difficult when producing a multilayer structure, whereas if the content is less than 25% by weight, then the crystallinity of the overall composition falls, and the reflow heat resistance decreases even if the crystalline melting peak temperature is greater than 260° C.
  • the reason that the content of the amorphous polyetherimide resin is restricted to within a range from 30 to 75% by weight is because if the content is less than 30% by weight, then the crystallinity becomes very high, making lamination more difficult when producing a multilayer structure, whereas if the content exceeds 75% by weight, then the crystallinity of the overall composition falls, and the reflow heat resistance decreases even if the crystalline melting peak temperature is greater than 260° C.
  • Inorganic fillers can also be added to a thermoplastic resin composition such as that described above.
  • inorganic filler there are no particular restrictions on the type of inorganic filler, and any known filler can be used. Specific examples of such inorganic fillers include talc, mica, glass flakes, boron nitride (BN), calcium carbonate flakes, aluminum hydroxide flakes, silica flakes, and potassium titanate flakes. These fillers may be used singularly, or in combinations of two or more different fillers.
  • Scale-like flakes of inorganic fillers with an average particle diameter of no more than 15 ⁇ m and an aspect ratio (particle diameter/thickness) of more than 30 are particularly preferred, as they enable the ratio of the coefficients of linear expansion ratio in the in-plane direction and the thickness direction to be suppressed to a low level, thereby suppressing the occurrence of cracking within the board during thermal shock cycle testing.
  • the quantity of these types of inorganic fillers added is preferably within a range from 20 to 50 parts by weight per 100 parts by weight of the thermoplastic resin composition. If the quantity exceeds 50 parts by weight, then problems including unsatisfactory dispersion of the inorganic filler develop, and the coefficient of linear expansion is more likely to vary.
  • the quantity of the filler is less than 20 parts by weight, then the difference in the coefficients of linear expansion of the glass stamper used in the thermal molding process and the insulating substrate 11 can cause a contraction in the dimensions of the insulating substrate 11 ; and the effect of the invention in reducing the coefficient of linear expansion and improving the dimensional stability is diminished, and in addition, internal stress develops during the reflow process as a result a of the difference in the coefficient of linear expansion, making the board more susceptible to warping and twisting.
  • thermoplastic resin composition of the present invention may also be added to a thermoplastic resin composition of the present invention, provided such addition does not impair the properties of the composition, and examples of these other additives include stabilizers. ultraviolet light absorbers, light stabilizers, nucleation agents, coloring agents, lubricants and flame retardants.
  • additives including the inorganic filters, can be added using known methods, such as the methods (a) and (b) described below.
  • each of the additives is mixed at a high concentration (for example, a quantity of 10 to 60% by weight) with the polyarylketone resin and/or the amorphous polyetherimide resin to generate a master batch, and this master batch is then mixed with the resins to be used and the concentration adjusted appropriately, before the mixture is finally blended mechanically using a kneader or an extruder.
  • a high concentration for example, a quantity of 10 to 60% by weight
  • the method (a) is preferable in terms of dispersibility and workability.
  • the surface of the insulating substrate 11 may also be subjected to appropriate embossing or corona treatment or the like, in order to improve handling.
  • the aforementioned conductive material 15 is produced by heating and curing a conductive paste.
  • suitable conductive pastes include resin based low temperature curing pastes such as silver (Ag) paste, silver (Ag)-palladium (Pd) paste, and copper (Cu) paste.
  • an insulating substrate 21 formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents is prepared.
  • This insulating substrate 21 is provided as a film, a thin plate or a sheet.
  • suitable methods for molding the substrate include conventionally known methods such as extrusion casting methods using a T die, or calender methods, and although there are no particular restrictions on the method employed, extrusion casting methods using a T die are preferred from the viewpoints of sheet film formation and production stability.
  • the molding temperature in such a casting method using a T die can be suitably adjusted in accordance with the fluidity and the film formation properties of the composition, although generally, the temperature should be greater than the crystalline melting peak temperature of the polyarylketone resin (260° C.), but no more than 430° C.
  • a laser or a mechanical drill or the like is used to open through holes 22 in predetermined positions within the insulating substrate 21 , which then function as via holes 13 .
  • the via holes 13 are filled with a conductive paste 23 using a squeegee printing technique or the like. Subsequently, this conductive paste 23 is heated for 30 to 60 minutes at a temperature of 120 to 160° C., thereby forming a conductive material 15 .
  • any residual conductive material 15 left on the surface of the insulating substrate 21 is ground off and removed using a technique such as mechanical polishing. yielding a wiring substrate 24 with the via holes 13 filled with a conductive material 15 formed by curing a conductive paste, and with the surface of the insulating substrate 21 smoothed to a predetermined surface roughness.
  • an impressing jig 32 with texture formed on one of the principal surfaces is positioned on top (on one surface) of the insulating substrate 21 with a metallic foil 31 disposed therebetween, while an elastic film 33 which displays a lower modulus of elasticity than the insulating substrate 21 at temperatures lower than the glass transition temperature (Tg 1 ) of the insulating substrate 21 is positioned on the lower surface (the other surface) of the insulating substrate 21 .
  • Tg 1 glass transition temperature
  • the impressing jig 32 is pressed against the insulating substrate 21 , and thermal molding is performed at a temperature greater than the glass transition temperature (Tg 2 ) of the elastic film 33 but lower than the crystallization start temperature (Tcs) of the insulating substrate 21 .
  • the glass transition temperature (Tg 1 ) and the crystallization start temperature (Tcs) of the insulating substrate 21 , and the glass transition temperature (Tg 2 ) of the elastic film 33 can be measured using differential scanning calorimetry (DSC). These temperatures can be determined from the DSC profile obtained by heating a measurement sample at a heating rate of 10° C./minute, for example.
  • the glass transition temperature (Tg 1 ) is 185° C. and the crystallization start temperature (Tcs) is 225° C.
  • the elastic film 33 displays a lower modulus of elasticity than the insulating substrate 21 at temperatures lower than the glass transition temperature (Tg 1 ) of the insulating substrate 21 , then any film is acceptable, and an elastic film formed from a syndiotactic polystyrene is an ideal example.
  • the glass transition temperature (Tg 2 ) of this elastic film 33 is 100° C.
  • FIG. 4 is a graph showing the temperature dependency of the modulus of elasticity of the insulating substrate 2 I and the elastic film 33 .
  • A represents the curve for an insulating substrate comprising 40% by weight of a polyarylketone resin with a crystalline melting peak temperature of at least 260° C., and 60% by weight of an amorphous polyetherimide resin
  • B represents the curve for an elastic film formed from a syndiotactic polystyrene.
  • the elastic film 33 undergoes softening prior to the softening of the insulating substrate 21 , and as a result, the insulating substrate 21 flexes, but plastic deformation does not occur, and consequently the metallic foil 31 is able to cut efficiently.
  • the temperature of thermal molding is preferably greater than the glass transition temperature (Tg 2 ) of the elastic film 33 , and lower than the crystallization start temperature (Tcs) of the insulating substrate 21 , and even more preferably, should be lower than the glass transition temperature (Tg 1 ) of the insulating substrate 21 .
  • the metallic foil 31 a embedded within the insulating substrate 21 has a high fusion strength and is bonded strongly to the insulating substrate 21 , whereas the remaining sections of the metallic foil 31 b have only very weak fusion strength, and can be easily stripped away from the insulating substrate 21 .
  • the unnecessary metallic foil 31 b can be easily stripped off the insulating substrate 21 and removed.
  • the conductive material 15 formed by curing a conductive paste and a via hole 13 need not necessarily exist beneath the metallic foil 31 , although by ensuring that the conductive material 15 is present beneath the entire metallic foil 31 . the difference in fusion strength is magnified, and the unnecessary metallic foil 31 b can be removed even more easily, Furthermore, there are no particular restrictions on the type or the thickness of the metallic foil 31 , although the thickness of the metallic foil 31 is preferably less than the thickness provided by the height difference of the texture of the impressing jig 32 .
  • both surfaces of the insulating substrate 21 including the metallic foil 31 and the conductive material 15 are subjected to thermal molding using a molding die not shown in the figure, at a pressure of 0.5 to 10 kg/cm 2 and at a temperature lower than the crystallization start temperature (Tcs) of the insulating substrate 21 , thereby smoothing and flattening both surfaces of the insulating substrate 21 including the metallic foil 31 a and the conductive material 15 .
  • Tcs crystallization start temperature
  • the metallic foil 14 can be embedded in an outermost layer substrate, namely the substrate 21 , with the surface of the foil protruding to the surface of the insulating substrate, and an uppermost layer substrate 34 (or a lowest layer substrate 35 ) with the via holes 13 filled with the conductive material 15 can be produced.
  • convex sections 42 of a stamper 41 are thermally transferred to a surface (one surface) of an insulating substrate 21 formed from an identical thermoplastic resin composition to that used for the outermost layer substrates described above.
  • the conditions for this thermal transfer include, for example, a temperature of 175 to 205° C. and a pressure of 20 to 60 kg/cm 2 .
  • This thermal transfer forms wiring circuit formation grooves 43 in the surface of the insulating substrate 21 , as shown in FIG. 5B .
  • the stamper 41 is constructed from a material with good releasability relative to the insulating substrate 21 such as glass or ceramic. Heat resistant glass of thickness 3 to 5 mm is particularly suitable.
  • the stamper 41 is produced by forming a resist mask on the surface of a heat resistant glass plate using photolithography techniques, and subsequently forming the convex sections 42 which correspond with the wiring circuit pattern using sand blasting techniques or the like.
  • a laser or a mechanical drill or the like is used to open through holes 44 in predetermined positions within the insulating substrate 21 , which then function as via holes 13 .
  • These via holes 13 may also be formed by the stamper 41 , at the same time as the formation of the wiring circuit formation grooves 43 .
  • the wiring circuit formation grooves 43 and the via holes 13 are filled with a conductive paste 45 using a squeegee printing technique or the like. Subsequently, this conductive paste 45 is heated for 30 to 60 minutes at a temperature of 120 to 160° C., thereby forming a conductive material 15 . This process enables the formation of a conductive circuit 46 and interlayer continuity sections 47 at predetermined positions on the insulating substrate 21 .
  • a sanding device 48 is used to grind off and remove any residual conductive material 15 left on the surface of the insulating substrate 21 , and smooth the surface of the insulating substrate 21 , yielding an inner layer substrate 49 (or an inner layer substrate 50 ) with a conductive circuit 46 and interlayer continuity sections 47 formed at predetermined positions on the insulating substrate 21 .
  • a cushion film 52 with good elasticity and releasability, a lowest layer substrate 35 , an inner layer substrate 49 , an inner layer substrate 50 , an uppermost layer substrate 34 , and another cushion film 52 with good elasticity and releasability are overlaid, in the above sequence, within a lamination jig 51 .
  • the layers from the lowest layer substrate 35 through to the uppermost layer substrate 34 are bonded together and integrated into a single unit by thermal fusion under conditions including a temperature of 200 to 260° C. and a pressure of 20 to 60 kg/cm 2 .
  • a multilayer wiring board 53 can be produced comprising the lowest layer substrate 35 , the inner layer substrate 49 , the inner layer substrate 50 and the uppermost layer substrate 34 which have been bonded together and then integrated into a single unit by thermal fusion.
  • the grooves 12 for forming a wiring circuit are formed in the insulating substrate 11 formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, the via holes 13 which pass through the insulating substrate 11 are formed, the metallic foil 14 is embedded within the grooves 12 so that the surface of the foil protrudes to the surface of the insulating substrate, and the conductive material 15 formed by curing a conductive paste is used to fill the via holes 13 , thereby generating a wiring substrate, and consequently a multilayer wiring board with excellent heat resistance, a high degree of mechanical strength and excellent electrical insulation, which is capable of low temperature fusion without the occurrence of resin flow, enables the problems resulting from resin flow such as wiring distortion to be resolved, and enables high precision, finely detailed conductive wiring can be produced. As a result, a multilayer wiring board with excellent electrical characteristics and reliability can be provided.
  • thermoplastic resin composition and the type and shape of the conductive wiring
  • a variety of different wiring substrates can be formed, and as a result, by combining wiring substrates with different specifications, the present invention can be applied to multilayer wiring boards with a wide variety of specifications.
  • FIG. 7 is a cross-sectional diagram showing an 1C package board (a semiconductor device mounting board) of a second embodiment of the present invention.
  • This IC package board is a multilayer interposer board 61 comprising a lowest layer substrate 35 , an inner layer substrate 49 and an inner layer substrate 50 laminated together in this sequence and integrated into a single unit by thermal fusion, and an IC chip (semiconductor device) 63 is fixed directly to the top of the inner layer substrate 50 which functions as an IC chip (semiconductor device) mounting section, so that the pins (terminals) 64 of the IC chip 63 and the conductive circuit 46 are electrically connected, and the IC chip 63 is then sealed with a sealing resin 65 such as an epoxy resin.
  • a sealing resin 65 such as an epoxy resin.
  • this IC package board In order to manufacture this IC package board, first, as shown in FIG. 8A , a cushion film 52 with good elasticity and releasability, a lowest layer substrate 35 , an inner layer substrate 49 , an inner layer substrate 50 , and another cushion film 52 with good elasticity and releasability are overlaid, in the above sequence, within a lamination jig 51 . Subsequently, the layers from the lowest layer substrate 35 through to the inner layer substrate 50 are bonded together and integrated into a single unit by thermal fusion under conditions including a temperature of 200 to 260° C. and a pressure of 20 to 60 kg/cm 2 , thereby forming the multilayer interposer board 61 .
  • the IC chip 63 is mounted on top of the inner layer substrate 50 which functions as an IC chip mounting section, and this IC chip 63 is then subjected to thermocompression bonding using a hot plate 68 at a predetermined temperature, such as a temperature within a range from 175 to 205° C., which is lower than the crystallization start temperature of the insulating substrate.
  • a predetermined temperature such as a temperature within a range from 175 to 205° C., which is lower than the crystallization start temperature of the insulating substrate.
  • the pins 64 of the IC chip 63 are connected electrically with the conductive circuit 46 .
  • a sealing resin agent 69 such as an epoxy resin is applied so as to cover the IC chip 63 , and this sealing resin agent 69 is then heated and cured, thereby forming the sealing resin 65 .
  • This second embodiment provides the same effects as those described for a multilayer wiring board of the first embodiment.
  • an IC chip 63 is fixed directly onto the inner layer substrate 50 which functions as an IC chip mounting section, a high precision, finely detailed, and high density IC package board can be produced.
  • FIG. 9 is a cross-sectional diagram showing an IC package board (a semiconductor device mounting board) of a third embodiment of the present invention.
  • This IC package board differs from the IC board of the second embodiment in that whereas in the IC package board of the second embodiment, the IC chip 63 was fixed directly onto the inner layer substrate 50 which functions as the IC chip mounting section, in the IC package board of this embodiment, the IC chip 63 is fixed to the top of the inner layer substrate 50 , which functions as the IC chip mounting section, via an IC chip fixing adhesive 62 .
  • a multilayer interposer board 61 is first prepared in the same manner as described for the IC package board of the second embodiment, and then, as shown in FIG. 10A , the IC chip fixing adhesive 62 is applied to the top of the inner layer substrate 50 which functions as the IC chip mounting section, an IC chip 63 is mounted to a fixed position on this IC chip fixing adhesive 62 , and the IC chip 63 is then subjected to thermocompression bonding using a hot plate 68 at a predetermined temperature, such as a temperature within a range from 175 to 205° C., which is lower than the crystallization start temperature of the insulating substrate. As shown in FIG. 10B . the pins 64 of the IC chip 63 are connected electrically with the conductive circuit 46 .
  • a sealing resin agent 69 such as an epoxy resin is applied so as to cover the IC chip 63 and the IC chip fixing adhesive 62 , and this sealing resin agent 69 is then heated and cured, thereby forming a sealing resin 65 .
  • This third embodiment provides the same effects as those described for a multilayer wiring board of the first embodiment.
  • the IC chip 63 is fixed to the inner layer substrate 50 , which functions as an IC chip mounting section, via the IC chip fixing adhesive 62 , good insulation can be ensured by the IC chip fixing adhesive 62 even in those cases in which the insulation between the inner layer substrate 50 and the chip 63 is not totally reliable, and consequently a high precision, finely detailed, and high density IC package board can be produced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)

Abstract

A multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring. can be ideally applied to low volume high mix manufacturing configurations, and also has little impact on the environment is provided, together with a semiconductor device mounting board using such a multilayer wiring board, and a method of manufacturing such a multilayer wiring board. In the multilayer wiring board, grooves for forming a wiring circuit and via holes are formed in an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, a metallic foil is embedded within the grooves so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material formed by curing a conductive paste is used for filling the via holes.

Description

    CROSS-REFERENCE
  • This application is a divisional of U.S. patent application Ser. No. 10/925,644, now pending, filed Aug. 24, 2004, which is a divisional of U.S. patent application Ser. No. 10/357,183, filed Feb. 3, 2003, now U.S. Pat. No. 6,797,367, issued Sep. 28, 2004, which claims priority to Japanese Patent Application No. 2002-028235, filed Feb. 5, 2002, all of which are hereby incorporated by reference in their entirety.
  • FIELD OF THE INVENTION
  • The present invention relates to a multilayer wiring board, a semiconductor device mounting board using such a wiring board, and a method of manufacturing such a multilayer wiring board.
  • BACKGROUND OF THE INVENTION
  • In recent years, the trend towards increased miniaturization and functionality of electronic equipment has produced a growing demand for higher density mounting of electronic components on the mounting boards used for mounting such electronic equipment. In order to enable these electronic components to be mounted on the mounting boards with higher densities, there are calls not only for further miniaturization of the electronic components, but also for finer and higher precision wiring processing on the printed wiring boards.
  • On the other hand, in order to ensure a minimal environmental impact, these days it is also necessary to consider the recycling of the aforementioned mounting boards. Consequently, wiring boards comprising a thermoplastic resin as a primary material have been attracting considerable attention.
  • These wiring boards use a highly heat resistant thermoplastic resin known as super engineering plastic, and not only enable finely detailed, high precision wiring processing, but also offer a number of other advantages including a high degree of mechanical strength, superior electrical insulation, and comparative ease of recycling. As a result, in order to meet the demands for increased wiring density, considerable research is being conducted into the use of highly heat resistant thermoplastic resins as the substrate materials for printed wiring boards.
  • Examples of thermoplastic resins which are used as these substrate materials include liquid crystal polymers and thermoplastic polyamides.
  • Furthermore, in a printed wiring board using one of these thermoplastic resins, a predetermined wiring circuit is formed on top of the printed wiring board in a similar manner to a conventional general purpose printed wiring board, namely using a so-called wet process in which copper foil is laminated on top of the printed wiring board and the copper foil is then subjected to etching treatment using wet etching or the like to form the wiring pattern.
  • Other methods of forming the wiring circuit on the printed wiring board include methods in which the wiring circuit is formed by a dry process.
  • In these methods, screen printing techniques or dispensing techniques are used to print a conductive paste onto the printed wiring board in a predetermined wiring pattern, and this conductive paste is then subjected to heat treatment to complete the formation of a predetermined wiring circuit on the printed wiring board.
  • This method of printing on a conductive paste does not require the wet etching process used in conventional copper foil etching methods, and consequently the manufacturing process can be converted to a dry process, which offers the advantage of being even gentler on the environment.
  • The thermoplastic resin enables a shortening of the process tact, and also offers the advantages pf superior moldability and plasticity, and is consequently considered a very favorable material as a board substrate material.
  • However, although conventional highly heat resistant thermoplastic resins offer advantages as highly heat resistant substrate materials, when the thermoplastic resin is laminated and integrated into a single unit, the resin must be heated to a temperature close to the resin melting point to ensure thermal fusion, and a problem arises during this heating and thermal fusion in that a resin flow, resulting from the large reduction in the modulus of elasticity at temperatures near the melting point, may cause distortions in the conducting material which forms the wiring circuit.
  • In addition, conventional printed wiring board production lines are suited to high volume low mix production, and consequently there is tendency for the production facilities to increase in size. Furthermore, chemical etching (wet etching) and plating techniques are typically used during the formation of wiring circuits on the printed wiring boards, and these techniques are undesirable from the viewpoint of environmental impact.
  • Furthermore as described above, examples of methods for wiring formation using dry processes include screen printing methods and dispensing methods using a conductive paste, although in both of these methods, there is a limit to the improvements in detail and precision of the conductive wiring which can be achieved in order to try and meet the ever increasing demands for higher density mounting.
  • In addition, as described above, in a laminated product of a thermoplastic resin on which a wiring circuit has been formed using a conductive paste, the resin must be heated to a temperature close to the melting point and subjected to pressure to fuse the thermoplastic resin layers together to create a single integrated unit, and as the pitch of the wiring becomes finer, distortion of the wiring resulting from resin flow during lamination is increasingly becoming a factor which cannot be ignored in substrate design.
  • SUMMARY OF THE INVENTION
  • The present invention aims to resolve the problems described above. with an object of providing a multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, can be ideally applied to low volume high mix manufacturing configurations, and also has little impact on the environment. as well as providing a semiconductor device mounting board using such a multilayer wiring board, and a method of manufacturing such a multilayer wiring board.
  • As a result of intensive research, the inventors of the present invention realized that if a substrate formed from a thermoplastic resin could be combined with a wiring pattern formed from a conductive paste to produce a wiring board, then a high performance, environmentally friendly multilayer wiring board could be produced, and were hence able to complete the present invention.
  • In other words, in a multilayer wiring board of the present invention, a wiring circuit is formed by embedding conductive wiring within an insulating substrate, formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, so that the surface of the wiring protrudes to the surface of the resin, and a plurality of wiring substrates, formed by smoothing the surface of an insulating substrate comprising embedded conductive wiring are laminated together, and wiring is provided which electrically connects the wiring substrates (1, 2, 3, 4) to one another, and the insulating substrates of these wiring substrates are bonded together by thermal fusion and crystallized, and the conductive wiring of the wiring circuit of each wiring substrate and the wiring used for electrically connecting each of the wiring substrates together, is formed from a conductive material produced by curing a conductive paste.
  • In this type of multilayer wiring board, the insulating substrate which forms an essential component of the wiring substrate utilizes a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, and conductive wiring is embedded within the insulating substrate formed from this thermoplastic resin composition so that the surface of the wiring protrudes to the surface of the resin composition. By subsequently laminating a plurality of these wiring substrates and then bonding and crystallizing the wiring substrates through thermal fusion of the insulating substrates, a multilayer wiring board with excellent heat resistance, a high degree of mechanical strength and excellent electrical insulation can be achieved, and in addition, low temperature fusion is possible without the occurrence of resin flow, meaning the problem of wiring distortions resulting from such resin flow can be resolved, making high precisian, finely detailed conductive wiring possible. As a result, a multilayer wiring board with excellent electrical characteristics and reliability can be provided.
  • Furthermore, by appropriate selection of both the thermoplastic resin composition, and the type and shape of the conductive wiring, a variety of different wiring substrates can be formed, and as a result, by combining wiring substrates with different specifications. the present invention can be applied to multilayer wiring boards with a wide variety of specifications.
  • In addition, the combination of a variety of wiring substrates of different specifications makes the invention ideally suited to low volume high mix type manufacturing configurations. Furthermore, by using a conductive paste for the electrical connections, wiring formation using wet processes becomes unnecessary, meaning the environmental impact can be reduced.
  • The aforementioned insulating substrate should preferably utilize an amorphous film produced by molten mixing and then rapid cooling of a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260 PC and an amorphous polyetherimide resin as the primary constituents.
  • Furthermore, the conductive wiring of the present invention preferably comprises a conductive material formed by curing a conductive paste and a metallic foil, with at least the surface of the metallic foil protruding to the surface of the substrate.
  • A semiconductor device mounting board of the present invention comprises a multilayer wiring board of the present invention with a semiconductor device mounted thereon.
  • According to a semiconductor device mounting board of the present invention, because the semiconductor device is mounted on a multilayer wiring board of the present invention, a high precision, finely detailed and high density semiconductor device mounting board can be produced with relative ease.
  • A method of manufacturing a multilayer wiring board according to the present invention comprises the steps of performing thermal molding on either one surface or both surfaces of an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, at a temperature which is higher than the glass transition temperature of the thermoplastic resin composition but lower than the crystallization start temperature, thereby forming a conductive region comprising grooves, via holes, or a combination of grooves and via holes on the aforementioned one surface or both surfaces, subsequently filling the conductive region with a conductive paste and forming a wiring circuit in which the conductive paste functions as conductive wiring, thereby forming a wiring substrate comprising the insulating substrate and the wiring circuit, and subsequently laminating a plurality of these wiring substrates together, bonding and crystallizing the insulating substrates of these wiring substrates by thermal fusion at a temperature higher than the aforementioned crystallization start temperature, and electrically connecting the plurality of wiring substrates with conductive paste.
  • In this method of manufacturing a multilayer wiring board, a wiring substrate is generated by forming a wiring circuit comprising conductive wiring formed from a conductive paste on an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, and a plurality of these wiring substrates are then laminated together, and the insulating substrates of these wiring substrates are then bonded together and crystallized by thermal fusion at a temperature higher than the aforementioned crystallization start temperature, while each of the wiring substrates are electrically connected together with conductive paste. Consequently, a multilayer wiring board with excellent heat resistance, a high degree of mechanical strength, excellent electrical insulation, and with high precision and finely detailed conductive wiring can be produced with relative ease. As a result, a multilayer wiring board with excellent electrical characteristics and reliability can be produced with relative ease.
  • Furthermore, by appropriate selection of the number of insulating substrates and the wiring circuits formed thereon, a variety of different wiring substrates can be formed, and by combining these wiring substrates, multilayer wiring boards with a wide variety of specifications can be produced with relative ease, meaning low volume high mix multilayer wiring boards can be prepared easily, and within a relatively short time period. Furthermore, in the manufacturing process, by employing a dry process in which electrical connection is achieved via a conductive paste, wiring formation processes relying on wet processes become unnecessary, meaning the environmental impact of the manufacturing process is lessened considerably.
  • In this method of manufacturing a multilayer wiring board, the insulating substrate should preferably utilize an amorphous film produced by molten mixing and then rapid cooling of a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents.
  • Another method of manufacturing a multilayer wiring board according to the present invention comprises the steps of positioning an impressing jig on one surface of an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystal line melting peak temperature of at feast 260° C. and an amorphous polyetherimide resin as the primary constituents, with a metallic foil disposed therebetween, and positioning an elastic film, which displays a lower modulus of elasticity than the insulating substrate at temperatures lower than the glass transition temperature of the insulating substrate, on the other surface of the insulating substrate, subsequently using the impressing jig for performing thermal molding at a temperature which is higher than the glass transition temperature of the elastic film but lower than the crystallization start temperature of the insulating substrate, and subsequently peeling off the metallic foil, so that only those sections of the metallic foil in positions corresponding with convex sections of the impressing jig are fused to the insulating substrate.
  • According to this method of manufacturing a multilayer wiring board, an impressing jig is positioned on one surface of the insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, with a metallic foil disposed therebetween, and an elastic film, which displays a lower modulus of elasticity than the insulating substrate at temperatures lower than the glass transition temperature of the insulating substrate, is positioned on the other surface of the insulating substrate. and in this state, by carrying out thermal molding by pressing the impressing jig against the insulating substrate at a temperature which is higher than the glass transition temperature of the elastic film but lower than the crystallization start temperature of the insulating substrate, only those sections of the metallic foil in positions corresponding with convex sections of the impressing jig are fused firmly to the insulating substrate. Consequently, a multilayer wiring board with excellent heat resistance, a high degree of mechanical strength, excellent electrical insulation, and with high precision and finely detailed conductive wiring can be produced with relative ease. As a result, a multilayer wiring board with excellent electrical characteristics and reliability can be produced with relative ease.
  • Furthermore, by appropriate selection of the number of insulating substrates and the wiring circuits formed thereon, a variety of different insulating substrates and conductive wiring can be formed, and by combining these substrates and wiring, multilayer wiring boards with a wide variety of specifications can be produced with relative ease, meaning low volume high mix multilayer wiring boards can be prepared easily, and within a relatively short time period. Furthermore, in the manufacturing process, by employing a dry process in which electrical connection is achieved via a conductive paste, wiring formation processes relying on wet processes become unnecessary, meaning the environmental impact of the manufacturing process is lessened considerably.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional diagram showing a multilayer wiring board of a first embodiment of the present invention.
  • FIGS. 2A, 2B, 2C, and 2D are process diagrams showing a method of manufacturing a multi layer wiring board of the first embodiment of the present invention.
  • FIGS. 3A, 3B, 3C, 3D and 3E are process diagrams showing a method of manufacturing a multilayer wiring board of the first embodiment of the present invention.
  • FIG. 4 is a graph showing the temperature dependency of the modulus of elasticity of an insulating substrate and an elastic film.
  • FIGS. 5A, 5B, 5C, 5D, 5E, and 5F are process diagrams showing a method of manufacturing a multilayer wiring board of the first embodiment of the present invention.
  • FIGS. 6A and 6B are process diagrams showing a method of manufacturing a multilayer wiring board of the first embodiment of the present invention.
  • FIG. 7 is a cross-sectional diagram showing an IC package board of a second embodiment of the present invention.
  • FIGS. 8A, 8B, and 8C are process diagrams showing a method of manufacturing an IC package board of the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional diagram showing an IC package board of a third embodiment of the present invention.
  • FIGS. 10A and 10B are process diagrams showing a method of manufacturing an IC package board of the third embodiment of the present invention.
  • DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • As follows is a description of embodiments of a multilayer wiring board of the present invention, a semiconductor device mounting board using such a multilayer wiring board, and a method of manufacturing a multilayer wiring board.
  • First Embodiment
  • FIG. 1 is a cross-sectional diagram showing a multilayer wiring board according to a first embodiment of the present invention. In the figure, symbol 1 represents an uppermost layer substrate (a wiring substrate of the uppermost layer), symbol 2 represents a lowest layer substrate (a wiring substrate of the lowest layer), and symbols 3 and 4 represent inner layer substrates (wiring substrates) sandwiched between the uppermost layer substrate 1 and the lowest layer substrate 4.
  • The uppermost layer substrate 1 is typically a film, a thin plate or a sheet of a thickness of no more than 100 μm, wherein grooves 12 for forming a wiring circuit are. formed in one surface (the upper surface in the figure) of an insulating substrate 11 formed from a film, a thin plate or a sheet of a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, via holes (through holes) 13 are formed which pass through the insulating substrate 11, a metallic foil 14 is embedded within the grooves 12 so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material 15 formed by curing a conductive paste is used to fill the via holes 13. The upper and lower surfaces of the insulating substrate 11, including the metallic foil 14, have been smoothed and flattened.
  • The lowest layer substrate 2 is of exactly the same construction as the uppermost layer substrate 1, and differs only in the fact that the grooves 12 for forming the wiring circuit are formed in the lower surface of the insulating substrate 11.
  • The inner layer substrate 3 is typically a film, a thin plate or a sheet of a thickness of no more than 100 μm, wherein grooves 12 for forming a wiring circuit are formed in one surface (the upper surface in the figure) of an insulating substrate 11 formed from a film, a thin plate or a sheet of an identical thermoplastic resin composition to the uppermost layer substrate 1, via holes 13 which pass through the insulating substrate 11 are formed in a portion of the grooves 12, and a conductive material 15 formed by curing a conductive paste is used to, fill the grooves 12 and the via holes 13. The upper and lower surfaces of the conductive paste 15, including the metallic foil 14, have been smoothed and flattened.
  • The inner layer substrate 4 is of exactly the same construction as the inner layer substrate 3 described above, and differs only in the fact that the grooves 12 for forming the wiring circuit are formed in the lower surface of the insulating substrate 11.
  • The lowest layer substrate 2, the inner layer substrates 4 and 3, and the uppermost layer substrate 1 are laminated together in that sequence, and then bonded together and integrated into a single unit by thermal fusion, and the wiring circuits of each of the substrates 1 to 4, and the wiring for establishing the electrical connections between each set of adjacent substrates 1 to 4 is formed from the conductive material 15 produced by curing a conductive paste.
  • The polyarylketone resin with a crystalline melting peak temperature of at least 260° C., which represents one of the primary constituents of the thermoplastic resin composition used for forming the insulating substrate 11, is a thermoplastic resin comprising an aromatic linkage, an ether linkage and a ketone linkage within the structural unit, and representative examples include polyetherketones, polyetheretherketones and polyetherketoneketones. Examples of commercially available polyetheretherketones include PEEK151G, PEEK381G, and PEEK450G (all of which are manufactured by Victrex Co., Ltd.)
  • The amorphous polyetherimide resin is an amorphous thermoplastic resin comprising an aromatic linkage. an ether linkage and an imide linkage within the structural unit, and there are no other particular restrictions on the structure. Examples of commercially available polyetherimides include Ultem CRS5001 and Ultem 1000 (both manufactured by General Electric Company).
  • The actual resin composition of the thermoplastic resin composition described above is preferably produced by mixing 20 to 50 parts by weight of an inorganic filler with 100 parts by weight of a thermoplastic resin composition formed from 70 to 25% by weight of the polyarylketone resin and 30 to 75% by weight of the amorphous polyetherimide resin.
  • The reason that the content of the polyarylketone resin is restricted to within a range from 70 to 25% by weight is because if the content exceeds 70% by weight, then the crystallinity becomes very high, making lamination more difficult when producing a multilayer structure, whereas if the content is less than 25% by weight, then the crystallinity of the overall composition falls, and the reflow heat resistance decreases even if the crystalline melting peak temperature is greater than 260° C.
  • Similarly, the reason that the content of the amorphous polyetherimide resin is restricted to within a range from 30 to 75% by weight is because if the content is less than 30% by weight, then the crystallinity becomes very high, making lamination more difficult when producing a multilayer structure, whereas if the content exceeds 75% by weight, then the crystallinity of the overall composition falls, and the reflow heat resistance decreases even if the crystalline melting peak temperature is greater than 260° C.
  • Inorganic fillers can also be added to a thermoplastic resin composition such as that described above.
  • There are no particular restrictions on the type of inorganic filler, and any known filler can be used. Specific examples of such inorganic fillers include talc, mica, glass flakes, boron nitride (BN), calcium carbonate flakes, aluminum hydroxide flakes, silica flakes, and potassium titanate flakes. These fillers may be used singularly, or in combinations of two or more different fillers. Scale-like flakes of inorganic fillers with an average particle diameter of no more than 15 μm and an aspect ratio (particle diameter/thickness) of more than 30 are particularly preferred, as they enable the ratio of the coefficients of linear expansion ratio in the in-plane direction and the thickness direction to be suppressed to a low level, thereby suppressing the occurrence of cracking within the board during thermal shock cycle testing.
  • The quantity of these types of inorganic fillers added is preferably within a range from 20 to 50 parts by weight per 100 parts by weight of the thermoplastic resin composition. If the quantity exceeds 50 parts by weight, then problems including unsatisfactory dispersion of the inorganic filler develop, and the coefficient of linear expansion is more likely to vary. In contrast, if the quantity of the filler is less than 20 parts by weight, then the difference in the coefficients of linear expansion of the glass stamper used in the thermal molding process and the insulating substrate 11 can cause a contraction in the dimensions of the insulating substrate 11; and the effect of the invention in reducing the coefficient of linear expansion and improving the dimensional stability is diminished, and in addition, internal stress develops during the reflow process as a result a of the difference in the coefficient of linear expansion, making the board more susceptible to warping and twisting.
  • Other resins, and additives other than the inorganic fillers described above may also be added to a thermoplastic resin composition of the present invention, provided such addition does not impair the properties of the composition, and examples of these other additives include stabilizers. ultraviolet light absorbers, light stabilizers, nucleation agents, coloring agents, lubricants and flame retardants.
  • Each of these additives, including the inorganic filters, can be added using known methods, such as the methods (a) and (b) described below.
  • (a) A method in which each of the additives is mixed at a high concentration (for example, a quantity of 10 to 60% by weight) with the polyarylketone resin and/or the amorphous polyetherimide resin to generate a master batch, and this master batch is then mixed with the resins to be used and the concentration adjusted appropriately, before the mixture is finally blended mechanically using a kneader or an extruder.
  • (b) A method in which each of the additives is added directly to the resins to be used, and then blended mechanically using a kneader or &I extruder.
  • Of these two methods, the method (a) is preferable in terms of dispersibility and workability. In addition, the surface of the insulating substrate 11 may also be subjected to appropriate embossing or corona treatment or the like, in order to improve handling.
  • Furthermore, the aforementioned conductive material 15 is produced by heating and curing a conductive paste. and examples of suitable conductive pastes include resin based low temperature curing pastes such as silver (Ag) paste, silver (Ag)-palladium (Pd) paste, and copper (Cu) paste.
  • Next is a description of a method of manufacturing a multilayer wiring board of this embodiment, based on FIGS. 2A-2D through FIGS. 6A-6B.
  • First is a description of a method of manufacturing the outermost layer substrates (the uppermost layer substrate and the lowest layer substrate) and the inner layer substrates, followed by a description of a method of manufacturing a multilayer wiring board using these outermost layer substrates and inner layer substrates.
  • (1) Method of Manufacturing an Outermost Layer Substrate
  • First, as shown in FIG. 2A, an insulating substrate 21 formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents is prepared.
  • This insulating substrate 21 is provided as a film, a thin plate or a sheet. Examples of suitable methods for molding the substrate include conventionally known methods such as extrusion casting methods using a T die, or calender methods, and although there are no particular restrictions on the method employed, extrusion casting methods using a T die are preferred from the viewpoints of sheet film formation and production stability. The molding temperature in such a casting method using a T die can be suitably adjusted in accordance with the fluidity and the film formation properties of the composition, although generally, the temperature should be greater than the crystalline melting peak temperature of the polyarylketone resin (260° C.), but no more than 430° C.
  • Next, as shown in FIG. 2B, a laser or a mechanical drill or the like is used to open through holes 22 in predetermined positions within the insulating substrate 21, which then function as via holes 13.
  • Next, as shown in FIG. 2C, the via holes 13 are filled with a conductive paste 23 using a squeegee printing technique or the like. Subsequently, this conductive paste 23 is heated for 30 to 60 minutes at a temperature of 120 to 160° C., thereby forming a conductive material 15.
  • Subsequently, any residual conductive material 15 left on the surface of the insulating substrate 21 is ground off and removed using a technique such as mechanical polishing. yielding a wiring substrate 24 with the via holes 13 filled with a conductive material 15 formed by curing a conductive paste, and with the surface of the insulating substrate 21 smoothed to a predetermined surface roughness.
  • Next, as shown in FIG. 3A, an impressing jig 32 with texture formed on one of the principal surfaces is positioned on top (on one surface) of the insulating substrate 21 with a metallic foil 31 disposed therebetween, while an elastic film 33 which displays a lower modulus of elasticity than the insulating substrate 21 at temperatures lower than the glass transition temperature (Tg1) of the insulating substrate 21 is positioned on the lower surface (the other surface) of the insulating substrate 21. Subsequently, as shown in FIG. 3B, the impressing jig 32 is pressed against the insulating substrate 21, and thermal molding is performed at a temperature greater than the glass transition temperature (Tg2) of the elastic film 33 but lower than the crystallization start temperature (Tcs) of the insulating substrate 21.
  • Here, the glass transition temperature (Tg1) and the crystallization start temperature (Tcs) of the insulating substrate 21, and the glass transition temperature (Tg2) of the elastic film 33 can be measured using differential scanning calorimetry (DSC). These temperatures can be determined from the DSC profile obtained by heating a measurement sample at a heating rate of 10° C./minute, for example.
  • For example, in the case of an insulating substrate comprising 40% by weight of a polyarylketone resin with a crystalline melting peak temperature of at least 260° C., and 60% by weight of an amorphous polyetherimide resin, the glass transition temperature (Tg1) is 185° C. and the crystallization start temperature (Tcs) is 225° C.
  • Furthermore, provided the elastic film 33 displays a lower modulus of elasticity than the insulating substrate 21 at temperatures lower than the glass transition temperature (Tg1) of the insulating substrate 21, then any film is acceptable, and an elastic film formed from a syndiotactic polystyrene is an ideal example. The glass transition temperature (Tg2) of this elastic film 33 is 100° C.
  • FIG. 4 is a graph showing the temperature dependency of the modulus of elasticity of the insulating substrate 2 I and the elastic film 33. In the figure. A represents the curve for an insulating substrate comprising 40% by weight of a polyarylketone resin with a crystalline melting peak temperature of at least 260° C., and 60% by weight of an amorphous polyetherimide resin, and B represents the curve for an elastic film formed from a syndiotactic polystyrene.
  • As shown in FIG. 4, the elastic film 33 undergoes softening prior to the softening of the insulating substrate 21, and as a result, the insulating substrate 21 flexes, but plastic deformation does not occur, and consequently the metallic foil 31 is able to cut efficiently.
  • The temperature of thermal molding is preferably greater than the glass transition temperature (Tg2) of the elastic film 33, and lower than the crystallization start temperature (Tcs) of the insulating substrate 21, and even more preferably, should be lower than the glass transition temperature (Tg1) of the insulating substrate 21.
  • As a result of thermal molding, a pattern is stamped into the metallic foil 31, as shown in FIG. 3C, due to the difference in the modulus of elasticity between the elastic film 33 and the insulating substrate 21, and a difference in fusion strength develops which corresponds with the differing pressure applied by the texture of the impressing jig 32. For example, the metallic foil 31 a embedded within the insulating substrate 21 has a high fusion strength and is bonded strongly to the insulating substrate 21, whereas the remaining sections of the metallic foil 31 b have only very weak fusion strength, and can be easily stripped away from the insulating substrate 21.
  • Consequently, as shown in FIG. 3D, the unnecessary metallic foil 31 b can be easily stripped off the insulating substrate 21 and removed.
  • The conductive material 15 formed by curing a conductive paste and a via hole 13 need not necessarily exist beneath the metallic foil 31, although by ensuring that the conductive material 15 is present beneath the entire metallic foil 31. the difference in fusion strength is magnified, and the unnecessary metallic foil 31 b can be removed even more easily, Furthermore, there are no particular restrictions on the type or the thickness of the metallic foil 31, although the thickness of the metallic foil 31 is preferably less than the thickness provided by the height difference of the texture of the impressing jig 32. For example, in the case of a height difference of the texture of the impressing jig 32 of 50 μm, a surface roughened conductive copper foil (metallic foil) with a thickness of 9 to 35 μm was used, although even with other thickness values, stripping of the unnecessary conductive copper fail was still possible.
  • Following removal of the unnecessary metallic foil 31 b from the insulating substrate 21, as shown in FIG. 3E, both surfaces of the insulating substrate 21 including the metallic foil 31 and the conductive material 15 are subjected to thermal molding using a molding die not shown in the figure, at a pressure of 0.5 to 10 kg/cm2 and at a temperature lower than the crystallization start temperature (Tcs) of the insulating substrate 21, thereby smoothing and flattening both surfaces of the insulating substrate 21 including the metallic foil 31 a and the conductive material 15.
  • Using the steps described above, the metallic foil 14 can be embedded in an outermost layer substrate, namely the substrate 21, with the surface of the foil protruding to the surface of the insulating substrate, and an uppermost layer substrate 34 (or a lowest layer substrate 35) with the via holes 13 filled with the conductive material 15 can be produced.
  • (2) Method of Manufacturing an Inner Layer Substrate
  • First, as is shown in FIG. 5A, convex sections 42 of a stamper 41 are thermally transferred to a surface (one surface) of an insulating substrate 21 formed from an identical thermoplastic resin composition to that used for the outermost layer substrates described above. The conditions for this thermal transfer include, for example, a temperature of 175 to 205° C. and a pressure of 20 to 60 kg/cm2.
  • This thermal transfer forms wiring circuit formation grooves 43 in the surface of the insulating substrate 21, as shown in FIG. 5B.
  • The stamper 41 is constructed from a material with good releasability relative to the insulating substrate 21 such as glass or ceramic. Heat resistant glass of thickness 3 to 5 mm is particularly suitable. The stamper 41 is produced by forming a resist mask on the surface of a heat resistant glass plate using photolithography techniques, and subsequently forming the convex sections 42 which correspond with the wiring circuit pattern using sand blasting techniques or the like.
  • Next, as shown in FIG. 5C, a laser or a mechanical drill or the like is used to open through holes 44 in predetermined positions within the insulating substrate 21, which then function as via holes 13. These via holes 13 may also be formed by the stamper 41, at the same time as the formation of the wiring circuit formation grooves 43.
  • Next, as shown in FIG. 5D, the wiring circuit formation grooves 43 and the via holes 13 are filled with a conductive paste 45 using a squeegee printing technique or the like. Subsequently, this conductive paste 45 is heated for 30 to 60 minutes at a temperature of 120 to 160° C., thereby forming a conductive material 15. This process enables the formation of a conductive circuit 46 and interlayer continuity sections 47 at predetermined positions on the insulating substrate 21.
  • Subsequently, as shown in FIG. 5E, a sanding device 48 is used to grind off and remove any residual conductive material 15 left on the surface of the insulating substrate 21, and smooth the surface of the insulating substrate 21, yielding an inner layer substrate 49 (or an inner layer substrate 50) with a conductive circuit 46 and interlayer continuity sections 47 formed at predetermined positions on the insulating substrate 21.
  • (3) Method of Manufacturing a Multilayer Wiring Board
  • First, as shown in FIG. 6A, a cushion film 52 with good elasticity and releasability, a lowest layer substrate 35, an inner layer substrate 49, an inner layer substrate 50, an uppermost layer substrate 34, and another cushion film 52 with good elasticity and releasability are overlaid, in the above sequence, within a lamination jig 51. Subsequently, the layers from the lowest layer substrate 35 through to the uppermost layer substrate 34 are bonded together and integrated into a single unit by thermal fusion under conditions including a temperature of 200 to 260° C. and a pressure of 20 to 60 kg/cm2.
  • Using the above process, a multilayer wiring board 53 can be produced comprising the lowest layer substrate 35, the inner layer substrate 49, the inner layer substrate 50 and the uppermost layer substrate 34 which have been bonded together and then integrated into a single unit by thermal fusion.
  • According to the present embodiment, the grooves 12 for forming a wiring circuit are formed in the insulating substrate 11 formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, the via holes 13 which pass through the insulating substrate 11 are formed, the metallic foil 14 is embedded within the grooves 12 so that the surface of the foil protrudes to the surface of the insulating substrate, and the conductive material 15 formed by curing a conductive paste is used to fill the via holes 13, thereby generating a wiring substrate, and consequently a multilayer wiring board with excellent heat resistance, a high degree of mechanical strength and excellent electrical insulation, which is capable of low temperature fusion without the occurrence of resin flow, enables the problems resulting from resin flow such as wiring distortion to be resolved, and enables high precision, finely detailed conductive wiring can be produced. As a result, a multilayer wiring board with excellent electrical characteristics and reliability can be provided.
  • Furthermore. by appropriate selection of both the thermoplastic resin composition, and the type and shape of the conductive wiring, a variety of different wiring substrates can be formed, and as a result, by combining wiring substrates with different specifications, the present invention can be applied to multilayer wiring boards with a wide variety of specifications.
  • In addition. the combination of a variety of wiring substrates of different specifications makes the invention ideally suited to low volume high mix type manufacturing configurations. Furthermore, by using a conductive paste for the electrical connections, wiring formation using wet processes becomes unnecessary, meaning the environmental impact can be reduced.
  • Second Embodiment
  • FIG. 7 is a cross-sectional diagram showing an 1C package board (a semiconductor device mounting board) of a second embodiment of the present invention.
  • This IC package board is a multilayer interposer board 61 comprising a lowest layer substrate 35, an inner layer substrate 49 and an inner layer substrate 50 laminated together in this sequence and integrated into a single unit by thermal fusion, and an IC chip (semiconductor device) 63 is fixed directly to the top of the inner layer substrate 50 which functions as an IC chip (semiconductor device) mounting section, so that the pins (terminals) 64 of the IC chip 63 and the conductive circuit 46 are electrically connected, and the IC chip 63 is then sealed with a sealing resin 65 such as an epoxy resin.
  • In order to manufacture this IC package board, first, as shown in FIG. 8A, a cushion film 52 with good elasticity and releasability, a lowest layer substrate 35, an inner layer substrate 49, an inner layer substrate 50, and another cushion film 52 with good elasticity and releasability are overlaid, in the above sequence, within a lamination jig 51. Subsequently, the layers from the lowest layer substrate 35 through to the inner layer substrate 50 are bonded together and integrated into a single unit by thermal fusion under conditions including a temperature of 200 to 260° C. and a pressure of 20 to 60 kg/cm2, thereby forming the multilayer interposer board 61.
  • Next, as shown in FIG. 8B, the IC chip 63 is mounted on top of the inner layer substrate 50 which functions as an IC chip mounting section, and this IC chip 63 is then subjected to thermocompression bonding using a hot plate 68 at a predetermined temperature, such as a temperature within a range from 175 to 205° C., which is lower than the crystallization start temperature of the insulating substrate. As shown in FIG. 8C, the pins 64 of the IC chip 63 are connected electrically with the conductive circuit 46.
  • Next, a sealing resin agent 69 such as an epoxy resin is applied so as to cover the IC chip 63, and this sealing resin agent 69 is then heated and cured, thereby forming the sealing resin 65.
  • In this manner, by keeping the temperature during the mounting of the IC chip 63 to a temperature of 175 to 205° C., lower than the crystallization start temperature of the insulating substrate, subsequent low temperature lamination becomes possible. Furthermore, a rapid heat curing type epoxy resin could also be supplied to the top of the inner layer substrate 50 and then bonded by thermocompression bonding.
  • This second embodiment provides the same effects as those described for a multilayer wiring board of the first embodiment.
  • Moreover, because an IC chip 63 is fixed directly onto the inner layer substrate 50 which functions as an IC chip mounting section, a high precision, finely detailed, and high density IC package board can be produced.
  • Third Embodiment
  • FIG. 9 is a cross-sectional diagram showing an IC package board (a semiconductor device mounting board) of a third embodiment of the present invention.
  • This IC package board differs from the IC board of the second embodiment in that whereas in the IC package board of the second embodiment, the IC chip 63 was fixed directly onto the inner layer substrate 50 which functions as the IC chip mounting section, in the IC package board of this embodiment, the IC chip 63 is fixed to the top of the inner layer substrate 50, which functions as the IC chip mounting section, via an IC chip fixing adhesive 62.
  • In order to manufacture this IC package board, a multilayer interposer board 61 is first prepared in the same manner as described for the IC package board of the second embodiment, and then, as shown in FIG. 10A, the IC chip fixing adhesive 62 is applied to the top of the inner layer substrate 50 which functions as the IC chip mounting section, an IC chip 63 is mounted to a fixed position on this IC chip fixing adhesive 62, and the IC chip 63 is then subjected to thermocompression bonding using a hot plate 68 at a predetermined temperature, such as a temperature within a range from 175 to 205° C., which is lower than the crystallization start temperature of the insulating substrate. As shown in FIG. 10B. the pins 64 of the IC chip 63 are connected electrically with the conductive circuit 46.
  • Next, a sealing resin agent 69 such as an epoxy resin is applied so as to cover the IC chip 63 and the IC chip fixing adhesive 62, and this sealing resin agent 69 is then heated and cured, thereby forming a sealing resin 65.
  • This third embodiment provides the same effects as those described for a multilayer wiring board of the first embodiment.
  • Moreover, because the IC chip 63 is fixed to the inner layer substrate 50, which functions as an IC chip mounting section, via the IC chip fixing adhesive 62, good insulation can be ensured by the IC chip fixing adhesive 62 even in those cases in which the insulation between the inner layer substrate 50 and the chip 63 is not totally reliable, and consequently a high precision, finely detailed, and high density IC package board can be produced.

Claims (18)

1. A method of manufacturing a multilayer wiring board comprising the steps of:
positioning an impressing jig on one surface of an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as primary constituents, with a metallic foil disposed therebetween, and positioning an elastic film, which displays a lower modulus of elasticity than said insulating substrate at temperatures lower than a glass transition temperature of said insulating substrate, on another surface of said insulating substrate,
subsequently using said impressing jig for performing thermal molding at a temperature which is higher than a glass transition temperature of said elastic film but lower than a crystallization start temperature of said insulating substrate, and
subsequently peeling off said metallic foil, so that only sections of said metallic foil in positions corresponding with convex sections of said impressing jib are fused to said insulating substrate.
2. The method of claim 1 wherein the insulating substrate has a thickness of about 100 μm or less.
3. The method of claim 1 wherein the insulating substrate is formed from an amorphous film produced by molten mixing and rapid cooling of the thermoplastic resin composition.
4. The method of claim 1 wherein the thermoplastic resin composition further comprises an inorganic filler.
5. The method of claim 4 wherein the inorganic filler is about 15 to 35% by weight of the thermoplastic resin composition.
6. The method of claim 4 wherein the inorganic filler has an average particle diameter of about 15 μm or less and an aspect ratio of about 30 or greater.
7. The method of claim 4 wherein the thermoplastic resin composition is formed by mixing about 100 parts by weight of a composition comprising the polyarylketone resin and the amorphous polyetherimide resin with about 20 to 50 parts by weight of the inorganic filler.
8. The method of claim 7 wherein the composition comprising the polyarylketone resin and the amorphous polyetherimide resin is formed from about 25 to 70% by weight of the polyarylketone resin.
9. The method of claim 8 wherein the composition comprising the polyarylketone resin and the amorphous polyetherimide resin is formed from about 30 to 75% by weight of the amorphous polyetherimide resin.
10. The method of claim 1 wherein the polyarylketone resin is selected from the group consisting of: a polyetherketone resin, a polyetheretherketone resin and a polyetherketoneketone resin.
11. The method of claim 1 wherein the glass transition temperature of the insulating substrate, the glass transition temperature of the elastic film, and the crystallization start temperature of the insulating substrate are measured using differential scanning calorimetry (DSC).
12. The method of claim 1 wherein the elastic film is formed from a syndiotactic polystyrene.
13. The method of claim 1 wherein the thermal molding is performed at a temperature lower than the glass transition temperature of the insulating substrate.
14. The method of claim 1 wherein the thermal molding is performed at a pressure of 0.5 to 10 kg/cm2.
15. The method of claim 1 wherein the thickness of the metallic foil is less than the height difference of the texture of the impressing jig.
16. The method of claim 1, further comprising forming a wiring substrate on said insulating substrate by forming via holes within the insulating substrate, filling the via holes with a conductive paste, and heating the conductive paste to form a conductive material.
17. The method of claim 16, further comprising laminating a plurality of said wiring substrates together, bonding and crystallizing the insulating substrates of said wiring substrates by thermal fusion at a temperature higher than said crystallization start temperature.
18. The method of claim 17 wherein the thermal fusion is performed at a temperature of about 200 to 260° C. and a pressure of about 20 to 60 kg/cm2.
US11/943,410 2002-02-05 2007-11-20 Method of Manufacturing Multilayer Wiring Board Abandoned US20080116611A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/943,410 US20080116611A1 (en) 2002-02-05 2007-11-20 Method of Manufacturing Multilayer Wiring Board

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2002-028235 2002-02-05
JP2002028235A JP4181778B2 (en) 2002-02-05 2002-02-05 Wiring board manufacturing method
US10/357,183 US6797367B2 (en) 2002-02-05 2003-02-03 Multilayer wiring board, semiconductor device mounting board using same, and method of manufacturing multilayer wiring board
US10/925,644 US7334324B2 (en) 2002-02-05 2004-08-24 Method of manufacturing multilayer wiring board
US11/943,410 US20080116611A1 (en) 2002-02-05 2007-11-20 Method of Manufacturing Multilayer Wiring Board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/925,644 Division US7334324B2 (en) 2002-02-05 2004-08-24 Method of manufacturing multilayer wiring board

Publications (1)

Publication Number Publication Date
US20080116611A1 true US20080116611A1 (en) 2008-05-22

Family

ID=27749517

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/357,183 Expired - Fee Related US6797367B2 (en) 2002-02-05 2003-02-03 Multilayer wiring board, semiconductor device mounting board using same, and method of manufacturing multilayer wiring board
US10/925,644 Expired - Fee Related US7334324B2 (en) 2002-02-05 2004-08-24 Method of manufacturing multilayer wiring board
US11/943,410 Abandoned US20080116611A1 (en) 2002-02-05 2007-11-20 Method of Manufacturing Multilayer Wiring Board

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10/357,183 Expired - Fee Related US6797367B2 (en) 2002-02-05 2003-02-03 Multilayer wiring board, semiconductor device mounting board using same, and method of manufacturing multilayer wiring board
US10/925,644 Expired - Fee Related US7334324B2 (en) 2002-02-05 2004-08-24 Method of manufacturing multilayer wiring board

Country Status (4)

Country Link
US (3) US6797367B2 (en)
JP (1) JP4181778B2 (en)
KR (1) KR100935837B1 (en)
TW (1) TWI267331B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8867219B2 (en) * 2011-01-14 2014-10-21 Harris Corporation Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI312166B (en) * 2001-09-28 2009-07-11 Toppan Printing Co Ltd Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board
JP4401070B2 (en) * 2002-02-05 2010-01-20 ソニー株式会社 Multilayer wiring board with built-in semiconductor device and manufacturing method thereof
JP4268434B2 (en) * 2003-04-09 2009-05-27 大日本印刷株式会社 Wiring board manufacturing method
EP1633175A4 (en) * 2003-09-29 2009-11-11 Ibiden Co Ltd Interlayer insulating layer for printed wiring board, printed wiring board and method for manufacturing same
US7321496B2 (en) * 2004-03-19 2008-01-22 Matsushita Electric Industrial Co., Ltd. Flexible substrate, multilayer flexible substrate and process for producing the same
JP4559163B2 (en) * 2004-08-31 2010-10-06 ルネサスエレクトロニクス株式会社 Package substrate for semiconductor device, method for manufacturing the same, and semiconductor device
CN101069075B (en) * 2004-12-08 2012-05-30 Abb专利有限公司 Method for producing a measuring transducer
JP4768994B2 (en) * 2005-02-07 2011-09-07 ルネサスエレクトロニクス株式会社 Wiring board and semiconductor device
US7714451B2 (en) * 2005-02-18 2010-05-11 Stats Chippac Ltd. Semiconductor package system with thermal die bonding
US7225536B2 (en) * 2005-04-07 2007-06-05 Ho-Ching Yang Precasting multi-layer PCB process
TWI298334B (en) * 2005-07-05 2008-07-01 Chang Chun Plastics Co Ltd Polyamic acid resin composition modified with laminate nanometer silica sheet and polyimide prepared therefrom
TWI277373B (en) * 2005-09-16 2007-03-21 Foxconn Advanced Tech Inc Method of continuous producing flexible printed circuit board
TWI272887B (en) * 2005-12-09 2007-02-01 High Tech Comp Corp Printed circuit board and manufacturing method thereof
TWI285424B (en) * 2005-12-22 2007-08-11 Princo Corp Substrate including a multi-layer interconnection structure, methods of manufacturing and recycling the same, method of packaging electronic devices by using the same, and method of manufacturing an interconnection device
JP5003082B2 (en) * 2006-09-26 2012-08-15 富士通株式会社 Interposer and manufacturing method thereof
KR100771467B1 (en) * 2006-10-30 2007-10-30 삼성전기주식회사 Circuit board and method for manufacturing there of
WO2008061004A2 (en) * 2006-11-09 2008-05-22 Stanley Fastening Systems, L.P. Cordless fastener driving device
US8312623B2 (en) * 2007-03-29 2012-11-20 Fry's Metals, Inc. Methods for producing electrical conductors
JP5324051B2 (en) * 2007-03-29 2013-10-23 新光電気工業株式会社 Wiring substrate manufacturing method, semiconductor device manufacturing method, and wiring substrate
US8227703B2 (en) * 2007-04-03 2012-07-24 Sumitomo Bakelite Company, Ltd. Multilayered circuit board and semiconductor device
TWI334324B (en) * 2007-09-19 2010-12-01 Unimicron Technology Corp Printed circuit board and method of fabricating the same
KR100897316B1 (en) * 2007-10-26 2009-05-14 삼성전기주식회사 Manufacturing method of PCB
KR100923501B1 (en) * 2007-11-13 2009-10-27 삼성전기주식회사 Manufacturing method of package board
US20110042124A1 (en) * 2007-12-05 2011-02-24 Mitsubishi Plastics, Inc. Multilayer wiring substrate having cavity portion
TWI342729B (en) * 2008-02-19 2011-05-21 Unimicron Technology Corp Manufacturing method of circuit board
US8932906B2 (en) 2008-08-19 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via bonding structure
JP5481854B2 (en) * 2008-12-16 2014-04-23 Tdk株式会社 Electronic components
US20100300734A1 (en) * 2009-05-27 2010-12-02 Raytheon Company Method and Apparatus for Building Multilayer Circuits
EP3570649A1 (en) * 2009-11-10 2019-11-20 Murata Manufacturing Co., Ltd. Multilayer board and manufacturing method thereof
WO2011062252A1 (en) * 2009-11-19 2011-05-26 株式会社村田製作所 Manufacturing method of module with built-in parts, and module with built-in parts
KR101624910B1 (en) * 2009-12-04 2016-05-30 삼성전자주식회사 Fuse structure and method of forming the same
US9793199B2 (en) * 2009-12-18 2017-10-17 Ati Technologies Ulc Circuit board with via trace connection and method of making the same
WO2011118785A1 (en) * 2010-03-26 2011-09-29 パナソニック電工株式会社 Glass substrate having silicon wiring embedded therein and method for manufacturing the glass substrate
KR20120051991A (en) * 2010-11-15 2012-05-23 삼성전기주식회사 Printed circuit board and method for manufacturing the same
JP5775747B2 (en) * 2011-06-03 2015-09-09 新光電気工業株式会社 Wiring board and manufacturing method thereof
CN104869762A (en) * 2014-02-24 2015-08-26 联想(北京)有限公司 Preparation method and structure of PCB and electronic equipment
KR102194719B1 (en) * 2014-06-12 2020-12-23 삼성전기주식회사 Package board and package using the same
US9847244B2 (en) * 2015-07-15 2017-12-19 Chip Solutions, LLC Semiconductor device and method
WO2017217126A1 (en) * 2016-06-17 2017-12-21 株式会社村田製作所 Method for manufacturing resin multilayer substrate
US9997442B1 (en) * 2016-12-14 2018-06-12 Advanced Semiconductor Engineering, Inc. Semiconductor device and method of manufacturing the same
CN219204859U (en) 2020-06-03 2023-06-16 株式会社村田制作所 Multilayer substrate

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444732A (en) * 1967-06-06 1969-05-20 Albert L Robbins Method and apparatus for determining optimum bonding parameters for thermoplastic material
US5325583A (en) * 1990-09-28 1994-07-05 Kabushiki Kaisha Toshiba Method for manufacturing printed circuit board
US5773882A (en) * 1994-04-28 1998-06-30 Kabushiki Kaisha Toshiba Seminconductor package
US6143116A (en) * 1996-09-26 2000-11-07 Kyocera Corporation Process for producing a multi-layer wiring board
US6207259B1 (en) * 1998-11-02 2001-03-27 Kyocera Corporation Wiring board
US6228467B1 (en) * 1998-01-21 2001-05-08 Mitsubishi Plastics, Inc. Heat-resistant insulating film, raw substrate for printed wiring board using the same and method for producing the substrate
US6359235B1 (en) * 1999-07-30 2002-03-19 Kyocera Corporation Electrical device mounting wiring board and method of producing the same
US6591491B2 (en) * 2000-03-22 2003-07-15 Nitto Denko Corporation Method for producing multilayer circuit board

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541572A (en) 1990-09-28 1993-02-19 Toshiba Corp Manufacture of printed circuit board and manufacture of multilayer printed circuit board
JPH05275834A (en) 1992-03-27 1993-10-22 Toshiba Corp Formation of metal pattern
JPH0955569A (en) 1995-08-11 1997-02-25 Hitachi Ltd Thin film wiring sheet, multilayer wiring board and their production
JP2728074B2 (en) * 1995-12-28 1998-03-18 日本電気株式会社 Stack structure of tape carrier package
JPH1140745A (en) * 1997-07-17 1999-02-12 Hitachi Ltd Semiconductor device and electronic device incorporating the same
JP3514647B2 (en) 1999-01-05 2004-03-31 三菱樹脂株式会社 Multilayer printed wiring board and method of manufacturing the same
JP3514656B2 (en) 1999-03-26 2004-03-31 三菱樹脂株式会社 Surface smooth wiring board and its manufacturing method
JP2001119148A (en) * 1999-10-14 2001-04-27 Sony Corp Multilayer board incorporating ic chips and production method therefor
JP2001196703A (en) 2000-01-14 2001-07-19 Sony Corp Printed wiring board and manufacturing method for the same
JP2001230520A (en) 2000-02-14 2001-08-24 Sony Corp Method of manufacturing wiring board and wiring board obtained thereby
JP2001244609A (en) 2000-02-25 2001-09-07 Sony Corp Method of manufacturing wiring board and wiring board obtained with the same method
JP2001257448A (en) 2000-03-10 2001-09-21 Sony Corp Method for manufacturing printed wiring board and printed wiring board obtained thereby
JP2002248626A (en) 2001-02-26 2002-09-03 Sony Corp Transfer mold and method for manufacturing the same
JP4576728B2 (en) 2001-03-06 2010-11-10 ソニー株式会社 Conductive paste, printed wiring board and manufacturing method thereof, and semiconductor device and manufacturing method thereof
JP2002261120A (en) 2001-03-06 2002-09-13 Sony Corp Mounting board, its manufacturing method and semiconductor device
JP2002261444A (en) 2001-03-06 2002-09-13 Sony Corp Laminated wiring board and its manufacturing method
JP2002270731A (en) 2001-03-14 2002-09-20 Sony Corp Wiring board, its manufacturing method and semiconductor device
JP2002290029A (en) 2001-03-26 2002-10-04 Sony Corp Wiring board and method of manufacturing the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444732A (en) * 1967-06-06 1969-05-20 Albert L Robbins Method and apparatus for determining optimum bonding parameters for thermoplastic material
US5325583A (en) * 1990-09-28 1994-07-05 Kabushiki Kaisha Toshiba Method for manufacturing printed circuit board
US5773882A (en) * 1994-04-28 1998-06-30 Kabushiki Kaisha Toshiba Seminconductor package
US6143116A (en) * 1996-09-26 2000-11-07 Kyocera Corporation Process for producing a multi-layer wiring board
US6228467B1 (en) * 1998-01-21 2001-05-08 Mitsubishi Plastics, Inc. Heat-resistant insulating film, raw substrate for printed wiring board using the same and method for producing the substrate
US6207259B1 (en) * 1998-11-02 2001-03-27 Kyocera Corporation Wiring board
US6359235B1 (en) * 1999-07-30 2002-03-19 Kyocera Corporation Electrical device mounting wiring board and method of producing the same
US6591491B2 (en) * 2000-03-22 2003-07-15 Nitto Denko Corporation Method for producing multilayer circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8867219B2 (en) * 2011-01-14 2014-10-21 Harris Corporation Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
US9420687B2 (en) 2011-01-14 2016-08-16 Harris Corporation Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
US9691698B2 (en) 2011-01-14 2017-06-27 Harris Corporation Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

Also Published As

Publication number Publication date
KR20030066359A (en) 2003-08-09
TW200303164A (en) 2003-08-16
US20050025944A1 (en) 2005-02-03
US20030180510A1 (en) 2003-09-25
US7334324B2 (en) 2008-02-26
KR100935837B1 (en) 2010-01-11
TWI267331B (en) 2006-11-21
US6797367B2 (en) 2004-09-28
JP2003229663A (en) 2003-08-15
JP4181778B2 (en) 2008-11-19

Similar Documents

Publication Publication Date Title
US7334324B2 (en) Method of manufacturing multilayer wiring board
US7022399B2 (en) Semiconductor device integrated multilayer wiring board
JP3312723B2 (en) Heat conductive sheet, method of manufacturing the same, heat conductive substrate using the same, and method of manufacturing the same
WO2006078027A1 (en) Multilayer printed wiring board
JPWO2006100909A1 (en) Semiconductor device and manufacturing method thereof
JP5543184B2 (en) Wiring board material, laminated board, multilayer board and wiring board
JP5003202B2 (en) Thermally conductive substrate, manufacturing method thereof, and circuit module
JP4409325B2 (en) Wiring board and manufacturing method thereof
JP4181897B2 (en) Multilayer wiring board with built-in semiconductor device and manufacturing method thereof
JP3922977B2 (en) Multilayer wiring board with built-in semiconductor device
JP3418617B2 (en) Heat conductive substrate and semiconductor module using the same
JP2001057408A (en) Power module and manufacture thereof
JP2006203115A (en) Multilayer printed wiring board
JP5163279B2 (en) LAMINATED MANUFACTURING METHOD, LAMINATED PLATE, CIRCUIT BOARD, SEMICONDUCTOR PACKAGE SUBSTRATE, AND SEMICONDUCTOR DEVICE
JP2008177382A (en) Thermally conductive substrate, method of manufacturing the same, and circuit module using the same
JP3614844B2 (en) Thermal conductive substrate
JP2005353781A (en) Conductive paste composition for multilayer interconnection substrate
WO2024095811A1 (en) Method for producing circuit board
JP3934249B2 (en) Method for manufacturing thermal conductive substrate and manufacturing jig therefor
JP3610156B2 (en) Manufacturing method of multilayer wiring board
JP2001308535A (en) Multilayer wiring board and method for manufacturing the same
JP2002252465A (en) Multilayer wiring board and its manufacturing method
JP2004079629A (en) Multilayer wiring board and semiconductor device built-in multilayer wiring board
JP3631028B2 (en) Metal base circuit board and manufacturing method thereof
JP2002334945A (en) Heat conductive substrate and method of manufacturing the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION