US20080017932A1 - Shallow trench isolation formation - Google Patents
Shallow trench isolation formation Download PDFInfo
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- US20080017932A1 US20080017932A1 US11/866,471 US86647107A US2008017932A1 US 20080017932 A1 US20080017932 A1 US 20080017932A1 US 86647107 A US86647107 A US 86647107A US 2008017932 A1 US2008017932 A1 US 2008017932A1
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- layer
- shallow trench
- trench isolation
- silicon dioxide
- semiconductor substrate
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- 238000002955 isolation Methods 0.000 title claims description 88
- 230000015572 biosynthetic process Effects 0.000 title description 11
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 63
- 239000000463 material Substances 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 139
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 73
- 229910052710 silicon Inorganic materials 0.000 claims description 73
- 239000010703 silicon Substances 0.000 claims description 73
- 235000012239 silicon dioxide Nutrition 0.000 claims description 69
- 239000000377 silicon dioxide Substances 0.000 claims description 69
- 230000000295 complement effect Effects 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 20
- 239000000126 substance Substances 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 16
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 12
- 239000004020 conductor Substances 0.000 description 8
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- 238000005137 deposition process Methods 0.000 description 7
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
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- 230000003628 erosive effect Effects 0.000 description 5
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- 238000001311 chemical methods and process Methods 0.000 description 2
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- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Definitions
- first layer of electrically insulative material located within the trench, wherein said first layer comprises a first recess and a second recess, and wherein the first recess is isolated from the second recess by a portion of the first layer;
- FIGS. 1A-1H illustrate stages in a fabrication of a shallow trench isolation 12 in a semiconductor device 2 , in accordance with embodiments of the present invention.
- the semiconductor device 2 illustrated in FIGS. 1A-1H is a cross sectional view. The fabrication is described in greater detail with reference to FIG. 4 .
- the fabrication begins in FIG. 1A with a formation of a silicon nitride layer 4 on a silicon substrate 6 .
- the silicon substrate 6 may be any silicon substrate known to a person of ordinary skill in the art including, inter alia, bulk silicon substrate, silicon on insulator (SOI) substrate, etc.
- FIG. 1B illustrates the semiconductor device 2 with a shallow trench 8 formed.
- the shallow trench 8 comprises side surfaces 8 a and 8 b and a bottom surface 8 c .
- FIG. 2H illustrates an alternative to FIG. 2G showing the shallow trench isolation 44 comprising a silicon oxynitride layer 53 over a surface 55 of the silicon dioxide layer 54 .
- the silicon oxynitride layer 53 may formed by nitridization of an oxide layer.
- the silicon oxynitride layer 53 may provide protection against erosion of the silicon dioxide layer 54 in subsequent processing steps (e.g., during a buffered hydrofluoric acid cleaning process) and ultimately preventing any substance (e.g., chemical cleaning agents) from leaking in to the areas 56 and 57 between the silicon substrate 46 and the shallow trench isolation fill 43 and 52 and forming divots in subsequent processing steps.
- any substance e.g., chemical cleaning agents
- the shallow trench isolation fill may be formed by any method known to a person of ordinary skill in the art including, inter alia, a tetra ethyl ortho silicate (TEOS) chemical vapor deposition (CVD) process, etc.
- TEOS tetra ethyl ortho silicate
- CVD chemical vapor deposition
- a planar surface is created on the shallow trench isolation fill by a CMP process.
- the silicon nitride layer is used as a polish stop to protect the silicon substrate 40 .
- the shallow trench isolation fill is recessed relative to the silicon nitride layer as to provide a top surface of the shallow trench isolation fill that is coplanar with a top surface of the silicon substrate.
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
- This application is a continuation application claiming priority to Ser. No. 11/445,786, filed Jun. 2, 2006, which is a Divisional of U.S. Pat. No. 7,087,531, issued Aug. 8, 2006.
- 1. Technical Field
- The present invention relates to a structure and associated method for fabricating a shallow trench isolation in a semiconductor device.
- 2. Related Art
- During a manufacturing process, electrical structures within electrical devices undergo structural changes. The structural changes may cause the electrical device to be built incorrectly. Therefore there exists a need to correct structural changes of electrical structures within electrical devices during a manufacturing process.
- The present invention provides a semiconductor structure, comprising:
- a semiconductor substrate, wherein said semiconductor substrate comprises a trench formed within a first portion of a first surface of said semiconductor substrate;
- a first layer of electrically insulative material located within the trench, wherein said first layer comprises a first recess and a second recess, and wherein the first recess is isolated from the second recess by a portion of the first layer; and
- a second layer of electrically insulative material located on said first layer and within a first portion of said first recess and a second portion of said second recess.
- The present invention provides a semiconductor structure, comprising:
- a semiconductor substrate, wherein said semiconductor substrate comprises a trench formed within a first portion of a first surface of said semiconductor substrate;
- a first layer of electrically insulative material form within the trench, wherein the first layer comprises a recess;
- a second layer of electrically insulative material within the recess; and
- a third layer of electrically insulative material over said second layer, wherein said third layer comprises a first portion extending laterally over and parallel to a second portion of said first surface of said semiconductor substrate and a second portion extending laterally over and parallel to a third portion of said first surface of said semiconductor substrate, wherein said first portion of said third layer comprises a first convex surface, and wherein said second portion of said third layer comprises a second convex surface.
- The present invention advantageously provides a structure and associated method to correct structural changes of electrical structures within electrical devices during a manufacturing process.
-
FIGS. 1A-1H illustrate stages in a fabrication of a shallow trench isolation in a semiconductor device, in accordance with embodiments of the present invention. -
FIGS. 2A-2H illustrates an alternative toFIGS. 1A-1H , in accordance with embodiments of the present invention. -
FIGS. 3A-3B illustrate an application of shallow trench isolation, in accordance with embodiments of the present invention. -
FIG. 4 is a flowchart illustrating a semiconductor device fabrication method ofFIGS. 1A-1H , in accordance with embodiments of the present invention. -
FIG. 5 is a flowchart illustrating a semiconductor device fabrication method ofFIGS. 2A-2H , in accordance with embodiments of the present invention. -
FIG. 6 is a flowchart illustrating a semiconductor device fabrication method ofFIGS. 3A-3B , in accordance with embodiments of the present invention. -
FIGS. 1A-1H , 2A-2H, 3A-3B, 4, 5, and 6 illustrate and describe a shallow trench isolation (STI) forming method and structure formed by layers of silicon dioxide. Note that any insulating material known to a person of ordinary skill in the art may be used instead of or in combination with silicon dioxide to form the shallow trench isolation. -
FIGS. 1A-1H illustrate stages in a fabrication of ashallow trench isolation 12 in asemiconductor device 2, in accordance with embodiments of the present invention. Thesemiconductor device 2 illustrated inFIGS. 1A-1H is a cross sectional view. The fabrication is described in greater detail with reference toFIG. 4 . The fabrication begins inFIG. 1A with a formation of a silicon nitride layer 4 on asilicon substrate 6. Thesilicon substrate 6 may be any silicon substrate known to a person of ordinary skill in the art including, inter alia, bulk silicon substrate, silicon on insulator (SOI) substrate, etc.FIG. 1B illustrates thesemiconductor device 2 with ashallow trench 8 formed. Theshallow trench 8 comprisesside surfaces bottom surface 8 c. Theshallow trench 8 may be formed by any method known to a person of ordinary skill in the art including, inter alia, a reactive ion etching (RIE) process, etc.FIG. 1C illustrates thesemiconductor device 2 comprising a shallow trench isolation fill 10 formed within theshallow trench 8. The shallow trench isolation fill 10 may comprise, inter alia, silicon dioxide, nitride, etc. The shallow trench isolation fill 10 may be formed by any method known to a person of ordinary skill in the art including, inter alia, a tetra ethyl ortho silicate (TEOS) chemical vapor deposition (CVD) process followed by a chemical/mechanical polishing (CMP) process, etc.FIG. 1D illustrates thesemiconductor device 2 after the silicon nitride layer 4 has been removed from thesilicon substrate 6. The silicon nitride layer 4 may be removed by any method known to a person of ordinary skill in the art including, inter alia, the use of hot phosphoric acid, etc.FIG. 1E illustrates thesemiconductor device 2 with asurface 16 of the shallow trench isolation fill 10 about coplanar with asurface 17 of thesilicon substrate 6. Additionally, the shallow trench isolation fill 10 comprises divots 14 a and 14 b (i.e., unwanted recesses). Thedivot 14 a is located betweenside surface 8 a of thetrench 8 and asurface 16 a of the shallow trench isolation fill 10. Thedivot 14 b is located between aside surface 8 a of thetrench 8 and asurface 16 b of the shallow trench isolation fill 10. Thesurface 16 a comprises a concave surface. Thesurface 16 b comprises a concave surface. Thedivots surface 17 of thesilicon substrate 6 prior to a gate dielectric formation. Thedivots divots FIG. 1F . An additional layer of silicon dioxide may extend laterally over and parallel to a portion of thesurface 17 of thesilicon substrate 6 as described with reference toFIG. 1G . Additionally, if desired, a layer of silicon oxynitride may be formed over the additional layer of silicon dioxide extending laterally over and parallel to a portion of thesurface 17 of thesilicon substrate 6 as described with reference toFIG. 1H . The term “selectively growing” silicon dioxide or any insulating material is defined herein as a process to grow the silicon dioxide (or any insulating material) only in a specified area (e.g., to fill a divot) and over a layer of silicon dioxide (or any insulating material). Selectively growing the silicon dioxide or any other electrically insulative material comprised by thetrench 8 may comprise using a liquid phase deposition process as described in U.S. Pat. No. 6,653,245 (issued Nov. 25, 2003) hereby incorporated by reference in it's entirety.FIG. 1F illustrates thesemiconductor structure 2 with ashallow trench isolation 12 comprising the shallow trench isolation fill 10, the shallow trench 8 (seeFIG. 1B ), selectively grown silicon dioxide layers 30 and 32 and to fill thedivots FIG. 1E ) in the shallow trench isolation fill 10. Thesilicon dioxide layer 30 has been selectively grown over thesurface divots silicon dioxide layer 30 comprises aconvex surface 30 a in contact with theconcave surface 16 a of the shallow trench isolation fill 10 and aconvex surface 30 b in contact with theconcave surface 16 b of the shallow trench isolation fill 10. Thesilicon dioxide layer 32 has been selectively grown over thesurface 34 of thesilicon dioxide layer 30 and within a portion of thedivots -
FIG. 1G illustrates an alternative toFIG. 1F showing theshallow trench isolation 12 comprising an additionalsilicon dioxide layer 36 selectively grown over asurface 35 of thesilicon dioxide layer 32 Additionally, thesilicon dioxide layer 36 is selectively grown to extend laterally over and parallel to portion of thesurface 17 of thesilicon substrate 16. Thesilicon dioxide layer 36 extending laterally over and parallel to a portion of thesurface 17 of thesilicon substrate 16 prevents any substance (e.g., chemical cleaning agents) from leaking in to theareas silicon substrate 6 and the shallow trench isolation fill 10 and forming divots in subsequent processing steps. -
FIG. 1H illustrates an alternative toFIG. 1G showing theshallow trench isolation 12 comprising asilicon oxynitride layer 38 over asurface 42 of the additionalsilicon dioxide layer 36. Thesilicon oxynitride layer 38 may formed by nitridization of an oxide layer. Thesilicon oxynitride layer 38 may provide protection against erosion of the additionalsilicon dioxide layer 36 subsequent processing steps (e.g., during a hydrofluoric acid cleaning process) and ultimately preventing any substance (e.g., chemical cleaning agents) from leaking in to theareas silicon substrate 6 and the shallow trench isolation fill 10 and forming divots in subsequent processing steps. -
FIGS. 2A-2H illustrates an alternative toFIGS. 1A-1H showing stages in a fabrication of ashallow trench isolation 44 in asemiconductor device 37, in accordance with embodiments of the present invention. The embodiment described with reference toFIGS. 1A-1H provides a method of filling shallow trench oxide divots (e.g.,divots 14 and 14 b inFIG. 1E ) but may not provide a final oxide surface that is co-planar with the silicon surface (seeFIG. 1F ). In contrast with the embodiment described with reference toFIGS. 1A-1H , the embodiment described with reference toFIGS. 2A-2H provides a method that allows divot formation to be avoided, with an option of providing a shallow trench isolation that is about co-planar with the silicon surface (seeFIG. 2F ). Thesemiconductor device 37 illustrated inFIGS. 2A-2H is a cross sectional view.FIGS. 2A-2H illustrates a method to avoid creating the divots 14 fromFIGS. 1A-1H . The fabrication is described in greater detail with reference toFIG. 5 . The fabrication begins inFIG. 2A with a formation of asilicon nitride layer 39 on asilicon substrate 40. Thesilicon substrate 40 may be any silicon substrate known to a person of ordinary skill in the art including, inter alia, bulk silicon substrate, silicon on insulator (SOI) substrate, etc.FIG. 2B illustrates thesemiconductor device 37 with ashallow trench 41 formed. Theshallow trench 41 may be formed by any method known to a person of ordinary skill in the art including, inter alia, a reactive ion etching (RIE) process, chemical etching, etc.FIG. 2C illustrates thesemiconductor device 37 comprising a shallow trench isolation fill 43 formed within theshallow trench 41. The shallow trench isolation fill 43 may comprise, inter alia, silicon dioxide, nitride, etc. The shallow trench isolation fill 43 may be formed by any method known to a person of ordinary skill in the art including, inter alia, a tetra ethyl ortho silicate (TEOS) chemical vapor deposition (CVD) process followed by a CMP process, etc.FIG. 2D illustrates theshallow trench isolation 43 fill recessed relative to thesilicon nitride layer 39 as to provide atop surface 45 of theshallow trench isolation 43 fill that is coplanar with atop surface 46 of thesilicon substrate 40. The shallow trench isolation fill 43 may be recessed to remove a top portion of the shallow trench isolation fill 43 using, inter alia, a reactive ion etching (RIE) or chemical etching process.FIG. 2E illustrates the shallow trench isolation fill 43 such that thetop surface 45 is recessed below thetop surface 46 of thesilicon substrate 40 thereby causing anunwanted recess 48. Theunwanted recess 48 may be caused inadvertently by, inter alia, chemical processes (e.g, a hydrofluoric acid dip) used at several points in the fabrication of a semiconductor device in order to clean thesurface 46 of thesilicon substrate 40 prior to a gate dielectric formation. Therecess 48 may be repaired (i.e., filled) by selectively growing silicon dioxide within therecess 48 as shown inFIG. 2F . Selectively growing the silicon dioxide or any other electrically insulative material comprised by thetrench 41 may comprise using a liquid phase deposition process. -
FIG. 2F illustrates thesemiconductor structure 37 with theshallow trench isolation 44 comprising the shallow trench isolation fill 43, the unwanted recess 48 (seeFIG. 2E ), and the selectively grownsilicon dioxide layer 52 within therecess 48. Thesilicon dioxide layer 52 comprises asurface 50 that is coplanar with thesurface 46 of thesilicon substrate 40 -
FIG. 2G illustrates an alternative toFIG. 2F showing theshallow trench isolation 44 comprising an additional selectively grownsilicon dioxide layer 54. Thesilicon dioxide layer 54 has been selectively grown over thesurface 50. Additionally, thesilicon dioxide layer 54 has been selectively grown to extend laterally over and parallel to [[a]] portions of thesurface 46 of thesilicon substrate 40. A first portion of thesilicon dioxide layer 54 that extends laterally over and parallel to aportion 46 a of thesurface 46 comprises aconvex surface 95 a. A second portion of thesilicon dioxide layer 54 that extends laterally over and parallel to aportion 46 b thesurface 46 comprises aconvex surface 95 b. Thesilicon dioxide layer 54 extending laterally over and parallel to a portion of thesurface 46 of thesilicon substrate 40 prevents any substance (e.g., chemical cleaning agents) from leaking in to theareas silicon substrate 40 and the shallow trench isolation fill 43 and 52 and forming recesses or divots in subsequent processing steps. -
FIG. 2H illustrates an alternative toFIG. 2G showing theshallow trench isolation 44 comprising asilicon oxynitride layer 53 over asurface 55 of thesilicon dioxide layer 54. Thesilicon oxynitride layer 53 may formed by nitridization of an oxide layer. Thesilicon oxynitride layer 53 may provide protection against erosion of thesilicon dioxide layer 54 in subsequent processing steps (e.g., during a buffered hydrofluoric acid cleaning process) and ultimately preventing any substance (e.g., chemical cleaning agents) from leaking in to theareas silicon substrate 46 and the shallow trench isolation fill 43 and 52 and forming divots in subsequent processing steps. -
FIGS. 3A-3B illustrate an application of ashallow trench isolation 67 and ashallow trench isolation 68 in aCMOS semiconductor device 59, in accordance with embodiments of the present invention. TheCMOS semiconductor device 59 may be a field effect transistor (FET) device. In a process sequence for a fabrication of theCMOS semiconductor device 59, a selective oxide growth of silicon dioxide may be performed at multiple points of the fabrication process. For example, a surface of the selectively grown silicon dioxide layer may be grown such that it is planar a surface of asilicon substrate 65 prior to formation of gate dielectric and gate conductor films and patterning. After the gate conductor is formed, subsequent clean steps can cause an additional unwanted recess of the silicon dioxide layers. If the silicon dioxide becomes too thin, then source/drain implants (see source/drain implants 79 inFIG. 3B ) may pass through the silicon dioxide comprising the unwanted and cause an electrical short between adjacent devices. In this case, it may be desirable to increase the thickness of the silicon dioxide layer, by means of selective oxide growth, such that the source/drain implants are sufficiently masked. Thesemiconductor device 59 illustrated inFIGS. 3A-3B is a cross sectional view. The fabrication is described in more detail with reference toFIG. 6 . The fabrication begins inFIG. 3A with a silicon substrate containing a typical CMOS semiconductor device (e.g., CMOS semiconductor device 59) processed up to agate conductor module 60.FIG. 3A illustrates the shallow trench isolation fill 67, the shallow trench isolation fill 68, agate dielectric 71, agate conductor 72, andsidewall spacers 70. The shallow trench fill 67 and 68 may be formed by any method known to a person of ordinary skill in the art including, inter alia, a reactive ion etching process (RIE), a chemical mechanical polish process, etc. The shallow trench isolation fill 67 and 68 may comprise, inter alia, silicon dioxide, silicon oxynitride, spun-on-glass, etc. The shallow trench isolation fill 67 and 68 may be formed by any method known to a person of ordinary skill in the art, including, inter alia, a tetra-ethyl orthosilicate (TEOS) chemical vapor deposition (CVD) process followed by a CMP process, etc. Thegate dielectric 71 andgate conductor 72 may be formed by conventional means known to an ordinary person skilled in the art. Thegate dielectric 71 may comprise silicon dioxide, silicon oxynitride, hafnium silicate or similar material. Thegate conductor 72 may comprise doped polysilicon, tungsten, or similar material as known in the art. At this point in the process, thesource 76 and drain 77 will be formed. As seen inFIG. 3A , the shallow trench isolation fill 67 and 68 have been recessed anddivots drain implants 79 to extend through the shallow trench isolation fill 67 and 68, and allow adjacent semiconductor devices (e.g.,source 74 and drain 75) to fail by an electrical shorting mechanism. Accordingly,additional layers shallow trench isolation 78 and 81 (FIG. 3B ). This can be achieved by means of the selective liquid-phase oxide deposition process as described with reference toFIGS. 1A-1H and shown inFIG. 3B . -
FIG. 3B illustrates the shallow trench isolation fill 67 and 68 replenished (i.e., made sufficiently thick) by selectively growingadditional layers shallow trench isolation FIGS. 1F-1H are also applicable to the embodiments described with reference toFIGS. 3A-3B . -
FIG. 4 is a flowchart illustrating a semiconductordevice fabrication method 88 including a formation of a shallow trench isolation in thesemiconductor device 2 ofFIGS. 1A-1H , in accordance with embodiments of the present invention. Instep 90, a silicon nitride layer is formed on a silicon substrate. Instep 92, the silicon nitride layer is patterned using a photolithography process. The patterned silicon nitride layer is used to define a shallow trench and the shallow trench is etched into the silicon substrate. Instep 94, the shallow trench is filled with silicon dioxide thereby forming a shallow trench isolation fill within the shallow trench. The shallow trench isolation fill may be formed by any method known to a person of ordinary skill in the art including, inter alia, a tetra ethyl ortho silicate (TEOS) chemical vapor deposition (CVD) process, etc. Instep 96, a planar surface is created on the shallow trench isolation fill by a chemical/mechanical polishing (CMP). The silicon nitride layer is used as a polish stop to protect the silicon substrate. Instep 98, silicon nitride layer 4 is removed from the silicon substrate using a hot phosphoric acid. Instep 100, semiconductor device processing is continued. The semiconductor device processing may include, inter alia, implanting ions of boron, phosphorous, and arsenic to create a conductive layer,silicon substrate 6 surface cleans, gate dielectric formation, etc. Duringstep 100, divots (i.e., unwanted recesses) are formed in the shallow trench isolation fill. Instep 102, the divots are repaired (i.e., filled) by selectively a growing layer(s) of silicon dioxide within the divots and over the shallow trench isolation fill comprising the divots. Additionally, an additional layer(s) of silicon dioxide may be selectively grown to extend laterally over and parallel to a portion of a surface of the silicon substrate to prevent any substance (e.g., chemical cleaning agents) from attacking the shallow trench isolation fill and forming divots in subsequent processing steps. Selectively growing the silicon dioxide may comprise using a liquid phase deposition process. Additionally a silicon oxynitride layer may be formed over a surface of the additional silicon dioxide layer(s). The silicon oxynitride layer may provide protection against erosion of the additional silicon dioxide layer(s) in subsequent processing steps (e.g., during a buffered hydrofluoric acid cleaning process). -
FIG. 5 is a flowchart illustrating a semiconductordevice fabrication method 104 including a formation of a shallow trench isolation in the semiconductor device ofFIGS. 2A-2H , in accordance with embodiments of the present invention. Instep 106, a silicon nitride layer is formed on a silicon substrate. Instep 92, the silicon nitride layer is patterned using a photolithography process. The patterned silicon nitride layer is used to define a shallow trench and the shallow trench is etched into the silicon substrate. Instep 110, the shallow trench is filled with silicon dioxide thereby forming a shallow trench isolation fill within theshallow trench 41. The shallow trench isolation fill may be formed by any method known to a person of ordinary skill in the art including, inter alia, a tetra ethyl ortho silicate (TEOS) chemical vapor deposition (CVD) process, etc. Instep 112, a planar surface is created on the shallow trench isolation fill by a CMP process. The silicon nitride layer is used as a polish stop to protect thesilicon substrate 40. Instep 115, the shallow trench isolation fill is recessed relative to the silicon nitride layer as to provide a top surface of the shallow trench isolation fill that is coplanar with a top surface of the silicon substrate. The shallow trench isolation fill may be recessed using, inter alia, a reactive ion etching (RIE) or chemical etching process. Instep 116 semiconductor device processing is continued. Due to hydrofluoric acid chemical cleaning agents, a top surface of the shallow trench isolation fill becomes recessed below the top surface of the silicon substrate thereby causing an unwanted recess. Instep 118, the recess is repaired (i.e., filled) by selectively growing silicon dioxide within the recess. Selectively growing the silicon dioxide may comprise using a liquid phase deposition process. Additionally, an additional layer(s) of silicon dioxide may be selectively grown to extend laterally over and parallel to a portion of a surface of the silicon substrate to prevent any substance (e.g., hydrofluoric acid) from attacking the shallow trench isolation fill and creating unwanted recesses and/or divots in subsequent processing steps. Additionally a silicon oxynitride layer may be formed over a surface the additional silicon dioxide layer(s). The silicon oxynitride layer may provide protection against erosion of the additional silicon dioxide layer(s) in subsequent processing steps (e.g., during a buffered hydrofluoric acid cleaning process). -
FIG. 6 is a flowchart illustrating a semiconductordevice fabrication method 120 including a formation of a shallow trench isolation in the semiconductor device ofFIGS. 3A-3B , in accordance with embodiments of the present invention. Instep 122, a silicon nitride layer is formed on a silicon substrate. Instep 124, the silicon nitride layer is patterned using a photolithography process. The patterned silicon nitride layer is used to define a shallow trench and the shallow trench is etched into the silicon substrate. Instep 126, the shallow trench is filled with silicon dioxide thereby forming a shallow trench isolation fill within the shallow trench. The shallow trench isolation fill may be formed by any method known to a person of ordinary skill in the art including, inter alia, a tetra ethyl ortho silicate (TEOS) chemical vapor deposition (CVD) process, etc. Instep 128, shallow trench isolation fill is chemically or mechanically polished to create a planar surface of the shallow trench isolation fill. The silicon nitride layer is used as a polish stop to protect the silicon substrate. Instep 130, the shallow trench isolation fill is recessed relative to the silicon nitride layer as to provide a top surface of the shallow trench isolation fill that is coplanar with a top surface of the silicon substrate. The shallow trench isolation fill may be recessed using, inter alia, a reactive ion etching (RIE) or chemical etching process. Instep 132, silicon nitride layer is removed from the silicon substrate using a hot phosphoric acid. Instep 134 semiconductor device processing is continued. Instep 136, a layer of silicon dioxide is selectively grown as described with reference toFIGS. 1A-1H and 2A-2H. Instep 138, a gate dielectric is formed, and a gate conductor material is deposited and patterned by conventional methods. Sidewall spacers of silicon nitride or oxide are also formed, by conventional methods. Due to hydrofluoric acid cleans, oxide hard mask removal, and spacer etching, a top surface of the layer of silicon dioxide selectively grown instep 136 becomes recessed such that the top surface is recessed below the top surface of the silicon substrate and/or divots are formed. The shallow trench isolation must be sufficiently thick to prevent source and drain implants (i.e., in a subsequent step 142) from passing through the shallow trench isolation and into a region of the silicon substrate underlying the shallow trench isolation. The source and drain implants cause the silicon substrate to become conductive and may short components together that may be located on both sides of the shallow trench isolation. Instep 140, the shallow trench isolation is replenished (i.e., be made sufficiently thick) by selectively growing silicon dioxide within the recess or portion of the recess. Selectively growing the silicon dioxide may comprise using a liquid phase deposition process. Additionally, an additional layer(s) of silicon dioxide may be selectively grown to extend laterally over and parallel to a portion of a surface of the silicon substrate to prevent any substance (e.g., chemical cleaning agents) from attacking the shallow trench isolation fill and creating unwanted trenches and/or divots in subsequent processing steps. Additionally a silicon oxynitride layer may be formed over a surface of the additional silicon dioxide layer(s). The silicon oxynitride layer may provide protection against erosion of the additional silicon dioxide layer(s) in subsequent processing steps (e.g., during a buffered hydrofluoric acid cleaning process). Instep 142, source/drain implants are formed. - While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims (20)
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US9059243B2 (en) | 2012-06-25 | 2015-06-16 | International Business Machines Corporation | Shallow trench isolation structures |
US9263556B2 (en) * | 2012-06-29 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide process using OD spacers |
US9698043B1 (en) | 2016-05-20 | 2017-07-04 | International Business Machines Corporation | Shallow trench isolation for semiconductor devices |
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US7087531B1 (en) | 2006-08-08 |
US20060160363A1 (en) | 2006-07-20 |
US7348634B2 (en) | 2008-03-25 |
US7652334B2 (en) | 2010-01-26 |
US20060220148A1 (en) | 2006-10-05 |
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