US20080003747A1 - Non-volatile memory device and manufacturing method thereof - Google Patents

Non-volatile memory device and manufacturing method thereof Download PDF

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Publication number
US20080003747A1
US20080003747A1 US11/635,910 US63591006A US2008003747A1 US 20080003747 A1 US20080003747 A1 US 20080003747A1 US 63591006 A US63591006 A US 63591006A US 2008003747 A1 US2008003747 A1 US 2008003747A1
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Prior art keywords
layer
charge trap
buffer layer
memory device
gate
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Abandoned
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US11/635,910
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English (en)
Inventor
Eun Seok Choi
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, EUN SEOK
Publication of US20080003747A1 publication Critical patent/US20080003747A1/en
Priority to US12/276,210 priority Critical patent/US7923335B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

Definitions

  • the invention relates, in general, to non-volatile memory devices and, more particularly, to a non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically horizontally and a method of manufacturing the same.
  • SONOS Polysilicon Oxide Nitride Oxide Semiconductor
  • Non-volatile Semiconductor Memories are largely classified into floating gate series and Metal Insulator Semiconductor (MIS) series in which two or more kinds of dielectric layers are laminated doubly or triply in terms of the process technology.
  • NVSM Non-volatile Semiconductor Memories
  • MIS Metal Insulator Semiconductor
  • the floating gate series implement a memory characteristic by employing the potential well.
  • a representative example of the floating gate series is an EPROM Tunnel Oxide (ETO) structure that has been widely used as flash Electrically Erasable Programmable Read Only Memory (EEPROM).
  • ETO EPROM Tunnel Oxide
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • the MIS series performs the memory function employing traps existing at the dielectric layer bulk, the dielectric layer dielectric layer interface, and the dielectric layer-semiconductor interface.
  • a representative example of the MIS series is a Metal/Polysilicon Oxide Nitride Oxide Semiconductor (MONOS/SONOS) that has been widely used as flash EEPROM.
  • MONOS/SONOS Metal/Polysilicon Oxide Nitride Oxide Semiconductor
  • a difference between the SONOS and general flash memory is that in the general flash memory, charges are stored in the floating gate, whereas in the SONOS, charges are stored in the nitride layer in terms of the structure.
  • the floating gate is formed using polysilicon.
  • the retention time of charge is significantly lowered.
  • the nitride layer is used instead of polysilicon as described above. Accordingly, the sensitivity to defect in process is relatively small.
  • tunnel oxide having a thickness of about 70 ⁇ is formed under the floating gate.
  • tunnel oxide having a thickness of about 70 ⁇ is formed under the floating gate.
  • SONOS direct tunneling oxide is formed under the nitride layer. It is therefore possible to implement a memory device having a lower voltage, lower power and high-speed operation.
  • a conventional flash memory device having the SONOS structure will be described below with reference to FIG. 1 .
  • a tunnel oxide layer 11 , a charge trap layer 12 , a blocking gate (oxide layer) 13 , and an electrode 14 for a gate are sequentially formed on a semiconductor substrate 10 .
  • Word line patterns are then formed by an etch process.
  • the charge trap layer 12 for storing charges and the tunnel oxide layer 11 different electric field (E-field) cannot be applied to the insulating layers, respectively.
  • the charges stored in the nitride layer 12 are moved toward the semiconductor substrate 10 by means of a Fowler-Nordheim (F-N) tunneling current through the tunnel oxide layer 11 and are then erased.
  • F-N Fowler-Nordheim
  • the invention addresses the above problems, and provides a non-volatile memory device having a SONOS structure, in which a charge trap layer in which charges are trapped toward source and drain is separated physically in order to prevent charges at both sides of the charge trap layer from being moved mutually, and interference between the charges at both sides can be prevented although the cell size is reduced, and a method of manufacturing the same.
  • the invention provides a non-volatile memory device, including a gate in which a gate insulating layer, a charge trap layer, a blocking oxide layer and a gate electrode are formed, respectively over a semiconductor substrate.
  • the charge trap layer is physically divided by a buffer layer.
  • the invention provides a method of manufacturing a non-volatile memory device, including the steps of depositing a gate insulating layer, a buffer layer, a blocking oxide layer and a gate electrode over a semiconductor substrate, respectively, etching the gate electrode, the blocking oxide layer, the buffer layer and the gate insulating layer to form a gate, performing an ion implant process to form source and drain regions within the semiconductor substrate, selectively forming a recessed pattern of the buffer layer by selectively etching the buffer layer both sides, and forming a charge trap layer in the recessed pattern of the buffer layer.
  • FIG. 1 is a cross-sectional view of a conventional flash memory device having the SONOS structure
  • FIGS. 2 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device having a SONOS structure according to an embodiment of the invention.
  • FIGS. 2 to 5 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device having a SONOS structure according to an embodiment of the invention.
  • a gate insulating layer 101 , a buffer layer 102 , a blocking oxide layer 103 and a gate electrode 104 are sequentially formed on a semiconductor substrate 100 .
  • the buffer layer 102 may be formed using a silicon oxide layer or a silicon nitride layer.
  • the blocking oxide layer 103 may be formed using a high dielectric layer, such as Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 , La 2 O 3 or TiO 2 , or a combination of them.
  • a silicon oxide layer may be used instead of the blocking oxide layer 103 .
  • the gate electrode 104 may be formed using polysilicon doped with an impurity.
  • the gate electrode 104 may be formed using transfer metal nitride such as TiN, TaN, TiCN, TaCN, TiSiN, TaSiN, WN or RuTiN.
  • the buffer layer 102 is preferably formed to a thickness of 20 ⁇ to 1000 ⁇ .
  • the gate electrode 104 , the blocking oxide layer 103 , the buffer layer 102 and the gate insulating layer 101 are sequentially partially etched by an etch process, forming a gate pattern.
  • An ion implant process is performed to form a source region 105 and a drain region 106 in the exposed semiconductor substrate 100 .
  • an etch process is performed to recess the sides of the exposed buffer layer 102 , thus forming a space. It is preferred that the recessed depth be 1/20 to 1 ⁇ 2 or less of the length of a gate pattern.
  • a charge trap layer 107 is then deposited on the entire surface.
  • the charge trap layer 107 is preferably formed to completely gap fill the empty space formed by etching the buffer layer 102 .
  • the charge trap layer 107 may be formed using a silicon nitride layer or metal oxide layer.
  • the process of forming the source region 105 and the drain region 106 may be carried out posterior to the process of depositing the charge trap layer 107 .
  • an etch process is performed in such a manner that the charge trap layer 107 remains only at both sides of the buffer layer 102 . That is, it is preferred that the charge trap layer 107 be physically separated by the buffer layer 102 . Due to this, the charge trap layer 107 that traps electric charges is divided into two horizontally at both sides of the gate due to a layer having a physically different property, i.e., the buffer layer 102 .
  • the process of forming the source region 105 and the drain region 106 may be performed posterior to the process of etching the charge trap layer 107 .
  • the charge trap layer that traps electric charges toward the source and drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
US11/635,910 2006-06-29 2006-12-08 Non-volatile memory device and manufacturing method thereof Abandoned US20080003747A1 (en)

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KR1020060059757A KR100812933B1 (ko) 2006-06-29 2006-06-29 Ｓｏｎｏｓ 구조를 갖는 반도체 메모리 소자 및 그것의제조 방법
KR2006-59757 2006-06-29

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128789A1 (en) * 2006-12-04 2008-06-05 Hynix Semiconductor Inc. Semiconductor memory device and method of manufacturing the same
US20080194066A1 (en) * 2007-02-14 2008-08-14 Micron Technology, Inc. Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates
US20090050983A1 (en) * 2006-01-25 2009-02-26 Nec Corporation Semiconductor device and method of producing the same
US20160234819A1 (en) * 2014-12-17 2016-08-11 Telefonaktiebolaget L M Ericsson (Publ) Flexible Assignment of Network Functions for Radio Access
US20170054614A1 (en) * 2015-08-19 2017-02-23 Google Inc. Filtering Content Based on User Mobile Network and Data-Plan

Families Citing this family (8)

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KR101488417B1 (ko) 2008-08-19 2015-01-30 삼성전자주식회사 전하의 측면 이동을 억제하는 메모리 소자
CN101807578A (zh) * 2010-03-16 2010-08-18 复旦大学 电荷俘获非挥发半导体存储器及其制造方法
CN102693984B (zh) * 2011-03-21 2015-04-15 中国科学院微电子研究所 一种多值非挥发存储器及其制备方法
CN102280377B (zh) * 2011-08-26 2015-11-11 上海华虹宏力半导体制造有限公司 Sonos结构及其制作方法
KR101897214B1 (ko) * 2011-11-16 2018-10-23 주식회사 원익아이피에스 박막 제조 방법
CN102496566B (zh) * 2011-11-29 2014-08-06 无锡中微晶园电子有限公司 用于sonos存储芯片批产工艺中的存储管多晶刻蚀方法
CN105047670B (zh) * 2015-06-29 2018-04-17 上海华虹宏力半导体制造有限公司 Sonos器件的制造方法
US10510903B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Impact ionization semiconductor device and manufacturing method thereof

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US6639271B1 (en) * 2001-12-20 2003-10-28 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
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US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US6639271B1 (en) * 2001-12-20 2003-10-28 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US7112842B2 (en) * 2003-10-29 2006-09-26 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of manufacturing the same
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090050983A1 (en) * 2006-01-25 2009-02-26 Nec Corporation Semiconductor device and method of producing the same
US7791129B2 (en) * 2006-01-25 2010-09-07 Nec Corporation Semiconductor device and method of producing the same including a charge accumulation layer with differing charge trap surface density
US20080128789A1 (en) * 2006-12-04 2008-06-05 Hynix Semiconductor Inc. Semiconductor memory device and method of manufacturing the same
US20080194066A1 (en) * 2007-02-14 2008-08-14 Micron Technology, Inc. Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates
US7915126B2 (en) * 2007-02-14 2011-03-29 Micron Technology, Inc. Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates
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US20160234819A1 (en) * 2014-12-17 2016-08-11 Telefonaktiebolaget L M Ericsson (Publ) Flexible Assignment of Network Functions for Radio Access
US20170054614A1 (en) * 2015-08-19 2017-02-23 Google Inc. Filtering Content Based on User Mobile Network and Data-Plan

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Publication number Publication date
KR100812933B1 (ko) 2008-03-11
US7923335B2 (en) 2011-04-12
US20090081841A1 (en) 2009-03-26
CN101097965A (zh) 2008-01-02
KR20080001352A (ko) 2008-01-03

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Effective date: 20061024

STCB Information on status: application discontinuation

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