US20070252288A1 - Semiconductor module and method for forming the same - Google Patents
Semiconductor module and method for forming the same Download PDFInfo
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- US20070252288A1 US20070252288A1 US11/772,901 US77290107A US2007252288A1 US 20070252288 A1 US20070252288 A1 US 20070252288A1 US 77290107 A US77290107 A US 77290107A US 2007252288 A1 US2007252288 A1 US 2007252288A1
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- semiconductor chip
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- 238000000034 method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000001465 metallisation Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 12
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- 239000004593 Epoxy Substances 0.000 description 1
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- 230000004888 barrier function Effects 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- 229920001169 thermoplastic Polymers 0.000 description 1
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- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Definitions
- the present invention generally relates to a semiconductor module and method for forming the same. Specifically, the present invention provides a semiconductor module having an interposer structure with metallurgical through connections for electrically connecting a semiconductor chip to a substrate.
- a semiconductor chip In the production of semiconductor modules, a semiconductor chip is often connected to a carrier such as a substrate. Typically, the connection is made using controlled collapse chip connection (C4) technology whereby solder bumps are used to join the two components together.
- C4 controlled collapse chip connection
- the semiconductor chip usually has a different coefficient of thermal expansion (CTE) than the substrate. Given the close physical proximity of the semiconductor chip to the substrate, the solder bumps often deteriorate as the module heats up and cools off. This is especially the case with larger die sizes.
- ceramic substrates are generally non-planar, which can become a gating factor as the substrate X-Y dimensions increase.
- shrinking pitch there is a need to shrink C4 bump dimensions to avoid nearest neighbor shorting.
- a small C4 bump height results in a larger percentage of variation across the grid of bumps.
- current methods of depositing and joining C4 interconnections are expensive and involve the use of specific under bump metallization (UBM), which might have to be customized.
- the UBM may need additional layers such as diffusion barriers and chip encapsulants so that it may endure a melting or partially melting C4 structure that reacts with the UBM during subsequent assembly operations.
- the present invention provides a semiconductor module and method for forming the same.
- a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure.
- the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
- the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate.
- a first aspect of the present invention provides a semiconductor module, comprising a semiconductor chip; a substrate; and an interposer structure electrically connecting the semiconductor chip to the substrate, wherein the interposer structure includes metallurgical through connections having a predetermined shape.
- a second aspect of the present invention provides a semiconductor module, comprising a semiconductor chip having an under bump metallization; a substrate having a top surface metallization; and an interposer structure electrically connecting the under bump metallization to the top surface metallization, wherein the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
- a third aspect of the present invention provides a method for forming a semiconductor module, comprising: embedding metallurgical through connections within an elastomeric, compliant material to form an interposer structure; and positioning the interposer structure between a semiconductor chip and a substrate to electrically connect the semiconductor chip to the substrate.
- the present invention provides a semiconductor module and method for forming the same.
- FIG. 1 depicts a semiconductor module having an interposer structure, according to the present invention.
- FIG. 2 depicts the semiconductor module of FIG. 1 further including a heat spreader and a heat sink.
- FIG. 3 depicts the semiconductor module of FIG. 2 further including underfill.
- FIG. 4 depicts the semiconductor module of FIG. 3 under a Land Grid Array load.
- FIG. 5 depicts the semiconductor module of FIG. 1 in a TCA application.
- the present invention provides a semiconductor module and method for forming the same.
- a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure.
- the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
- the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate.
- semiconductor module 10 includes semiconductor chip 12 and carrier/substrate 14 with interposer structure 16 positioned therebetween.
- semiconductor module 10 could be a single chip module or a multi-chip module.
- interposer structure 16 could be positioned between each semiconductor chip and substrate 14 .
- substrate 14 could be any type of substrate now known or later developed.
- substrate 14 could be ceramic or organic.
- interposer structure 16 is positioned between semiconductor chip 12 and substrate 14 under the present invention to preserve the interface therebetween.
- interposer structure 16 generally comprises a elastomeric, compliant material 20 having metallurgical through connections 18 “embedded” or “positioned” therein.
- Metallurgical through connections 18 electrically connect under bump metallization (UBM) or bottom layer metallurgy (BLM) 22 of semiconductor chip 12 to top surface metallurgy (TSM) 24 of substrate 14 .
- interposer structure 16 can comprise Cupil-T, which is commercially available from Nitto Denko, Inc. of Osaka, Japan.
- metallurgical through connections 18 can be formed to have a predetermined shape depending on the load applied to semiconductor module 10 to best optimize the contact.
- metallurgical through connections 18 could be spherical, ellipsoid, s-shaped, c-shaped, or elongate (i.e., column-like). various factors can be considered when determining the shape of metallurgical through connections 18 .
- Such factors include, among other things: (1) camber (i.e., non-flatness of substrate 14 and semiconductor chip 12 ) in that more camber might mean taller through connections with an overall greater degree of compressibility; (2) distortion (i.e., positional accuracy of the I/O pads on substrate 14 ) in that the worse the distortion, the bigger the contact area on metallurgical through connections 18 that would have to be provided so that some degree of contact is always present between metallurgical through connections 18 and the I/O pads; and (3) process considerations such as how the through connections are made.
- metallurgical through connections 18 could be formed from one or more materials. To this extent, metallurgical through connections 18 could have a core formed from Copper, Copper-Beryllium, or the like that is coated with gold. Still yet, UBM 22 and/or TSM 24 could be gold, solder or the like.
- interposer structure 16 could be rigidly attached (e.g., hard soldered) to either UBM 22 or TSM 24 , or both.
- LGA Land Grid Array
- metallurgical through connections 18 could be hard soldered to TSM 24 , while the contact between metallurgical through connections 18 and UBM 22 is maintained solely by the LGA load. This would enable free expansion of the semiconductor chip side of interposer structure 16 under the influence of temperature. Since interposer structure 16 would not cause any strains due to TCE mismatch, the reliability of semiconductor module 10 would increase considerably. Further, this method would allow for self-aligned solder joining of metallurgical through connections 18 to the I/O pads on substrate 14 , thus eliminating the concern of inadequate surface contact area when the to pad distortion is on the high end of the specification.
- LGA Land Grid Array
- FIG. 2 semiconductor module 10 of FIG. 1 further including a heat spreader 26 and heat sink 30 is shown.
- heat spreader 26 is attached to semiconductor chip 12 using thermally conductive adhesive 28 .
- substrate 14 and/or interposer structure 16 support posts 32 A-B can be provided adjacent to interposer structure 16 .
- support posts 32 A-B extend from substrate 14 to heat spreader 26 , and support heat spreader 26 over semiconductor chip 12 . It should be appreciated that the quantity of support posts 32 A-B shown in FIG. 2 is intended to be illustrative only, and should not be limiting.
- underfill 34 can be provided throughout the interconnection, or at predetermined locations.
- underfill 34 can be a heat-curable material, selected from a broad range of chemical compositions including both rigid and flexibilized thermosetting epoxies, thermoplastics, urethanes, polysulfones, polyimides, polyetheramides/imides, and hybrids of same.
- underfill 34 can be a more compliant, thermoplastic material such as a silicone based product.
- underfill 34 when underfill 34 is used, metallurgical through connections 18 could be rigidly attached to both UBM 22 and TSM 24 to provide a desired level of thermo-mechanical fatigue.
- underfill 34 may be applied between interposer structure 16 and semiconductor chip 12 , between interposer structure 16 and substrate 14 , or between semiconductor chip 12 and substrate 14 (including interposer structure 16 ).
- a typical, high-modulus of elasticity underfill is indicated, e.g., materials having modulus ranging from 1-10 Giga Pascals.
- yet another embodiment uses underfill 34 between semiconductor chip 12 and interposer structure 16 if metallurgical through connections 18 are permanently attached to the semiconductor chip 12 .
- a more compliant, flexible, underfill material (having elastic modulus in the tens or hundreds of Mega Pascals, for example) is provided between the semiconductor chip 12 and substrate, including metallurgical through connections 18 .
- This feature would allow lateral displacement of the electrical contacts in response to thermally-induced stresses while preserving environmental protection of the IC devices(s) and joints.
- interposer structure 16 can be used within semiconductor modules 10 in a variety of scenarios and applications. In addition, although not shown herein, interposer structure 16 could be used as a fan-out layer so that a very fine pitch in UBM 22 may be connected to a more coarse pitch in substrate 14 .
- interposer structure 16 could be integrated at the wafer level (e.g., 8 or 12 inch wafers) and electrically tested before chip singulation (e.g., dicing) is performed.
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Abstract
Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.
Description
- The current application is a continuation application of co-pending U.S. patent application Ser. No. 10/721,984, filed on 25 Nov. 2003, which is hereby incorporated by reference.
- 1. Field of the Invention
- The present invention generally relates to a semiconductor module and method for forming the same. Specifically, the present invention provides a semiconductor module having an interposer structure with metallurgical through connections for electrically connecting a semiconductor chip to a substrate.
- 2. Related Art
- In the production of semiconductor modules, a semiconductor chip is often connected to a carrier such as a substrate. Typically, the connection is made using controlled collapse chip connection (C4) technology whereby solder bumps are used to join the two components together. Unfortunately, several problems emerge with the existing technology. First, the semiconductor chip usually has a different coefficient of thermal expansion (CTE) than the substrate. Given the close physical proximity of the semiconductor chip to the substrate, the solder bumps often deteriorate as the module heats up and cools off. This is especially the case with larger die sizes.
- In addition, ceramic substrates (if used) are generally non-planar, which can become a gating factor as the substrate X-Y dimensions increase. With shrinking pitch, there is a need to shrink C4 bump dimensions to avoid nearest neighbor shorting. However, a small C4 bump height results in a larger percentage of variation across the grid of bumps. Further, when the interconnections at the chip to substrate level migrate to a lead-free system, there will be no solder temperature hierarchy between first and second level interconnections, thus, creating an increased strain on the C4 structure due to higher temperatures of subsequent assembly operations. Still yet, current methods of depositing and joining C4 interconnections are expensive and involve the use of specific under bump metallization (UBM), which might have to be customized. Also, the UBM may need additional layers such as diffusion barriers and chip encapsulants so that it may endure a melting or partially melting C4 structure that reacts with the UBM during subsequent assembly operations.
- In view of the foregoing, there exists a need for an improved semiconductor module and method for forming the same. Specifically, a need exists for a semiconductor chip to be electrically connected to a substrate or the like so that the above concerns are alleviated.
- In general, the present invention provides a semiconductor module and method for forming the same. Specifically, under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.
- A first aspect of the present invention provides a semiconductor module, comprising a semiconductor chip; a substrate; and an interposer structure electrically connecting the semiconductor chip to the substrate, wherein the interposer structure includes metallurgical through connections having a predetermined shape.
- A second aspect of the present invention provides a semiconductor module, comprising a semiconductor chip having an under bump metallization; a substrate having a top surface metallization; and an interposer structure electrically connecting the under bump metallization to the top surface metallization, wherein the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
- A third aspect of the present invention provides a method for forming a semiconductor module, comprising: embedding metallurgical through connections within an elastomeric, compliant material to form an interposer structure; and positioning the interposer structure between a semiconductor chip and a substrate to electrically connect the semiconductor chip to the substrate.
- Therefore, the present invention provides a semiconductor module and method for forming the same.
- These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
-
FIG. 1 depicts a semiconductor module having an interposer structure, according to the present invention. -
FIG. 2 depicts the semiconductor module ofFIG. 1 further including a heat spreader and a heat sink. -
FIG. 3 depicts the semiconductor module ofFIG. 2 further including underfill. -
FIG. 4 depicts the semiconductor module ofFIG. 3 under a Land Grid Array load. -
FIG. 5 depicts the semiconductor module ofFIG. 1 in a TCA application. - The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.
- As indicated above, the present invention provides a semiconductor module and method for forming the same. Specifically, under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.
- Referring now to
FIG. 1 , anillustrative semiconductor module 10 formed in accordance with the present invention is shown. As depicted,semiconductor module 10 includessemiconductor chip 12 and carrier/substrate 14 withinterposer structure 16 positioned therebetween. It should be appreciated in advance thatsemiconductor module 10 could be a single chip module or a multi-chip module. In the case of a multi-chip module,interposer structure 16 could be positioned between each semiconductor chip andsubstrate 14. Moreover, it should be understood thatsubstrate 14 could be any type of substrate now known or later developed. For example,substrate 14 could be ceramic or organic. In any event,interposer structure 16 is positioned betweensemiconductor chip 12 andsubstrate 14 under the present invention to preserve the interface therebetween. As indicated above, differences in the CTE between semiconductor chip 12 (e.g., 3 ppm/° C., CTE) and substrate 14 (15-18 ppm/° C., CTE for an organic substrate) cause various issues assemiconductor module 10 is subjected to temperature change. Positioninginterposer structure 16 betweensemiconductor chip 12 andsubstrate 14 increases the distance between the two components and alleviates the problems associated with the difference in CTEs. - In any event,
interposer structure 16 generally comprises a elastomeric,compliant material 20 having metallurgical throughconnections 18 “embedded” or “positioned” therein. Metallurgical throughconnections 18 electrically connect under bump metallization (UBM) or bottom layer metallurgy (BLM) 22 ofsemiconductor chip 12 to top surface metallurgy (TSM) 24 ofsubstrate 14. In a typical embodiment,interposer structure 16 can comprise Cupil-T, which is commercially available from Nitto Denko, Inc. of Osaka, Japan. Moreover, metallurgical throughconnections 18 can be formed to have a predetermined shape depending on the load applied tosemiconductor module 10 to best optimize the contact. For example, metallurgical throughconnections 18 could be spherical, ellipsoid, s-shaped, c-shaped, or elongate (i.e., column-like). various factors can be considered when determining the shape of metallurgical throughconnections 18. Such factors include, among other things: (1) camber (i.e., non-flatness ofsubstrate 14 and semiconductor chip 12) in that more camber might mean taller through connections with an overall greater degree of compressibility; (2) distortion (i.e., positional accuracy of the I/O pads on substrate 14) in that the worse the distortion, the bigger the contact area on metallurgical throughconnections 18 that would have to be provided so that some degree of contact is always present between metallurgical throughconnections 18 and the I/O pads; and (3) process considerations such as how the through connections are made. In addition, metallurgical throughconnections 18 could be formed from one or more materials. To this extent, metallurgical throughconnections 18 could have a core formed from Copper, Copper-Beryllium, or the like that is coated with gold. Still yet,UBM 22 and/orTSM 24 could be gold, solder or the like. - To provide a more stable structure,
interposer structure 16 could be rigidly attached (e.g., hard soldered) to eitherUBM 22 orTSM 24, or both. For example, ifsemiconductor module 10 is placed under a Land Grid Array (LGA) load, metallurgical throughconnections 18 could be hard soldered toTSM 24, while the contact between metallurgical throughconnections 18 andUBM 22 is maintained solely by the LGA load. This would enable free expansion of the semiconductor chip side ofinterposer structure 16 under the influence of temperature. Sinceinterposer structure 16 would not cause any strains due to TCE mismatch, the reliability ofsemiconductor module 10 would increase considerably. Further, this method would allow for self-aligned solder joining of metallurgical throughconnections 18 to the I/O pads onsubstrate 14, thus eliminating the concern of inadequate surface contact area when the to pad distortion is on the high end of the specification. - Referring now to
FIG. 2 ,semiconductor module 10 ofFIG. 1 further including aheat spreader 26 andheat sink 30 is shown. As depicted,heat spreader 26 is attached tosemiconductor chip 12 using thermallyconductive adhesive 28. To prevent the increased weight cause byheat spreader 26 andheat sink 30 from damagingsemiconductor chip 12,substrate 14 and/orinterposer structure 16, support posts 32A-B can be provided adjacent tointerposer structure 16. Specifically, support posts 32A-B extend fromsubstrate 14 to heatspreader 26, and supportheat spreader 26 oversemiconductor chip 12. It should be appreciated that the quantity of support posts 32A-B shown inFIG. 2 is intended to be illustrative only, and should not be limiting. - Regardless, to further seal
interposer member 16 betweensemiconductor chip 12 andsubstrate 14, underfill could be provided. Specifically, referring toFIG. 3 ,semiconductor module 10 ofFIG. 2 is shown as further includingunderfill 34. Under the present invention, underfill 34 can be provided throughout the interconnection, or at predetermined locations. Further, underfill 34 can be a heat-curable material, selected from a broad range of chemical compositions including both rigid and flexibilized thermosetting epoxies, thermoplastics, urethanes, polysulfones, polyimides, polyetheramides/imides, and hybrids of same. Alternatively, underfill 34 can be a more compliant, thermoplastic material such as a silicone based product. - In any event, when underfill 34 is used, metallurgical through
connections 18 could be rigidly attached to bothUBM 22 andTSM 24 to provide a desired level of thermo-mechanical fatigue. To this extent, underfill 34 may be applied betweeninterposer structure 16 andsemiconductor chip 12, betweeninterposer structure 16 andsubstrate 14, or betweensemiconductor chip 12 and substrate 14 (including interposer structure 16). In a typical embodiment, it is desirable to rigidly affixinterposer structure 16 tosubstrate 14 whenever metallurgical throughconnections 18 are soldered to thesubstrate 14. In this case, a typical, high-modulus of elasticity underfill is indicated, e.g., materials having modulus ranging from 1-10 Giga Pascals. Similarly, yet another embodiment usesunderfill 34 betweensemiconductor chip 12 andinterposer structure 16 if metallurgical throughconnections 18 are permanently attached to thesemiconductor chip 12. - In yet another embodiment of the invention, a more compliant, flexible, underfill material (having elastic modulus in the tens or hundreds of Mega Pascals, for example) is provided between the
semiconductor chip 12 and substrate, including metallurgical throughconnections 18. This feature would allow lateral displacement of the electrical contacts in response to thermally-induced stresses while preserving environmental protection of the IC devices(s) and joints. - Referring now to
FIG. 4 ,semiconductor module 10 ofFIG. 3 under an LGA load is shown. Under an LGA load, forces are exerted onsemiconductor module 10 in the direction of the arrows shown. As indicated above in conjunction withFIG. 1 , metallurgical throughconnections 18 could be rigidly attached toTSM 24 under such a load. Referring toFIG. 5 ,semiconductor module 10 under a Temporary Chip Attachment (TCA) application is depicted. Under a TCA application, a porous surface is provided for vacuum pickup and/or placement ofsemiconductor chip 10. Accordingly, as can be seen,interposer structure 16 can be used withinsemiconductor modules 10 in a variety of scenarios and applications. In addition, although not shown herein,interposer structure 16 could be used as a fan-out layer so that a very fine pitch inUBM 22 may be connected to a more coarse pitch insubstrate 14. - The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims. For example, in another embodiment,
interposer structure 16 could be integrated at the wafer level (e.g., 8 or 12 inch wafers) and electrically tested before chip singulation (e.g., dicing) is performed.
Claims (11)
1. A temporary chip attachment structure, comprising:
a semiconductor chip;
a substrate;
an interposer structure electrically connecting the semiconductor chip to the substrate, wherein the interposer structure includes metallurgical through connections having a predetermined shape; and
a chip pick and place head adapted to one of pick up or place the semiconductor chip.
2. The temporary chip attachment structure of claim 1 , the chip pick and place head further comprising a vacuum system for picking up the semiconductor chip.
3. The temporary chip attachment structure of claim 2 , the vacuum system further comprising a porous surface on a side of the head adjacent the semiconductor chip.
4. The temporary chip attachment structure of claim 1 , the chip pick and place head further comprising a cooling system configured to cool the head.
5. A temporary chip attachment structure, comprising:
a semiconductor chip having an under bump metallization;
a substrate having a top surface metallization;
an interposer structure electrically connecting the under bump metallization to the top surface metallization, wherein the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape; and
a chip pick and place head including a vacuum chip pick-up.
6. The temporary chip attachment structure of claim 5 , the vacuum chip pick-up further comprising a porous surface on a side of the head adjacent the semiconductor chip.
7. The temporary chip attachment structure of claim 5 , the chip pick and place head further comprising a cooling system configured to cool the head.
8. A method for attaching a semiconductor module, comprising:
providing embedded metallurgical through connections within an elastomeric, compliant material to form an interposer structure;
positioning the interposer structure between a semiconductor chip and a substrate to electrically connect the semiconductor chip to the substrate;
providing a chip pick and place head; and
attaching the chip pick and place head to the semiconductor chip.
9. The method of claim 8 , the attaching further comprising using a vacuum system for picking up the semiconductor chip.
10. The method of claim 9 , the vacuum system further comprising a porous surface on a side of the head adjacent the semiconductor chip.
11. The method of claim 8 , the chip pick and place head further comprising a cooling system configured to cool the head.
Priority Applications (1)
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US11/772,901 US20070252288A1 (en) | 2003-11-25 | 2007-07-03 | Semiconductor module and method for forming the same |
Applications Claiming Priority (2)
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US10/721,984 US7245022B2 (en) | 2003-11-25 | 2003-11-25 | Semiconductor module with improved interposer structure and method for forming the same |
US11/772,901 US20070252288A1 (en) | 2003-11-25 | 2007-07-03 | Semiconductor module and method for forming the same |
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US10/721,984 Continuation US7245022B2 (en) | 2003-11-25 | 2003-11-25 | Semiconductor module with improved interposer structure and method for forming the same |
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US20070252288A1 true US20070252288A1 (en) | 2007-11-01 |
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US10/721,984 Expired - Fee Related US7245022B2 (en) | 2003-11-25 | 2003-11-25 | Semiconductor module with improved interposer structure and method for forming the same |
US11/772,901 Abandoned US20070252288A1 (en) | 2003-11-25 | 2007-07-03 | Semiconductor module and method for forming the same |
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US10/721,984 Expired - Fee Related US7245022B2 (en) | 2003-11-25 | 2003-11-25 | Semiconductor module with improved interposer structure and method for forming the same |
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US7245022B2 (en) | 2007-07-17 |
US20050110160A1 (en) | 2005-05-26 |
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