US20070120194A1 - Semiconductor device and a method of manufacturing the same - Google Patents
Semiconductor device and a method of manufacturing the same Download PDFInfo
- Publication number
- US20070120194A1 US20070120194A1 US11/657,592 US65759207A US2007120194A1 US 20070120194 A1 US20070120194 A1 US 20070120194A1 US 65759207 A US65759207 A US 65759207A US 2007120194 A1 US2007120194 A1 US 2007120194A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor region
- gate
- type
- type semiconductor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 226
- 238000004519 manufacturing process Methods 0.000 title description 23
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 21
- 239000010410 layer Substances 0.000 claims 11
- 239000011229 interlayer Substances 0.000 claims 1
- 230000002265 prevention Effects 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 37
- 239000002019 doping agent Substances 0.000 description 31
- 150000002500 ions Chemical class 0.000 description 30
- 239000012212 insulator Substances 0.000 description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 21
- 229920005591 polysilicon Polymers 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 13
- 238000007254 oxidation reaction Methods 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000004020 conductor Substances 0.000 description 10
- 238000002513 implantation Methods 0.000 description 8
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000009877 rendering Methods 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Definitions
- the invention relates to a semiconductor device and for a method of manufacturing the same, and in particular, to a semiconductor device and method employing power MISFETs (Metal Insulator Semiconductor Field Effect Transistors).
- MISFETs Metal Insulator Semiconductor Field Effect Transistors
- a trench (groove) gate type power MOSFET Metal Oxide Semiconductor Field Effect Transistor
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- a power transistor such as the power MOSFET, may be used for high power applications, such as wherein the power is not less than several watts.
- a power MISFET may be a vertical type and/or a lateral type MISFET, depending on the structure of the gate thereof.
- a MISFET may be further classified as a trench (groove) gate type, or a planar gate type.
- a power MISFET may be used as a switching element of a DC-DC converter, for example, such as for use as a power source circuit for a computer. Since there has recently been a trend of larger current requirements for a CPU (Central Processing Unit) of a computer, to which the DC-DC converter supplies power, a larger current is required of the DC-DC converter as well. Requiring larger currents may cause an increase in ON-loss for a power MISFET. Accordingly, lower ON-resistance also is requited of a power MISFET used in a DC-DC converter.
- CPU Central Processing Unit
- a deep groove is formed in a top, element-forming surface of a semiconductor substrate (hereinafter referred to as a substrate), and a gate is formed by embedding a conductor in the groove.
- a gate is formed over a top surface of a substrate through the intermediary of a gate insulator. Accordingly, in the trench gate type power MISFET, a current flow path in the substrate becomes shorter as compared with a planar gate type power MISFET, so that ON-resistance can be reduced.
- a gate insulator is formed on the sidewalls and bottom surface of the groove, there may be an increase in capacitance due to the gate insulator acting as a capacitance insulator, and the gate part acting as a capacitance electrode, as the groove is rendered deeper.
- capacitance from the gate insulator acting as the capacitance insulator and the gate acting as the capacitance electrode is reduced as compared with the trench gate type power MISFET, but the number of the gate parts that can be disposed per unit area is reduced if a sufficient gate length to prevent pinch off is present.
- the number of the gate parts that can be disposed on the semiconductor chip is less than that in the case of a trench gate type power MISFET.
- ON-resistance of the semiconductor chip increases as compared with the trench gate type power MISFET.
- a power MISFET may include a multitude, such as, for example, several tens of thousands, of finely patterned MISFETs may be connected in parallel.
- Such a power MISFET may be used as a switching element of a DC-DC converter, for example, such as for use as a power source circuit for a computer, such as a desktop type, note type, server, and the like.
- Minimization of capacitance for a choke coil, I/O, and so forth, as well as fast response to variation in load, is required of a DC-DC converter. Accordingly, there is a trend for a DC-DC converter towards higher frequency, and as the DC-DC converter operates higher in frequency, an increase in switching loss and drive loss may occur in a power MISFET. Since the switching loss is proportional to a feedback capacitance of a power MISFET, and the drive loss is proportional to an input capacitance, reduction in these capacitances is required for a power MISFET used in a DC-DC converter.
- FIG. 34 illustrates the capacitance between the gate and the source, and the capacitance between the gate and the drain.
- respective voltages applied to a gate electrode GELE, an n + type semiconductor region NSEM as the source, and an n ⁇ type single crystal layer NEPI as the drain are denoted by VG, VS, and VD, respectively, and it is assumed that the voltage VS is at the same potential as that for the source.
- the capacitance between the gate and the source can be expressed as capacitance C 1 between the gate electrode GELE and the p ⁇ type semiconductor region PBOD, acting as capacitance electrodes, wherein a gate insulator GINS acts as a capacitance insulator.
- This capacitance C 1 may be coupled in series with capacitance C 2 between the gate electrode GELE and the p ⁇ type semiconductor region PBOD acting as capacitance electrodes, wherein a depletion layer DEP (see FIG. 34 , in gray scale) acts as a capacitance insulator.
- the capacitance between the gate and the drain can be expressed as capacitance C 3 , with the gate electrode GELE and the n ⁇ type single crystal layer NEPI acting as capacitance electrodes, and the gate insulator GINS acting as a capacitance insulator.
- Capacitance C 3 may be coupled in series with capacitance C 4 , with the gate electrode GELE and the n ⁇ type single crystal layer NEPI acting as capacitance electrodes, and the depletion layer DEP acting as a capacitance insulator.
- the trench gate type power MISFET shown in FIG. 35 has a trench gate structure wherein grooves 103 are formed in a top surface of an n + type single crystal silicon substrate 101 , and in an n ⁇ type single crystal silicon layer 102 formed in the upper part thereof. A conductor is embedded in each of the grooves 103 through gate insulator 104 , thereby forming a gate 105 .
- a current flow path in the n ⁇ type single crystal silicon layer 102 which is relatively low in impurity concentration can be rendered shorter than that in a planar gate structure, thereby reducing JFET (Junction FET) resistance acting as ON-resistance.
- a source electrode 106 may be formed to fill each of grooves 108 in the top surface of the substrate and insulating film 107 , which source electrode may be electrically connected to a p + type semiconductor region 110 formed in a p ⁇ type semiconductor region 109 serving as a channel layer, wherein an n + type semiconductor region 111 serves as a source region.
- the p + type semiconductor region 110 can be formed by self-aligned implantation of dopant ions from the groove 108 into the substrate, so that mask alignment allowance for implantation of the dopant ions need not be taken into account. Accordingly, because MISFET cell pitches can be scaled down, higher integration of the power MISFETs can be attained, and ON-resistance can be reduced.
- a channel length runs along a depth of the substrate, so as to allow for scale-down of the power MISFET cell pitches as compared with the planar gate type power MISFET (in which a channel length runs along the top surface of the substrate).
- the gate insulator may act as a capacitance insulator and the gate may act as a capacitance electrode.
- Input capacitance among the capacitance components is proportional to a length of the periphery of the groove 103 (a surface area of the groove 103 under the n + type semiconductor region 111 ), and feedback capacitance is proportional to a distance D 12 of a portion of the groove 103 extending from the p ⁇ type semiconductor region 109 toward the n ⁇ type single crystal silicon layer 102 (a surface area of the potion of the groove 103 , in contact with the n ⁇ type single crystal silicon layer 102 ).
- narrowing a width of the groove 103 reduces the input capacitance, and reducing the distance D 12 of the portion of the groove 103 extending from the p ⁇ type semiconductor region 109 toward the n ⁇ type single crystal silicon layer 102 (thus rendering the groove shallower) reduces feedback capacitance.
- the threshold voltage of the MISFET may increase, resulting in an increase in ON-resistance.
- the p ⁇ type semiconductor region 109 has the same depth as that of the groove 103 in order to reduce the distance of the groove 103 , the bottom of the groove 103 may be covered by the p ⁇ type semiconductor region 109 due to manufacturing variation of the groove 103 , and the threshold voltage of the MISFET thus increases, thereby resulting in an increase in the ON-resistance.
- a semiconductor device having MISFETs including: a first semiconductor layer having a first conductivity type, formed over the top surface of a semiconductor substrate; a second semiconductor layer having a second conductivity type opposite the first conductivity type, formed over the first semiconductor layer; a plurality of first groove parts of not more than 1 ⁇ m in depth, formed in the top surface of the semiconductor substrate, wherein at least a portion of respective bottoms of ones of the first groove parts are in contact with the first semiconductor layer; a first insulating film formed on the sidewall and bottom of each of the first groove parts; a first conductor formed over the first insulating film, wherein the first conductor fills up the respective first groove parts; a third semiconductor layer having the first conductivity type, formed in the second semiconductor layer adjacent to respective ones of the first groove parts; a fourth semiconductor layer having the second conductivity type, formed in the second semiconductor layer
- the invention provides in an aspect a method of manufacturing a semiconductor device having MISFETs, including the steps of:
- first groove parts are formed to have a depth not more than 1 ⁇ m, and wherein at least part of the respective bottoms of the first groove parts are in contact with the first semiconductor layer, and wherein the fifth semiconductor layer is formed to be higher in impurity concentration than the second semiconductor layer, thereby forming MISFETs that each have the first semiconductor layer and the third semiconductor layer as a source or a drain thereof, and the second semiconductor layer as a channel forming region thereof.
- the present invention provides a semiconductor device and method that provides a power MISFET that simultaneously provides lower ON-resistance and lower capacitance.
- FIG. 1 is a sectional view of a semiconductor device according to the invention.
- FIG. 2 is a sectional view of a step of manufacturing the semiconductor device, subsequent to a step shown in FIG. 1 ;
- FIG. 3 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown in FIG. 2 ;
- FIG. 4 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown in FIG. 3 ;
- FIG. 5 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown in FIG. 4 ;
- FIG. 6 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown in FIG. 5 ;
- FIG. 7 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown in FIG. 6 ;
- FIG. 8 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown in FIG. 7 ;
- FIG. 9 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown in FIG. 8 ;
- FIG. 10 is a plan view of a step of manufacturing the semiconductor device
- FIG. 11 is a plan view of a step of manufacturing the semiconductor device
- FIG. 12 is an expanded sectional view of a step of manufacturing the semiconductor device
- FIG. 13 is a schematic representation showing a depth from the surface of a substrate and impurity concentration, at a position along a line A-A in FIG. 12 ;
- FIG. 14 is a schematic representation showing a source-drain voltage and a drain current for each of power MISFETs in the semiconductor device provided with a punch-through stopper layer, and without the punch-through stopper layer;
- FIG. 15 is a circuit diagram of a DC-DC converter including the semiconductor device
- FIG. 16 is a schematic illustration showing breakdown of components in the DC-DC converter shown in FIG. 15 ;
- FIG. 17 is a schematic illustration showing breakdown of components in the DC-DC converter shown in FIG. 15 ;
- FIG. 18 is a schematic representation showing a gate resistance Rg of each of the power MISFETs in the DC-DC converter shown in FIG. 15 and efficiency ⁇ of a DC-DC converter system;
- FIG. 19 is a plan view of the semiconductor device
- FIG. 20 is a sectional view of the semiconductor device
- FIG. 21 is a sectional view the semiconductor device
- FIG. 22 is a plan view of an off-angle substrate
- FIG. 23 is a sectional view on line C-C in FIG. 22 ;
- FIG. 24 is a schematic representation showing a depth from the surface of a substrate and impurity concentration distribution when dopant ions are implanted into the substrate;
- FIG. 25 is a schematic representation showing a depth from the surface of a substrate and impurity concentration distribution when dopant ions are implanted into the off-angle substrate;
- FIG. 26 is a sectional view of a semiconductor device
- FIG. 27 is a sectional view of the semiconductor device
- FIG. 28 is a schematic representation showing a drain voltage and an input capacitance in the case of a power MISFET
- FIG. 29 is a schematic representation showing the drain voltage and a feedback capacitance in the case of a power MISFET
- FIG. 30 is a schematic representation showing calculation results on respective losses of a power MISFET, in the case of those being used as the switching element of the DC-DC converter;
- FIG. 31 is a sectional view of a semiconductor device
- FIG. 32 is a sectional view of the semiconductor device
- FIG. 33 is an equivalent circuit diagram for describing feedback capacitance and input capacitance of a power MISFET
- FIG. 34 is a sectional view of the power MISFET in FIG. 33 , and describes capacitance between a gate and a source, and capacitance between the gate and a drain;
- FIG. 35 is a sectional view of a trench gate type power MISFET.
- a semiconductor substrate (hereinafter also referred to as a substrate) 1 is provided.
- An n ⁇ type single crystal silicon layer (a first semiconductor layer) 1 B may doped with a dopant ⁇ for example p (phosphorus) ⁇ having an n-type conductivity to undergo epitaxial growth of an n + type single crystal silicon substrate 1 A having the n-type conductivity (a first conductivity type).
- a dopant for example p (phosphorus) ⁇ having an n-type conductivity to undergo epitaxial growth of an n + type single crystal silicon substrate 1 A having the n-type conductivity (a first conductivity type).
- An off-angle substrate formed by use of a semiconductor wafer (hereinafter referred to as a first wafer), the ( 100 ) face of which is the top surface (an element forming surface), may be used as the base substrate, and a second wafer, the top surface of which is a face, and the normal to which is a straight line tilted by a predetermined angle from the normal to the top surface of the first wafer in the direction of an orientation flat or a notch may be formed in the first wafer.
- the n + type single crystal silicon substrate 1 A and the n ⁇ type single crystal silicon layer 1 B may serve as a drain region for the respective power MISFETs.
- a silicon oxide film 3 may be formed by applying, for example, thermal oxidation to a surface (the top surface) of the n ⁇ type single crystal silicon layer 1 B. Subsequently, using a silicon nitride film (not shown) patterned on the silicon oxide film 3 by photolithographic techniques, such as a mask, a dopant ⁇ for example B (boron) ⁇ having a p-type conductivity may be implanted into the substrate 1 and may undergo thermal diffusion, thereby forming a p-type well 5 . Thereafter, the silicon nitride film may be removed.
- grooves 7 may be formed by etching the silicon oxide film 3 and the substrate 1 , such as by use of a photo resist film patterned by the photolithographic techniques, such as a mask.
- the grooves 7 may be formed to have a depth of about 1 ⁇ m or less. Further, the grooves 7 may be formed in a shape, such as a square, polygon, or hexagon, extending in a mesh-like pattern, or may be formed in a multitude of stripes extending in substantially the same direction.
- a thermal oxidation film (first insulating film) 9 is formed on the bottom and sidewall of each of the grooves 7 .
- the thermal oxidation film 9 may serve as a gate insulator for the respective power MISFETs.
- a polysilicon film doped with, for example, P is deposited on the silicon oxide film 3 , including on the inside of each of the grooves 7 , to thereby fill the respective grooves 7 with the polysilicon film.
- the polysilicon film layer is formed on a portion of the silicon oxide film 3 , over the p-type well 5 .
- the polysilicon film is etched so as to leave portions thereof in the grooves 7 , thereby forming a gate electrode (first conductor) 10 for the respective power MISFETs inside the respective grooves 7 .
- a portion of the polysilicon film is left on the silicon oxide film 3 , in a peripheral part of a chip region (not shown), thereby forming a polysilicon film pattern 11 .
- the gate electrodes 10 and the polysilicon film pattern 11 are electrically connected to each other in at least one region (not shown in FIG. 4 ).
- the silicon oxide film 3 is etched to thereby remove unnecessary portions thereof.
- a region whereat the silicon oxide film 3 is formed that is underneath the polysilicon film pattern 11 becomes an isolation region, and regions defined by the isolation region become element forming regions (active regions).
- a silicon oxide film 12 is deposited over the substrate 1 .
- dopant ions ⁇ for example B (boron) ⁇ having a p-type conductivity type, i.e. a second conductivity type different from the first conductivity type are implanted into the n ⁇ type single crystal silicon layer 1 B at a concentration on the order of 5 ⁇ 10 12 ions/cm 2 .
- the dopant ions are caused to undergo diffusion, thereby forming a p ⁇ type semiconductor region (a second semiconductor layer) 13 .
- the p ⁇ type semiconductor region 13 may be formed in such a way as not to cover the respective bottoms of the grooves 7 .
- the p ⁇ type semiconductor region 13 may serve as a channel layer for the respective power MISFETs.
- the p ⁇ type semiconductor region 13 may have a depth not less than about 10% shallower than the respective bottoms of the grooves 7 . That is, as described above, since the grooves 7 are formed to have a depth of about 10 ⁇ m or less, the portion of each of the grooves 7 extending off of the p ⁇ type semiconductor region 13 may be kept to a depth of not more than about 0.1 ⁇ m.
- dopant ions for example B
- dopant ions having the p-type conductivity may be implanted into the n ⁇ type single crystal silicon layer 1 B at a concentration in the order of 3 ⁇ 10 12 ions/cm 2 , thereby forming a p-type semiconductor region (fifth semiconductor layer) 14 higher in impurity concentration than the p ⁇ type semiconductor region 13 .
- the photo mask uses in patterning the photo resist film at this stage may be reused from the a photo mask used in patterning the photo resist film at the time of forming the p ⁇ type semiconductor region 13 , for example.
- dopant ions for example, As (arsenic) ⁇ having the n-type conductivity are implanted into the n ⁇ type single crystal silicon layer 1 B.
- the dopant ions are caused to undergo diffusion, thereby forming an n + type semiconductor region (a third semiconductor layer) 15 over the p-type semiconductor region 14 inside the p ⁇ type semiconductor region 13 .
- respective power MISFETs having the drain region in the n + type single crystal silicon substrate 1 A and the n ⁇ type single crystal silicon layer 1 B, and the source region in the n + type semiconductor region 15 .
- the p-type semiconductor region 14 may serve as a punch-through stopper layer for the respective power MISFETs.
- a PSG (Phospho-Silicate Glass) film is deposited over the substrate 1 , and subsequently an SOG (Spin On Glass) film is applied to the top of the PSG film, thereby forming an insulating film 16 of the PSG film and the SOG film.
- the insulating film 16 , the silicon oxide film 12 , and the substrate 1 are etched, thereby forming contact grooves (a second groove part) 17 .
- the contact groove 17 is formed between the gate electrodes 10 adjacent to each other so as to penetrate through the n + type semiconductor region 15 serving as the source region.
- the insulating film 16 and the silicon oxide film 12 over the polysilicon film pattern 11 are also patterned, thereby forming contact grooves 18 reaching the polysilicon film pattern 11 .
- BF 2 (boron difluoride) ions as dopant ions having the p-type conductivity may be introduced from the bottom of each of the contact grooves 17 , thereby forming a p + type semiconductor region (a fourth semiconductor layer) 20 in such a way as to cover the respective bottoms of the contact grooves 17 .
- Impurity concentration in the p + type semiconductor region 20 may be rendered higher than that in the p-type semiconductor region 14 .
- the p + type semiconductor region 20 is formed in a self-aligned fashion on the respective bottoms of the contact grooves 17 , so that, for example, allowance for mask alignment can be reduced, thereby enabling spacing between the gate electrodes 10 adjacent to each other to be minimized.
- the p + type semiconductor region 20 may cause interconnects formed in later steps of this exemplary process to come in ohmic contact with the p ⁇ type semiconductor region 13 at the respective bottoms of the contact grooves 17 .
- the Al film includes Al as the main constituent, and may contain other metals as will be apparent to those skilled in the art.
- FIGS. 10 and 11 show a chip region CHP corresponding to one chip obtained when the substrate 1 is divided into individual chips in a manufacturing step.
- FIG. 10 exhibits a case of the respective gate electrodes 10 being formed in the shape of a square and arranged in a mesh-like pattern
- FIG. 11 exhibits a case of the respective gate electrodes 10 being formed in a stripe-like pattern.
- FIG. 12 is an expanded sectional view showing the vicinity of the gate electrode 10 .
- FIG. 13 is a schematic representation showing relationship between a depth from the surface of the substrate 1 , and an impurity concentration at a position along a line A-A in FIG. 12 .
- the grooves 7 may be formed to have a depth D 1 as shallow as about 1 ⁇ m or less. By rendering the grooves 7 shallower, it is possible to reduce an input capacitance among capacitive components in a gate insulator (thermal oxidation film 9 ) that cause the gate insulator to act as a capacitance insulator and the gate electrodes 10 to act as capacitance electrodes.
- a gate insulator thermal oxidation film 9
- a gate capacitance can be rendered to be not more than about 1 ⁇ 10 ⁇ 3 per 1 ⁇ m in a direction in which the gate electrodes 10 (grooves 7 ) extend in a given plane, if a voltage of 0V is applied to the gate electrodes 10 and the source region (the n + type semiconductor region 15 ), while a voltage varying from 0V to 10V at a frequency of 1 MHz is applied to the drain region (the n + type single crystal silicon substrate 1 A and the n ⁇ type single crystal silicon layer 1 B).
- a direction (first direction) in which the gate electrodes 10 (grooves 7 ) are extended in a plane can be defined as the y-direction.
- the p ⁇ type semiconductor region 13 may be formed at a shallow depth and a junction of the p ⁇ type semiconductor region 13 and the n ⁇ type single crystal silicon layer 1 B may be set at a shallow position (shallower junctioning). In the case of such shallower junctioning, however, when a voltage is applied between the drain and the source, depletion may occur to the channel layer (the p ⁇ type semiconductor region 13 ) for the respective power MISFETs, resulting in punch through. If the impurity concentration of the p ⁇ type semiconductor region 13 is raised in order to prevent the depletion from occurring to the channel layer, the threshold voltage of the power MISFET may become higher, resulting in an increase in the ON-resistance.
- the p-type semiconductor region 14 may be locally higher in impurity concentration than the p ⁇ type semiconductor region 13 , and is formed inside the p ⁇ type semiconductor region 13 without raising the impurity concentration of the p ⁇ type semiconductor region 13 , thereby causing the p-type semiconductor region 14 to function as a punch-through stopper layer.
- the occurrence of punch through can be prevented, as can be a rise in threshold voltage and an increase in the ON-resistance.
- reduction of the input capacitance can be implemented while preventing the occurrence of punch through.
- the threshold voltage can be held to not higher than about 2V.
- the sum of a dopant dose for the formation of the p ⁇ type semiconductor region 13 , and a dopant dose for the formation of the p-type semiconductor region 14 may be rendered similar in magnitude as compared to a dopant dose for the formation of the p ⁇ type semiconductor region 13 in the first case of a power MISFET with grooves 7 having a depth of about 1 ⁇ m or more, and without a punch-through stopper layer (the p-type semiconductor region 14 ).
- the dopant dose for the formation of the p ⁇ type semiconductor region 13 may be reduced as compared with that in the first case power MISFET.
- the groove 7 may become shallower in depth, so that in heat treatment after dopant implantation for the formation of the p ⁇ type semiconductor region 13 , applied in order to form the p ⁇ type semiconductor region 13 in such a way as not to cover the bottom of the groove 7 , and to implement the shallower junctioning of the p ⁇ type semiconductor region 13 and the n ⁇ type single crystal silicon layer 1 B, a treatment temperature may be lowered.
- the treatment time may be shortened as compared with that in the manufacturing process for the first case power MISFET.
- the p-type semiconductor region 14 serving as the punch-through stopper layer is may be formed after the heat treatment for the formation of the p ⁇ type semiconductor region 13 .
- time for heat treatment applied to the substrate 1 after dopant implantation for the formation of the p-type semiconductor region 14 can be shortened, so that localized formation of the p-type semiconductor region 14 inside the p ⁇ type semiconductor region 13 becomes possible.
- treatment time is may be shortened as much as possible in order to form the same at a shallow depth, and adoption of a short heat treatment time, such as, for example, by a lamp anneal treatment, may occur.
- the region 13 is designed so as to have a depth shallower by, for example, not less than about 10% of the respective depths of the grooves 7 , in order to prevent the p ⁇ type semiconductor region 13 from covering the bottoms of the grooves 7 .
- the grooves 7 are to have a depth about 1 ⁇ m or less, the distance D 2 of the portion of the groove 7 , extending from the p ⁇ type semiconductor region 13 toward the n ⁇ type single crystal silicon layer 1 B, can be rendered not more than about 0.1 ⁇ m.
- the p-type semiconductor region 14 it becomes possible to reduce base resistance of a parasitic npn bipolar transistor developed by the n ⁇ type single crystal silicon layer 1 B acting as a collector, the p ⁇ type semiconductor region 13 acting as a base, and the n + type semiconductor region 15 acting as an emitter. Accordingly, avalanche yield strength of the power MISFET can be enhanced.
- FIG. 14 shows a source-drain voltage Vds, and a drain current Id, of the power MISFETs in the case wherein the p-type semiconductor region 14 is provided, and in the case wherein the p-type semiconductor region 14 is not provided.
- Vds source-drain voltage
- Id drain current
- the power MISFETs may be used as switching elements (High-side MISFETQ H and Low-side MISFETQ L ) in, for example, a DC-DC converter circuit, as shown in FIG. 15 .
- a component analyses on the total loss of the DC-DC converter has been performed by a simulation to examine the breakdown of components. In a simulation condition of an input voltage Vin at 12V, an output voltage Vout at 1.3V, and a circuit operation frequency at 1 MHz, output current Iout at 2 A and 10 A, respectively, were analyzed.
- FIGS. 16 and 17 show breakdown of components and the total loss of the DC-DC converter at output current Iout at 2 A and 10 A, respectively. As show in FIGS.
- the sum of a switching loss and a drive loss occupies about 56% of the total loss of the DC-DC converter at output current lout at 2 A, and about 41% of the same at output current Iout at 10 A.
- the switching loss refers to a loss occurring when the power MISFET is turned ON or OFF
- the drive loss refers to power required for driving the power MISFET.
- a drain-source voltage of the power MISFET is Vds
- a drain current is Id
- ON-time is tr
- OFF-time is tf
- an input gate capacitance is Qg
- a gate-source voltage is Vgs
- a circuit operation frequency is f
- a switching loss can be expressed as: 1 ⁇ 2 ⁇ (tr+tf) ⁇ Id ⁇ Vds ⁇ f
- a drive loss can be expressed as: Qg ⁇ Vgs ⁇ f.
- the switching loss and the drive loss are proportional to a frequency, such that the switching loss and the drive loss increase as the circuit operation frequency becomes higher. Further, the switching loss is proportional to the feedback capacitance of the power MISFET, and the drive loss is proportional to the input capacitance of the power MISFET. As previously described, since the feedback capacitance as well as the input capacitance of the power MISFET can be reduced, the loss of the DC-DC converter can be significantly reduced. Thus, it is possible to implement a higher efficiency DC-DC converter system through the use of the present invention.
- FIG. 18 is a schematic representation showing the relationship between a gate resistance Rg of each of the power MISFETs in the DC-DC converter shown in FIG. 15 , and efficiency ⁇ of the DC-DC converter system. Results shown in FIG. 18 were obtained for circuit operation frequencies of 300 kHz and 1 MHz, respectively, when the input voltage Vin was at 12V, the output voltage Vout at 1.3V, and the output current at 10 A. As shown in FIG. 18 , with the gate resistance Rg increases, the efficiency ⁇ of the DC-DC converter system deteriorates, and in particular, the higher the circuit operation frequency becomes, the greater the efficiency ⁇ of the DC-DC converter system deteriorates.
- a “gate finger” structure as shown in FIG. 19 , may be adopted. More specifically, a gate finger part (the second electrode, a second part) 21 A, formed integrally with the gate interconnect 21 formed along the periphery of the chip region CHP, may be provided. Further, a gate interconnect 21 B may be formed integrally with both the gate interconnect 21 and the gate finger part 21 A. The gate finger part 21 A may be extended from the gate interconnect 21 toward the inner side of the chip region CHP, in a plane, and under the gate finger part 21 A, the polysilicon film pattern 11 (refer to FIG. 9 ), which is electrically connected to the gate electrodes 10 , is disposed.
- the gate finger part 21 A is formed so as to fill up the contact grooves 18 (refer to FIG. 9 ). Since the gate finger part 21 A is formed integrally with the gate interconnect 21 , the gate finger part 21 A becomes a metal interconnect having the Al film as the main conductor layer. By providing the gate finger part 21 A as described, the gate finger part 21 A has lower resistivity than the polysilicon film pattern 11 , and is extended over the polysilicon film pattern 11 , rather than extending the polysilicon film pattern 11 under the gate interconnect 21 . As a result, the gate resistance Rg can be reduced as compared with extending the polysilicon film pattern 11 under the gate interconnect 21 . In FIG. 19 , a section taken along line B-B corresponds to a sectional view shown in FIG. 9 .
- a structure ( FIG. 20 ) of a silicide layer (silicon compound film) 10 B, such as a tungsten silicide layer, deposited on top of a polysilicon layer 10 A, or a structure ( FIG. 21 ) of a tungsten nitride layer (metal film) 10 C, and a tungsten layer (metal film) 10 D, sequentially deposited on top of the polysilicon layer 10 A, may be adopted.
- resistivity of the gate electrodes 10 can be reduced as compared with an embodiment wherein the gate electrodes 10 are formed of the polysilicon layer only, and thereby the gate resistance can be further reduced.
- the gate electrodes 10 and the polysilicon film pattern 11 may be formed in the same manufacturing step, the silicide layer 10 B, or a stacked film of the tungsten nitride layer 10 C and the tungsten layer 10 D, may be formed over the polysilicon film pattern 11 .
- the localized formation of the p-type semiconductor region 14 may be implemented in the p ⁇ type semiconductor region 13 , as discussed hereinthroughout. Because the heat treatment time for the formation of the p-type semiconductor region 14 may be short in duration, a formation position of the p-type semiconductor region 14 , and a peak impurity concentration, may be decided by implantation energies for B ions as dopant ions. Accordingly, concentration distribution must be closely monitored, due to channeling of the B ions. Since the B ions are small in atomic radius, there is a particular concern in this regard with respect to the B ions.
- an off-angle substrate may be used as the substrate 1 .
- the off-angle substrate is described hereinafter with reference to FIGS. 22 and 23 .
- FIG. 23 is a sectional view taken on line C-C in FIG. 22 .
- the first wafer W 1 ( 100 ) face is the top surface (element forming surface), and the normal to the top surface is designated as n 1 .
- a straight line tiled by an angle (a first angle) ⁇ from the normal n 1 in a direction toward an orientation OF is designated as n 2 .
- the second wafer having the top surface, the normal to which is the straight line n 2 is the off-angle substrate.
- the angle ⁇ may be set to about 4°, by way of example.
- FIG. 24 is a schematic representation showing the relationship between depth from the surface of the substrate (the wafer W 1 ), and impurity concentration distribution, when B ions as a dopant are implanted into the first wafer W 1 from a direction perpendicular to the top surface.
- FIG. 24 shows three different cases of B ion implantation energies, namely 60 keV, 200 keV, and 1000 keV.
- FIG. 25 is a schematic representation showing the relationship between depth from the surface of the substrate (the second wafer) and impurity concentration distribution when B ions as a dopant are implanted into the second wafer that is the off-angle substrate with the angle ⁇ set to 4° from a direction perpendicular to the top surface.
- FIG. 24 shows three different cases of B ion implantation energies, namely 60 keV, 200 keV, and 1000 keV.
- FIG. 25 is a schematic representation showing the relationship between depth from the surface of the substrate (the second wafer) and impurity
- FIGS. 24 and 25 show three different cases of B ion implantation energies, namely 60 keV, 200 keV, and 1000 keV.
- the impurity concentration distribution is steeper as compared to the B ions being implanted into the first wafer, and the greater the B ion implantation energies, the more pronounced is this tendency. That is, when the p-type semiconductor region 14 is formed by implanting the B ions into the substrate 1 from the direction perpendicular to the top surface, the spread of the B ions as implanted, due to channeling, may be prevented by use of the off-angle substrate as the substrate 1 . As a result, the localized formation of the p-type semiconductor region 14 inside the p ⁇ type semiconductor region 13 can be implemented.
- the gate interconnect 21 , and the source pad 22 for example, a polyimide resin film as a protective film may be applied over the substrate 1 , and portions of the polyimide resin film, on top of the gate interconnect 21 and the source pad 22 , may be removed by exposure and development, thereby forming openings.
- the substrate 1 may be turned upside down such that a protected face thereof is on the underside, and the back surface of the n + type single crystal silicon substrate 1 A is on the upper side.
- a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film, as electrically conductive films may be sequentially deposited over the back surface of the n + type single crystal silicon substrate 1 A by, for example, a sputtering process, thereby forming a stacked film.
- the stacked film may serve as an extraction electrode (drain electrodes) for the drain (the n + type single crystal silicon substrate 1 A and the n ⁇ type single crystal silicon layer 1 B).
- dicing may be applied to the substrate, along, for example, dividing regions, thereby dividing the substrate into individual chips. Thereafter, the individual chips may be placed on respective lead frames (mounting boards) having, for example, external pins, and may be encapsulated (mounted) with resin or the like.
- a p ⁇ type semiconductor region 13 may serve as a channel layer for respective power MISFETs, formed to completely cover the side face of a groove 7 , and the whole face or part of the bottom of the groove 7 may be in contact with a n ⁇ type single crystal silicon layer 1 B.
- the formation of the p ⁇ type semiconductor region 13 as described may be implemented by changing, for example, heat treatment temperature or heat treatment time at the time of forming the p ⁇ type semiconductor region 13 .
- a surface area of a thermal oxidation film 9 extending from the p ⁇ type semiconductor region 13 toward the n ⁇ type single crystal silicon layer 1 B, can be rendered smaller.
- the bottom of the groove 7 may be covered with the p ⁇ type semiconductor region 13 due to manufacturing variation occurring to a depth of the groove 7 .
- the n ⁇ type semiconductor region (a sixth semiconductor layer) 13 A having a conductivity type opposite to that for the p ⁇ type semiconductor region 13 , and having an impurity concentration at substantially the same level as that of the p ⁇ type semiconductor region 13 , but having a higher impurity concentration than the n ⁇ type single crystal silicon layer 1 B.
- the p ⁇ type semiconductor region 13 is covered the bottom of the groove 7 . Accordingly, even if manufacturing variation occurs to the depth of the groove 7 , the surface area of the thermal oxidation film 9 , extending from the p ⁇ type semiconductor region 13 toward the n ⁇ type single crystal silicon layer 1 B, can be maintained at a predetermined size.
- the n ⁇ type semiconductor region 13 A described can be formed by implanting n-type dopant ions (for example, As) from the bottom of the groove 7 , after the formation of the groove 7 but prior to the formation of the thermal oxidation film 9 , using the silicon oxide film 3 (refer to FIG. 3 ) as a mask. Further, since the dopant ions are implanted by use of the silicon oxide film 3 as the mask, the patterning of a photo resist film over a substrate 1 , such as for use as a mask when implanting the dopant ions, can be omitted. It therefore follows that the n ⁇ type semiconductor region 13 A can be formed simply by increasing by one the number of manufacturing steps, for implantation of the dopant ions.
- n-type dopant ions for example, As
- FIG. 28 shows the relationship between a drain voltage and an input capacitance in the power MISFET having the n ⁇ type semiconductor region 13 A as described with reference to FIG. 27 , and in the first case power MISFET.
- FIG. 29 shows the relationship between the drain voltage and a feedback capacitance in a power MISFET having the n ⁇ type semiconductor region 13 A as described with reference to FIG. 27 , and in the first case power MISFET. As shown in FIGS.
- both the input capacitance and the feedback capacitance can be reduced as compared with the first case power MISFET.
- a loss of the DC-DC converter can be considerably reduced. Accordingly, higher efficiency of a DC-DC converter system can be implemented.
- FIG. 30 shows calculation results of respective losses of the power MISFET according to an embodiment wherein the n ⁇ type semiconductor region 13 A is as described with reference to FIG. 27 , and wherein the power MISFET is the first case power MISFET, wherein the respective power MISFETS are used as the switching elements of the DC-DC converter (refer to FIG. 15 ).
- the conditions illustrated are that the input voltage Vin is at 12V, the output voltage Vout at 1.3V, the output current Iout at 2 A, and the circuit operation frequency at 1 MHz.
- the groove 7 is formed at a shallower depth as compared with the case of the first power MISFET studied by the inventors, so that the input capacitance of the power MISFET can be reduced.
- a drive loss of the DC-DC converter can be reduced as compared with the first case power MISFET, and such reduction in the drive loss may amount to about 20%.
- a groove 7 for forming a gate electrode 10 of the power MISFET may be formed in a V shape (in a shape tapering to the bottom of the groove 7 ).
- the formation of the groove 7 as described can be implemented by adopting wet etching with KOH (potassium hydroxide), or by adjusting a composition ratio of an etching gas used in dry etching when executing the etching of a substrate 1 for forming the groove 7 , for example.
- a surface area of a portion of the groove 7 (the thermal oxidation film 9 ), under an n + type semiconductor region 15 , and a surface area of a portion of the groove 7 (the thermal oxidation film 9 ) in contact with an n ⁇ type single crystal silicon layer 1 B, can be reduced.
- both an input capacitance and a feedback capacitance can be reduced.
- a loss of the DC-DC converter can be considerably reduced.
- n ⁇ type semiconductor region 13 A directly underneath the groove 7 there may be formed an n ⁇ type semiconductor region 13 A. Since the n ⁇ type semiconductor region 13 A is formed so as to cover the bottom of the groove 7 , it is possible to prevent the p ⁇ type semiconductor region 13 from covering the bottom of the groove 7 . Accordingly, a surface area of the thermal oxidation film 9 , extending from the p ⁇ type semiconductor region 13 toward the n ⁇ type single crystal silicon layer 1 B, can be maintained at a predetermined size.
- the semiconductor device according to the present invention can be used as a switching element of a DC-DC converter for use as a power source circuit of, for example, a computer.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p− type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p− type semiconductor region is formed under a n+ type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.
Description
- This application is a Continuation application of U.S. application Ser. No. 10/886,041 filed on Jul. 8, 2004. Priority is claimed based on U.S. application Ser. No. 10/886,041 filed on Jul. 8, 2004, which claims priority to Japanese Patent Application No. 2003-286142 filed on Aug. 4, 2003, all of which is incorporated by reference.
- The invention relates to a semiconductor device and for a method of manufacturing the same, and in particular, to a semiconductor device and method employing power MISFETs (Metal Insulator Semiconductor Field Effect Transistors).
- In the case of a trench (groove) gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in a structure incorporating, for example, a p-type epitaxial layer as an upper layer of an n+ type substrate, it is known to reduce the risk of punch-through breakdown of the trench gate by forming an n-type drain region extended between the n+ type substrate and the bottom of a trench, and by forming a junction of the n-type drain region and the p-type epitaxial layer extended between the n-type substrate and a partition wall of the trench. This is illustrated in, for example, Japanese Patent Laid-Open No. 2000-164869.
- It is also known to improve switching loss of the trench gate power MOSFET by providing an n− type epitaxial layer doped to have a first conductivity type, and a well layer doped to have a second conductivity type, over a semiconductor substrate heavily doped to have the first conductivity type, thereby providing a deep trench gate, isolated by an insulating layer, inside an upper side layer made up of the n− type epitaxial layer and the well layer, and thereby providing a drain region of high conductivity under the trench gate. It is further known to provide source regions heavily doped to have the first conductivity type, adjacent to the trench gate, and to provide a main body region doped more heavily than the well layer, in the upper part of the well layer, to thereby reduce ON-resistance of the drain region. This is illustrated, for example, in Japanese Patent Laid-Open No. 2000-299464.
- A power transistor, such as the power MOSFET, may be used for high power applications, such as wherein the power is not less than several watts. One such power transistor, a power MISFET, may be a vertical type and/or a lateral type MISFET, depending on the structure of the gate thereof. A MISFET may be further classified as a trench (groove) gate type, or a planar gate type.
- A power MISFET may be used as a switching element of a DC-DC converter, for example, such as for use as a power source circuit for a computer. Since there has recently been a trend of larger current requirements for a CPU (Central Processing Unit) of a computer, to which the DC-DC converter supplies power, a larger current is required of the DC-DC converter as well. Requiring larger currents may cause an increase in ON-loss for a power MISFET. Accordingly, lower ON-resistance also is requited of a power MISFET used in a DC-DC converter.
- In a trench gate type power MISFET, a deep groove is formed in a top, element-forming surface of a semiconductor substrate (hereinafter referred to as a substrate), and a gate is formed by embedding a conductor in the groove. Further, in a planar gate type power MISFET, a gate is formed over a top surface of a substrate through the intermediary of a gate insulator. Accordingly, in the trench gate type power MISFET, a current flow path in the substrate becomes shorter as compared with a planar gate type power MISFET, so that ON-resistance can be reduced. However, since a gate insulator is formed on the sidewalls and bottom surface of the groove, there may be an increase in capacitance due to the gate insulator acting as a capacitance insulator, and the gate part acting as a capacitance electrode, as the groove is rendered deeper. On the other hand, in a planar gate type power MISFET, capacitance from the gate insulator acting as the capacitance insulator and the gate acting as the capacitance electrode is reduced as compared with the trench gate type power MISFET, but the number of the gate parts that can be disposed per unit area is reduced if a sufficient gate length to prevent pinch off is present. Hence, if an area of a semiconductor chip, over which the planar gate type power MISFET is formed is constant, the number of the gate parts that can be disposed on the semiconductor chip is less than that in the case of a trench gate type power MISFET. As a result, in the case of the planar gate type power MISFET, ON-resistance of the semiconductor chip increases as compared with the trench gate type power MISFET. Hence, if the trend for the DC-DC converter to higher frequency and larger current continues, the known art cannot simultaneously meet lower ON-resistance and lower capacitance required of a power MISFET.
- Thus, the need exists for a semiconductor device and method that provides a power MISFET that simultaneously provides lower ON-resistance and lower capacitance.
- A power MISFET, may include a multitude, such as, for example, several tens of thousands, of finely patterned MISFETs may be connected in parallel. Such a power MISFET may be used as a switching element of a DC-DC converter, for example, such as for use as a power source circuit for a computer, such as a desktop type, note type, server, and the like. Minimization of capacitance for a choke coil, I/O, and so forth, as well as fast response to variation in load, is required of a DC-DC converter. Accordingly, there is a trend for a DC-DC converter towards higher frequency, and as the DC-DC converter operates higher in frequency, an increase in switching loss and drive loss may occur in a power MISFET. Since the switching loss is proportional to a feedback capacitance of a power MISFET, and the drive loss is proportional to an input capacitance, reduction in these capacitances is required for a power MISFET used in a DC-DC converter.
-
FIG. 33 is an equivalent circuit diagram of the feedback capacitance and input capacitance for a power MISFET. As shown, assuming that capacitance between a gate and a drain is Cgd, capacitance between the gate and a source is Cgs, and capacitance between the drain and the source is Cds, an input capacitance Cin can be expressed as Cin□Cgd+Cgs, and a feedback capacitance Cfb can be expressed as Cfb=Cgd. -
FIG. 34 illustrates the capacitance between the gate and the source, and the capacitance between the gate and the drain. As shown inFIG. 34 , respective voltages applied to a gate electrode GELE, an n+ type semiconductor region NSEM as the source, and an n− type single crystal layer NEPI as the drain, are denoted by VG, VS, and VD, respectively, and it is assumed that the voltage VS is at the same potential as that for the source. Assuming that the voltages VG, VS are 0V, respectively, and the voltage VD is a voltage varying from 0V to 10V at a frequency of 1 MHz under the conditions described, the capacitance between the gate and the source can be expressed as capacitance C1 between the gate electrode GELE and the p− type semiconductor region PBOD, acting as capacitance electrodes, wherein a gate insulator GINS acts as a capacitance insulator. This capacitance C1 may be coupled in series with capacitance C2 between the gate electrode GELE and the p− type semiconductor region PBOD acting as capacitance electrodes, wherein a depletion layer DEP (seeFIG. 34 , in gray scale) acts as a capacitance insulator. The capacitance between the gate and the drain can be expressed as capacitance C3, with the gate electrode GELE and the n− type single crystal layer NEPI acting as capacitance electrodes, and the gate insulator GINS acting as a capacitance insulator. Capacitance C3 may be coupled in series with capacitance C4, with the gate electrode GELE and the n− type single crystal layer NEPI acting as capacitance electrodes, and the depletion layer DEP acting as a capacitance insulator. - The trench gate type power MISFET shown in
FIG. 35 has a trench gate structure whereingrooves 103 are formed in a top surface of an n+ type singlecrystal silicon substrate 101, and in an n− type singlecrystal silicon layer 102 formed in the upper part thereof. A conductor is embedded in each of thegrooves 103 throughgate insulator 104, thereby forming agate 105. In the case of the trench gate structure described, a current flow path in the n− type singlecrystal silicon layer 102 which is relatively low in impurity concentration can be rendered shorter than that in a planar gate structure, thereby reducing JFET (Junction FET) resistance acting as ON-resistance. Further, asource electrode 106 may be formed to fill each ofgrooves 108 in the top surface of the substrate andinsulating film 107, which source electrode may be electrically connected to a p+type semiconductor region 110 formed in a p−type semiconductor region 109 serving as a channel layer, wherein an n+type semiconductor region 111 serves as a source region. The p+type semiconductor region 110 can be formed by self-aligned implantation of dopant ions from thegroove 108 into the substrate, so that mask alignment allowance for implantation of the dopant ions need not be taken into account. Accordingly, because MISFET cell pitches can be scaled down, higher integration of the power MISFETs can be attained, and ON-resistance can be reduced. Furthermore, with the adoption of the trench gate structure, a channel length runs along a depth of the substrate, so as to allow for scale-down of the power MISFET cell pitches as compared with the planar gate type power MISFET (in which a channel length runs along the top surface of the substrate). - However, because the
groove 103 having thegate 105 formed therein is at a depth as deep as, for example, about 1 μm, the gate insulator may act as a capacitance insulator and the gate may act as a capacitance electrode. Input capacitance among the capacitance components is proportional to a length of the periphery of the groove 103 (a surface area of thegroove 103 under the n+ type semiconductor region 111), and feedback capacitance is proportional to a distance D12 of a portion of thegroove 103 extending from the p−type semiconductor region 109 toward the n− type single crystal silicon layer 102 (a surface area of the potion of thegroove 103, in contact with the n− type single crystal silicon layer 102). Accordingly, narrowing a width of thegroove 103 reduces the input capacitance, and reducing the distance D12 of the portion of thegroove 103 extending from the p−type semiconductor region 109 toward the n− type single crystal silicon layer 102 (thus rendering the groove shallower) reduces feedback capacitance. - Nonetheless, there are limits to process dimensions for narrowing the width of the
groove 103, and if thegroove 103 is rendered too narrow, an increase in resistance of thegate 105 results. Furthermore, to render thegroove 13 shallower, a junction is needed between the p−type semiconductor region 109 and the n− type singlecrystal silicon layer 102 at a position correspondingly shallower (shallower junctioning). In the case of such shallower junctioning, when a voltage is applied between the drain and the source, depletion may occurs to the channel layer (the p− type semiconductor region 109), thereby causing punch through. for the known art does not allow for the reduction of capacitance by rendering the groove shallower while preventing. - If the impurity concentration of the p−
type semiconductor region 109 is raised to prevent depletion from occurring to the channel layer, the threshold voltage of the MISFET may increase, resulting in an increase in ON-resistance. Further, if the p−type semiconductor region 109 has the same depth as that of thegroove 103 in order to reduce the distance of thegroove 103, the bottom of thegroove 103 may be covered by the p−type semiconductor region 109 due to manufacturing variation of thegroove 103, and the threshold voltage of the MISFET thus increases, thereby resulting in an increase in the ON-resistance. - The present invention achieves lower ON-resistance and lower capacitance for trench gate type power MISFETs. In accordance with an aspect of the invention, there is provided a semiconductor device having MISFETs, including: a first semiconductor layer having a first conductivity type, formed over the top surface of a semiconductor substrate; a second semiconductor layer having a second conductivity type opposite the first conductivity type, formed over the first semiconductor layer; a plurality of first groove parts of not more than 1 μm in depth, formed in the top surface of the semiconductor substrate, wherein at least a portion of respective bottoms of ones of the first groove parts are in contact with the first semiconductor layer; a first insulating film formed on the sidewall and bottom of each of the first groove parts; a first conductor formed over the first insulating film, wherein the first conductor fills up the respective first groove parts; a third semiconductor layer having the first conductivity type, formed in the second semiconductor layer adjacent to respective ones of the first groove parts; a fourth semiconductor layer having the second conductivity type, formed in the second semiconductor layer between adjacent ones of the first groove parts; and a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer, wherein the first semiconductor layer and the third semiconductor layer form a source or a drain of each of the MISFETs, the second semiconductor layer forms a channel forming region of each of the MISFETs, and a fifth semiconductor layer having the second conductivity type and higher in impurity concentration than the second semiconductor layer is formed under the third semiconductor layer, in the second semiconductor layer.
- The invention provides in an aspect a method of manufacturing a semiconductor device having MISFETs, including the steps of:
- (a) forming a first semiconductor layer, having a first conductivity type, over the top surface of a semiconductor substrate;
- (b) introducing a dopant having a second conductivity type opposite the first conductivity type into the semiconductor substrate, and forming a second semiconductor layer having the second conductivity type over the first semiconductor layer;
- (c) forming a plurality of first groove parts in the top surface of the semiconductor substrate;
- (d) forming a first insulating film inside the respective first groove parts;
- (e) embedding a first conductor in the respective first groove parts to thereby form a gate electrode;
- (f) introducing a dopant having the first conductivity type into the semiconductor substrate to thereby form a third semiconductor layer having the first conductivity type adjacent to the respective first groove parts;
- (g) introducing a dopant having the second conductivity type into the semiconductor substrate to thereby form a fifth semiconductor layer having the second conductivity type under the third semiconductor layer and within the second semiconductor layer;
- (h) forming a plurality of second groove parts each penetrating through the third semiconductor layer to be disposed between adjacent ones of the gate electrodes;
- (i) introducing a dopant having the second conductivity type into the semiconductor substrate from the respective bottoms of the second groove parts to thereby form a fourth semiconductor layer having the second conductivity type in the second semiconductor layer to cover the respective bottoms of the second groove parts; and
- (j) filling the second groove parts to thereby form a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer,
- wherein the first groove parts are formed to have a depth not more than 1 μm, and wherein at least part of the respective bottoms of the first groove parts are in contact with the first semiconductor layer, and wherein the fifth semiconductor layer is formed to be higher in impurity concentration than the second semiconductor layer, thereby forming MISFETs that each have the first semiconductor layer and the third semiconductor layer as a source or a drain thereof, and the second semiconductor layer as a channel forming region thereof.
- Thus, the present invention provides a semiconductor device and method that provides a power MISFET that simultaneously provides lower ON-resistance and lower capacitance.
- The various features of the present invention will now be described in greater detail with reference to the drawings of aspects of the present invention, and various related elements thereof, wherein like reference numerals designate like elements, and wherein:
-
FIG. 1 is a sectional view of a semiconductor device according to the invention; -
FIG. 2 is a sectional view of a step of manufacturing the semiconductor device, subsequent to a step shown inFIG. 1 ; -
FIG. 3 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown inFIG. 2 ; -
FIG. 4 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown inFIG. 3 ; -
FIG. 5 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown inFIG. 4 ; -
FIG. 6 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown inFIG. 5 ; -
FIG. 7 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown inFIG. 6 ; -
FIG. 8 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown inFIG. 7 ; -
FIG. 9 is a sectional view of a step of manufacturing the semiconductor device, subsequent to the step shown inFIG. 8 ; -
FIG. 10 is a plan view of a step of manufacturing the semiconductor device; -
FIG. 11 is a plan view of a step of manufacturing the semiconductor device; -
FIG. 12 is an expanded sectional view of a step of manufacturing the semiconductor device; -
FIG. 13 is a schematic representation showing a depth from the surface of a substrate and impurity concentration, at a position along a line A-A inFIG. 12 ; -
FIG. 14 is a schematic representation showing a source-drain voltage and a drain current for each of power MISFETs in the semiconductor device provided with a punch-through stopper layer, and without the punch-through stopper layer; -
FIG. 15 is a circuit diagram of a DC-DC converter including the semiconductor device; -
FIG. 16 is a schematic illustration showing breakdown of components in the DC-DC converter shown inFIG. 15 ; -
FIG. 17 is a schematic illustration showing breakdown of components in the DC-DC converter shown inFIG. 15 ; -
FIG. 18 is a schematic representation showing a gate resistance Rg of each of the power MISFETs in the DC-DC converter shown inFIG. 15 and efficiency η of a DC-DC converter system; -
FIG. 19 is a plan view of the semiconductor device; -
FIG. 20 is a sectional view of the semiconductor device; -
FIG. 21 is a sectional view the semiconductor device -
FIG. 22 is a plan view of an off-angle substrate; -
FIG. 23 is a sectional view on line C-C inFIG. 22 ; -
FIG. 24 is a schematic representation showing a depth from the surface of a substrate and impurity concentration distribution when dopant ions are implanted into the substrate; -
FIG. 25 is a schematic representation showing a depth from the surface of a substrate and impurity concentration distribution when dopant ions are implanted into the off-angle substrate; -
FIG. 26 is a sectional view of a semiconductor device; -
FIG. 27 is a sectional view of the semiconductor device; -
FIG. 28 is a schematic representation showing a drain voltage and an input capacitance in the case of a power MISFET; -
FIG. 29 is a schematic representation showing the drain voltage and a feedback capacitance in the case of a power MISFET; -
FIG. 30 is a schematic representation showing calculation results on respective losses of a power MISFET, in the case of those being used as the switching element of the DC-DC converter; -
FIG. 31 is a sectional view of a semiconductor device; -
FIG. 32 is a sectional view of the semiconductor device; -
FIG. 33 is an equivalent circuit diagram for describing feedback capacitance and input capacitance of a power MISFET; -
FIG. 34 is a sectional view of the power MISFET inFIG. 33 , and describes capacitance between a gate and a source, and capacitance between the gate and a drain; and -
FIG. 35 is a sectional view of a trench gate type power MISFET. - It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, many other elements found in a typical semiconductor device and method. Those of ordinary skill in the art will recognize that other elements are desirable and/or required in order to implement the present invention. But because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. The disclosure herein is directed to all such variations and modifications to the applications, networks, systems and methods disclosed herein and as will be known, or apparent, to those skilled in the art.
- As shown in
FIG. 1 , a semiconductor substrate (hereinafter also referred to as a substrate) 1 is provided. An n− type single crystal silicon layer (a first semiconductor layer) 1B may doped with a dopant {for example p (phosphorus)} having an n-type conductivity to undergo epitaxial growth of an n+ type singlecrystal silicon substrate 1A having the n-type conductivity (a first conductivity type). An off-angle substrate formed by use of a semiconductor wafer (hereinafter referred to as a first wafer), the (100) face of which is the top surface (an element forming surface), may be used as the base substrate, and a second wafer, the top surface of which is a face, and the normal to which is a straight line tilted by a predetermined angle from the normal to the top surface of the first wafer in the direction of an orientation flat or a notch may be formed in the first wafer. The n+ type singlecrystal silicon substrate 1A and the n− type singlecrystal silicon layer 1B may serve as a drain region for the respective power MISFETs. - As shown in
FIG. 2 , asilicon oxide film 3 may be formed by applying, for example, thermal oxidation to a surface (the top surface) of the n− type singlecrystal silicon layer 1B. Subsequently, using a silicon nitride film (not shown) patterned on thesilicon oxide film 3 by photolithographic techniques, such as a mask, a dopant {for example B (boron)} having a p-type conductivity may be implanted into thesubstrate 1 and may undergo thermal diffusion, thereby forming a p-type well 5. Thereafter, the silicon nitride film may be removed. - Subsequently, as shown in
FIG. 3 ,grooves 7 may be formed by etching thesilicon oxide film 3 and thesubstrate 1, such as by use of a photo resist film patterned by the photolithographic techniques, such as a mask. Thegrooves 7 may be formed to have a depth of about 1 μm or less. Further, thegrooves 7 may be formed in a shape, such as a square, polygon, or hexagon, extending in a mesh-like pattern, or may be formed in a multitude of stripes extending in substantially the same direction. Subsequently, by applying heat treatment to thesubstrate 1, a thermal oxidation film (first insulating film) 9 is formed on the bottom and sidewall of each of thegrooves 7. Thethermal oxidation film 9 may serve as a gate insulator for the respective power MISFETs. - As shown in
FIG. 4 , a polysilicon film doped with, for example, P, is deposited on thesilicon oxide film 3, including on the inside of each of thegrooves 7, to thereby fill therespective grooves 7 with the polysilicon film. At this point in time, the polysilicon film layer is formed on a portion of thesilicon oxide film 3, over the p-type well 5. Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, the polysilicon film is etched so as to leave portions thereof in thegrooves 7, thereby forming a gate electrode (first conductor) 10 for the respective power MISFETs inside therespective grooves 7. Also, at this time, a portion of the polysilicon film is left on thesilicon oxide film 3, in a peripheral part of a chip region (not shown), thereby forming apolysilicon film pattern 11. Thegate electrodes 10 and thepolysilicon film pattern 11 are electrically connected to each other in at least one region (not shown inFIG. 4 ). - Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, the
silicon oxide film 3 is etched to thereby remove unnecessary portions thereof. By so doing, a region whereat thesilicon oxide film 3 is formed that is underneath thepolysilicon film pattern 11 becomes an isolation region, and regions defined by the isolation region become element forming regions (active regions). - As shown in
FIG. 5 , asilicon oxide film 12 is deposited over thesubstrate 1. Subsequently, as shown inFIG. 6 , by use of a photo resist film patterned by photolithographic techniques as a mask, dopant ions {for example B (boron)} having a p-type conductivity type, i.e. a second conductivity type different from the first conductivity type, are implanted into the n− type singlecrystal silicon layer 1B at a concentration on the order of 5×1012 ions/cm2. Subsequently, by applying heat treatment to thesubstrate 1, the dopant ions are caused to undergo diffusion, thereby forming a p− type semiconductor region (a second semiconductor layer) 13. At this point in time, the p−type semiconductor region 13 may be formed in such a way as not to cover the respective bottoms of thegrooves 7. The p−type semiconductor region 13 may serve as a channel layer for the respective power MISFETs. The p−type semiconductor region 13 may have a depth not less than about 10% shallower than the respective bottoms of thegrooves 7. That is, as described above, since thegrooves 7 are formed to have a depth of about 10 μm or less, the portion of each of thegrooves 7 extending off of the p−type semiconductor region 13 may be kept to a depth of not more than about 0.1 μm. - Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, dopant ions (for example B) having the p-type conductivity may be implanted into the n− type single
crystal silicon layer 1B at a concentration in the order of 3×1012 ions/cm2, thereby forming a p-type semiconductor region (fifth semiconductor layer) 14 higher in impurity concentration than the p−type semiconductor region 13. The photo mask uses in patterning the photo resist film at this stage may be reused from the a photo mask used in patterning the photo resist film at the time of forming the p−type semiconductor region 13, for example. By so doing, it becomes unnecessary to prepare a new photo mask for use in the formation of the p-type semiconductor region 14, thus enabling a reduction in manufacturing cost of the semiconductor device. Thereafter, by use of a photo resist film patterned by photolithographic techniques as a mask, dopant ions {for example, As (arsenic)} having the n-type conductivity are implanted into the n− type singlecrystal silicon layer 1B. Subsequently, by applying heat treatment to thesubstrate 1, the dopant ions are caused to undergo diffusion, thereby forming an n+ type semiconductor region (a third semiconductor layer) 15 over the p-type semiconductor region 14 inside the p−type semiconductor region 13. Thus are formed respective power MISFETs having the drain region in the n+ type singlecrystal silicon substrate 1A and the n− type singlecrystal silicon layer 1B, and the source region in the n+type semiconductor region 15. Further, the p-type semiconductor region 14 may serve as a punch-through stopper layer for the respective power MISFETs. - As shown in
FIG. 7 , for example, a PSG (Phospho-Silicate Glass) film is deposited over thesubstrate 1, and subsequently an SOG (Spin On Glass) film is applied to the top of the PSG film, thereby forming an insulatingfilm 16 of the PSG film and the SOG film. Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, the insulatingfilm 16, thesilicon oxide film 12, and thesubstrate 1 are etched, thereby forming contact grooves (a second groove part) 17. Thecontact groove 17 is formed between thegate electrodes 10 adjacent to each other so as to penetrate through the n+type semiconductor region 15 serving as the source region. Further, the insulatingfilm 16 and thesilicon oxide film 12 over thepolysilicon film pattern 11 are also patterned, thereby formingcontact grooves 18 reaching thepolysilicon film pattern 11. - As shown in
FIG. 8 , BF2 (boron difluoride) ions as dopant ions having the p-type conductivity may be introduced from the bottom of each of thecontact grooves 17, thereby forming a p+ type semiconductor region (a fourth semiconductor layer) 20 in such a way as to cover the respective bottoms of thecontact grooves 17. Impurity concentration in the p+type semiconductor region 20 may be rendered higher than that in the p-type semiconductor region 14. Thus, by forming thecontact grooves 17 as above, and introducing the dopant ions from thecontact grooves 17 using the insulatingfilm 16 as a mask, the p+type semiconductor region 20 is formed in a self-aligned fashion on the respective bottoms of thecontact grooves 17, so that, for example, allowance for mask alignment can be reduced, thereby enabling spacing between thegate electrodes 10 adjacent to each other to be minimized. The p+type semiconductor region 20 may cause interconnects formed in later steps of this exemplary process to come in ohmic contact with the p−type semiconductor region 13 at the respective bottoms of thecontact grooves 17. - As shown in FIGS. 9 to 11, after thinly depositing a TiW (titanium-tungsten) film serving as a barrier conductor film in the upper part of the insulating
film 16, including the inside of each of thecontact grooves 17 as well as the inside of each of thecontact grooves 18, by, for example, sputtering, heat treatment is applied to thesubstrate 1. Subsequently, an Al (aluminum) film (a second conductor) lower in resistivity than the polysilicon film for forming thegate electrodes 10 may be deposited on top of the TiW film by, for example, sputtering. The barrier conductor film, in part, prevents an undesirable reactive layer from being formed due to Al contacting with the substrate (Si). As discussed hereinabove, “the Al film” includes Al as the main constituent, and may contain other metals as will be apparent to those skilled in the art. - Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, the TiW film and the Al film may be etched, thereby forming a gate interconnect (second electrode, a first part) 21 electrically connected to the
gate electrodes 10, a source pad (a first electrode) 22 electrically connected to the n+type semiconductor region 15 serving as the source region for the respective power MISFETs, a gate pad GP electrically connected to thegate interconnect 21, and interconnects L1, L2, and L3, electrically connected to thesource pad 22.FIGS. 10 and 11 show a chip region CHP corresponding to one chip obtained when thesubstrate 1 is divided into individual chips in a manufacturing step.FIG. 10 exhibits a case of therespective gate electrodes 10 being formed in the shape of a square and arranged in a mesh-like pattern, andFIG. 11 exhibits a case of therespective gate electrodes 10 being formed in a stripe-like pattern. -
FIG. 12 is an expanded sectional view showing the vicinity of thegate electrode 10.FIG. 13 is a schematic representation showing relationship between a depth from the surface of thesubstrate 1, and an impurity concentration at a position along a line A-A inFIG. 12 . - As discussed hereinabove, the
grooves 7 may be formed to have a depth D1 as shallow as about 1 μm or less. By rendering thegrooves 7 shallower, it is possible to reduce an input capacitance among capacitive components in a gate insulator (thermal oxidation film 9) that cause the gate insulator to act as a capacitance insulator and thegate electrodes 10 to act as capacitance electrodes. In the case of thegate electrodes 10 acting as capacitance electrodes and the gate insulator (thermal oxidation film 9) acting as the capacitance insulator, a gate capacitance can be rendered to be not more than about 1×10−3 per 1 μm in a direction in which the gate electrodes 10 (grooves 7) extend in a given plane, if a voltage of 0V is applied to thegate electrodes 10 and the source region (the n+ type semiconductor region 15), while a voltage varying from 0V to 10V at a frequency of 1 MHz is applied to the drain region (the n+ type singlecrystal silicon substrate 1A and the n− type singlecrystal silicon layer 1B). For example, if the gate electrodes 10 (grooves 7) are formed in the stripe-like pattern shown inFIG. 11 , and assuming that a direction from side to side on the plane of the figure is an x-direction, and a direction from the top to the bottom of the illustration is a y-direction, a direction (first direction) in which the gate electrodes 10 (grooves 7) are extended in a plane can be defined as the y-direction. - In conjunction with rendering the
grooves 7 shallower, the p−type semiconductor region 13 may be formed at a shallow depth and a junction of the p−type semiconductor region 13 and the n− type singlecrystal silicon layer 1B may be set at a shallow position (shallower junctioning). In the case of such shallower junctioning, however, when a voltage is applied between the drain and the source, depletion may occur to the channel layer (the p− type semiconductor region 13) for the respective power MISFETs, resulting in punch through. If the impurity concentration of the p−type semiconductor region 13 is raised in order to prevent the depletion from occurring to the channel layer, the threshold voltage of the power MISFET may become higher, resulting in an increase in the ON-resistance. Accordingly, the p-type semiconductor region 14 may be locally higher in impurity concentration than the p−type semiconductor region 13, and is formed inside the p−type semiconductor region 13 without raising the impurity concentration of the p−type semiconductor region 13, thereby causing the p-type semiconductor region 14 to function as a punch-through stopper layer. By so doing, the occurrence of punch through can be prevented, as can be a rise in threshold voltage and an increase in the ON-resistance. In other words, reduction of the input capacitance can be implemented while preventing the occurrence of punch through. The threshold voltage can be held to not higher than about 2V. - The sum of a dopant dose for the formation of the p−
type semiconductor region 13, and a dopant dose for the formation of the p-type semiconductor region 14, may be rendered similar in magnitude as compared to a dopant dose for the formation of the p−type semiconductor region 13 in the first case of a power MISFET withgrooves 7 having a depth of about 1 μm or more, and without a punch-through stopper layer (the p-type semiconductor region 14). As a result, the dopant dose for the formation of the p−type semiconductor region 13 may be reduced as compared with that in the first case power MISFET. Furthermore, as compared with the first case power MISFET, thegroove 7 may become shallower in depth, so that in heat treatment after dopant implantation for the formation of the p−type semiconductor region 13, applied in order to form the p−type semiconductor region 13 in such a way as not to cover the bottom of thegroove 7, and to implement the shallower junctioning of the p−type semiconductor region 13 and the n− type singlecrystal silicon layer 1B, a treatment temperature may be lowered. The treatment time may be shortened as compared with that in the manufacturing process for the first case power MISFET. Further, the p-type semiconductor region 14 serving as the punch-through stopper layer is may be formed after the heat treatment for the formation of the p−type semiconductor region 13. By so doing, time for heat treatment applied to thesubstrate 1 after dopant implantation for the formation of the p-type semiconductor region 14 can be shortened, so that localized formation of the p-type semiconductor region 14 inside the p−type semiconductor region 13 becomes possible. Still further, as for the n+type semiconductor region 15 serving as the source region of the power MISFET, during heat treatment applied after dopant implantation for the formation of the n+type semiconductor region 15, treatment time is may be shortened as much as possible in order to form the same at a shallow depth, and adoption of a short heat treatment time, such as, for example, by a lamp anneal treatment, may occur. - Further, by forming the
groove 7 at a shallower depth, manufacturing variation in depth can be reduced, so that a distance D2 of a portion of thegroove 7, extending from the p−type semiconductor region 13 toward with the n− type singlecrystal silicon layer 1B, can be reduced. That is, among the capacitance components in the gate insulator (the thermal oxidation film 9) acting as a capacitance insulator, and thegate electrodes 10 acting as the capacitance electrodes, a feedback capacitance is proportional to the distance of the portion of thegroove 7 extending from the p−type semiconductor region 13 toward with the n− type singlecrystal silicon layer 1B. Accordingly, as a result of reduction in the distance of the portion of thegroove 7 extending from the lower edge of the p− type semiconductor region toward with the n− type singlecrystal silicon layer 1B, the feedback capacitance can be reduced. - With regard to the p−
type semiconductor region 13, theregion 13 is designed so as to have a depth shallower by, for example, not less than about 10% of the respective depths of thegrooves 7, in order to prevent the p−type semiconductor region 13 from covering the bottoms of thegrooves 7. However, since thegrooves 7 are to have a depth about 1 μm or less, the distance D2 of the portion of thegroove 7, extending from the p−type semiconductor region 13 toward the n− type singlecrystal silicon layer 1B, can be rendered not more than about 0.1 μm. - In addition, as a result of the formation of the p-
type semiconductor region 14, it becomes possible to reduce base resistance of a parasitic npn bipolar transistor developed by the n− type singlecrystal silicon layer 1B acting as a collector, the p−type semiconductor region 13 acting as a base, and the n+type semiconductor region 15 acting as an emitter. Accordingly, avalanche yield strength of the power MISFET can be enhanced. - Experimentation has been performed to examine occurrence of punch through in the p−
type semiconductor region 13 serving as the channel layer in the case wherein the p-type semiconductor region 14 serves as the punch-through stopper layer.FIG. 14 shows a source-drain voltage Vds, and a drain current Id, of the power MISFETs in the case wherein the p-type semiconductor region 14 is provided, and in the case wherein the p-type semiconductor region 14 is not provided. As shown inFIG. 14 , it is evident that, in the case wherein the p-type semiconductor region 14 is not provided, punch through occurs to the p−type semiconductor region 13 and leak current increases as compared with the case wherein the p-type semiconductor region 14 is provided. More specifically, even in the case of setting the junction of the p−type semiconductor region 13 and the n− type singlecrystal silicon layer 1B at a shallow position (shallower junctioning), by providing the power MISFET with the p-type semiconductor region 14 it is possible to prevent the occurrence of punch through due to depletion occurring to the channel layer (the p− type semiconductor region 13) when a voltage is applied between the drain and the source. - The power MISFETs may be used as switching elements (High-side MISFETQH and Low-side MISFETQL) in, for example, a DC-DC converter circuit, as shown in
FIG. 15 . A component analyses on the total loss of the DC-DC converter has been performed by a simulation to examine the breakdown of components. In a simulation condition of an input voltage Vin at 12V, an output voltage Vout at 1.3V, and a circuit operation frequency at 1 MHz, output current Iout at 2A and 10 A, respectively, were analyzed.FIGS. 16 and 17 show breakdown of components and the total loss of the DC-DC converter at output current Iout at 2A and 10A, respectively. As show inFIGS. 16 and 17 , the sum of a switching loss and a drive loss occupies about 56% of the total loss of the DC-DC converter at output current lout at 2A, and about 41% of the same at output current Iout at 10A. Herein, the switching loss refers to a loss occurring when the power MISFET is turned ON or OFF, and the drive loss refers to power required for driving the power MISFET. Assuming that a drain-source voltage of the power MISFET is Vds, a drain current is Id, ON-time is tr, OFF-time is tf, an input gate capacitance is Qg, a gate-source voltage is Vgs, and a circuit operation frequency is f, a switching loss can be expressed as:
½×(tr+tf)×Id×Vds×f,
and a drive loss can be expressed as:
Qg×Vgs×f. - Based on these formulae, the switching loss and the drive loss are proportional to a frequency, such that the switching loss and the drive loss increase as the circuit operation frequency becomes higher. Further, the switching loss is proportional to the feedback capacitance of the power MISFET, and the drive loss is proportional to the input capacitance of the power MISFET. As previously described, since the feedback capacitance as well as the input capacitance of the power MISFET can be reduced, the loss of the DC-DC converter can be significantly reduced. Thus, it is possible to implement a higher efficiency DC-DC converter system through the use of the present invention.
- However, if the grooves 7 (refer to
FIG. 9 ) are rendered shallower, a cross sectional area of each of thegate electrodes 10 becomes smaller, so that there arises an increase in gate resistance.FIG. 18 is a schematic representation showing the relationship between a gate resistance Rg of each of the power MISFETs in the DC-DC converter shown inFIG. 15 , and efficiency η of the DC-DC converter system. Results shown inFIG. 18 were obtained for circuit operation frequencies of 300 kHz and 1 MHz, respectively, when the input voltage Vin was at 12V, the output voltage Vout at 1.3V, and the output current at 10A. As shown inFIG. 18 , with the DC-DC converter shown inFIG. 15 , as the gate resistance Rg increases, the efficiency η of the DC-DC converter system deteriorates, and in particular, the higher the circuit operation frequency becomes, the greater the efficiency η of the DC-DC converter system deteriorates. - For this reason, a “gate finger” structure, as shown in
FIG. 19 , may be adopted. More specifically, a gate finger part (the second electrode, a second part) 21A, formed integrally with thegate interconnect 21 formed along the periphery of the chip region CHP, may be provided. Further, agate interconnect 21B may be formed integrally with both thegate interconnect 21 and thegate finger part 21A. Thegate finger part 21A may be extended from thegate interconnect 21 toward the inner side of the chip region CHP, in a plane, and under thegate finger part 21A, the polysilicon film pattern 11 (refer toFIG. 9 ), which is electrically connected to thegate electrodes 10, is disposed. Further, as with thegate interconnect 21, thegate finger part 21A is formed so as to fill up the contact grooves 18 (refer toFIG. 9 ). Since thegate finger part 21A is formed integrally with thegate interconnect 21, thegate finger part 21A becomes a metal interconnect having the Al film as the main conductor layer. By providing thegate finger part 21A as described, thegate finger part 21A has lower resistivity than thepolysilicon film pattern 11, and is extended over thepolysilicon film pattern 11, rather than extending thepolysilicon film pattern 11 under thegate interconnect 21. As a result, the gate resistance Rg can be reduced as compared with extending thepolysilicon film pattern 11 under thegate interconnect 21. InFIG. 19 , a section taken along line B-B corresponds to a sectional view shown inFIG. 9 . - As shown in
FIGS. 20 and 21 , for thegate electrodes 10, a structure (FIG. 20 ) of a silicide layer (silicon compound film) 10B, such as a tungsten silicide layer, deposited on top of apolysilicon layer 10A, or a structure (FIG. 21 ) of a tungsten nitride layer (metal film) 10C, and a tungsten layer (metal film) 10D, sequentially deposited on top of thepolysilicon layer 10A, may be adopted. By adopting such structures for thegate electrodes 10, resistivity of thegate electrodes 10 can be reduced as compared with an embodiment wherein thegate electrodes 10 are formed of the polysilicon layer only, and thereby the gate resistance can be further reduced. Further, since thegate electrodes 10 and thepolysilicon film pattern 11 may be formed in the same manufacturing step, thesilicide layer 10B, or a stacked film of thetungsten nitride layer 10C and thetungsten layer 10D, may be formed over thepolysilicon film pattern 11. - The localized formation of the p-
type semiconductor region 14 may be implemented in the p−type semiconductor region 13, as discussed hereinthroughout. Because the heat treatment time for the formation of the p-type semiconductor region 14 may be short in duration, a formation position of the p-type semiconductor region 14, and a peak impurity concentration, may be decided by implantation energies for B ions as dopant ions. Accordingly, concentration distribution must be closely monitored, due to channeling of the B ions. Since the B ions are small in atomic radius, there is a particular concern in this regard with respect to the B ions. - Hence, as described with reference to
FIG. 1 , an off-angle substrate may be used as thesubstrate 1. The off-angle substrate is described hereinafter with reference toFIGS. 22 and 23 .FIG. 23 is a sectional view taken on line C-C inFIG. 22 . - As shown in
FIGS. 22 and 23 , the first wafer W1 (100) face is the top surface (element forming surface), and the normal to the top surface is designated as n1. - A straight line tiled by an angle (a first angle) θ from the normal n1 in a direction toward an orientation OF is designated as n2. The second wafer having the top surface, the normal to which is the straight line n2, is the off-angle substrate. The angle θ may be set to about 4°, by way of example.
-
FIG. 24 is a schematic representation showing the relationship between depth from the surface of the substrate (the wafer W1), and impurity concentration distribution, when B ions as a dopant are implanted into the first wafer W1 from a direction perpendicular to the top surface.FIG. 24 shows three different cases of B ion implantation energies, namely 60 keV, 200 keV, and 1000 keV.FIG. 25 is a schematic representation showing the relationship between depth from the surface of the substrate (the second wafer) and impurity concentration distribution when B ions as a dopant are implanted into the second wafer that is the off-angle substrate with the angle θ set to 4° from a direction perpendicular to the top surface.FIG. 25 shows three different cases of B ion implantation energies, namely 60 keV, 200 keV, and 1000 keV. As shown inFIGS. 24 and 25 , in the case of the B ions being implanted into the second wafer, the impurity concentration distribution is steeper as compared to the B ions being implanted into the first wafer, and the greater the B ion implantation energies, the more pronounced is this tendency. That is, when the p-type semiconductor region 14 is formed by implanting the B ions into thesubstrate 1 from the direction perpendicular to the top surface, the spread of the B ions as implanted, due to channeling, may be prevented by use of the off-angle substrate as thesubstrate 1. As a result, the localized formation of the p-type semiconductor region 14 inside the p−type semiconductor region 13 can be implemented. - After the formation of the gate pad GP, the
gate interconnect 21, and thesource pad 22, for example, a polyimide resin film as a protective film may be applied over thesubstrate 1, and portions of the polyimide resin film, on top of thegate interconnect 21 and thesource pad 22, may be removed by exposure and development, thereby forming openings. - Subsequently, after protecting the surface of the
substrate 1 with, for example, a tape, thesubstrate 1 may be turned upside down such that a protected face thereof is on the underside, and the back surface of the n+ type singlecrystal silicon substrate 1A is on the upper side. Subsequently, for example, a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film, as electrically conductive films, may be sequentially deposited over the back surface of the n+ type singlecrystal silicon substrate 1A by, for example, a sputtering process, thereby forming a stacked film. The stacked film may serve as an extraction electrode (drain electrodes) for the drain (the n+ type singlecrystal silicon substrate 1A and the n− type singlecrystal silicon layer 1B). - When the protection, such as the tape, is removed, and after forming bump electrodes made of, for example, Au, over the openings formed in the polyimide resin film, dicing may be applied to the substrate, along, for example, dividing regions, thereby dividing the substrate into individual chips. Thereafter, the individual chips may be placed on respective lead frames (mounting boards) having, for example, external pins, and may be encapsulated (mounted) with resin or the like.
- As shown in
FIG. 26 , a p−type semiconductor region 13 may serve as a channel layer for respective power MISFETs, formed to completely cover the side face of agroove 7, and the whole face or part of the bottom of thegroove 7 may be in contact with a n− type singlecrystal silicon layer 1B. The formation of the p−type semiconductor region 13 as described may be implemented by changing, for example, heat treatment temperature or heat treatment time at the time of forming the p−type semiconductor region 13. By forming the p−type semiconductor region 13 as described, a surface area of athermal oxidation film 9, extending from the p−type semiconductor region 13 toward the n− type singlecrystal silicon layer 1B, can be rendered smaller. Accordingly, feedback capacitance among capacitance components in a gate insulator (the thermal oxidation film 9) acting as a capacitance insulator and agate electrode 10 acting as a capacitance electrode may be reduced. By use of such power MISFETs as switching elements of the DC-DC converter (refer toFIG. 15 ), a switching loss may be further reduced. - As described with reference to
FIG. 26 , since the p−type semiconductor region 13 is formed so as to completely cover the side face of thegroove 7 by implantation B ions, the bottom of thegroove 7 may be covered with the p−type semiconductor region 13 due to manufacturing variation occurring to a depth of thegroove 7. For this reason, as shown inFIG. 27 , directly underneath thegroove 7, there may be formed an n− type semiconductor region (a sixth semiconductor layer) 13A having a conductivity type opposite to that for the p−type semiconductor region 13, and having an impurity concentration at substantially the same level as that of the p−type semiconductor region 13, but having a higher impurity concentration than the n− type singlecrystal silicon layer 1B. Thereby, it is possible to prevent the p−type semiconductor region 13 from covering the bottom of thegroove 7. Accordingly, even if manufacturing variation occurs to the depth of thegroove 7, the surface area of thethermal oxidation film 9, extending from the p−type semiconductor region 13 toward the n− type singlecrystal silicon layer 1B, can be maintained at a predetermined size. - The n−
type semiconductor region 13A described can be formed by implanting n-type dopant ions (for example, As) from the bottom of thegroove 7, after the formation of thegroove 7 but prior to the formation of thethermal oxidation film 9, using the silicon oxide film 3 (refer toFIG. 3 ) as a mask. Further, since the dopant ions are implanted by use of thesilicon oxide film 3 as the mask, the patterning of a photo resist film over asubstrate 1, such as for use as a mask when implanting the dopant ions, can be omitted. It therefore follows that the n−type semiconductor region 13A can be formed simply by increasing by one the number of manufacturing steps, for implantation of the dopant ions. -
FIG. 28 shows the relationship between a drain voltage and an input capacitance in the power MISFET having the n−type semiconductor region 13A as described with reference toFIG. 27 , and in the first case power MISFET. Further,FIG. 29 shows the relationship between the drain voltage and a feedback capacitance in a power MISFET having the n−type semiconductor region 13A as described with reference toFIG. 27 , and in the first case power MISFET. As shown inFIGS. 28 and 29 , wherein thegroove 7 is formed at a shallow depth, the p−type semiconductor region 13 completely covers the side face of thegroove 7, and the n−type semiconductor region 13A is formed directly underneath thegroove 7, both the input capacitance and the feedback capacitance can be reduced as compared with the first case power MISFET. In the case of using such a power MISFET as the switching element of the DC-DC converter (refer toFIG. 15 ), a loss of the DC-DC converter can be considerably reduced. Accordingly, higher efficiency of a DC-DC converter system can be implemented. -
FIG. 30 shows calculation results of respective losses of the power MISFET according to an embodiment wherein the n−type semiconductor region 13A is as described with reference toFIG. 27 , and wherein the power MISFET is the first case power MISFET, wherein the respective power MISFETS are used as the switching elements of the DC-DC converter (refer toFIG. 15 ). The conditions illustrated are that the input voltage Vin is at 12V, the output voltage Vout at 1.3V, the output current Iout at 2 A, and the circuit operation frequency at 1 MHz. With the power MISFET according to the second embodiment, thegroove 7 is formed at a shallower depth as compared with the case of the first power MISFET studied by the inventors, so that the input capacitance of the power MISFET can be reduced. As shown inFIG. 30 , in the case of using the power MISFET wherein thegroove 7 is formed at a shallower depth, a drive loss of the DC-DC converter can be reduced as compared with the first case power MISFET, and such reduction in the drive loss may amount to about 20%. - As shown in
FIG. 31 , agroove 7 for forming agate electrode 10 of the power MISFET may be formed in a V shape (in a shape tapering to the bottom of the groove 7). The formation of thegroove 7 as described can be implemented by adopting wet etching with KOH (potassium hydroxide), or by adjusting a composition ratio of an etching gas used in dry etching when executing the etching of asubstrate 1 for forming thegroove 7, for example. By forming thegroove 7 as described, a surface area of a portion of the groove 7 (the thermal oxidation film 9), under an n+type semiconductor region 15, and a surface area of a portion of the groove 7 (the thermal oxidation film 9) in contact with an n− type singlecrystal silicon layer 1B, can be reduced. As a result, both an input capacitance and a feedback capacitance can be reduced. Further, a loss of the DC-DC converter can be considerably reduced. - As shown in
FIG. 32 , directly underneath thegroove 7 there may be formed an n−type semiconductor region 13A. Since the n−type semiconductor region 13A is formed so as to cover the bottom of thegroove 7, it is possible to prevent the p−type semiconductor region 13 from covering the bottom of thegroove 7. Accordingly, a surface area of thethermal oxidation film 9, extending from the p−type semiconductor region 13 toward the n− type singlecrystal silicon layer 1B, can be maintained at a predetermined size. - The semiconductor device according to the present invention can be used as a switching element of a DC-DC converter for use as a power source circuit of, for example, a computer.
- If not otherwise stated herein, it may be assumed that all components and/or processes described heretofore may, if appropriate, be considered to be interchangeable with similar components and/or processes disclosed elsewhere in the specification. It should be appreciated that the systems and methods of the present invention may be configured and conducted as appropriate for any context at hand. The embodiments described hereinabove are to be considered in all respects only as illustrative and not restrictive. As such, all modifications and variations of the present invention that come within the meaning, range, and equivalency of the claims hereinbelow are to be embraced within the scope thereof.
Claims (3)
1. A semiconductor device including a trench gate type MISFET, comprising:
a semiconductor substrate having a main surface and a bottom surface opposite to said main surface, said semiconductor substrate having a first conductivity type;
a first semiconductor layer formed on the main surface of the semiconductor substrate, said first semiconductor layer having a top surface apart from the semiconductor substrate, said first semiconductor layer having the first conductivity type, and said first semiconductor layer acting as a drain region of the MISFET;
a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 μm;
a gate insulating film of the MISFET formed on an inner surface of the trench;
a gate electrode of the MISFET formed on the gate insulating film in the trench;
a channel forming region of the MISFET formed in the first semiconductor layer, said channel forming region being in contact with the trench, said bottom of the trench being positioned below a bottom of the channel forming region, and said channel forming region having a second conductivity type opposite to the first conductivity type;
a source region of the MISFET formed over the channel forming region in the first semiconductor layer; said source region being in contact with the trench, and said source region having the first conductivity type; and
a punch through stopper region formed between the source region and channel forming region in the first semiconductor layer, said punch through stopper region having the second conductivity type, and said punch through stopper region having a higher impurity concentration than the channel forming region.
2. A semiconductor device according to claim 1 , further comprising:
a drain electrode formed on the bottom surface of the semiconductor substrate, said drain electrode being electrically connected with the semiconductor substrate and first semiconductor layer;
an interlayer insulating film formed over the gate electrode and source region;
a contact groove formed in the insulating film, a part of the source region being exposed from the contact groove; and
a source electrode formed in the contact groove, said source electrode being electrically connected with the source region.
3. A semiconductor device according to claim 1 , wherein the first semiconductor layer is formed by an epitaxial growth method.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/657,592 US20070120194A1 (en) | 2003-08-04 | 2007-01-25 | Semiconductor device and a method of manufacturing the same |
US12/385,979 US7981747B2 (en) | 2003-08-04 | 2009-04-27 | Semiconductor device and a method of manufacturing the same |
US13/067,566 US20110233664A1 (en) | 2003-08-04 | 2011-06-09 | Semiconductor device and a method of manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003286142A JP4945055B2 (en) | 2003-08-04 | 2003-08-04 | Semiconductor device and manufacturing method thereof |
JP2003-286142 | 2003-08-04 | ||
US10/886,041 US20050029584A1 (en) | 2003-08-04 | 2004-07-08 | Semiconductor device and a method of manufacturing the same |
US11/657,592 US20070120194A1 (en) | 2003-08-04 | 2007-01-25 | Semiconductor device and a method of manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/886,041 Continuation US20050029584A1 (en) | 2003-08-04 | 2004-07-08 | Semiconductor device and a method of manufacturing the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/385,979 Continuation US7981747B2 (en) | 2003-08-04 | 2009-04-27 | Semiconductor device and a method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070120194A1 true US20070120194A1 (en) | 2007-05-31 |
Family
ID=34113935
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/886,041 Abandoned US20050029584A1 (en) | 2003-08-04 | 2004-07-08 | Semiconductor device and a method of manufacturing the same |
US11/657,592 Abandoned US20070120194A1 (en) | 2003-08-04 | 2007-01-25 | Semiconductor device and a method of manufacturing the same |
US12/385,979 Active US7981747B2 (en) | 2003-08-04 | 2009-04-27 | Semiconductor device and a method of manufacturing the same |
US13/067,566 Abandoned US20110233664A1 (en) | 2003-08-04 | 2011-06-09 | Semiconductor device and a method of manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/886,041 Abandoned US20050029584A1 (en) | 2003-08-04 | 2004-07-08 | Semiconductor device and a method of manufacturing the same |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/385,979 Active US7981747B2 (en) | 2003-08-04 | 2009-04-27 | Semiconductor device and a method of manufacturing the same |
US13/067,566 Abandoned US20110233664A1 (en) | 2003-08-04 | 2011-06-09 | Semiconductor device and a method of manufacturing the same |
Country Status (2)
Country | Link |
---|---|
US (4) | US20050029584A1 (en) |
JP (1) | JP4945055B2 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080150017A1 (en) * | 2006-12-25 | 2008-06-26 | Sanyo Electric Co., Ltd. | Semiconductor device |
US20090321824A1 (en) * | 2008-06-25 | 2009-12-31 | Fujitsu Microelectronics Limited | Semiconductor device |
US20100176485A1 (en) * | 2009-01-09 | 2010-07-15 | Chiu-Chuan Chen | storage capacitor having an increased aperture ratio and method of manufacturing the same |
US20100176447A1 (en) * | 2007-05-30 | 2010-07-15 | Rohm Co., Ltd. | Semiconductor device |
US20100327348A1 (en) * | 2009-06-24 | 2010-12-30 | Renesas Electronics Corporation | Semiconductor device, method of manufacturing the same and power-supply device using the same |
US20110079824A1 (en) * | 2009-10-07 | 2011-04-07 | Derek Hullinger | Alternate 4-terminal jfet geometry to reduce gate to source capacitance |
CN102386233A (en) * | 2010-08-30 | 2012-03-21 | 精工电子有限公司 | Semiconductor device |
US20120112266A1 (en) * | 2010-11-10 | 2012-05-10 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing the same |
US20120132912A1 (en) * | 2010-11-25 | 2012-05-31 | Mitsubishi Electric Corporation | Semiconductor device |
KR101286220B1 (en) | 2011-07-25 | 2013-07-15 | 미쓰비시덴키 가부시키가이샤 | Silicon carbide semiconductor device |
US8643102B2 (en) | 2010-09-10 | 2014-02-04 | Renesas Electronics Corporation | Control device of semiconductor device |
US20150118810A1 (en) * | 2013-10-24 | 2015-04-30 | Madhur Bobde | Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path |
US9653597B2 (en) | 2010-05-20 | 2017-05-16 | Infineon Technologies Americas Corp. | Method for fabricating a shallow and narrow trench FET and related structures |
US20220169449A1 (en) * | 2020-11-27 | 2022-06-02 | Terry Michael Brown, SR. | Split drive sprocket assembly |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4860122B2 (en) * | 2004-06-25 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP2006049341A (en) | 2004-07-30 | 2006-02-16 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
US7453119B2 (en) * | 2005-02-11 | 2008-11-18 | Alphs & Omega Semiconductor, Ltd. | Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact |
US7285822B2 (en) * | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
US8093651B2 (en) * | 2005-02-11 | 2012-01-10 | Alpha & Omega Semiconductor Limited | MOS device with integrated schottky diode in active region contact trench |
US7948029B2 (en) | 2005-02-11 | 2011-05-24 | Alpha And Omega Semiconductor Incorporated | MOS device with varying trench depth |
US8362547B2 (en) * | 2005-02-11 | 2013-01-29 | Alpha & Omega Semiconductor Limited | MOS device with Schottky barrier controlling layer |
US8283723B2 (en) * | 2005-02-11 | 2012-10-09 | Alpha & Omega Semiconductor Limited | MOS device with low injection diode |
US7786531B2 (en) * | 2005-03-18 | 2010-08-31 | Alpha & Omega Semiconductor Ltd. | MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification |
JP4955222B2 (en) | 2005-05-20 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
KR100824205B1 (en) * | 2006-12-26 | 2008-04-21 | 매그나칩 반도체 유한회사 | Dmos transistor and manufacturing method thereof |
KR100777593B1 (en) * | 2006-12-27 | 2007-11-16 | 동부일렉트로닉스 주식회사 | Trench gate mosfet device and the fabricating method thereof |
JP5285874B2 (en) * | 2007-07-03 | 2013-09-11 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
KR100970282B1 (en) * | 2007-11-19 | 2010-07-15 | 매그나칩 반도체 유한회사 | Trench MOSFET and Manufacturing Method thereof |
CN101465376B (en) * | 2007-12-21 | 2012-07-04 | 万国半导体股份有限公司 | MOS device with low injection diode |
US7977737B2 (en) * | 2008-03-06 | 2011-07-12 | Infineon Technologies Austria Ag | Semiconductor device having additional capacitance to inherent gate-drain or inherent drain-source capacitance |
JP5819064B2 (en) * | 2008-05-20 | 2015-11-18 | ローム株式会社 | Semiconductor device |
JP5297104B2 (en) | 2008-07-01 | 2013-09-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US8193579B2 (en) * | 2008-07-29 | 2012-06-05 | Rohm Co., Ltd. | Trench type semiconductor device and fabrication method for the same |
US8362552B2 (en) * | 2008-12-23 | 2013-01-29 | Alpha And Omega Semiconductor Incorporated | MOSFET device with reduced breakdown voltage |
US8846473B2 (en) * | 2009-06-01 | 2014-09-30 | Sensor Electronic Technology, Inc. | Low-resistance electrode design |
US8168497B2 (en) * | 2009-06-01 | 2012-05-01 | Sensor Electronic Technology, Inc. | Low-resistance electrode design |
US9425305B2 (en) | 2009-10-20 | 2016-08-23 | Vishay-Siliconix | Structures of and methods of fabricating split gate MIS devices |
US9419129B2 (en) | 2009-10-21 | 2016-08-16 | Vishay-Siliconix | Split gate semiconductor device with curved gate oxide profile |
US9577089B2 (en) | 2010-03-02 | 2017-02-21 | Vishay-Siliconix | Structures and methods of fabricating dual gate devices |
JP5662865B2 (en) * | 2010-05-19 | 2015-02-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP5638340B2 (en) * | 2010-10-20 | 2014-12-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US20120175699A1 (en) * | 2011-01-06 | 2012-07-12 | Force Mos Technology Co., Ltd. | Trench mosfet with super pinch-off regions and self-aligned trenched contact |
CN102184945A (en) * | 2011-05-03 | 2011-09-14 | 成都芯源***有限公司 | Groove gate type MOSFET device |
WO2012158977A2 (en) | 2011-05-18 | 2012-11-22 | Vishay-Siliconix | Semiconductor device |
JP6290526B2 (en) * | 2011-08-24 | 2018-03-07 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
US8368192B1 (en) * | 2011-09-16 | 2013-02-05 | Powertech Technology, Inc. | Multi-chip memory package with a small substrate |
US8716787B2 (en) * | 2012-03-27 | 2014-05-06 | Super Group Semiconductor Co., Ltd. | Power semiconductor device and fabrication method thereof |
US9000497B2 (en) * | 2012-09-14 | 2015-04-07 | Renesas Electronics Corporation | Trench MOSFET having an independent coupled element in a trench |
US9105713B2 (en) * | 2012-11-09 | 2015-08-11 | Infineon Technologies Austria Ag | Semiconductor device with metal-filled groove in polysilicon gate electrode |
JP5876008B2 (en) * | 2013-06-03 | 2016-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
TWI487115B (en) * | 2013-06-07 | 2015-06-01 | Sinopower Semiconductor Inc | Trench power device and manufacturing method thereof |
JP6356803B2 (en) * | 2013-11-29 | 2018-07-11 | アーベーベー・テクノロジー・アーゲー | Insulated gate bipolar transistor |
US9773863B2 (en) * | 2014-05-14 | 2017-09-26 | Infineon Technologies Austria Ag | VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body |
US10468479B2 (en) | 2014-05-14 | 2019-11-05 | Infineon Technologies Austria Ag | VDMOS having a drift zone with a compensation structure |
EP3183753A4 (en) | 2014-08-19 | 2018-01-10 | Vishay-Siliconix | Electronic circuit |
TWI581425B (en) | 2015-11-24 | 2017-05-01 | Macroblock Inc | And a power semiconductor device having an edge terminal structure having a gradation concentration |
DE102016101801B4 (en) * | 2016-02-02 | 2021-01-14 | Infineon Technologies Ag | LOAD CONNECTION OF A POWER SEMICONDUCTOR ELEMENT, POWER SEMICONDUCTOR MODULE WITH IT AND MANUFACTURING PROCESS FOR IT |
DE102019101326A1 (en) * | 2018-01-19 | 2019-07-25 | Infineon Technologies Ag | Semiconductor device containing first and second contact layers, and manufacturing method |
JP6994991B2 (en) * | 2018-03-16 | 2022-02-04 | 株式会社 日立パワーデバイス | Semiconductor devices, power modules and power converters |
JP7272071B2 (en) * | 2019-04-04 | 2023-05-12 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
US11217541B2 (en) | 2019-05-08 | 2022-01-04 | Vishay-Siliconix, LLC | Transistors with electrically active chip seal ring and methods of manufacture |
US11218144B2 (en) | 2019-09-12 | 2022-01-04 | Vishay-Siliconix, LLC | Semiconductor device with multiple independent gates |
JP7120192B2 (en) * | 2019-09-17 | 2022-08-17 | 株式会社デンソー | semiconductor equipment |
TWI739252B (en) * | 2019-12-25 | 2021-09-11 | 杰力科技股份有限公司 | Trench mosfet and manufacturing method of the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5282018A (en) * | 1991-01-09 | 1994-01-25 | Kabushiki Kaisha Toshiba | Power semiconductor device having gate structure in trench |
US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
US6150693A (en) * | 1996-09-18 | 2000-11-21 | Advanced Micro Devices | Short channel non-self aligned VMOS field effect transistor |
US20010001494A1 (en) * | 1999-04-01 | 2001-05-24 | Christopher B. Kocon | Power trench mos-gated device and process for forming same |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60186068A (en) * | 1985-01-31 | 1985-09-21 | Hitachi Ltd | Insulated gate field effect transistor |
JPH0653514A (en) * | 1992-08-03 | 1994-02-25 | Nippon Telegr & Teleph Corp <Ntt> | Fabrication of semiconductor device |
JP3167457B2 (en) * | 1992-10-22 | 2001-05-21 | 株式会社東芝 | Semiconductor device |
GB9313843D0 (en) * | 1993-07-05 | 1993-08-18 | Philips Electronics Uk Ltd | A semiconductor device comprising an insulated gate field effect transistor |
WO2000038244A1 (en) * | 1998-12-18 | 2000-06-29 | Infineon Technologies Ag | Field effect transistor arrangement with a trench gate electrode and an additional highly doped layer in the body region |
JP2000269487A (en) * | 1999-03-15 | 2000-09-29 | Toshiba Corp | Semiconductor device and its manufacture |
JP2000269518A (en) * | 1999-03-18 | 2000-09-29 | Toshiba Corp | Powering semiconductor device and method for forming semiconductor layer |
US6348712B1 (en) * | 1999-10-27 | 2002-02-19 | Siliconix Incorporated | High density trench-gated power MOSFET |
JP3884206B2 (en) * | 2000-01-20 | 2007-02-21 | 株式会社東芝 | Semiconductor device |
JP4179491B2 (en) * | 2000-04-25 | 2008-11-12 | 株式会社ルネサステクノロジ | Semiconductor device, manufacturing method thereof, and characteristic evaluation method thereof |
JP4150496B2 (en) * | 2000-12-28 | 2008-09-17 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
JP3531613B2 (en) * | 2001-02-06 | 2004-05-31 | 株式会社デンソー | Trench gate type semiconductor device and manufacturing method thereof |
JP2002270825A (en) * | 2001-03-08 | 2002-09-20 | Hitachi Ltd | Method of manufacturing field effect transistor and semiconductor device |
JP4025063B2 (en) * | 2001-12-06 | 2007-12-19 | 株式会社ルネサステクノロジ | Semiconductor device |
-
2003
- 2003-08-04 JP JP2003286142A patent/JP4945055B2/en not_active Expired - Fee Related
-
2004
- 2004-07-08 US US10/886,041 patent/US20050029584A1/en not_active Abandoned
-
2007
- 2007-01-25 US US11/657,592 patent/US20070120194A1/en not_active Abandoned
-
2009
- 2009-04-27 US US12/385,979 patent/US7981747B2/en active Active
-
2011
- 2011-06-09 US US13/067,566 patent/US20110233664A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5282018A (en) * | 1991-01-09 | 1994-01-25 | Kabushiki Kaisha Toshiba | Power semiconductor device having gate structure in trench |
US6150693A (en) * | 1996-09-18 | 2000-11-21 | Advanced Micro Devices | Short channel non-self aligned VMOS field effect transistor |
US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
US20010001494A1 (en) * | 1999-04-01 | 2001-05-24 | Christopher B. Kocon | Power trench mos-gated device and process for forming same |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080150017A1 (en) * | 2006-12-25 | 2008-06-26 | Sanyo Electric Co., Ltd. | Semiconductor device |
US7649222B2 (en) | 2006-12-25 | 2010-01-19 | Sanyo Electric Co., Ltd. | Semiconductor device |
US20100176447A1 (en) * | 2007-05-30 | 2010-07-15 | Rohm Co., Ltd. | Semiconductor device |
US8575687B2 (en) * | 2007-05-30 | 2013-11-05 | Rohm Co., Ltd. | Semiconductor switch device |
US20090321824A1 (en) * | 2008-06-25 | 2009-12-31 | Fujitsu Microelectronics Limited | Semiconductor device |
US8080845B2 (en) * | 2008-06-25 | 2011-12-20 | Fujitsu Semiconductor Limited | Semiconductor device |
US20100176485A1 (en) * | 2009-01-09 | 2010-07-15 | Chiu-Chuan Chen | storage capacitor having an increased aperture ratio and method of manufacturing the same |
US8269310B2 (en) * | 2009-01-09 | 2012-09-18 | Century Display (Shenzhen) Co., Ltd. | Storage capacitor having an increased aperture ratio and method of manufacturing the same |
US20100327348A1 (en) * | 2009-06-24 | 2010-12-30 | Renesas Electronics Corporation | Semiconductor device, method of manufacturing the same and power-supply device using the same |
US8664716B2 (en) | 2009-06-24 | 2014-03-04 | Renesas Electronics Corporation | Semiconductor device, method of manufacturing the same and power-supply device using the same |
US20110079824A1 (en) * | 2009-10-07 | 2011-04-07 | Derek Hullinger | Alternate 4-terminal jfet geometry to reduce gate to source capacitance |
US8058674B2 (en) * | 2009-10-07 | 2011-11-15 | Moxtek, Inc. | Alternate 4-terminal JFET geometry to reduce gate to source capacitance |
US9653597B2 (en) | 2010-05-20 | 2017-05-16 | Infineon Technologies Americas Corp. | Method for fabricating a shallow and narrow trench FET and related structures |
CN102386233A (en) * | 2010-08-30 | 2012-03-21 | 精工电子有限公司 | Semiconductor device |
US8643102B2 (en) | 2010-09-10 | 2014-02-04 | Renesas Electronics Corporation | Control device of semiconductor device |
US8987817B2 (en) * | 2010-11-10 | 2015-03-24 | Mitsubishi Electric Corporation | Semiconductor device having a gate insulating film with a thicker portion covering a surface of an epitaxial protrusion and manufacturing method thereof |
US20120112266A1 (en) * | 2010-11-10 | 2012-05-10 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing the same |
CN105702717A (en) * | 2010-11-25 | 2016-06-22 | 三菱电机株式会社 | Silicon carbide semiconductor device |
US20150243753A1 (en) * | 2010-11-25 | 2015-08-27 | Mitsubishi Electric Corporation | Semiconductor device |
KR20140095044A (en) * | 2010-11-25 | 2014-07-31 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
KR101437961B1 (en) * | 2010-11-25 | 2014-09-11 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
US20120132912A1 (en) * | 2010-11-25 | 2012-05-31 | Mitsubishi Electric Corporation | Semiconductor device |
DE102011086943B4 (en) * | 2010-11-25 | 2020-09-10 | Mitsubishi Electric Corp. | Semiconductor device |
US9041007B2 (en) * | 2010-11-25 | 2015-05-26 | Mitsubishi Electric Corporation | Semiconductor device |
CN102610639A (en) * | 2010-11-25 | 2012-07-25 | 三菱电机株式会社 | Semiconductor device |
KR101319469B1 (en) * | 2010-11-25 | 2013-10-17 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
KR101642753B1 (en) * | 2010-11-25 | 2016-07-26 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
US9842906B2 (en) * | 2010-11-25 | 2017-12-12 | Mitsubishi Electric Corporation | Semiconductor device |
KR101286220B1 (en) | 2011-07-25 | 2013-07-15 | 미쓰비시덴키 가부시키가이샤 | Silicon carbide semiconductor device |
US20150118810A1 (en) * | 2013-10-24 | 2015-04-30 | Madhur Bobde | Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path |
US20220169449A1 (en) * | 2020-11-27 | 2022-06-02 | Terry Michael Brown, SR. | Split drive sprocket assembly |
Also Published As
Publication number | Publication date |
---|---|
US20050029584A1 (en) | 2005-02-10 |
US7981747B2 (en) | 2011-07-19 |
US20110233664A1 (en) | 2011-09-29 |
JP2005057050A (en) | 2005-03-03 |
US20090212358A1 (en) | 2009-08-27 |
JP4945055B2 (en) | 2012-06-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7981747B2 (en) | Semiconductor device and a method of manufacturing the same | |
US11127852B2 (en) | Vertical trench gate MOSFET with deep well region for junction termination | |
US8357973B2 (en) | Inverted-trench grounded-source FET structure with trenched source body short electrode | |
US9356122B2 (en) | Through silicon via processing method for lateral double-diffused MOSFETs | |
US7825480B2 (en) | Power semiconductor device and manufacturing method of the same | |
US7645661B2 (en) | Semiconductor device | |
US7211862B2 (en) | Semiconductor device and a method of manufacturing the same | |
US5897343A (en) | Method of making a power switching trench MOSFET having aligned source regions | |
US6444527B1 (en) | Method of operation of punch-through field effect transistor | |
US20060145250A1 (en) | LDMOS transistor | |
US9735254B2 (en) | Trench-gate RESURF semiconductor device and manufacturing method | |
JP2004537162A (en) | Power device and its manufacturing method | |
US9356134B2 (en) | Charged balanced devices with shielded gate trench | |
US9443975B1 (en) | Method of manufacturing a device having a shield plate dopant region | |
US20230335639A1 (en) | Source contact formation of mosfet with gate shield buffer for pitch reduction | |
US20010023957A1 (en) | Trench-gate semiconductor devices | |
JP5876008B2 (en) | Semiconductor device | |
CN117497586A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RENESAS TECHNOLOGY CORP., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIRAISHI, MASAKI;NAKAZAWA, YOSHITO;REEL/FRAME:018830/0496 Effective date: 20040618 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |