US20070109852A1 - One time programming memory cell using MOS device - Google Patents
One time programming memory cell using MOS device Download PDFInfo
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- US20070109852A1 US20070109852A1 US11/272,657 US27265705A US2007109852A1 US 20070109852 A1 US20070109852 A1 US 20070109852A1 US 27265705 A US27265705 A US 27265705A US 2007109852 A1 US2007109852 A1 US 2007109852A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Definitions
- This invention relates to one time programming memory cells, and more particularly to memory cells formed based on a soft breakdown mechanism.
- MOS metal-oxide-semiconductor
- Soft breakdown and hard breakdown are irreversible under normal device operating conditions. Hard breakdown will cause the device to malfunction, resulting in integrated circuit failure. A device experiencing soft breakdown, on the other hand, may still function correctly. However, a device experiencing soft breakdown will draw an excessive leakage current, and may lead to hard breakdown. Therefore, previous researchers have treated soft breakdown as an undesirable effect and have concentrated on how to eliminate or at least reduce soft breakdown.
- the preferred embodiments of the present invention provide a new approach for researching and using the soft breakdown mechanism.
- a non-volatile memory cell based on a soft breakdown mechanism and capable of one time programming is provided.
- a preferred memory cell includes a resistor coupled in series to a MOS device. With the resistor connected, soft breakdown can reliably occur when the MOS device is electrically stressed. Leakage current flowing through the gate dielectric increases after soft breakdown. Different levels of leakage currents are used to indicate different states of the memory cell.
- the source and drain regions of the MOS device are preferably shorted; thus the MOS device acts as a capacitor.
- the memory cell is preferably connected to a program pin and a read pin, which are external to the chip in which the memory cell is formed.
- a memory array includes memory cells arranged in a plurality of rows and a plurality of columns.
- a plurality of word-lines are respectively connected to the rows of memory cells with each respective word-line connected to the memory cells of each respective row.
- a plurality of bit-lines are respectively connected to the columns of memory cells with each respective bit-line connected to the memory cells of each respective column.
- Each memory cell comprises a MOS device adapted to soft breakdown.
- the MOS devices in a same row (or a same column) may share a common resistor.
- Each respective row (or column) is preferably coupled to a program pin and a read pin.
- a program operation of the preferred embodiments of the present invention includes applying a program voltage to a gate of a MOS device through a resistor and incurring a soft breakdown.
- the program voltage is preferably higher than the normal operation voltage of the integrated circuit.
- the program operation is performed in a short period of time, and the required program voltage can be estimated based on calculation.
- a read operation of the preferred embodiments of the present invention includes applying a reading voltage and measuring a leakage current through the gate oxide.
- a reference MOS device is preferably used to determine the state of the memory cell.
- FIG. 1 illustrates a prior art MOS device having a leakage current
- FIG. 2 illustrates a leakage current as a function of stress time in a PMOS device, wherein multiple soft breakdowns are shown;
- FIGS. 3A through 3D are variations of the preferred embodiment of the present invention.
- FIGS. 4A and 4B are cross-sectional views of the preferred embodiment of the present invention.
- FIGS. 5A and 5B illustrate a reference memory cell used for determining a state of a memory cell
- FIG. 6 illustrates a result obtained from a preferred memory cell embodiment, wherein a leakage current in the gate dielectric is shown as a function of a program time
- FIG. 7 illustrates a memory cell array formed of the preferred memory cell embodiment.
- FIG. 1 illustrates a conventional MOS device 2 , which includes a gate dielectric 4 (sometimes referred to as a gate oxide 4 ) formed on a substrate 10 and a gate electrode 6 on the gate dielectric 4 .
- a gate voltage V g is applied to the gate electrode 6 .
- I g leakage current flowing through the gate dielectric 4 .
- MOS devices manufactured using 130 nm technology or below the leakage current I g is typically in an order of nano amps.
- FIG. 2 illustrates how a leakage current I g increases over time on a sample PMOS device.
- the PMOS device is stressed by a gate voltage at about ⁇ 3.56V.
- the sample device Before being stressed, the sample device has a very small leakage current (point 12 ).
- the leakage current I g increases to about 60 ⁇ A after a soft breakdown occurs (point 14 ).
- the leakage current I g stays relatively stable for a period of time before another soft breakdown occurs, thus a step (level) 15 is formed.
- the second breakdown causes leakage current I g to increase to a higher level (point 16 ). Over time, more soft breakdowns may occur.
- a memory device can be formed using the soft breakdown mechanism, wherein different states can be represented by different magnitudes of the leakage currents. Since soft breakdown is un-recoverable, the resulting memory devices are non-volatile. For example, a MOS device having no soft breakdown may be used to store a state “0,” while a MOS device having soft breakdown may be used to store a state “1.”
- Soft breakdown however, has been found to be an unreliable mechanism. It is likely that a hard breakdown occurs before any noticeable soft breakdown. This prevents the use of the soft breakdown to form a reliable device.
- the occurrence of soft breakdown is often found to be a probability affected by various factors. For example, the occurrence of soft breakdown is related to the size of MOS devices. Research has revealed the following results. For a sample MOS device having a channel length of 0.12 ⁇ m, the probability of having a hard breakdown is almost one hundred percent when the MOS device is electrically stressed. If the channel length increases to about 0.24 ⁇ m, the probability of having a hard breakdown is about 70 percent, and the probability of having one or more soft breakdown increases to about 30 percent. When the channel length is further increased to about 0.5 ⁇ m, about 1.2 ⁇ m and about 10 ⁇ m, the probability of having soft breakdown(s) increases to about 55 percent, 70 percent and 88 percent, respectively.
- a memory cell based on a soft breakdown mechanism should have an improved probability that soft breakdown can reliably occur, and thus the memory cell can be reliably programmed to a soft breakdown state without causing a hard breakdown.
- FIGS. 3A through 7 A solution is provided by the preferred embodiments of the present invention, as shown in FIGS. 3A through 7 , wherein like reference numbers are used to identify like elements.
- a memory cell 30 includes a resistor 34 coupled in series with a MOS device 31 .
- the terms “series” or “serially” are used to refer to the connection or coupling between a resistor and a MOS device, indicating that the resistor connects/couples either to the gate of the MOS device, or to both source and drain regions of the MOS device.
- the MOS device 31 is adapted to soft breakdown. More preferably, MOS device 31 is a PMOS device, as soft breakdowns are more likely to occur on a PMOS device. However, an NMOS device can also be used. Due to the modulation of the resistor 34 , the program operation of the memory cell 30 can be reliably controlled without causing a hard breakdown.
- the resistor 34 is directly connected to the gate 32 of the MOS device 31 by interconnections such as conductive lines, vias and contacts.
- the resistor 34 and the gate 32 of the transistor 30 includes other conductive feature(s) 41 in between, wherein substantially the same current flows through the resistor 34 and the gate 32 .
- source and drain regions 36 of the MOS device 31 are interconnected, as shown in FIG. 3C .
- the source and drain regions 36 are preferably grounded.
- the resistor 34 may also be connected serially to the source and drain regions 36 , as shown in FIG. 3D .
- the preferred embodiments of the present invention also include forming a non-volatile memory cell by serially coupling a semiconductor capacitor and a resistor.
- the memory cells shown in FIG. 3A through 3D are coupled to program pins 40 and read pins 42 , which are external pins used for programming and reading.
- program pins 40 and read pins 42 are external pins used for programming and reading.
- read and program operations share a common pin 40 .
- program and read pins are internal pins and external signals are communicated via other intermediary circuitry (not shown).
- the resistor 34 preferably has a resistance between about 5 k ohm and about 10 M ohm, and more preferably between about 50 k ohm and about 1 M ohm, and can be formed using methods and structures known in the art.
- FIG. 4A illustrates a cross-sectional view of an exemplary embodiment, wherein the resistor 34 is formed of a poly-silicon line. Poly-silicon lines, depending on the doping concentration, may have a wide range of resistivity, and therefore are suitable for forming resistors.
- FIG. 4B illustrates another embodiment, wherein the resistor 34 is formed of a metal line in a metallization layer.
- a program voltage V p is applied to program pin 40 (refer to FIGS. 3A through 3D ).
- the program voltage V p is preferably higher than the operation voltage of the integrated circuit.
- the gate dielectric of the MOS device 31 is stressed by the voltage V p and a soft breakdown occurs.
- Resistor 34 attenuates the leakage current and prevents any leakage current pulse that may cause hard breakdown.
- a program operation requires determining an appropriate program voltage and an appropriate program time, which can be found through routine experiments by applying a program voltage and measuring a resulting leakage current.
- the preferred embodiments of the present invention further provide a method to determine an appropriate program voltage for a pre-determined program time. It is known that a program time T BD , which is the time used to incur a soft breakdown, relates to the program voltage V p , and a shorter program time is needed if a higher program voltage is applied.
- n is high, typically about 40 , when program voltage V p increases, the required program time T BD decreases dramatically. This leads to favorable results. Firstly, a program operation can be performed quickly using a high program voltage. Secondly, when operated under a low operation voltage during normal read operations, the preferred embodiments of the present invention are very stable.
- the pre-determined program time T p is substantially less than about one milli-second in order to quickly program multiple memory cells.
- a first voltage V p1 is applied to stress the memory cell, and a first program time T 1 is measured.
- the first program time T 1 is preferably longer than the pre-determined program time T p for a more accurate measurement of time. Accordingly, a lower first program voltage V p is selected.
- a read voltage which is preferably substantially lower than the program voltage, is applied to the read pin 42 of the memory cell and a leakage current is measured. If the leakage current indicates that the memory cell 30 has a soft breakdown, the memory cell is known to be in a programmed state, for example, state “1.” Otherwise, the memory cell is in an un-programmed state, such as state “0.”
- a reference memory cell 44 which is preferably substantially identical to the memory cell 30 , is therefore preferably formed for comparison purposes, as shown in FIG. 5A .
- the reference memory cell 44 is preferably formed simultaneously and identically to memory cell 30 .
- the reference memory cell 44 is not programmed. With a same read voltage applied, if a leakage current of the memory cell 30 is significantly greater than that of the reference memory cell 44 , it is known that memory cell 30 has been programmed. On the contrary, if a leakage current of a memory cell 30 is substantially close to that of the reference memory cell 44 , the memory cell is un-programmed.
- the reference memory cell 44 is pre-programmed. At read time, if a leakage current of the memory cell 30 is substantially close to that of the reference memory cell 44 , the memory cell 30 is programmed. An un-programmed memory cell 30 provides a substantially smaller leakage current then the reference memory cell 44 .
- FIG. 5B illustrates a variation of the diagram shown in FIG. 5A , wherein the reference memory cell 44 shares a common resistor 34 with the memory cell 30 . A read voltage is applied on read point 42 . If node 39 is grounded while node 37 is floating, the memory cell 30 is read. Conversely, if node 37 is grounded while node 39 is floating, the reference memory cell 44 is read.
- FIG. 6 illustrates an exemplary program operation, wherein a leakage current is shown as a function of program time.
- Line 50 shows an experimental result obtained from the preferred embodiment of the present invention. It is found that the leakage current I g of the preferred embodiment rises from about 2 ⁇ 10 ⁇ 8 amps before programming to over about 1 ⁇ 10 ⁇ 7 amps after programming. If a memory cell with no resistor is programmed, as line 52 shows, however, the leakage current jumps from 2 ⁇ 10 ⁇ 8 amps to over 1 ⁇ 10 ⁇ 4 amps, and a hard breakdown occurs.
- FIG. 6 indicates that soft breakdown is a more favorable mechanism for building a memory cell than hard breakdown.
- Memory cells having soft breakdown draw lower leakage currents, thus consuming less power than memory cells formed based on hard breakdown.
- a memory chip formed based on soft breakdown may thus contain more memory cells.
- FIG. 7 schematically illustrates a memory array, which comprises rows (sometimes referred to as words) 50 1 , 50 2 , . . . , 50 m and columns (sometimes referred to as bits) 60 1 , 60 2 , . . . , 60 n .
- Each row preferably shares a read pin and a program pin. Note that the memory cells in a row share a resistor. This not only saves chip area, but the deviation between the induced leakage current for the memory cells is also reduced.
- a memory cell C jk (wherein j is between 1 and m, and k is between 1 and n) is selected for programming, a programming voltage is applied to the respective program pin 54 j , and the respective column 60 k is connected to a lower voltage potential such as ground. Remaining rows and columns are preferably floating. Similarly, if a selected memory cell C jk is selected for reading, a read voltage is applied to the respective read pin 52 j , and the respective column 60 k is connected to a low potential. Remaining rows and columns are preferably floating. A leakage current between read pin 52 j and bit line 60 k is read to determine the state of the memory cell C jk . It is understood that memory cells in the array may be connected in different ways. For example, resistors 58 1 through 58 m (and respective program pins 52 1 through 52 m and read pins 54 1 through 54 m ) may be connected to columns instead of rows. Also, rows and columns can be reversed.
- the preferred embodiments of the present invention are suitable for, but not limited to, building low density memories, such as memories for storing security code, chip ID, and the like.
- the preferred embodiments of the present invention have several advantageous features. Firstly, the fabrication of the preferred embodiments of the present invention is fully compatible with existing semiconductor manufacturing processes. Secondly, since soft breakdown is not recoverable, stored states will not leak over time like some electron-storing memory cells. The preferred embodiments of the present invention are therefore suitable for long time storage.
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Abstract
Description
- This invention relates to one time programming memory cells, and more particularly to memory cells formed based on a soft breakdown mechanism.
- With the increasing scaling of integrated circuits, metal-oxide-semiconductor (MOS) devices become increasingly smaller. Gate oxides, sometimes referred to as gate dielectrics, in MOS devices become thinner accordingly. This increases the possibility of certain side effects.
- In a newly manufactured MOS device, there is a random number of traps in the gate oxide. Over time, due to operational stress, more traps form, leading to small transient conductive paths through the oxide. During this process, current conduction is caused by a combination of conductive paths formed by oxide traps and tunneling through the oxide. The formation of these conductive paths is referred to as soft breakdown (SBD). These conductive paths may become fixed by a high current density that causes a high temperature at the defect location. High temperature may alternatively relocate some of the oxide traps, breaking the conductive path. However, under normal operating conditions, soft breakdown persists. After a number of SBD incidents, many traps exist within the oxide, leading to a consistently high current density. Eventually, the resulting heat may generate holes in the oxide and melt the conductive materials at the gate. Thus, a persistent low-resistance path is formed, leading to a hard breakdown (HBD).
- Both soft breakdown and hard breakdown are irreversible under normal device operating conditions. Hard breakdown will cause the device to malfunction, resulting in integrated circuit failure. A device experiencing soft breakdown, on the other hand, may still function correctly. However, a device experiencing soft breakdown will draw an excessive leakage current, and may lead to hard breakdown. Therefore, previous researchers have treated soft breakdown as an undesirable effect and have concentrated on how to eliminate or at least reduce soft breakdown.
- The preferred embodiments of the present invention provide a new approach for researching and using the soft breakdown mechanism.
- A non-volatile memory cell based on a soft breakdown mechanism and capable of one time programming is provided.
- In accordance with one aspect of the present invention, a preferred memory cell includes a resistor coupled in series to a MOS device. With the resistor connected, soft breakdown can reliably occur when the MOS device is electrically stressed. Leakage current flowing through the gate dielectric increases after soft breakdown. Different levels of leakage currents are used to indicate different states of the memory cell. The source and drain regions of the MOS device are preferably shorted; thus the MOS device acts as a capacitor.
- In accordance with another aspect of the present invention, the memory cell is preferably connected to a program pin and a read pin, which are external to the chip in which the memory cell is formed.
- In accordance with yet another aspect of the present invention, a memory array includes memory cells arranged in a plurality of rows and a plurality of columns. A plurality of word-lines are respectively connected to the rows of memory cells with each respective word-line connected to the memory cells of each respective row. A plurality of bit-lines are respectively connected to the columns of memory cells with each respective bit-line connected to the memory cells of each respective column. Each memory cell comprises a MOS device adapted to soft breakdown. The MOS devices in a same row (or a same column) may share a common resistor. Each respective row (or column) is preferably coupled to a program pin and a read pin.
- In accordance with yet another aspect of the present invention, a program operation of the preferred embodiments of the present invention includes applying a program voltage to a gate of a MOS device through a resistor and incurring a soft breakdown. The program voltage is preferably higher than the normal operation voltage of the integrated circuit. Preferably, the program operation is performed in a short period of time, and the required program voltage can be estimated based on calculation.
- In accordance with yet another aspect of the present invention, a read operation of the preferred embodiments of the present invention includes applying a reading voltage and measuring a leakage current through the gate oxide. A reference MOS device is preferably used to determine the state of the memory cell.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
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FIG. 1 illustrates a prior art MOS device having a leakage current; -
FIG. 2 illustrates a leakage current as a function of stress time in a PMOS device, wherein multiple soft breakdowns are shown; -
FIGS. 3A through 3D are variations of the preferred embodiment of the present invention; -
FIGS. 4A and 4B are cross-sectional views of the preferred embodiment of the present invention; -
FIGS. 5A and 5B illustrate a reference memory cell used for determining a state of a memory cell; -
FIG. 6 illustrates a result obtained from a preferred memory cell embodiment, wherein a leakage current in the gate dielectric is shown as a function of a program time; and -
FIG. 7 illustrates a memory cell array formed of the preferred memory cell embodiment. - The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
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FIG. 1 illustrates aconventional MOS device 2, which includes a gate dielectric 4 (sometimes referred to as a gate oxide 4) formed on asubstrate 10 and a gate electrode 6 on the gate dielectric 4. During operation, a gate voltage Vg is applied to the gate electrode 6. Typically, there is a small leakage current Ig flowing through the gate dielectric 4. For small-scaled MOS devices, for example, MOS devices manufactured using 130 nm technology or below, the leakage current Ig is typically in an order of nano amps. - Soft breakdown or hard breakdown may occur when MOS devices are electrically stressed, resulting in a significant increase in leakage current Ig,
FIG. 2 illustrates how a leakage current Ig increases over time on a sample PMOS device. The PMOS device is stressed by a gate voltage at about −3.56V. Before being stressed, the sample device has a very small leakage current (point 12). The leakage current Ig increases to about 60 μA after a soft breakdown occurs (point 14). The leakage current Ig stays relatively stable for a period of time before another soft breakdown occurs, thus a step (level) 15 is formed. The second breakdown causes leakage current Ig to increase to a higher level (point 16). Over time, more soft breakdowns may occur. - Since devices have different leakage currents before and after breakdown, a memory device can be formed using the soft breakdown mechanism, wherein different states can be represented by different magnitudes of the leakage currents. Since soft breakdown is un-recoverable, the resulting memory devices are non-volatile. For example, a MOS device having no soft breakdown may be used to store a state “0,” while a MOS device having soft breakdown may be used to store a state “1.”
- Soft breakdown, however, has been found to be an unreliable mechanism. It is likely that a hard breakdown occurs before any noticeable soft breakdown. This prevents the use of the soft breakdown to form a reliable device. The occurrence of soft breakdown is often found to be a probability affected by various factors. For example, the occurrence of soft breakdown is related to the size of MOS devices. Research has revealed the following results. For a sample MOS device having a channel length of 0.12 μm, the probability of having a hard breakdown is almost one hundred percent when the MOS device is electrically stressed. If the channel length increases to about 0.24 μm, the probability of having a hard breakdown is about 70 percent, and the probability of having one or more soft breakdown increases to about 30 percent. When the channel length is further increased to about 0.5 μm, about 1.2 μm and about 10 μm, the probability of having soft breakdown(s) increases to about 55 percent, 70 percent and 88 percent, respectively.
- Advantageously, a memory cell based on a soft breakdown mechanism should have an improved probability that soft breakdown can reliably occur, and thus the memory cell can be reliably programmed to a soft breakdown state without causing a hard breakdown. A solution is provided by the preferred embodiments of the present invention, as shown in
FIGS. 3A through 7 , wherein like reference numbers are used to identify like elements. - Referring to
FIG. 3A , amemory cell 30 includes aresistor 34 coupled in series with aMOS device 31. Throughout the description, the terms “series” or “serially” are used to refer to the connection or coupling between a resistor and a MOS device, indicating that the resistor connects/couples either to the gate of the MOS device, or to both source and drain regions of the MOS device. TheMOS device 31 is adapted to soft breakdown. More preferably,MOS device 31 is a PMOS device, as soft breakdowns are more likely to occur on a PMOS device. However, an NMOS device can also be used. Due to the modulation of theresistor 34, the program operation of thememory cell 30 can be reliably controlled without causing a hard breakdown. - In the preferred embodiment, as shown in
FIG. 3A , theresistor 34 is directly connected to thegate 32 of theMOS device 31 by interconnections such as conductive lines, vias and contacts. In other embodiments, as shown inFIG. 3B , theresistor 34 and thegate 32 of thetransistor 30 includes other conductive feature(s) 41 in between, wherein substantially the same current flows through theresistor 34 and thegate 32. Preferably, source and drainregions 36 of theMOS device 31 are interconnected, as shown inFIG. 3C . During program or read operations, the source and drainregions 36 are preferably grounded. Theresistor 34 may also be connected serially to the source and drainregions 36, as shown inFIG. 3D . It is noted that when source and drainregions 36 are interconnected, theMOS device 31 acts as a capacitor. Therefore, the preferred embodiments of the present invention also include forming a non-volatile memory cell by serially coupling a semiconductor capacitor and a resistor. In the preferred embodiment, the memory cells shown inFIG. 3A through 3D are coupled to program pins 40 and readpins 42, which are external pins used for programming and reading. In other embodiments, read and program operations share acommon pin 40. In yet other embodiments, program and read pins are internal pins and external signals are communicated via other intermediary circuitry (not shown). - The
resistor 34 preferably has a resistance between about 5 k ohm and about 10 M ohm, and more preferably between about 50 k ohm and about 1 M ohm, and can be formed using methods and structures known in the art.FIG. 4A illustrates a cross-sectional view of an exemplary embodiment, wherein theresistor 34 is formed of a poly-silicon line. Poly-silicon lines, depending on the doping concentration, may have a wide range of resistivity, and therefore are suitable for forming resistors.FIG. 4B illustrates another embodiment, wherein theresistor 34 is formed of a metal line in a metallization layer. - During a program operation, a program voltage Vp is applied to program pin 40 (refer to
FIGS. 3A through 3D ). The program voltage Vp is preferably higher than the operation voltage of the integrated circuit. The gate dielectric of theMOS device 31 is stressed by the voltage Vp and a soft breakdown occurs.Resistor 34 attenuates the leakage current and prevents any leakage current pulse that may cause hard breakdown. - A program operation requires determining an appropriate program voltage and an appropriate program time, which can be found through routine experiments by applying a program voltage and measuring a resulting leakage current. The preferred embodiments of the present invention further provide a method to determine an appropriate program voltage for a pre-determined program time. It is known that a program time TBD, which is the time used to incur a soft breakdown, relates to the program voltage Vp, and a shorter program time is needed if a higher program voltage is applied. A relationship between the program time TBD and the program voltage Vp can be expressed as:
T BD=τ0 *V p −n [Eq. 1]
wherein τ0 and n are related to the characteristics of theMOS device 31, such as dimensions and materials. Since n is high, typically about 40, when program voltage Vp increases, the required program time TBD decreases dramatically. This leads to favorable results. Firstly, a program operation can be performed quickly using a high program voltage. Secondly, when operated under a low operation voltage during normal read operations, the preferred embodiments of the present invention are very stable. - Preferably, the pre-determined program time Tp is substantially less than about one milli-second in order to quickly program multiple memory cells. To find the corresponding program voltage, a first voltage Vp1 is applied to stress the memory cell, and a first program time T1 is measured. The first program time T1 is preferably longer than the pre-determined program time Tp for a more accurate measurement of time. Accordingly, a lower first program voltage Vp is selected. The required program voltage Vp can then be derived from the following equations:
T 1=τ0 *V p1 −n [Eq. 2]
and T p=τ0 *V p −n [Eq. 3]
FromEquations 2 and 3, it is found that:
Vp=e(1nVp1+(1nT1−1nTp)/n) [Eq. 4] - Therefore, an appropriate program voltage Vp is found, and the memory device can be programmed by applying the program voltage Vp for the period of time Tp. It is to be appreciated that the previous discussion gives an estimation. To further improve accuracy of the program operations, routine experiments may be combined with the previously discussed method to find the optimum program voltage and time.
- For reading a memory cell, a read voltage, which is preferably substantially lower than the program voltage, is applied to the
read pin 42 of the memory cell and a leakage current is measured. If the leakage current indicates that thememory cell 30 has a soft breakdown, the memory cell is known to be in a programmed state, for example, state “1.” Otherwise, the memory cell is in an un-programmed state, such as state “0.” - Obviously, leakage currents will be different if the memory cells are formed with different sizes, materials and/or processes. A
reference memory cell 44, which is preferably substantially identical to thememory cell 30, is therefore preferably formed for comparison purposes, as shown inFIG. 5A . Thereference memory cell 44 is preferably formed simultaneously and identically tomemory cell 30. In the preferred embodiment, thereference memory cell 44 is not programmed. With a same read voltage applied, if a leakage current of thememory cell 30 is significantly greater than that of thereference memory cell 44, it is known thatmemory cell 30 has been programmed. On the contrary, if a leakage current of amemory cell 30 is substantially close to that of thereference memory cell 44, the memory cell is un-programmed. - In alternative embodiments, the
reference memory cell 44 is pre-programmed. At read time, if a leakage current of thememory cell 30 is substantially close to that of thereference memory cell 44, thememory cell 30 is programmed. Anun-programmed memory cell 30 provides a substantially smaller leakage current then thereference memory cell 44.FIG. 5B illustrates a variation of the diagram shown inFIG. 5A , wherein thereference memory cell 44 shares acommon resistor 34 with thememory cell 30. A read voltage is applied on readpoint 42. If node 39 is grounded whilenode 37 is floating, thememory cell 30 is read. Conversely, ifnode 37 is grounded while node 39 is floating, thereference memory cell 44 is read. -
FIG. 6 illustrates an exemplary program operation, wherein a leakage current is shown as a function of program time.Line 50 shows an experimental result obtained from the preferred embodiment of the present invention. It is found that the leakage current Ig of the preferred embodiment rises from about 2×10−8 amps before programming to over about 1×10−7 amps after programming. If a memory cell with no resistor is programmed, asline 52 shows, however, the leakage current jumps from 2×10−8 amps to over 1×10−4 amps, and a hard breakdown occurs. -
FIG. 6 indicates that soft breakdown is a more favorable mechanism for building a memory cell than hard breakdown. Memory cells having soft breakdown draw lower leakage currents, thus consuming less power than memory cells formed based on hard breakdown. A memory chip formed based on soft breakdown may thus contain more memory cells. - The preferred embodiments of the present invention may be used to form memory arrays.
FIG. 7 schematically illustrates a memory array, which comprises rows (sometimes referred to as words) 50 1, 50 2, . . . , 50 m and columns (sometimes referred to as bits) 60 1, 60 2, . . . , 60 n. Each row preferably shares a read pin and a program pin. Note that the memory cells in a row share a resistor. This not only saves chip area, but the deviation between the induced leakage current for the memory cells is also reduced. If a memory cell Cjk (wherein j is between 1 and m, and k is between 1 and n) is selected for programming, a programming voltage is applied to the respective program pin 54 j, and the respective column 60 k is connected to a lower voltage potential such as ground. Remaining rows and columns are preferably floating. Similarly, if a selected memory cell Cjk is selected for reading, a read voltage is applied to therespective read pin 52 j, and the respective column 60 k is connected to a low potential. Remaining rows and columns are preferably floating. A leakage current betweenread pin 52 j and bit line 60 k is read to determine the state of the memory cell Cjk. It is understood that memory cells in the array may be connected in different ways. For example, resistors 58 1 through 58 m (and respective program pins 52 1 through 52 m and read pins 54 1 through 54 m) may be connected to columns instead of rows. Also, rows and columns can be reversed. - Due to the limitation of the relatively high leakage current, the preferred embodiments of the present invention are suitable for, but not limited to, building low density memories, such as memories for storing security code, chip ID, and the like.
- The preferred embodiments of the present invention have several advantageous features. Firstly, the fabrication of the preferred embodiments of the present invention is fully compatible with existing semiconductor manufacturing processes. Secondly, since soft breakdown is not recoverable, stored states will not leak over time like some electron-storing memory cells. The preferred embodiments of the present invention are therefore suitable for long time storage.
- Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (17)
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US11/272,657 US7307880B2 (en) | 2005-11-14 | 2005-11-14 | One time programming memory cell using MOS device |
TW095110238A TWI279810B (en) | 2005-11-14 | 2006-03-24 | An non-volatile memory cell, memory cell array and device |
CNB2006100743103A CN100538889C (en) | 2005-11-14 | 2006-04-05 | Non-volatile memory cells, memory cell matrix and memory storage |
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US11/272,657 US7307880B2 (en) | 2005-11-14 | 2005-11-14 | One time programming memory cell using MOS device |
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US20130263117A1 (en) * | 2012-03-28 | 2013-10-03 | International Business Machines Corporation | Allocating resources to virtual machines via a weighted cost ratio |
US10665595B2 (en) | 2017-08-30 | 2020-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal isolation testing in the context of memory cells |
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US20090052102A1 (en) * | 2007-08-20 | 2009-02-26 | Kabushiki Kaisha Toshiba | Semiconductor device |
EP2045349A1 (en) * | 2007-10-05 | 2009-04-08 | Linde Aktiengesellschaft | Method and apparatus for continuous hot-dip coating of metal strips |
US8400813B2 (en) * | 2009-02-10 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | One-time programmable fuse with ultra low programming current |
US8675381B2 (en) | 2010-07-20 | 2014-03-18 | Macronix International Co., Ltd. | Transistor having an adjustable gate resistance and semiconductor device comprising the same |
US8482952B2 (en) | 2011-02-17 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | One time programming bit cell |
JP2015026709A (en) * | 2013-07-26 | 2015-02-05 | マイクロン テクノロジー, インク. | Semiconductor device |
CN105513642B (en) * | 2014-09-24 | 2019-11-05 | 珠海创飞芯科技有限公司 | Otp memory |
US9245648B1 (en) | 2014-09-26 | 2016-01-26 | Qualcomm Incorporated | Logic high-dielectric-constant (HK) metal-gate (MG) one-time-programming (OTP) memory device sensing method |
TWI747288B (en) * | 2019-12-12 | 2021-11-21 | 友達光電股份有限公司 | Chip |
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US20130263117A1 (en) * | 2012-03-28 | 2013-10-03 | International Business Machines Corporation | Allocating resources to virtual machines via a weighted cost ratio |
US10665595B2 (en) | 2017-08-30 | 2020-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal isolation testing in the context of memory cells |
US11631682B2 (en) | 2017-08-30 | 2023-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal isolation testing in the context of memory cells |
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CN1967718A (en) | 2007-05-23 |
US7307880B2 (en) | 2007-12-11 |
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