US20070105316A1 - Nanocrystal memory element, method for fabricating the same and memory having the memory element - Google Patents

Nanocrystal memory element, method for fabricating the same and memory having the memory element Download PDF

Info

Publication number
US20070105316A1
US20070105316A1 US11/495,528 US49552806A US2007105316A1 US 20070105316 A1 US20070105316 A1 US 20070105316A1 US 49552806 A US49552806 A US 49552806A US 2007105316 A1 US2007105316 A1 US 2007105316A1
Authority
US
United States
Prior art keywords
nanocrystal
nanocrystals
memory element
layer
fabricating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/495,528
Inventor
Pei-Ren Jeng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Original Assignee
Industrial Technology Research Institute ITRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE reassignment INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JENG, PEI-REN
Publication of US20070105316A1 publication Critical patent/US20070105316A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate

Definitions

  • the present invention relates to a memory device and a method for fabricating the same, and more particularly, to a nanocrystal memory for accessing charges and a method for fabricating the same.
  • nanocrystal memory is most likely to replace the traditional flash memory.
  • a distinguishing feature of a traditional flash memory is that, in addition to an oxide insulating layer typically formed in a traditional MOSFET, a floating gate is formed in between a gate and a channel in the MOS of the tradition flash memory, such that data are stored by introducing into or removing from the floating gate negative charges.
  • a traditional floating gate is designed to achieve electric conduction, using the charges stored in doped polysilicon which forms the floating gate. Therefore, charges will hardly be stored in the doped polysilicon when there is a current leakage from any point of a tunnel oxide layer beneath the polysilicon floating gate.
  • the tunnel oxide layer will have to be thinned down if the size of the memory is to be reduced.
  • whatever thinning-down effort is subject to the physical limit of direct tunneling, thus a thinning down process does have its own limit.
  • a nanocrystal memory is proposed to overcome the drawbacks of high operational voltage and slow reading speed as found in the traditional flash memory and enhance memory retention.
  • the proposed nanocrystal memory has charges stored in each nanocrystal; in the event of a current leakage from any point of the tunnel oxide layer, only the charges close to the leakage point will get lost, but the rest of the charges will still be confined to individual nanocrystals, because the nanocrystals are separated from one another.
  • the proposed doped polysilicon floating gate overcomes the drawback of the prior art, that is, charge storage is difficult in the presence of a current leakage from any point of the tunnel oxide layer underlying the floating gate.
  • a nanocrystal fabrication process should be preferably provided with sufficient nanocrystals to store charges so as to create a significant difference between the threshold voltage associated with the presence of charge storage and the threshold voltage associated with the lack of charge storage, thereby enabling the memory to perform effective interpretation.
  • an existing method for storing sufficient charges involves sputtering, depositing or implanting a thick layer of metal ions, and then performing annealing to form nanocrystals in a silicide layer.
  • the drawback of the method is poor control over the levels and positions of the nanocrystals in the silicide layer and, as a result, the nanocrystals are scattered, making barrier width between the nanocrystals and the gate inconsistent. In consequence it is difficult to keep a writing-related or erasure-related threshold voltage constant. In other words, if nanocrystals are scattered, the distance between the underlying substrate or the tunnel oxide layer and individual nanocrystals will be inconsistent, and in consequence the energy barrier varies from nanocrystal to nanocrystal.
  • a plurality of nanocrystals 106 in a nanocrystal layer 107 embedded in between a gate oxide 104 and a gate 105 of a traditional nanocrystal memory are scattered and unevenly distributed, wherein once a voltage is applied to the gate 105 , individual nanocrystals 106 are subjected to electric field of different strengths because individual nanocrystals 106 are separated from the gate 105 by different distances. As a result, it is rather difficult to control transistor threshold voltage. Moreover, nanocrystals with relatively narrow barrier width may be over-erased as a result of an attempt to remove all the charges stored in the nanocrystal 106 during an erasing process.
  • an urgent issue to be addressed involves fabricating a nanocrystal layer with a high density and a uniform distribution.
  • a primary objective of the present invention is to provide a nanocrystal memory element characterized by uniform distribution of threshold voltage of the nanocrystals and lack of over-erasing and a method for fabricating the same.
  • Another objective of the present invention is to provide a nanocrystal memory with equal level distribution.
  • the present invention proposes a method for fabricating a nanocrystal memory element, the method comprising the steps of: forming a tunnel oxide layer on a substrate; depositing conductive layers and dielectric layers on the tunnel oxide layer repeatedly and alternately; performing a rapid thermal annealing process to the conductive layers and the dielectric layers, such that a plurality of nanocrystals are formed as a result of crystallization of the conductive layers, and the nanocrystals formed as a result of the crystallization of the same conductive layer are located at the same level; forming an integration layer by combining the conductive layers and the dielectric layers previously treated with the rapid thermal annealing process; and forming a gate on the integration layer.
  • a method for fabricating a nanocrystal memory element involves disposing at the same level the nanocrystals formed as a result of the crystallization of any conductive layer such that every nanocrystal has the same barrier width in relation to the gate, with a view to achieving uniform distribution of threshold voltage of the nanocrystals, preventing over-erasing from occurring, and thereby enhancing the performance of the memory.
  • the present invention further provides a nanocrystal memory element comprising a substrate, a tunnel oxide layer formed on the substrate, an integration layer formed on the tunnel oxide layer, and a gate formed on the integration layer.
  • the integration layer comprises a dielectric material, and nanocrystal groups, each collectively formed by a plurality of nanocrystals located at the same level in the dielectric material, such that distances, and therefore barrier widths, between the tunnel oxide layer and the nanocrystals in the same nanocrystal group are equal.
  • the present invention further provides a memory comprising the nanocrystal memory element.
  • the memory comprises a substrate, a source and a drain both formed on the substrate and spaced apart by an appropriate distance, a tunnel oxide layer formed on the substrate and disposed between the source and the drain, an integration layer formed on the tunnel oxide layer, and a gate formed on the integration layer.
  • the integration layer comprises a dielectric material, and nanocrystal groups, each collectively formed by a plurality of nanocrystals located at the same level in the dielectric material, such that distances, and therefore barrier widths, between the tunnel oxide layer and the nanocrystals in the same nanocrystal group are equal.
  • FIG. 1 is a cross sectional view of a nanocrystal layer of the traditional nanocrystal memory
  • FIG. 2A illustrates formation of a tunnel oxide layer on a substrate
  • FIG. 2B which is similar to the cross-sectional view shown in FIG. 2A , illustrates how conductive layers and dielectric layers are deposited on the tunnel oxide layer repeatedly and alternately;
  • FIG. 2C which is similar to the cross-sectional view shown in FIG. 2B , illustrates how to perform a thermal oxidation process, such as a rapid thermal annealing process;
  • FIG. 2D which is similar to the cross-sectional view shown in FIG. 2C , illustrates a plurality of nanocrystals formed as a result of crystallization of the conductive layers;
  • FIG. 2E which is similar to the cross-sectional view shown in FIG. 2D , illustrates a gate fabricated in a process
  • FIG. 3 is a cross-sectional view of a nanocrystal memory of the present invention.
  • a nanocrystal memory element, a method for fabricating the same, and the memory with the memory element provided in accordance with the present invention are described with the following specific embodiments and drawings.
  • FIGS. 2A to 2 E illustrate a method for fabricating a nanocrystal memory element of the present invention.
  • a tunnel oxide layer 21 is formed on a substrate 20 made of silicon material by thermal oxidation known in the prior art.
  • the tunnel oxide layer 21 is made of silicon oxides or other dielectric materials and is preferably 5 nanometers thick.
  • the method for forming the tunnel oxide layer 21 is known in the prior art, thus no related detailed description is given in here.
  • atomic layer chemical vapor deposition known in the prior art, depositing on the tunnel oxide layer 21 a dielectric layer, then depositing a conductive layer on the dielectric layer, and finally depositing another dielectric layer on the conductive layer, in a way that the thickness of each deposit layer deposited on the tunnel oxide layer is precisely controlled.
  • multiple conductive layers 220 and dielectric layers 221 are alternately deposited, such that any two neighboring conductive layers 220 are separated by a dielectric layer 221 .
  • three conductive layers 220 and three dielectric layers 221 are alternately disposed.
  • examples of a method for depositing the dielectric layers and the conductive layers on the tunnel oxide layer are molecular beam epitaxy (MBE), chemical vapor deposition (CVD), physical vapor deposition (PVD), and other appropriate methods.
  • the dielectric layers 221 are made of conventional dielectric materials, such as silicon oxides.
  • the conductive layers 220 are made of one selected from the group consisting of metals, metallic compounds, and doped silicides. The metals are, namely nickel, gold, silver, and platinum.
  • the metallic compounds is titanium nitride (TiN), and that of the silicides is silicon germanium.
  • the doping impurities are, namely gallium phosphide (GaP), cadmium sulfide (CdS), gallium arsenide (GaAs), and indium phosphide (InP), that is, compounds which result from reactions between a group III element and a group V element, or between a group II element and a group VI element; alternatively, the above-mentioned may be replaced by equivalent doping impurities and equivalent compounds known in the prior art and therefore are not discussed in detail here.
  • a thermal oxidation process such as rapid thermal annealing, is performed on the conductive layers 220 and the dielectric layers 221 alternately stacked, such that a plurality of nanocrystals 220 a are formed as a result of crystallization of the metals or the doping impurities in the conductive layers 220 , so as to form an integration layer 22 by combining the conductive layers 220 with the dielectric layers 221 .
  • the nanocrystals 220 a formed in the same conductive layer 220 within the integration layer 22 are located at the same level and form a nanocrystal group.
  • any two conductive layers 220 are separated by one dielectric layer 221 ; therefore, the nanocrystal groups formed by crystallizing two neighboring upper-lower conductive layers 220 are also separated by the dielectric material which forms the dielectric layer 221 .
  • all the nanocrystals 220 a in the same nanocrystal group are disposed at the same level; distances, and therefore barrier widths, between each nanocrystal 220 a and the tunnel oxide layer 21 lies thereunder, are the same. Therefore, the fabricated memory allows threshold voltage to be evenly distributed and prevents the over-erasing of charges, thus enhancing memory performance.
  • the rapid thermal annealing process is performed at temperature that ranges between 800° C. and 1200° C. However, the rapid thermal annealing process is not the only method for forming the nanocrystals 220 a; instead, a nitriding process and other appropriate methods can also be used.
  • a gate 23 is formed on the integration layer 22 .
  • the gate 23 is formed by a conventional method, for example, chemical vapor deposition, and is made of any conventional material, such as doped polysilicon. Fabrication of the memory element of the present invention is completed after the gate 23 is formed.
  • FIG. 3 shows a memory 2 into which the foregoing memory element is integrated.
  • the memory 2 comprises a substrate 20 , a tunnel oxide layer 21 formed on the substrate 20 , an integration layer 22 formed on the tunnel oxide layer 21 , a gate 23 formed on the integration layer 22 , and a source 24 and a drain 25 , both formed in the substrate 20 , flanking and underlying the tunnel oxide layer 21 .
  • a plurality of nanocrystals 220 a are evenly distributed within the integration layer 22 , and the nanocrystals 220 a located at the same level form a nanocrystal group.
  • a nanocrystal 220 a always belongs to a nanocrystal group formed by the nanocrystals 220 a located at a same level, any two neighboring upper-lower nanocrystal groups are separated by a distance.

Abstract

A nanocrystal memory element and a method for fabricating the same involves repeatedly and alternately depositing, by atomic layer deposition, conductive layers and dielectric layers on a substrate with a tunnel oxide layer formed thereon, forming multiple layers of nanocrystal groups as a result of crystallization of conductive layers in a rapid thermal annealing process, and forming a gate on the top dielectric layer. The nanocrystal groups disposed at any two neighboring levels are separated by one dielectric layer, thus a plurality of nanocrystals formed in an integration layer are disposed at the same level. Barrier widths between a channel and the nanocrystals of the nanocrystal groups disposed at the same level are equal. Therefore, the nanocrystals at the same level are subjected the same electric field when voltage is applied to the gate, resulting in improved transistor performance, enhanced control of threshold voltage, and avoidance of over-erasing.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a memory device and a method for fabricating the same, and more particularly, to a nanocrystal memory for accessing charges and a method for fabricating the same.
    • BACKGROUND OF THE INVENTION
  • Among existing non-volatile memories, nanocrystal memory is most likely to replace the traditional flash memory. A distinguishing feature of a traditional flash memory is that, in addition to an oxide insulating layer typically formed in a traditional MOSFET, a floating gate is formed in between a gate and a channel in the MOS of the tradition flash memory, such that data are stored by introducing into or removing from the floating gate negative charges. However, a traditional floating gate is designed to achieve electric conduction, using the charges stored in doped polysilicon which forms the floating gate. Therefore, charges will hardly be stored in the doped polysilicon when there is a current leakage from any point of a tunnel oxide layer beneath the polysilicon floating gate. Moreover, the tunnel oxide layer will have to be thinned down if the size of the memory is to be reduced. However, whatever thinning-down effort is subject to the physical limit of direct tunneling, thus a thinning down process does have its own limit.
  • Therefore, a nanocrystal memory is proposed to overcome the drawbacks of high operational voltage and slow reading speed as found in the traditional flash memory and enhance memory retention. Unlike the doped polysilicon floating gate of the traditional flash memory, the proposed nanocrystal memory has charges stored in each nanocrystal; in the event of a current leakage from any point of the tunnel oxide layer, only the charges close to the leakage point will get lost, but the rest of the charges will still be confined to individual nanocrystals, because the nanocrystals are separated from one another. Accordingly, the proposed doped polysilicon floating gate overcomes the drawback of the prior art, that is, charge storage is difficult in the presence of a current leakage from any point of the tunnel oxide layer underlying the floating gate.
  • However, the most important issue that existing technology has to address is about the control of the formation of nanocrystals during a nanocrystal fabrication process. For instance, it will be impossible to store enough charges in a nanocrystal layer disposed with nanocrystals, if the nanocrystals disposed in the nanocrystal layer are too small or over-dispersed; as a result, the charges present in a channel beneath an oxidation layer decrease, causing difficulty in interpretation. In other words, in the event that few charges are stored in the nanocrystal layer, there will be a negligible difference between a threshold voltage associated with the presence of nanocrystals in the nanocrystal layer and a threshold voltage associate with the absence of nanocrystals from the nanocrystal layer, and in consequence it is impossible to determine whether charges are stored in the nanocrystal layer and perform effective interpretation. Accordingly, a nanocrystal fabrication process should be preferably provided with sufficient nanocrystals to store charges so as to create a significant difference between the threshold voltage associated with the presence of charge storage and the threshold voltage associated with the lack of charge storage, thereby enabling the memory to perform effective interpretation.
  • At present, an existing method for storing sufficient charges involves sputtering, depositing or implanting a thick layer of metal ions, and then performing annealing to form nanocrystals in a silicide layer. The drawback of the method is poor control over the levels and positions of the nanocrystals in the silicide layer and, as a result, the nanocrystals are scattered, making barrier width between the nanocrystals and the gate inconsistent. In consequence it is difficult to keep a writing-related or erasure-related threshold voltage constant. In other words, if nanocrystals are scattered, the distance between the underlying substrate or the tunnel oxide layer and individual nanocrystals will be inconsistent, and in consequence the energy barrier varies from nanocrystal to nanocrystal. Accordingly, by the time a voltage is applied, some nanocrystals have already been stored with charges, but others have not; similarly, by the time an erasure operation is performed, some nanocrystals have already got rid of charges, but others have not. For this reason, interpretation is wrong, which in turn causes over-erasing.
  • Referring to FIG. 1, a plurality of nanocrystals 106 in a nanocrystal layer 107 embedded in between a gate oxide 104 and a gate 105 of a traditional nanocrystal memory are scattered and unevenly distributed, wherein once a voltage is applied to the gate 105, individual nanocrystals 106 are subjected to electric field of different strengths because individual nanocrystals 106 are separated from the gate 105 by different distances. As a result, it is rather difficult to control transistor threshold voltage. Moreover, nanocrystals with relatively narrow barrier width may be over-erased as a result of an attempt to remove all the charges stored in the nanocrystal 106 during an erasing process.
  • Therefore, an urgent issue to be addressed involves fabricating a nanocrystal layer with a high density and a uniform distribution.
    • SUMMARY OF THE INVENTION
  • In light of the above drawbacks of the prior art, a primary objective of the present invention is to provide a nanocrystal memory element characterized by uniform distribution of threshold voltage of the nanocrystals and lack of over-erasing and a method for fabricating the same.
  • Another objective of the present invention is to provide a nanocrystal memory with equal level distribution.
  • In order to achieve the foregoing and other objectives, the present invention proposes a method for fabricating a nanocrystal memory element, the method comprising the steps of: forming a tunnel oxide layer on a substrate; depositing conductive layers and dielectric layers on the tunnel oxide layer repeatedly and alternately; performing a rapid thermal annealing process to the conductive layers and the dielectric layers, such that a plurality of nanocrystals are formed as a result of crystallization of the conductive layers, and the nanocrystals formed as a result of the crystallization of the same conductive layer are located at the same level; forming an integration layer by combining the conductive layers and the dielectric layers previously treated with the rapid thermal annealing process; and forming a gate on the integration layer.
  • According to the present invention, a method for fabricating a nanocrystal memory element involves disposing at the same level the nanocrystals formed as a result of the crystallization of any conductive layer such that every nanocrystal has the same barrier width in relation to the gate, with a view to achieving uniform distribution of threshold voltage of the nanocrystals, preventing over-erasing from occurring, and thereby enhancing the performance of the memory.
  • The present invention further provides a nanocrystal memory element comprising a substrate, a tunnel oxide layer formed on the substrate, an integration layer formed on the tunnel oxide layer, and a gate formed on the integration layer. The integration layer comprises a dielectric material, and nanocrystal groups, each collectively formed by a plurality of nanocrystals located at the same level in the dielectric material, such that distances, and therefore barrier widths, between the tunnel oxide layer and the nanocrystals in the same nanocrystal group are equal.
  • The present invention further provides a memory comprising the nanocrystal memory element. The memory comprises a substrate, a source and a drain both formed on the substrate and spaced apart by an appropriate distance, a tunnel oxide layer formed on the substrate and disposed between the source and the drain, an integration layer formed on the tunnel oxide layer, and a gate formed on the integration layer. The integration layer comprises a dielectric material, and nanocrystal groups, each collectively formed by a plurality of nanocrystals located at the same level in the dielectric material, such that distances, and therefore barrier widths, between the tunnel oxide layer and the nanocrystals in the same nanocrystal group are equal.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
  • FIG. 1 (PRIOR ART) is a cross sectional view of a nanocrystal layer of the traditional nanocrystal memory;
  • FIG. 2A illustrates formation of a tunnel oxide layer on a substrate;
  • FIG. 2B, which is similar to the cross-sectional view shown in FIG. 2A, illustrates how conductive layers and dielectric layers are deposited on the tunnel oxide layer repeatedly and alternately;
  • FIG. 2C, which is similar to the cross-sectional view shown in FIG. 2B, illustrates how to perform a thermal oxidation process, such as a rapid thermal annealing process;
  • FIG. 2D, which is similar to the cross-sectional view shown in FIG. 2C, illustrates a plurality of nanocrystals formed as a result of crystallization of the conductive layers;
  • FIG. 2E, which is similar to the cross-sectional view shown in FIG. 2D, illustrates a gate fabricated in a process; and
  • FIG. 3 is a cross-sectional view of a nanocrystal memory of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A nanocrystal memory element, a method for fabricating the same, and the memory with the memory element provided in accordance with the present invention are described with the following specific embodiments and drawings.
  • FIGS. 2A to 2E illustrate a method for fabricating a nanocrystal memory element of the present invention.
  • Referring to FIG. 2A, first of all, a tunnel oxide layer 21 is formed on a substrate 20 made of silicon material by thermal oxidation known in the prior art. The tunnel oxide layer 21 is made of silicon oxides or other dielectric materials and is preferably 5 nanometers thick. The method for forming the tunnel oxide layer 21 is known in the prior art, thus no related detailed description is given in here.
  • Referring to FIG. 2B, by atomic layer chemical vapor deposition known in the prior art, depositing on the tunnel oxide layer 21 a dielectric layer, then depositing a conductive layer on the dielectric layer, and finally depositing another dielectric layer on the conductive layer, in a way that the thickness of each deposit layer deposited on the tunnel oxide layer is precisely controlled. In so doing, multiple conductive layers 220 and dielectric layers 221 are alternately deposited, such that any two neighboring conductive layers 220 are separated by a dielectric layer 221. In this embodiment, referring to FIG. 2B, three conductive layers 220 and three dielectric layers 221 are alternately disposed. Noteworthily, the number of the conductive layers 220 and the dielectric layers 221 alternately disposed solely depends on requirements for designing a memory element, but is subject to no specific restriction. In addition to atomic layer chemical vapor deposition, examples of a method for depositing the dielectric layers and the conductive layers on the tunnel oxide layer are molecular beam epitaxy (MBE), chemical vapor deposition (CVD), physical vapor deposition (PVD), and other appropriate methods. The dielectric layers 221 are made of conventional dielectric materials, such as silicon oxides. The conductive layers 220 are made of one selected from the group consisting of metals, metallic compounds, and doped silicides. The metals are, namely nickel, gold, silver, and platinum. An example of the metallic compounds is titanium nitride (TiN), and that of the silicides is silicon germanium. The doping impurities are, namely gallium phosphide (GaP), cadmium sulfide (CdS), gallium arsenide (GaAs), and indium phosphide (InP), that is, compounds which result from reactions between a group III element and a group V element, or between a group II element and a group VI element; alternatively, the above-mentioned may be replaced by equivalent doping impurities and equivalent compounds known in the prior art and therefore are not discussed in detail here.
  • Referring to FIG. 2C, a thermal oxidation process, such as rapid thermal annealing, is performed on the conductive layers 220 and the dielectric layers 221 alternately stacked, such that a plurality of nanocrystals 220 a are formed as a result of crystallization of the metals or the doping impurities in the conductive layers 220, so as to form an integration layer 22 by combining the conductive layers 220 with the dielectric layers 221. Referring FIG. 2D, the nanocrystals 220 a formed in the same conductive layer 220 within the integration layer 22 are located at the same level and form a nanocrystal group.
  • Moreover, any two conductive layers 220 are separated by one dielectric layer 221; therefore, the nanocrystal groups formed by crystallizing two neighboring upper-lower conductive layers 220 are also separated by the dielectric material which forms the dielectric layer 221. In other words, all the nanocrystals 220 a in the same nanocrystal group are disposed at the same level; distances, and therefore barrier widths, between each nanocrystal 220 a and the tunnel oxide layer 21 lies thereunder, are the same. Therefore, the fabricated memory allows threshold voltage to be evenly distributed and prevents the over-erasing of charges, thus enhancing memory performance. In addition, the rapid thermal annealing process is performed at temperature that ranges between 800° C. and 1200° C. However, the rapid thermal annealing process is not the only method for forming the nanocrystals 220 a; instead, a nitriding process and other appropriate methods can also be used.
  • Finally, referring to FIG. 2E, a gate 23 is formed on the integration layer 22. The gate 23 is formed by a conventional method, for example, chemical vapor deposition, and is made of any conventional material, such as doped polysilicon. Fabrication of the memory element of the present invention is completed after the gate 23 is formed.
  • Moreover, FIG. 3 shows a memory 2 into which the foregoing memory element is integrated. As shown in FIG. 3, the memory 2 comprises a substrate 20, a tunnel oxide layer 21 formed on the substrate 20, an integration layer 22 formed on the tunnel oxide layer 21, a gate 23 formed on the integration layer 22, and a source 24 and a drain 25, both formed in the substrate 20, flanking and underlying the tunnel oxide layer 21. In addition, referring to the foregoing description, a plurality of nanocrystals 220 a are evenly distributed within the integration layer 22, and the nanocrystals 220 a located at the same level form a nanocrystal group. A nanocrystal 220 a always belongs to a nanocrystal group formed by the nanocrystals 220 a located at a same level, any two neighboring upper-lower nanocrystal groups are separated by a distance.
  • The present invention is illustrated with the aforesaid embodiments, such that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the invention. The present invention may also be implemented and applied according to other embodiments, and the details may be modified based on different views and applications without departing from the spirit of the invention.

Claims (19)

1. A method for fabricating a nanocrystal memory element, the method comprising the steps of:
forming a tunnel oxide layer on a substrate;
depositing conductive layers and dielectric layers on the tunnel oxide layer repeatedly and alternately;
forming a plurality of nanocrystals in the conductive layers, forming an integration layer by combining the conductive layers and the dielectric layers, wherein the nanocrystals which are formed in the same conductive layer are located at a same level and collectively form a nanocrystal group, such that all the nanocrystals in the nanocrystal group are located at the same level; and
forming a gate on the integration layer.
2. The method for fabricating a nanocrystal memory element of claim 1, wherein the steps of depositing the conductive layers and the dielectric layers repeatedly and alternately are performed by means of atomic layer deposition.
3. The method for fabricating a nanocrystal memory element of claim 1, wherein the steps of depositing the conductive layers and the dielectric layers repeatedly and alternately are performed by means of molecular beam epitaxy.
4. The method for fabricating a nanocrystal memory element of claim 1, wherein the steps of depositing the conductive layers and the dielectric layers repeatedly and alternately are performed by means of chemical vapor deposition.
5. The method for fabricating a nanocrystal memory element of claim 1, wherein the steps of depositing the conductive layers and the dielectric layers repeatedly and alternately are performed by means of physical vapor deposition.
6. The method for fabricating a nanocrystal memory element of claim 1, wherein the steps of forming a plurality of nanocrystals in the conductive layers are performed by means of thermal oxidation.
7. The method for fabricating a nanocrystal memory element of claim 6, wherein the thermal oxidation is rapid thermal annealing.
8. The method for fabricating a nanocrystal memory element of claim 1, wherein the dielectric layers are made of a dielectric material.
9. The method for fabricating a nanocrystal memory element of claim 8, wherein the dielectric material is made of silicon oxides.
10. The method for fabricating a nanocrystal memory element of claim 1, wherein any two neighboring upper-lower conductive layers are separated by a dielectric layer interposed therebetween.
11. The method for fabricating a nanocrystal memory element of claim 1, wherein the conductive layers are made of metals.
12. The method for fabricating a nanocrystal memory element of claim 1, wherein the conductive layers are made of metallic compounds.
13. The method for fabricating a nanocrystal memory element of claim 1, wherein the conductive layers are made of doped suicides.
14. A nanocrystal memory element, comprising:
a substrate;
a tunnel oxide layer formed on the substrate;
an integration layer formed on the tunnel oxide layer, wherein a plurality of nanocrystals are disposed in the integration layer such that a nanocrystal always belongs to a nanocrystal group formed by the nanocrystals located at a same level, any two neighboring upper-lower nanocrystal groups are separated by a dielectric material forming the integration layer; and
forming a gate on the integration layer.
15. The nanocrystal memory element of claim 14, wherein distances between the tunnel oxide layer and the nanocrystals in the same nanocrystal group are equal, such that the nanocrystals are disposed at the same level in the integration layer.
16. The nanocrystal memory element of claim 14, wherein the dielectric material of the tunnel oxide layer and the integration layer is made of silicon oxides.
17. A nanocrystal memory, comprising:
a substrate;
a source and a drain both formed on the substrate and spaced apart by an appropriate distance;
a tunnel oxide layer formed on the substrate;
an integration layer formed on the tunnel oxide layer, wherein a plurality of nanocrystals are disposed in the integration layer such that a nanocrystal always belongs to a nanocrystal group formed by the nanocrystals located at a same level, any two neighboring upper-lower nanocrystal groups are separated by a dielectric material forming the integration layer; and
a gate formed on the integration layer.
18. The nanocrystal memory of claim 17, wherein distances between the tunnel oxide layer and the nanocrystals in the same nanocrystal group are equal, such that the nanocrystals are disposed at the same level in the integration layer.
19. The nanocrystal memory of claim 17, wherein the dielectric material of the tunnel oxide layer and the integration layer is made of silicon oxides.
US11/495,528 2005-11-07 2006-07-31 Nanocrystal memory element, method for fabricating the same and memory having the memory element Abandoned US20070105316A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW094138938 2005-11-07
TW094138938A TWI289336B (en) 2005-11-07 2005-11-07 Nanocrystal memory component, manufacturing method thereof and memory comprising the same

Publications (1)

Publication Number Publication Date
US20070105316A1 true US20070105316A1 (en) 2007-05-10

Family

ID=38004297

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/495,528 Abandoned US20070105316A1 (en) 2005-11-07 2006-07-31 Nanocrystal memory element, method for fabricating the same and memory having the memory element

Country Status (2)

Country Link
US (1) US20070105316A1 (en)
TW (1) TWI289336B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070128796A1 (en) * 2005-12-05 2007-06-07 Chih-Hsun Chu Method for manufacturing non-volatile memory
US20080211039A1 (en) * 2006-12-07 2008-09-04 Samsung Electronics Co., Ltd. Nonvolatile memory devices having metal silicide nanocrystals, methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices having metal silicide nanocrystals
US20090155967A1 (en) * 2007-12-18 2009-06-18 Vinod Robert Purayath Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US20110020992A1 (en) * 2009-07-21 2011-01-27 Vinod Robert Purayath Integrated Nanostructure-Based Non-Volatile Memory Fabrication
US8193055B1 (en) 2007-12-18 2012-06-05 Sandisk Technologies Inc. Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010030340A1 (en) * 1998-11-04 2001-10-18 Ichiro Fujiwara Nonvolatile semiconductor memory device and process of production and write method thereof
US6333214B1 (en) * 1998-06-29 2001-12-25 Hynix Semiconductor Inc. Memory of multilevel quantum dot structure and method for fabricating the same
US6487121B1 (en) * 2000-08-25 2002-11-26 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a vertical electric field
US6649542B2 (en) * 1997-04-25 2003-11-18 Nippon Steel Corporation Multi-level type nonvolatile semiconductor memory device
US6690059B1 (en) * 2002-08-22 2004-02-10 Atmel Corporation Nanocrystal electron device
US20040248381A1 (en) * 2000-11-01 2004-12-09 Myrick James J. Nanoelectronic interconnection and addressing
US6995433B1 (en) * 2004-03-02 2006-02-07 Advanced Micro Devices, Inc. Microdevice having non-linear structural component and method of fabrication
US20060166435A1 (en) * 2005-01-21 2006-07-27 Teo Lee W Synthesis of GE nanocrystal memory cell and using a block layer to control oxidation kinetics
US7166509B2 (en) * 2002-06-21 2007-01-23 Micron Technology, Inc. Write once read only memory with large work function floating gates
US7309650B1 (en) * 2005-02-24 2007-12-18 Spansion Llc Memory device having a nanocrystal charge storage region and method
US7355238B2 (en) * 2004-12-06 2008-04-08 Asahi Glass Company, Limited Nonvolatile semiconductor memory device having nanoparticles for charge retention
US7361567B2 (en) * 2005-01-26 2008-04-22 Freescale Semiconductor, Inc. Non-volatile nanocrystal memory and method therefor

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649542B2 (en) * 1997-04-25 2003-11-18 Nippon Steel Corporation Multi-level type nonvolatile semiconductor memory device
US6333214B1 (en) * 1998-06-29 2001-12-25 Hynix Semiconductor Inc. Memory of multilevel quantum dot structure and method for fabricating the same
US20010030340A1 (en) * 1998-11-04 2001-10-18 Ichiro Fujiwara Nonvolatile semiconductor memory device and process of production and write method thereof
US6487121B1 (en) * 2000-08-25 2002-11-26 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a vertical electric field
US20040248381A1 (en) * 2000-11-01 2004-12-09 Myrick James J. Nanoelectronic interconnection and addressing
US7166509B2 (en) * 2002-06-21 2007-01-23 Micron Technology, Inc. Write once read only memory with large work function floating gates
US6690059B1 (en) * 2002-08-22 2004-02-10 Atmel Corporation Nanocrystal electron device
US6995433B1 (en) * 2004-03-02 2006-02-07 Advanced Micro Devices, Inc. Microdevice having non-linear structural component and method of fabrication
US7355238B2 (en) * 2004-12-06 2008-04-08 Asahi Glass Company, Limited Nonvolatile semiconductor memory device having nanoparticles for charge retention
US20060166435A1 (en) * 2005-01-21 2006-07-27 Teo Lee W Synthesis of GE nanocrystal memory cell and using a block layer to control oxidation kinetics
US7361567B2 (en) * 2005-01-26 2008-04-22 Freescale Semiconductor, Inc. Non-volatile nanocrystal memory and method therefor
US7309650B1 (en) * 2005-02-24 2007-12-18 Spansion Llc Memory device having a nanocrystal charge storage region and method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070128796A1 (en) * 2005-12-05 2007-06-07 Chih-Hsun Chu Method for manufacturing non-volatile memory
US20080211039A1 (en) * 2006-12-07 2008-09-04 Samsung Electronics Co., Ltd. Nonvolatile memory devices having metal silicide nanocrystals, methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices having metal silicide nanocrystals
US20090155967A1 (en) * 2007-12-18 2009-06-18 Vinod Robert Purayath Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US7723186B2 (en) 2007-12-18 2010-05-25 Sandisk Corporation Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US20100190319A1 (en) * 2007-12-18 2010-07-29 Vinod Robert Purayath Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US8193055B1 (en) 2007-12-18 2012-06-05 Sandisk Technologies Inc. Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution
US8263465B2 (en) 2007-12-18 2012-09-11 Sandisk Technologies Inc. Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US20110020992A1 (en) * 2009-07-21 2011-01-27 Vinod Robert Purayath Integrated Nanostructure-Based Non-Volatile Memory Fabrication
US8383479B2 (en) 2009-07-21 2013-02-26 Sandisk Technologies Inc. Integrated nanostructure-based non-volatile memory fabrication
US8946022B2 (en) 2009-07-21 2015-02-03 Sandisk Technologies Inc. Integrated nanostructure-based non-volatile memory fabrication

Also Published As

Publication number Publication date
TW200719409A (en) 2007-05-16
TWI289336B (en) 2007-11-01

Similar Documents

Publication Publication Date Title
JP4927550B2 (en) Nonvolatile memory device, method of manufacturing nonvolatile memory device, and nonvolatile memory array
US6444545B1 (en) Device structure for storing charge and method therefore
US7393745B2 (en) Method for fabricating self-aligned double layered silicon-metal nanocrystal memory element
US7579646B2 (en) Flash memory with deep quantum well and high-K dielectric
TWI609480B (en) Non-volatile semiconductor memory and non-volatile semiconductor memory manufacturing method
EP0649178A2 (en) Flash EEPROM cell having gap between floating gate and drain for high hot electron injection efficiency for programming
KR100843229B1 (en) Flash memory device including hybrid structure of charge trap layer and method of manufacturing the same
KR20030094497A (en) Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell
CN101221987B (en) Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure
US6960794B2 (en) Formation of thin channels for TFT devices to ensure low variability of threshold voltages
US20090096014A1 (en) Nonvolatile memory devices that include an insulating film with nanocrystals embedded therein and methods of manufacturing the same
JP2009094170A (en) Nonvolatile semiconductor memory and method of manufacturing the same
CN103824860A (en) Method for manufacturing memory cell, method for manufacturing memory cell arrangement, and memory cell
CN101783350A (en) Flash memory device and manufacturing method the same
US20070105316A1 (en) Nanocrystal memory element, method for fabricating the same and memory having the memory element
JP2641844B2 (en) EEPROM flash memory cell, memory device, and manufacturing method thereof
US20060027854A1 (en) Non-volatile memory device and method of fabricating the same
US20140209995A1 (en) Non-Volatile Memory Cells Having Carbon Impurities and Related Manufacturing Methods
JP2007513519A (en) Flash memory device
US7098505B1 (en) Memory device with multiple memory layers of local charge storage
KR101188551B1 (en) Flash memory device and method for manufacturing Flash memory device
US20070114572A1 (en) Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same
US6249021B1 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
US20100044775A1 (en) Semiconductor memory device and semiconductor device
WO2001017031A1 (en) Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same

Legal Events

Date Code Title Description
AS Assignment

Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JENG, PEI-REN;REEL/FRAME:018140/0798

Effective date: 20060515

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION