US20060157738A1 - Semiconductor memory device and its manufacturing method - Google Patents
Semiconductor memory device and its manufacturing method Download PDFInfo
- Publication number
- US20060157738A1 US20060157738A1 US11/369,041 US36904106A US2006157738A1 US 20060157738 A1 US20060157738 A1 US 20060157738A1 US 36904106 A US36904106 A US 36904106A US 2006157738 A1 US2006157738 A1 US 2006157738A1
- Authority
- US
- United States
- Prior art keywords
- forming
- active layer
- transistors
- silicon active
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 6
- 239000007924 injection Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000007772 electrode material Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 230000003213 activating effect Effects 0.000 claims abstract description 3
- -1 oxygen ions Chemical class 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 abstract description 4
- 210000004027 cell Anatomy 0.000 description 44
- 210000000746 body region Anatomy 0.000 description 25
- 239000003990 capacitor Substances 0.000 description 9
- 239000012535 impurity Substances 0.000 description 9
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000010354 integration Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000036961 partial effect Effects 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Definitions
- This invention relates to a semiconductor memory device, and more particularly, to a MIS-type semiconductor memory device using a SOI (silicon on insulator) element formed on an insulating film.
- SOI silicon on insulator
- Density of integration and resultant increase of the memory capacity are important factors for improving the performance of memory LSI using MIS (Metal-Insulator-Semiconductor) type semiconductor elements. Improvement of density of integration has conventionally relied on reducing the size of elements.
- SRAM Static Random Access Memory
- DRAM Dynamic Random Access Memory
- memory LSI memory LSI
- one storage cell is made up of a combination of one capacitor for holding an electric charge and one transistor for controlling injection and emission of the electric charge. Therefore, DRAM eliminates the use of transistors in cross connection, which are required in SRAM, thereby can reduce the memory size, and is suitable for enhancing the integration. Actually, therefore, DRAM has moved on toward higher and higher integration.
- a memory cell employing a SOI (Silicon On Insulator) structure in which an element is formed on an insulating film is known as one of such proposals.
- This memory cell uses a partial depletion type SOI element and is based on the principle of having an electric charge accumulated in or exhaled from the floating body region of the element in response to the stored data to vary the threshold voltage of the element such that, upon reading, data is distinguished by detection of the threshold value.
- FIG. 13 shows a basic circuit diagram of a memory cell using such a SOI element.
- the gate of a partial depletion type transistor Tr is connected to a word line WL, one of the source and the drain to a bit line BL, and the other to Vss.
- nMOSFET n-channel MOSFET
- the word line WL as the gate electrode is set in a high potential (HIGH) state, such as Vcc, and the bit line BL in a HIGH state, also such as Vcc. Then, when a channel current flows, impact ionization occurs, and holes are accumulated in the body region. Additionally, since the diffusion layer connected to the bit line and the pn junction located in the body region are reverse-biased, a leak current in the reverse direction is generated, and this results in increasing the potential of the body region and decreasing the threshold voltage of the element. This status is determined as writing of data “1”, for example.
- the word line is set in a HIGH state, such as Vcc
- the bit line is set in a low potential (LOW) state, such as ⁇ Vcc
- LOW low potential
- the diffusion layer connected to the bit line and the pn junction located in the body region are forward-biased. Therefore, holes in the body region flow toward the bit line, and the hole concentration in the body region decreases. As a result, potential of the body region lowers, and the threshold voltage of the element rises. This status is determined as writing of data “0”.
- This method makes it possible to make up a single memory cell using only one transistor without using a capacitor that has been cumbersome because of the area it occupied, and makes it possible to accomplish higher integration, simplification of the manufacturing process, reduction of the cost, and so forth.
- a semiconductor memory device comprising:
- a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each said memory cell being connected to a bit line and the other side of each said memory cell being supplied with a reference potential.
- a semiconductor memory device comprising:
- a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each said memory cell being connected to a bit line and the other side of each said memory cell being supplied with a reference potential,
- the threshold value is controlled by controlling injection or discharge of an electric charge to or from a body region of one of said transistors of a selected memory cell, thereby to store data.
- a semiconductor memory device manufacturing method comprising:
- gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it;
- FIG. 1 is a schematic diagram illustrating the basic concept of an embodiment of the memory cell used in a semiconductor memory device according to the invention
- FIG. 2 is a rough connection diagram that shows an aspect of memory cell array made by using a plurality of memory cells shown in FIG. 1 ;
- FIG. 3 is a rough connection diagram that shows an aspect of memory cell array made by using a plurality of memory cells shown in FIG. 1 ;
- FIG. 4 is a timing chart that shows operations upon writing data “1” in a selected memory cell
- FIG. 5 is a timing chart that shows operations upon writing data “0” in a selected memory cell
- FIG. 6 is a graph that shows how the drain current changes with the content of stored data when data is read out
- FIG. 7 is a timing chart that shows waveforms upon read-out operations when data “1” is written
- FIG. 8 is a timing chart that shows waveforms upon read-out operations when data “0” is written
- FIGS. 9A through 9D are cross-sectional views of different steps of an embodiment of the manufacturing method according to the invention for manufacturing the semiconductor memory device shown in FIG. 1 ;
- FIG. 10 is a plan view of an element made by the steps of FIGS. 9A through 9D ;
- FIGS. 11A through 11F are cross-sectional views of an element under different steps for explaining another embodiment of the manufacturing method of a semiconductor memory device according to the invention.
- FIG. 12 is a plan view of the element made by the steps of FIGS. 11A through 11D ;
- FIG. 13 is a circuit diagram that shows the basic configuration of a memory cell using a conventional SOI element.
- FIG. 1 is a schematic diagram that shows the basis concept of a memory cell 10 used in an embodiment of the semiconductor memory device according to the invention.
- the memory cell is made up by serially connecting a transistor Tr 1 and a transistor Tr 2 that are two n-channel partially-depeleted MOSFETs (nMOS) formed in a semiconductor layer on an insulating film (SOI), connecting one of diffusion layers of the transistor Tr 1 to a bit line BL, connecting the other diffusion layer of the transistor Tr 1 to one of diffusion layers of the transistor Tr 2 , and connecting the other diffusion layer of the transistor Tr 2 to the power source Vss illustrated as a ground connection.
- the connection node between the other side of the transistor Tr 1 and one side of the transistor Tr 2 is floating, and let this node called as node f.
- first word line WL that is a selection signal line of the memory cell
- second word line /WL that is a selection signal line of the inverse logic from the first word line
- FIG. 1 An aspect of memory cell array made by using a plurality of memory cells 10 shown in FIG. 1 is shown in rough connection diagrams of FIGS. 2 and 3 .
- memory cells 10 shown in FIG. 1 are arranged in a matrix, and word lines WL and word lines /WL are alternately arranged to extend vertically and connected to gate electrodes of respective memory cells 10 , whereas bit lines BL and grounded source potentials Vss are alternately arranged to extend horizontally between memory cells 10 and connected to terminals of the memory cells.
- memory cells 10 belonging to adjacent columns have a positional relation making a specular relation one another.
- FIG. 3 is the same as FIG. 2 in arrangement, etc. of the memory cells 10 ; however, a word line WL and a word line /WL make a pair, and a complementary relation is established by supplying a word line /WL with a signal level made by inverting the signal level of the counterpart word line WL by an inverter INV.
- the first word line becomes the LOW potential; the transistor Tr 1 becomes OFF; the second word line becomes the HIGH potential; and the transistor Tr 2 is ON. Therefore, the potential Vss appears at the node f common to the transistor Tr 1 and the transistor Tr 2 .
- FIG. 4 is a timing chart that shows operations upon writing data “1” in a selected memory cell 10 .
- the first word line WL is changed from Vss to Vcc, and the second word line /WL is simultaneously changed from Vcc to Vss.
- the transistor Tr 1 becomes ON and the transistor Tr 2 becomes OFF.
- capacitive coupling between the word line and the body region of the transistor Tr 1 raises the body potential Vbody 1 of the transistor Tr 1 .
- the bit lien BL is changed from Vss to Vcc.
- capacitive coupling of the pn junction between the diffusion layer in connection with the bit line and the body region raises the body potential of the transistor Tr 1 .
- this technique is a normal technique to pre-charge the bit line BL to an arbitrary potential. Also in this embodiment, this technique is applicable.
- This pre-charge potential is not limited, and any desired potential may be employed provided it does not adversely affects the operations.
- a channel current flows in the transistor Tr 1 . In response to the channel current, impact ionization occurs, holes flow into the body region, and the body potential gradually rises.
- the diffusion region connected to the bit line BL and the pn junction located in the body region are reverse biased, and a resultant flow of a leak current in the reverse direction causes more holes to flow into the body region.
- potential of the node f asymptotically approaches and reaches Vcc, and that Vcc is maintained thereafter.
- bit line BL changes before a change of the potential of the first and second word lines, a similar channel current flows in the transistor Tr 1 , similar impact ionization occurs, and the body potential of the transistor Tr 1 rises.
- the bit line is changed from Vcc to, for example, Vss.
- capacitive coupling of the pn junction lowers the body potential for a moment, but since the channel current flows in the transistor Tr 1 and impact ionization occurs responsively, holes flow into the body region, and the body potential of the transistor Tr 1 is still maintained.
- the potential of the node f asymptotically approaches Vss.
- Changes in potential of the first and second word lines may precede potential changes of the bit line BL. In this case, however, impact ionization does not occur. Therefore, the bit line is preferably changed earlier, as explained above.
- FIG. 5 is a timing chart that shows operation timings upon writing data “0” in a selected memory cell 10 .
- the first word line WL is changed from Vss to Vcc, and the second word line /WL is simultaneously changed from Vcc to Vss.
- the transistor Tr 1 becomes ON and the transistor Tr 2 becomes OFF.
- capacitive coupling of the first word line and the body region of the transistor Tr 1 raises the body potential Vbody 1 of the transistor Tr 1 .
- the bit line BL is changed from Vss to the pre-charge potential ⁇ Vcc.
- the pre-charge potential may be any desired potential, and also in this embodiment, a different potential may be used.
- the body region of the transistor Tr 1 and the pn junction between the diffusion layer in connection with the bit line BL and the node f are biased in the forward direction. Therefore, holes in the body region are exhaled, and the body potential Vbody 1 of the transistor Tr 1 further lowers. Simultaneously, potential f the node f asymptotically approaches ⁇ Vcc.
- the transistor Tr 2 is OFF the node f is floating, almost no channel current flows in the transistor Tr 1 accordingly, holes in he body region are effectively drawn out, and the LOW potential can be written stably.
- potential change of the bit line BL may precede to potential changes of the word line WL and the word line /WL.
- the pn junction with the body region is biased forwardly, so the potential of the body can be instantaneously changed to about ⁇ 0.5V.
- the margin for writing data “0” is improved.
- a difference between current values based on a difference between element threshold voltages of the transistor Tr 1 due to stored data is detected by using, for example, a current-sensing type sense-amplifier.
- FIG. 6 is a graph that shows how the drain current changes with the content of stored data when the data is read out.
- the gate voltage Vg is taken on the abscissa, and the logarithm of the drain current is taken on the ordinate.
- the gate voltage necessary for a certain drain current is higher in a transistor Tr 1 written with data “0” than in a transistor Tr 1 written with data “1”. Therefore, the threshold value of a transistor Tr 1 with data “1” lowers whereas the threshold voltage of a transistor Tr 1 with “0” rises.
- a potential corresponding to one half the normal source potential, such as Vcc/2, is used as the gate potential, that is, the word line potential, for judgment.
- FIG. 7 is a timing chart that shows read-out operation waveforms in case of data “1” being written in the transistor Tr 1 .
- bit line is pre-charged to Vcc/2 in the non-selection period, and a memory cell selected at time t 21 where read-out operation is started.
- bit line potential BL rises due to an increase of the current flowing into the bit line in response to the rise of the body potential Vbody 1 of the transistor Tr 1 .
- FIG. 8 is a timing chart that shows read-operation waveforms in case of data “0” being written in the transistor Tr 1 .
- the bit line is pre-charged to Vcc/2, and the word lines WL and /WL are set in Vcc/2” at the read-out start time t 31 .
- Vbody 1 since the body potential Vbody 1 of the transistor Tr 1 is currently low, Vbody 1 maintains the minus value even after time t 31 . Therefore, the current flowing into the bit line is smaller than that of FIG. 7 , and the bit line potential BL does not change. By detecting it, the data can be judged to be “0”.
- each memory cell is made by serially connecting two transistors, thereby to bring out the advantage of enabling higher integration by eliminating capacitors and to enable stable write of data.
- nMOS p-channel MOS transistors
- CMOS configuration in which two transistors are opposite in conduction type from each other. This configuration will be explained later.
- FIGS. 9A through 9D are cross-sectional views of such an element under different manufacturing steps, that show an embodiment of the manufacturing method of the semiconductor memory device shown in FIG. 1 .
- First made is a SOI structure having a SOI active layer 13 formed on a semiconductor substrate 11 via a buried oxide (BOX) film 12 such as a silicon oxide film by using an appropriate method, such as SIMOX (separation by implantation of oxygen) technique that obtains an oxide layer and a silicon layer thereon by ion implantation of oxygen ions into a silicon semiconductor substrate and subsequent annealing, or bonding technique that bonds a silicon plate having an oxide film at the bottom to a surface of a silicon semiconductor substrate.
- the SOI active layer is thereafter thinned to a desired thickness about 150 nm, for example, by thermal oxidation and etching by NH 4 F, for example.
- element isolation regions 14 are formed by, for example, STI (shallow trench isolation) technique that buries shallow trenches with an insulating film.
- impurities are introduced into the SOI active layer 13 in the element-forming regions by the dose of 1.5 ⁇ 10 ⁇ 12 cm ⁇ 2 by, for example, ion implantation.
- an insulating film 15 which will become a gate insulating film, is formed on the SOI active layer 13 by thermal oxidation, for example. Further stacked thereon is polycrystalline silicon 16 of the thickness of 200 nm by CVD (chemical vapor deposition).
- the polycrystalline silicon 16 is patterned by selectively removing it from above the source and drain regions by etching, such as reactive ion etching (RIE), thereby to obtain gate electrodes 17 .
- etching such as reactive ion etching (RIE)
- impurities are introduced into regions for forming diffusion layers in by ion implantation, for example.
- the impurities introduced by ion implantation are activated in a heat process using annealing such as RTA (rapid thermal annealing).
- a layer insulating film 18 is stacked; contact holes are formed at given positions; an electrode wiring material like aluminum is formed to bury the contact holes and lie on the layer insulating film 18 ; and it is patterned to form the first word line (WL) electrode wiring 19 , second word line (/WL) electrode wiring 20 , bit line electrode wiring 21 and Vss electrode wiring 22 , thereby to complete the desired partially-depleted SOI semiconductor device.
- the wirings may be multi-layered according to the specification required.
- FIG. 10 is a plan view of an element made through those steps, in which the same components as those shown in FIG. 9D are labeled with common reference numerals.
- FIGS. 11A thorough 11 E are cross-sectional views of different steps of a further embodiment of the semiconductor memory device manufacturing method according to the invention, and they show an example using a CMOS type memory cell 50 .
- First made is a SOI structure having a SOI active layer 53 formed on a semiconductor substrate 51 via a buried oxide (BOX) film 52 such as a silicon oxide film by using an appropriate method, such as SIMOX (separation by implantation of oxygen) technique or bonding technique.
- the SOI active layer 53 is thereafter thinned to a desired thickness about 150 nm, for example, by thermal oxidation and etching by NH 4 F, for example.
- trench-shaped element isolation regions 54 are formed by, for example STI (shallow trench isolation) technique.
- FIG. 11B shows the configuration as introducing impurities into regions for forming pMOS in.
- impurities boron ions are introduced by the dose of, for example, 1.5 ⁇ 10 13 cm ⁇ 2 .
- a similar step of injecting ions is conducted for the regions for forming nMOS in as well, and phosphorus ions are introduced as impurities by the dose of 1.5 ⁇ 10 13 cm ⁇ 2.
- a gate insulating film 56 is formed on the SOI active layer 53 by, for example, thermal oxidation. Further stacked thereon is polycrystalline silicon 57 of the thickness of 200 nm by CVD (chemical vapor deposition).
- the polycrystalline silicon 57 is patterned by selectively removing it from above the source and drain regions by, for example, reactive ion etching (RIE), thereby to obtain gate electrodes 58 .
- RIE reactive ion etching
- impurities are introduced into regions for forming diffusion layers in by ion implantation, for example.
- ions introduced are different between pMOS and nMOS
- the nMOS regions are masked by a resist 59
- boon ions for example, are injected by the dose of 3 ⁇ 10 15 cm ⁇ 2 .
- pMOS regions are masked by a resist, and phosphorus ions, for example, are injected by the dose of 3 ⁇ 10 15 cm ⁇ 2 .
- the impurities introduced by ion implantation are activated in a heat process using annealing such as RTA (rapid thermal annealing).
- a silicide 60 such as CoSi 2 is formed on the source regions, drain regions and gate electrode regions through a salicide step for self-aligned deposition.
- a layer insulating film 61 is stacked; contact holes 62 are formed at given positions; and an electrode wiring material 63 like aluminum is deposited by vapor deposition to bury the contact holes 62 and lie on the layer insulating film 60 .
- the electrode wiring material on the layer insulating film 60 is patterned to form the fist word line (WL) electrode wiring 64 , second word line (/WL) electrode wiring (not shown), electrode wiring 65 for the bit line BL, and Vss electrode wiring 66 , thereby to complete the desired partially-depleted SOI semiconductor device.
- nMOS diffusion layers are connected to bit lines
- pMOS diffusion layers are connected to Vss source lines.
- FIG. 12 shows a plan view of a memory cell 50 formed through those steps. This is a CMOS memory cell, so the same gate electrode 64 can be commonly shared by nMOS and pMOS without the need of electrically separating the second word line from the first word line.
- a DRAM element made up solely of MIS elements and eliminating capacitors can be manufactured easily.
- the invention is not limited in process of forming elements and in parameter of the device to those shown in the embodiments, but can be brought into practice in appropriately modified forms.
- the embodiments have been explained as using single layered wirings, they can be modified to multi-layered wirings according to the specification required. In this case, for making one or more upper layers, the steps of forming the layer insulating film, forming contact holes, vapor deposition of the electrode material and patterning thereof will be repeated.
- nMOSFET complementary metal-oxide-semiconductor
- CMOSFET complementary metal-oxide-semiconductor
- SOI semiconductor-oxide-semiconductor
- the invention is not limited to it, but can use other types of substrate such as pMOSFET, SOS (silicon on sapphire), and so forth.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask; forming said paired transistors by activating the injected ions through a heat process; and forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.
Description
- This application is based upon and claims the benefit of priority under 35 USC §119 to the prior Japanese Patent Application No. 2001-381458 filed on Dec. 14, 2001; the entire contents of which are incorporated herein by reference.
- This invention relates to a semiconductor memory device, and more particularly, to a MIS-type semiconductor memory device using a SOI (silicon on insulator) element formed on an insulating film.
- Density of integration and resultant increase of the memory capacity are important factors for improving the performance of memory LSI using MIS (Metal-Insulator-Semiconductor) type semiconductor elements. Improvement of density of integration has conventionally relied on reducing the size of elements.
- SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are well known as memory LSI. In DRAM, one storage cell is made up of a combination of one capacitor for holding an electric charge and one transistor for controlling injection and emission of the electric charge. Therefore, DRAM eliminates the use of transistors in cross connection, which are required in SRAM, thereby can reduce the memory size, and is suitable for enhancing the integration. Actually, therefore, DRAM has moved on toward higher and higher integration.
- However, since miniaturization of capacitors was more difficult than miniaturization of transistors, as the integration of LSI progressed, the area occupied by capacitors, which needed a relatively large area, relatively increased, and this have made it difficult to form capacitors ensuring reliable operation. Beside this, because DRAM needs the process of producing capacitors as an additional process, it has complicated the manufacturing process and has caused a longer period of time for the manufacture, higher cost and lower ratio of non-defective products (production yield).
- For the purpose of overcoming those problems attendant to the presence of capacitors, various proposals have been presented. A memory cell employing a SOI (Silicon On Insulator) structure in which an element is formed on an insulating film is known as one of such proposals. This memory cell uses a partial depletion type SOI element and is based on the principle of having an electric charge accumulated in or exhaled from the floating body region of the element in response to the stored data to vary the threshold voltage of the element such that, upon reading, data is distinguished by detection of the threshold value.
-
FIG. 13 shows a basic circuit diagram of a memory cell using such a SOI element. The gate of a partial depletion type transistor Tr is connected to a word line WL, one of the source and the drain to a bit line BL, and the other to Vss. - Behaviors of the memory cell will be explained below. Here is taken an example using an n-channel MOSFET (nMOSFET).
- When data is written in the body region in a floating condition, the word line WL as the gate electrode is set in a high potential (HIGH) state, such as Vcc, and the bit line BL in a HIGH state, also such as Vcc. Then, when a channel current flows, impact ionization occurs, and holes are accumulated in the body region. Additionally, since the diffusion layer connected to the bit line and the pn junction located in the body region are reverse-biased, a leak current in the reverse direction is generated, and this results in increasing the potential of the body region and decreasing the threshold voltage of the element. This status is determined as writing of data “1”, for example.
- On the other hand, when the word line is set in a HIGH state, such as Vcc, and the bit line is set in a low potential (LOW) state, such as −Vcc, for example, the diffusion layer connected to the bit line and the pn junction located in the body region are forward-biased. Therefore, holes in the body region flow toward the bit line, and the hole concentration in the body region decreases. As a result, potential of the body region lowers, and the threshold voltage of the element rises. This status is determined as writing of data “0”.
- In this manner, it is possible to let the partially depleted transistor change in threshold value in response to the stored data.
- This method makes it possible to make up a single memory cell using only one transistor without using a capacitor that has been cumbersome because of the area it occupied, and makes it possible to accomplish higher integration, simplification of the manufacturing process, reduction of the cost, and so forth.
- Such configuration, however, invited undesirable flow of a channel current also upon application of −Vcc to a bit line for the purpose of writing data “0”, which made it difficult to efficiently draw out holes of the body region, and therefore involved the problem of taking much time for writing data “0” or rendering the writing unstable.
- According to one embodiment of the present invention, there is provided a semiconductor memory device comprising:
- a semiconductor layer formed on an insulating film; and
- a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each said memory cell being connected to a bit line and the other side of each said memory cell being supplied with a reference potential.
- According to another embodiment of the present invention, there is provided a semiconductor memory device comprising:
- a semiconductor layer formed on an insulating film; and
- a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each said memory cell being connected to a bit line and the other side of each said memory cell being supplied with a reference potential,
- wherein the threshold value is controlled by controlling injection or discharge of an electric charge to or from a body region of one of said transistors of a selected memory cell, thereby to store data.
- Also, according to further embodiment of the present invention, there is provided a semiconductor memory device manufacturing method comprising:
- forming an oxide layer and a silicon active layer on a semiconductor substrate;
- forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer;
- forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it;
- injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask;
- forming said paired transistors by activating the injected ions through a heat process; and
- forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.
- In the accompanying drawings,
-
FIG. 1 is a schematic diagram illustrating the basic concept of an embodiment of the memory cell used in a semiconductor memory device according to the invention; -
FIG. 2 is a rough connection diagram that shows an aspect of memory cell array made by using a plurality of memory cells shown inFIG. 1 ; -
FIG. 3 is a rough connection diagram that shows an aspect of memory cell array made by using a plurality of memory cells shown inFIG. 1 ; -
FIG. 4 is a timing chart that shows operations upon writing data “1” in a selected memory cell; -
FIG. 5 is a timing chart that shows operations upon writing data “0” in a selected memory cell; -
FIG. 6 is a graph that shows how the drain current changes with the content of stored data when data is read out; -
FIG. 7 is a timing chart that shows waveforms upon read-out operations when data “1” is written; -
FIG. 8 is a timing chart that shows waveforms upon read-out operations when data “0” is written; -
FIGS. 9A through 9D are cross-sectional views of different steps of an embodiment of the manufacturing method according to the invention for manufacturing the semiconductor memory device shown inFIG. 1 ; -
FIG. 10 is a plan view of an element made by the steps ofFIGS. 9A through 9D ; -
FIGS. 11A through 11F are cross-sectional views of an element under different steps for explaining another embodiment of the manufacturing method of a semiconductor memory device according to the invention; -
FIG. 12 is a plan view of the element made by the steps ofFIGS. 11A through 11D ; and -
FIG. 13 is a circuit diagram that shows the basic configuration of a memory cell using a conventional SOI element. - Embodiments of the invention will now be explained in detail with reference to the drawings.
-
FIG. 1 is a schematic diagram that shows the basis concept of amemory cell 10 used in an embodiment of the semiconductor memory device according to the invention. - Referring to
FIG. 1 , the memory cell is made up by serially connecting a transistor Tr1 and a transistor Tr2 that are two n-channel partially-depeleted MOSFETs (nMOS) formed in a semiconductor layer on an insulating film (SOI), connecting one of diffusion layers of the transistor Tr1 to a bit line BL, connecting the other diffusion layer of the transistor Tr1 to one of diffusion layers of the transistor Tr2, and connecting the other diffusion layer of the transistor Tr2 to the power source Vss illustrated as a ground connection. The connection node between the other side of the transistor Tr1 and one side of the transistor Tr2 is floating, and let this node called as node f. - Connected to the gate of the transistor Tr1 is a first word line WL that is a selection signal line of the memory cell, and connected to the gate of the transistor Tr2 is a second word line /WL that is a selection signal line of the inverse logic from the first word line.
- An aspect of memory cell array made by using a plurality of
memory cells 10 shown inFIG. 1 is shown in rough connection diagrams ofFIGS. 2 and 3 . - In
FIG. 2 ,memory cells 10 shown inFIG. 1 are arranged in a matrix, and word lines WL and word lines /WL are alternately arranged to extend vertically and connected to gate electrodes ofrespective memory cells 10, whereas bit lines BL and grounded source potentials Vss are alternately arranged to extend horizontally betweenmemory cells 10 and connected to terminals of the memory cells. In this arrangement,memory cells 10 belonging to adjacent columns have a positional relation making a specular relation one another. By enabling individual word lines WL and /WL to be selected absolutely independently, each column of memory cells can be selected easily. -
FIG. 3 is the same asFIG. 2 in arrangement, etc. of thememory cells 10; however, a word line WL and a word line /WL make a pair, and a complementary relation is established by supplying a word line /WL with a signal level made by inverting the signal level of the counterpart word line WL by an inverter INV. - Behaviors of the memory cell using the partial depletion type SOI will be next explained below in detail. Here is shown an embodiment of operations in case a
singe memory cell 10 is made by using two nMOSs as shown inFIG. 1 , and it is explained as the low potential (LOW) level of bit lines and word lines being Vss, for example, and the high potential (HIGH) level being Vcc, for example. - In case the memory cell is not selected, the first word line becomes the LOW potential; the transistor Tr1 becomes OFF; the second word line becomes the HIGH potential; and the transistor Tr2 is ON. Therefore, the potential Vss appears at the node f common to the transistor Tr1 and the transistor Tr2.
-
FIG. 4 is a timing chart that shows operations upon writing data “1” in a selectedmemory cell 10. At time t1, the first word line WL is changed from Vss to Vcc, and the second word line /WL is simultaneously changed from Vcc to Vss. As a result, the transistor Tr1 becomes ON and the transistor Tr2 becomes OFF. At that time, capacitive coupling between the word line and the body region of the transistor Tr1 raises the body potential Vbody1 of the transistor Tr1. - At time t2 slightly later than time t1, the bit lien BL is changed from Vss to Vcc. At that time, capacitive coupling of the pn junction between the diffusion layer in connection with the bit line and the body region raises the body potential of the transistor Tr1. In this case, it is a normal technique to pre-charge the bit line BL to an arbitrary potential. Also in this embodiment, this technique is applicable. This pre-charge potential is not limited, and any desired potential may be employed provided it does not adversely affects the operations. Following to the potential change of the bit line BL, a channel current flows in the transistor Tr1. In response to the channel current, impact ionization occurs, holes flow into the body region, and the body potential gradually rises. At that time, the diffusion region connected to the bit line BL and the pn junction located in the body region are reverse biased, and a resultant flow of a leak current in the reverse direction causes more holes to flow into the body region. As a result, potential of the node f asymptotically approaches and reaches Vcc, and that Vcc is maintained thereafter. Also when the bit line BL changes before a change of the potential of the first and second word lines, a similar channel current flows in the transistor Tr1, similar impact ionization occurs, and the body potential of the transistor Tr1 rises.
- At time t3, the bit line is changed from Vcc to, for example, Vss. At that time, capacitive coupling of the pn junction lowers the body potential for a moment, but since the channel current flows in the transistor Tr1 and impact ionization occurs responsively, holes flow into the body region, and the body potential of the transistor Tr1 is still maintained. The potential of the node f asymptotically approaches Vss.
- After that, by changing the first word line WL from Vcc to, for example, Vss, and changing the second word line /WL from Vcc to Vcc at time t4, data write operations are completed. At that time, the above-mentioned capacitive coupling again lowers the body potential slightly from Vcc.
- Changes in potential of the first and second word lines may precede potential changes of the bit line BL. In this case, however, impact ionization does not occur. Therefore, the bit line is preferably changed earlier, as explained above.
-
FIG. 5 is a timing chart that shows operation timings upon writing data “0” in a selectedmemory cell 10. - First, in the same manner as the process of writing data “1”, at time t11, the first word line WL is changed from Vss to Vcc, and the second word line /WL is simultaneously changed from Vcc to Vss. As a result, the transistor Tr1 becomes ON and the transistor Tr2 becomes OFF. At that time, capacitive coupling of the first word line and the body region of the transistor Tr1 raises the body potential Vbody1 of the transistor Tr1.
- In order to realize a potential corresponding to the LOW potential of the bit line, holes in the body region of the transistor Tr1 must be drawn sufficiently. Therefore, at time t12, the bit line BL is changed from Vss to the pre-charge potential −Vcc. As a result, capacitive coupling of the diffusion layer connected to the bit line and the pn junction located in the body region, lowers the body potential of the transistor Tr1. The pre-charge potential may be any desired potential, and also in this embodiment, a different potential may be used.
- Following the potential change of the bit line, the body region of the transistor Tr1 and the pn junction between the diffusion layer in connection with the bit line BL and the node f are biased in the forward direction. Therefore, holes in the body region are exhaled, and the body potential Vbody1 of the transistor Tr1 further lowers. Simultaneously, potential f the node f asymptotically approaches −Vcc. When the transistor Tr2 is OFF the node f is floating, almost no channel current flows in the transistor Tr1 accordingly, holes in he body region are effectively drawn out, and the LOW potential can be written stably.
- After that, at time t13, once the word line WL is changed to Vss and the word line /WL to Vcc, the body potential Vbody1 of the transistor Tr1 lowers. Then at t14 immediately thereafter, by changing the bit line from −Vcc to, for example, Vss, data write operations are completed.
- Here again, the body potential Vbody1 rises due to the capacitive coupling explained above.
- As explained with reference to
FIG. 4 , potential change of the bit line BL may precede to potential changes of the word line WL and the word line /WL. - Through the above-explained control, once the voltage of the bit line is set to, for example, −1V, the pn junction with the body region is biased forwardly, so the potential of the body can be instantaneously changed to about −0.5V. Thus the margin for writing data “0” is improved.
- In the above explanation of write operations, the example has been taken, in which complementary potentials are given in synchronism to the first word line and the second word line; however, potential changes of the respective word lines may be controlled asynchronously.
- Next explained are data read-out operations. For reading out data, a difference between current values based on a difference between element threshold voltages of the transistor Tr1 due to stored data is detected by using, for example, a current-sensing type sense-amplifier.
-
FIG. 6 is a graph that shows how the drain current changes with the content of stored data when the data is read out. The gate voltage Vg is taken on the abscissa, and the logarithm of the drain current is taken on the ordinate. As apparent from the graph, the gate voltage necessary for a certain drain current is higher in a transistor Tr1 written with data “0” than in a transistor Tr1 written with data “1”. Therefore, the threshold value of a transistor Tr1 with data “1” lowers whereas the threshold voltage of a transistor Tr1 with “0” rises. As a result, when data is read out by using a predetermined word line potential shown by the broken line, the drain current of the transistor Tr1 with data “1” exhibits a high value than the drain current of the transistor Tr1 with data “0”. Thus by detecting the difference between these current values, data “1” and data “0” can be judged. - More specifically, a potential corresponding to one half the normal source potential, such as Vcc/2, is used as the gate potential, that is, the word line potential, for judgment.
-
FIG. 7 is a timing chart that shows read-out operation waveforms in case of data “1” being written in the transistor Tr1. - Assume here that the bit line is pre-charged to Vcc/2 in the non-selection period, and a memory cell selected at time t21 where read-out operation is started. At that time, by detecting that the bit line potential BL rises due to an increase of the current flowing into the bit line in response to the rise of the body potential Vbody1 of the transistor Tr1, data can be judged as being “1”.
-
FIG. 8 is a timing chart that shows read-operation waveforms in case of data “0” being written in the transistor Tr1. Similarly to the case ofFIG. 7 , the bit line is pre-charged to Vcc/2, and the word lines WL and /WL are set in Vcc/2” at the read-out start time t31. However, since the body potential Vbody1 of the transistor Tr1 is currently low, Vbody1 maintains the minus value even after time t31. Therefore, the current flowing into the bit line is smaller than that ofFIG. 7 , and the bit line potential BL does not change. By detecting it, the data can be judged to be “0”. - According to the embodiment, each memory cell is made by serially connecting two transistors, thereby to bring out the advantage of enabling higher integration by eliminating capacitors and to enable stable write of data.
- The foregoing embodiment has been explained by way of the example using two nMOS; however, the same object can be accomplished by employing two p-channel MOS transistors (pMOS) as well. Note here, however, that nMOS is more advantageous for miniaturization if the write condition is the same because the write margin of data “1” in nMOS is larger than that in pMOS.
- It is also possible to employ a CMOS configuration in which two transistors are opposite in conduction type from each other. This configuration will be explained later.
- Further, while the same configuration is used regarding the transistor Tr1 and the transistor Tr2, if the bit line and Vss are operated oppositely and the timing of their signals is controlled by the second word line, then it is possible to hold two data with two elements by writing a datum in the body region of the transistor Tr1 and simultaneously writing another datum in the transistor Tr2.
-
FIGS. 9A through 9D are cross-sectional views of such an element under different manufacturing steps, that show an embodiment of the manufacturing method of the semiconductor memory device shown inFIG. 1 . - First made is a SOI structure having a SOI
active layer 13 formed on asemiconductor substrate 11 via a buried oxide (BOX)film 12 such as a silicon oxide film by using an appropriate method, such as SIMOX (separation by implantation of oxygen) technique that obtains an oxide layer and a silicon layer thereon by ion implantation of oxygen ions into a silicon semiconductor substrate and subsequent annealing, or bonding technique that bonds a silicon plate having an oxide film at the bottom to a surface of a silicon semiconductor substrate. The SOI active layer is thereafter thinned to a desired thickness about 150 nm, for example, by thermal oxidation and etching by NH4F, for example. - In the next step, as shown in
FIG. 9A , for the purpose of electrically separating the SOIactive layer 13 into discrete element-forming regions,element isolation regions 14 are formed by, for example, STI (shallow trench isolation) technique that buries shallow trenches with an insulating film. - After that, for the purpose of adjusting the threshold voltage of the elements, impurities are introduced into the SOI
active layer 13 in the element-forming regions by the dose of 1.5×10−12 cm−2 by, for example, ion implantation. - Subsequently, as shown in
FIG. 9B , an insulatingfilm 15, which will become a gate insulating film, is formed on the SOIactive layer 13 by thermal oxidation, for example. Further stacked thereon ispolycrystalline silicon 16 of the thickness of 200 nm by CVD (chemical vapor deposition). - Next as shown in
FIG. 9C , using a mask of a resist, for example, thepolycrystalline silicon 16 is patterned by selectively removing it from above the source and drain regions by etching, such as reactive ion etching (RIE), thereby to obtaingate electrodes 17. - Using these
gate electrodes 17 as a mask against introduction of ions, impurities are introduced into regions for forming diffusion layers in by ion implantation, for example. After that, the impurities introduced by ion implantation are activated in a heat process using annealing such as RTA (rapid thermal annealing). - After that, as shown in
FIG. 9D , alayer insulating film 18 is stacked; contact holes are formed at given positions; an electrode wiring material like aluminum is formed to bury the contact holes and lie on thelayer insulating film 18; and it is patterned to form the first word line (WL)electrode wiring 19, second word line (/WL)electrode wiring 20, bitline electrode wiring 21 andVss electrode wiring 22, thereby to complete the desired partially-depleted SOI semiconductor device. The wirings may be multi-layered according to the specification required. -
FIG. 10 is a plan view of an element made through those steps, in which the same components as those shown inFIG. 9D are labeled with common reference numerals. -
FIGS. 11A thorough 11E are cross-sectional views of different steps of a further embodiment of the semiconductor memory device manufacturing method according to the invention, and they show an example using a CMOStype memory cell 50. - First made is a SOI structure having a SOI
active layer 53 formed on asemiconductor substrate 51 via a buried oxide (BOX)film 52 such as a silicon oxide film by using an appropriate method, such as SIMOX (separation by implantation of oxygen) technique or bonding technique. The SOIactive layer 53 is thereafter thinned to a desired thickness about 150 nm, for example, by thermal oxidation and etching by NH4F, for example. - In the next step, as shown in
FIG. 11A , for the purpose of electrically separating the SOIactive layer 53 into discrete element-forming regions, trench-shapedelement isolation regions 54 are formed by, for example STI (shallow trench isolation) technique. - Next as shown in
FIG. 11B , for the purpose of adjusting the threshold voltage of the elements, impurities are introduced into the SOIactive layer 53 in the element-forming regions. In this embodiment using the CMOS structure, a resist 55 is selectively formed to mask the remainder regions other than the element-forming regions against ions to be introduced.FIG. 11B shows the configuration as introducing impurities into regions for forming pMOS in. As the impurities, boron ions are introduced by the dose of, for example, 1.5×1013 cm−2. A similar step of injecting ions is conducted for the regions for forming nMOS in as well, and phosphorus ions are introduced as impurities by the dose of 1.5×1013 cm−2. - After that, as shown in
FIG. 11C , agate insulating film 56 is formed on the SOIactive layer 53 by, for example, thermal oxidation. Further stacked thereon ispolycrystalline silicon 57 of the thickness of 200 nm by CVD (chemical vapor deposition). - Next as shown in
FIG. 11D , using a mask of a resist, for example, thepolycrystalline silicon 57 is patterned by selectively removing it from above the source and drain regions by, for example, reactive ion etching (RIE), thereby to obtaingate electrodes 58. - Using these
gate electrodes 58 as a mask against introduction of ions, impurities are introduced into regions for forming diffusion layers in by ion implantation, for example. In this case, since ions introduced are different between pMOS and nMOS, upon forming pMOS diffusion layers shown inFIG. 11E , the nMOS regions are masked by a resist 59, and boon ions, for example, are injected by the dose of 3×1015 cm−2. Similarly, upon forming nMOS diffusion layers, pMOS regions are masked by a resist, and phosphorus ions, for example, are injected by the dose of 3×1015 cm−2. After that, the impurities introduced by ion implantation are activated in a heat process using annealing such as RTA (rapid thermal annealing). - Thereafter, as shown in
FIG. 11F , asilicide 60 such as CoSi2 is formed on the source regions, drain regions and gate electrode regions through a salicide step for self-aligned deposition. - Subsequently, a
layer insulating film 61 is stacked; contact holes 62 are formed at given positions; and anelectrode wiring material 63 like aluminum is deposited by vapor deposition to bury the contact holes 62 and lie on thelayer insulating film 60. Then the electrode wiring material on thelayer insulating film 60 is patterned to form the fist word line (WL)electrode wiring 64, second word line (/WL) electrode wiring (not shown),electrode wiring 65 for the bit line BL, andVss electrode wiring 66, thereby to complete the desired partially-depleted SOI semiconductor device. In this semiconductor device, nMOS diffusion layers are connected to bit lines, and pMOS diffusion layers are connected to Vss source lines. -
FIG. 12 shows a plan view of amemory cell 50 formed through those steps. This is a CMOS memory cell, so thesame gate electrode 64 can be commonly shared by nMOS and pMOS without the need of electrically separating the second word line from the first word line. - According to these embodiments, a DRAM element made up solely of MIS elements and eliminating capacitors can be manufactured easily.
- The invention is not limited in process of forming elements and in parameter of the device to those shown in the embodiments, but can be brought into practice in appropriately modified forms. For example, although the embodiments have been explained as using single layered wirings, they can be modified to multi-layered wirings according to the specification required. In this case, for making one or more upper layers, the steps of forming the layer insulating film, forming contact holes, vapor deposition of the electrode material and patterning thereof will be repeated.
- Furthermore, although the embodiments have been explained by way of nMOSFET or CMOSFET using the SOI substrate, the invention is not limited to it, but can use other types of substrate such as pMOSFET, SOS (silicon on sapphire), and so forth.
- Also in the other respects, the invention can be modified in various forms within the concept and scope of the invention.
Claims (6)
1-15. (canceled)
16. A semiconductor memory device manufacturing method comprising:
forming an oxide layer and a silicon active layer on a semiconductor substrate;
forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer;
forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it;
injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask;
forming said paired transistors by activating the injected ions through a heat process; and
forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.
17. A semiconductor memory device manufacturing method according to claim 16 , wherein said paired transistors are MIS-type partially depleted transistors.
18. A semiconductor memory device manufacturing method according to claim 16 , wherein the process of forming said oxide layer and said silicon active layer on said semiconductor substrate includes;
ion injection of oxygen ions into a silicon semiconductor substrate; and
annealing said silicon semiconductor substrate.
19. A semiconductor memory device manufacturing method according to claim 16 , wherein the process of forming said oxide layer and said silicon active layer on said semiconductor substrate includes bonding a silicon active layer having an oxide layer on the bottom surface thereof onto said semiconductor substrate.
20. A semiconductor memory device manufacturing method according to claim 16 , wherein said silicon active layer is thinned to a predetermined thickness by etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/369,041 US20060157738A1 (en) | 2001-12-14 | 2006-03-07 | Semiconductor memory device and its manufacturing method |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001381458A JP3808763B2 (en) | 2001-12-14 | 2001-12-14 | Semiconductor memory device and manufacturing method thereof |
JP2001-381458 | 2001-12-14 | ||
US10/075,464 US7081653B2 (en) | 2001-12-14 | 2002-02-15 | Semiconductor memory device having mis-type transistors |
US11/369,041 US20060157738A1 (en) | 2001-12-14 | 2006-03-07 | Semiconductor memory device and its manufacturing method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/075,464 Division US7081653B2 (en) | 2001-12-14 | 2002-02-15 | Semiconductor memory device having mis-type transistors |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060157738A1 true US20060157738A1 (en) | 2006-07-20 |
Family
ID=19187339
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/075,464 Expired - Fee Related US7081653B2 (en) | 2001-12-14 | 2002-02-15 | Semiconductor memory device having mis-type transistors |
US11/369,041 Abandoned US20060157738A1 (en) | 2001-12-14 | 2006-03-07 | Semiconductor memory device and its manufacturing method |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/075,464 Expired - Fee Related US7081653B2 (en) | 2001-12-14 | 2002-02-15 | Semiconductor memory device having mis-type transistors |
Country Status (5)
Country | Link |
---|---|
US (2) | US7081653B2 (en) |
JP (1) | JP3808763B2 (en) |
KR (1) | KR100532894B1 (en) |
CN (1) | CN1263154C (en) |
TW (1) | TW563242B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070076467A1 (en) * | 2005-10-04 | 2007-04-05 | Renesas Technology Corp. | Semiconductor memory device |
US20090184371A1 (en) * | 2008-01-17 | 2009-07-23 | Shigeru Kawanaka | Semiconductor device with an soi structure |
US11917807B2 (en) | 2021-06-22 | 2024-02-27 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
US11968822B2 (en) | 2021-07-09 | 2024-04-23 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
US11980022B2 (en) | 2021-08-03 | 2024-05-07 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
US11990204B2 (en) | 2021-07-06 | 2024-05-21 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003257178A (en) * | 2002-03-06 | 2003-09-12 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
KR100481868B1 (en) * | 2002-11-26 | 2005-04-11 | 삼성전자주식회사 | Modified silicon-on-insulator substrate having isolation structure of preventing leakage current and method of fabricating the same |
CN1965404B (en) * | 2004-06-09 | 2010-05-26 | 株式会社瑞萨科技 | Semiconductor storage |
KR100852456B1 (en) * | 2007-01-25 | 2008-08-14 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
KR100891329B1 (en) * | 2007-01-26 | 2009-03-31 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
KR100891963B1 (en) | 2007-02-02 | 2009-04-08 | 삼성전자주식회사 | One transistor dram device and method of forming the same |
KR100909902B1 (en) | 2007-04-27 | 2009-07-30 | 삼성전자주식회사 | Flash memory device and Flash memory system |
US7847338B2 (en) | 2007-10-24 | 2010-12-07 | Yuniarto Widjaja | Semiconductor memory having both volatile and non-volatile functionality and method of operating |
KR101049600B1 (en) * | 2008-12-23 | 2011-07-14 | 주식회사 하이닉스반도체 | Semiconductor memory device including cell isolation structure using inactive transistor |
JP5631607B2 (en) * | 2009-08-21 | 2014-11-26 | 株式会社東芝 | High frequency circuit having multi-chip module structure |
US8680619B2 (en) * | 2010-03-16 | 2014-03-25 | Taiwan Semiconductor Manufacturing Compnay, Ltd. | Method of fabricating hybrid impact-ionization semiconductor device |
US8582359B2 (en) | 2010-11-16 | 2013-11-12 | Zeno Semiconductor, Inc. | Dual-port semiconductor memory and first-in first-out (FIFO) memory having electrically floating body transistor |
US9230651B2 (en) | 2012-04-08 | 2016-01-05 | Zeno Semiconductor, Inc. | Memory device having electrically floating body transitor |
JP6362542B2 (en) | 2012-02-16 | 2018-07-25 | ジーノ セミコンダクター, インコーポレイテッド | Memory cell comprising first and second transistors and method of operation |
FR2990553B1 (en) * | 2012-05-09 | 2015-02-20 | Soitec Silicon On Insulator | COMPLEMENTARY FET INJECTION FOR FLOATING BODY CELL |
US9281022B2 (en) | 2013-07-10 | 2016-03-08 | Zeno Semiconductor, Inc. | Systems and methods for reducing standby power in floating body memory devices |
CN106158804B (en) | 2015-04-02 | 2018-11-16 | 台达电子工业股份有限公司 | A kind of semiconductor package and its semiconductor power device |
JP7057032B1 (en) | 2020-12-25 | 2022-04-19 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor elements |
WO2022208587A1 (en) * | 2021-03-29 | 2022-10-06 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element, and method for manufacturing same |
WO2022208658A1 (en) * | 2021-03-30 | 2022-10-06 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device having memory element |
WO2022215155A1 (en) * | 2021-04-06 | 2022-10-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2022215157A1 (en) * | 2021-04-06 | 2022-10-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device having memory element |
WO2022219704A1 (en) | 2021-04-13 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2022219694A1 (en) * | 2021-04-13 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2022219703A1 (en) | 2021-04-13 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device employing semiconductor element |
WO2022219763A1 (en) * | 2021-04-15 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2022219762A1 (en) * | 2021-04-15 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device having memory element |
WO2022219767A1 (en) * | 2021-04-15 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device having memory element |
WO2022234656A1 (en) | 2021-05-07 | 2022-11-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device having semiconductor element |
WO2022239100A1 (en) | 2021-05-11 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2022239199A1 (en) | 2021-05-13 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2022239228A1 (en) | 2021-05-14 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2023073765A1 (en) * | 2021-10-25 | 2023-05-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Method for manufacturing semiconductor memory device |
WO2023135631A1 (en) * | 2022-01-11 | 2023-07-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
JPWO2023148799A1 (en) * | 2022-02-01 | 2023-08-10 | ||
WO2023162039A1 (en) * | 2022-02-22 | 2023-08-31 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
WO2023162036A1 (en) * | 2022-02-22 | 2023-08-31 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
WO2023166608A1 (en) * | 2022-03-02 | 2023-09-07 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2023170755A1 (en) * | 2022-03-07 | 2023-09-14 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2023170782A1 (en) * | 2022-03-08 | 2023-09-14 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
JPWO2023175792A1 (en) * | 2022-03-16 | 2023-09-21 | ||
WO2023181172A1 (en) * | 2022-03-23 | 2023-09-28 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
WO2023188006A1 (en) * | 2022-03-29 | 2023-10-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
WO2023195047A1 (en) * | 2022-04-04 | 2023-10-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
WO2023238370A1 (en) * | 2022-06-10 | 2023-12-14 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device |
WO2023248418A1 (en) * | 2022-06-23 | 2023-12-28 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2024042609A1 (en) * | 2022-08-23 | 2024-02-29 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2024062551A1 (en) * | 2022-09-21 | 2024-03-28 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device in which semiconductor element is used |
WO2024079818A1 (en) * | 2022-10-12 | 2024-04-18 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Memory device using semiconductor element |
WO2024089809A1 (en) * | 2022-10-26 | 2024-05-02 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Method for manufacturing memory device using semiconductor element |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722910A (en) * | 1986-05-27 | 1988-02-02 | Analog Devices, Inc. | Partially self-aligned metal contact process |
US5162880A (en) * | 1989-09-27 | 1992-11-10 | Kabushiki Kaisha Toshiba | Nonvolatile memory cell having gate insulation film with carrier traps therein |
US5416041A (en) * | 1993-09-27 | 1995-05-16 | Siemens Aktiengesellschaft | Method for producing an insulating trench in an SOI substrate |
US5494857A (en) * | 1993-07-28 | 1996-02-27 | Digital Equipment Corporation | Chemical mechanical planarization of shallow trenches in semiconductor substrates |
US5604700A (en) * | 1995-07-28 | 1997-02-18 | Motorola, Inc. | Non-volatile memory cell having a single polysilicon gate |
US5693975A (en) * | 1995-10-05 | 1997-12-02 | Integrated Device Technology, Inc. | Compact P-channel/N-channel transistor structure |
US5736435A (en) * | 1995-07-03 | 1998-04-07 | Motorola, Inc. | Process for fabricating a fully self-aligned soi mosfet |
US5804495A (en) * | 1990-04-24 | 1998-09-08 | Mitsubishi Materials Corporation | Method of making SOI structure |
US5863820A (en) * | 1998-02-02 | 1999-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of sac and salicide processes on a chip having embedded memory |
US6160300A (en) * | 1999-01-26 | 2000-12-12 | Advanced Micro Devices, Inc. | Multi-layer gate conductor having a diffusion barrier in the bottom layer |
US6265250B1 (en) * | 1999-09-23 | 2001-07-24 | Advanced Micro Devices, Inc. | Method for forming SOI film by laser annealing |
US6461939B1 (en) * | 1999-04-09 | 2002-10-08 | Shin-Etsu Handotai Co., Ltd. | SOI wafers and methods for producing SOI wafer |
US20020171106A1 (en) * | 2001-05-21 | 2002-11-21 | International Business Machines Corporation | Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI |
US6534373B1 (en) * | 2001-03-26 | 2003-03-18 | Advanced Micro Devices, Inc. | MOS transistor with reduced floating body effect |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS627150A (en) | 1985-07-03 | 1987-01-14 | Agency Of Ind Science & Technol | Semiconductor memory device |
JPS627149A (en) | 1985-07-03 | 1987-01-14 | Agency Of Ind Science & Technol | Semiconductor memory device |
JPH03171768A (en) | 1989-11-30 | 1991-07-25 | Toshiba Corp | Semiconductor storage device |
JPH05110037A (en) | 1991-10-14 | 1993-04-30 | Toshiba Corp | Semiconductor device |
US5619446A (en) | 1992-01-10 | 1997-04-08 | Kawasaki Steel Corporation | Hierarchical encoder including timing and data detection devices for a content addressable memory |
US5448513A (en) | 1993-12-02 | 1995-09-05 | Regents Of The University Of California | Capacitorless DRAM device on silicon-on-insulator substrate |
JPH09135030A (en) | 1995-11-08 | 1997-05-20 | Hitachi Ltd | Semiconductor integrated circuit device, computer system using the device and manufacturing method for the semiconductor integrated circuit device |
-
2001
- 2001-12-14 JP JP2001381458A patent/JP3808763B2/en not_active Expired - Fee Related
-
2002
- 2002-02-15 US US10/075,464 patent/US7081653B2/en not_active Expired - Fee Related
- 2002-10-22 TW TW091124317A patent/TW563242B/en active
- 2002-12-13 CN CNB021560749A patent/CN1263154C/en not_active Expired - Fee Related
- 2002-12-13 KR KR10-2002-0079536A patent/KR100532894B1/en not_active IP Right Cessation
-
2006
- 2006-03-07 US US11/369,041 patent/US20060157738A1/en not_active Abandoned
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722910A (en) * | 1986-05-27 | 1988-02-02 | Analog Devices, Inc. | Partially self-aligned metal contact process |
US5162880A (en) * | 1989-09-27 | 1992-11-10 | Kabushiki Kaisha Toshiba | Nonvolatile memory cell having gate insulation film with carrier traps therein |
US5804495A (en) * | 1990-04-24 | 1998-09-08 | Mitsubishi Materials Corporation | Method of making SOI structure |
US5494857A (en) * | 1993-07-28 | 1996-02-27 | Digital Equipment Corporation | Chemical mechanical planarization of shallow trenches in semiconductor substrates |
US5416041A (en) * | 1993-09-27 | 1995-05-16 | Siemens Aktiengesellschaft | Method for producing an insulating trench in an SOI substrate |
US5736435A (en) * | 1995-07-03 | 1998-04-07 | Motorola, Inc. | Process for fabricating a fully self-aligned soi mosfet |
US5604700A (en) * | 1995-07-28 | 1997-02-18 | Motorola, Inc. | Non-volatile memory cell having a single polysilicon gate |
US5693975A (en) * | 1995-10-05 | 1997-12-02 | Integrated Device Technology, Inc. | Compact P-channel/N-channel transistor structure |
US5863820A (en) * | 1998-02-02 | 1999-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of sac and salicide processes on a chip having embedded memory |
US6160300A (en) * | 1999-01-26 | 2000-12-12 | Advanced Micro Devices, Inc. | Multi-layer gate conductor having a diffusion barrier in the bottom layer |
US6461939B1 (en) * | 1999-04-09 | 2002-10-08 | Shin-Etsu Handotai Co., Ltd. | SOI wafers and methods for producing SOI wafer |
US6265250B1 (en) * | 1999-09-23 | 2001-07-24 | Advanced Micro Devices, Inc. | Method for forming SOI film by laser annealing |
US6534373B1 (en) * | 2001-03-26 | 2003-03-18 | Advanced Micro Devices, Inc. | MOS transistor with reduced floating body effect |
US20020171106A1 (en) * | 2001-05-21 | 2002-11-21 | International Business Machines Corporation | Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070076467A1 (en) * | 2005-10-04 | 2007-04-05 | Renesas Technology Corp. | Semiconductor memory device |
US7639525B2 (en) * | 2005-10-04 | 2009-12-29 | Renesas Technology Corp. | Semiconductor memory device |
US20100065911A1 (en) * | 2005-10-04 | 2010-03-18 | Renesas Technology Corp. | Semiconductor memory device |
US20110122681A1 (en) * | 2005-10-04 | 2011-05-26 | Renesas Electronics Corporation | Semiconductor memory device |
US7995377B2 (en) | 2005-10-04 | 2011-08-09 | Renesas Electronics Corporation | Semiconductor memory device |
US8203868B2 (en) | 2005-10-04 | 2012-06-19 | Renesas Electronics Corporation | Semiconductor memory device |
US20090184371A1 (en) * | 2008-01-17 | 2009-07-23 | Shigeru Kawanaka | Semiconductor device with an soi structure |
US11917807B2 (en) | 2021-06-22 | 2024-02-27 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
US11990204B2 (en) | 2021-07-06 | 2024-05-21 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
US11968822B2 (en) | 2021-07-09 | 2024-04-23 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
US11980022B2 (en) | 2021-08-03 | 2024-05-07 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
Also Published As
Publication number | Publication date |
---|---|
JP3808763B2 (en) | 2006-08-16 |
US20030111681A1 (en) | 2003-06-19 |
CN1263154C (en) | 2006-07-05 |
TW563242B (en) | 2003-11-21 |
KR20030051299A (en) | 2003-06-25 |
CN1427484A (en) | 2003-07-02 |
JP2003188279A (en) | 2003-07-04 |
KR100532894B1 (en) | 2005-12-02 |
US7081653B2 (en) | 2006-07-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7081653B2 (en) | Semiconductor memory device having mis-type transistors | |
US6903984B1 (en) | Floating-body DRAM using write word line for increased retention time | |
JP4053738B2 (en) | Semiconductor memory device | |
US7447104B2 (en) | Word line driver for DRAM embedded in a logic process | |
US6828689B2 (en) | Semiconductor latches and SRAM devices | |
US10403627B2 (en) | Memory device for a dynamic random access memory | |
US20020053691A1 (en) | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same | |
JP2004527901A (en) | DRAM cell with capacitor structure partially fabricated in cavity and method of operating the same | |
US20060138558A1 (en) | Semiconductor memory device and method of fabricating the same | |
US6856030B2 (en) | Semiconductor latches and SRAM devices | |
US6201730B1 (en) | Sensing of memory cell via a plateline | |
JP2001093989A (en) | Semiconductor device | |
US6504741B2 (en) | Semiconductor device in which storage electrode of capacitor is connected to gate electrode of FET and inspection method thereof | |
US6133608A (en) | SOI-body selective link method and apparatus | |
US20180040365A1 (en) | Semiconductor device and method for manufacturing the same | |
US6150686A (en) | Semiconductor integrated circuit device with trench capacitor and method of manufacturing the same | |
US6509595B1 (en) | DRAM cell fabricated using a modified logic process and method for operating same | |
US7208799B2 (en) | Floating body cell dynamic random access memory with optimized body geometry | |
US6262447B1 (en) | Single polysilicon DRAM cell and array with current gain | |
US7061032B2 (en) | Semiconductor device with upper portion of plugs contacting source and drain regions being a first self-aligned silicide | |
US6410369B1 (en) | Soi-body selective link method and apparatus | |
JP3607499B2 (en) | Semiconductor integrated circuit device | |
EP1420413B1 (en) | Improved memory device | |
JP2002230969A (en) | Semiconductor memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |