US20060049785A1 - Brushless motor drive device - Google Patents
Brushless motor drive device Download PDFInfo
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- US20060049785A1 US20060049785A1 US10/907,240 US90724005A US2006049785A1 US 20060049785 A1 US20060049785 A1 US 20060049785A1 US 90724005 A US90724005 A US 90724005A US 2006049785 A1 US2006049785 A1 US 2006049785A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/14—Electronic commutators
- H02P6/16—Circuit arrangements for detecting position
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/14—Electronic commutators
- H02P6/15—Controlling commutation time
Definitions
- the present invention relates to a motor drive device and, more particularly, to a motor drive device for a brushless DC motor.
- FIG. 1 ( a ) is a circuit block diagram showing a conventional brushless motor drive device.
- a motor M is a three-phase DC brushless motor having three phase coils U, V, and W.
- a Hall sensing circuit 11 is arranged around the motor M for detecting a position of a rotor of the motor M, thereby generating three positional detection signals HU, HV, and HW.
- a signal synthesizing circuit 12 In response to the positional detection signals HU, HV, and HW, a signal synthesizing circuit 12 generates three sinusoidal drive signals SU, SV, and SW.
- the sinusoidal drive signals SU, SV, and SW are input to a pulse width modulation (PWM) comparing circuit 13 for being individually compared with respect to a high-frequency triangular signal T generated by an oscillating circuit 1 4 .
- the PWM comparing circuit 13 Based on the comparison of the sinusoidal drive signals SU, SV, and SW individually with the high-frequency triangular signal T, the PWM comparing circuit 13 generates three pulse signals PU, PV, and PW to be supplied to three pre-drivers N 1 , N 2 , and N 3 .
- the pre-driver N 1 generates a pair of switching signals UH and UL.
- the pre-driver N 2 generates a pair of switching signals VH and VL.
- the pre-driver N 3 In response to the pulse signal PW, the pre-driver N 3 generates a pair of switching signals WH and WL.
- a three-phase switching circuit 15 has a pair of switches S 1 and S 2 , a pair of switches S 3 and S 4 , and a pair of switches S 5 and S 6 , each pair being controlled by one corresponding pair of the switching signals UH and UL, VH and VL, and WH and WL.
- a motor drive current Im is allowed to flow from a drive voltage source Vdd to the coil U when the switch S 1 becomes short-circuited and to flow from the coil U to a ground potential when the switch S 2 becomes short-circuited.
- the motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil V when the switch S 3 becomes short-circuited and to flow from the coil V to the ground potential when the switch S 4 becomes short-circuited.
- the motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil W when the switch S 5 becomes short-circuited and to flow from the coil W to the ground potential when the switch S 6 becomes short-circuited.
- a resistor Rs is series-connected between the common connecting point of the switches S 2 , S 4 , and S 6 and the ground potential.
- a voltage difference caused by the motor drive current Im flowing through the resistor Rs is supplied as a negative feedback to an inverting input terminal of an error amplifier EA.
- the error amplifier EA compares the voltage difference representative of the motor drive current Im with a current command signal Icom for generating a current error signal Ierr. Subsequently, the signal synthesizing circuit 12 adjusts the amplitudes of the sinusoidal drive signals SU, SV, and SW in accordance with the current error signal Ierr.
- FIG. 1 ( b ) is a waveform timing chart showing operations of the conventional brushless motor drive device. For the sake of simplicity, only is illustrated in FIG. 1 ( b ) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and W of the motor M is operated with similar waveforms.
- the pulse signal PU is generated from the comparison of the sinusoidal drive signal SU and the high-frequency triangular signal T through using the PWM comparing circuit 13 .
- the HIGH level of the pulse signal PU corresponds to an interval of time when the sinusoidal drive signal SU goes higher than the high-frequency triangular signal T and the LOW level of the pulse signal PU corresponds to an interval of time when the sinusoidal drive signal SU goes lower than the high-frequency triangular signal T.
- the pre-driver N 1 In response to the pulse signal PU, the pre-driver N 1 generates the switching signals UH and UL for controlling the switches S 1 and S 2 , respectively.
- the error amplifier EA supplies the current error signal Ierr to the signal synthesizing circuit 12 for adjusting the amplitude of the sinusoidal drive signal SU.
- the current error signal Ierr controls the signal synthesizing circuit 12 to increase the amplitude of the sinusoidal drive signal SU so as to obtain a sinusoidal drive signal SU′.
- the sinusoidal drive signal SU′ with a larger amplitude causes the PWM comparing circuit 13 to generate a pulse signal PU′ with a larger duty ratio.
- the three-phase switching circuit 15 causes an increase of the motor drive current Im and therefore the motor drive current Im approaches to the current command signal Icom.
- the signal synthesizing circuit 12 may even generate a sinusoidal drive signal SU′′ with an amplitude larger than that of the high-frequency triangular T in response to an extremely great current error signal Ierr.
- the PWM comparing circuit 13 generates a pulse signal PU′′ with a frequency lower than that of the high-frequency triangular signal T.
- the low-frequency pulse signal PU′′ induces a large ripple to the motor torque and deteriorates the smooth rotation of the motor M.
- the low-frequency pulse signal PU′′ remains at the HIGH/LOW level each cycle for a relatively long time such that the three-phase switching circuit 15 supplies the motor drive current Im in the continuous mode other than the PWM mode.
- the long-time continuous supply of the motor drive current Im may damage the motor M and the three-phase switching circuit 15 .
- the temperature rising caused by the large heat dissipation may trigger the thermal shutdown mechanism.
- an object of the present invention is to provide a brushless motor drive device capable of limiting the duty ratio of the pulse signal.
- Another object of the present invention is to provide a brushless motor drive device capable of preventing the frequency of the pulse signal from becoming lower.
- Still another object of the present invention is to provide a brushless motor drive device capable of preventing the pulse signal from remaining at the HIGH/LOW level for a relatively long time.
- a brushless motor drive device with a comparing circuit and a limiting circuit.
- the comparing circuit compares a drive signal and a reference signal to generate a pulse signal.
- the limiting circuit has a first circuit, a second circuit, a first logic circuit, and a second logic circuit.
- the first circuit generates a first-half duty-ratio limit signal.
- the second circuit generates a second-half duty-ratio limit signal.
- the first logic circuit constrains a duty ratio of the pulse signal by using the first-half duty-ratio limit signal and then generating an output signal.
- the second logic circuit constrains a duty ratio of the output signal of the first logic circuit by using the second-half duty-ratio limit signal.
- a brushless motor drive device is provided with a comparing circuit and a limiting circuit.
- the comparing circuit is implemented by at least one tri-input comparator for comparing a drive signal, a reference signal, and a first-half limit level to generate a pulse signal with limitation on a duty ratio of a first half of the pulse signal.
- the limiting circuit has a circuit for generating a second-half duty-ratio limit signal, and a logic circuit for constraining a duty ratio of a second half of the pulse signal by using the second-half duty-ratio limit signal.
- a brushless motor drive device with a comparing circuit and a limiting circuit.
- the comparing circuit is implemented by at least one first tri-input comparator and at least one second tri-input comparator.
- the first tri-input comparator compares a drive signal, a reference signal, and a first-half limit level to generate a first pulse signal with limitation on a duty ratio of a first half of the first pulse signal.
- the second tri-input comparator compares a drive signal, a reference signal, and a second-half limit level to generate a second pulse signal with limitation on a duty ratio of a second half of the second pulse signal.
- FIG. 1 ( a ) is a circuit block diagram showing a conventional brushless motor drive device
- FIG. 1 ( b ) is a waveform timing chart showing operations of a conventional brushless motor drive device
- FIG. 2 is a circuit block diagram showing a brushless motor drive device according to the present invention.
- FIG. 3 ( a ) is a detailed circuit diagram showing a first embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention
- FIG. 3 ( b ) is a waveform timing chart showing an operation of a first embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention
- FIG. 4 ( a ) is a detailed circuit diagram showing a second embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention
- FIG. 4 ( b ) is a waveform timing chart showing an operation of a second embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention
- FIG. 5 ( a ) is a detailed circuit diagram showing a third embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention
- FIG. 5 ( b ) is a waveform timing chart showing an operation of a third embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention
- FIG. 6 ( a ) is a detailed circuit diagram showing a fourth embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention.
- FIG. 6 ( b ) is a waveform timing chart showing an operation of a fourth embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention.
- FIG. 2 is a circuit block diagram showing a brushless motor drive device according to the present invention.
- a motor M is a three-phase DC brushless motor having three phase coils U, V, and W.
- a Hall sensing circuit 11 may include three Hall sensors and three Hall amplifiers for the three phase coils U, V, and W, respectively.
- the Hall sensing circuit 11 is arranged around the motor M for generating three positional detection signals HU, HV, and HW representative of the positional relationships between a rotor of the motor M and the three phase coils U, V, and W, respectively.
- Each of the positional detection signals HU, HV, and HW is a sinusoidal signal synchronous with the rotation of the motor M and is 120 degrees out of phase with respect to each other.
- a signal synthesizing circuit 12 In response to the positional detection signals HU, HV, and HW, a signal synthesizing circuit 12 generates three drive signals SU, SV, and SW.
- the drive signals SU, SV, and SW may be implemented by shifting 30 degrees the phases of the corresponding positional detection signals HU, HV, and HW, and therefore the waveforms of the drive signals SU, SV, and SW still remain sinusoidal.
- the drive signals SU, SV, and SW may be implemented by superposing an appropriate correction signal for compensating the turn-on delay onto the corresponding positional detection signals HU, HV, and HW after the 30-degree phase shifting. Consequently, the waveforms of the drive signals SU, SV, and SW become the superposition of the sinusoidal signal and the correction signal.
- Many kinds of correction signals have already been disclosed in U.S. Pat. No. 5,811,949, which is incorporated herein by reference.
- a high-frequency reference signal T may be implemented by a single triangular signal in which an average value of an amplitude of the triangular signal substantially coincides with an average value of an amplitude of each of the drive signals SU, SV, and SW.
- the high-frequency reference signal T may be implemented by combining an upper triangular signal and a lower triangular signal, both of which have the same frequency.
- the valley of the upper triangular signal substantially corresponds in time to the peak of the lower triangular signal.
- the valley of the upper triangular signal substantially coincides with the average value of the amplitude of each of the drive signals SU, SV, and SW.
- the peak of the lower triangular signal substantially coincides with the average value of the amplitude of each of the drive signals SU, SV, and SW.
- Such upper and lower triangular signals have already been disclosed in U.S. Pat. No. 3,585,517, which is incorporated herein by reference.
- a PWM comparing circuit 20 and a duty-ratio limiting circuit 21 are operated in coordination for generating three duty-ratio-limited pulse signals PU d , PV d , and PW d .
- a pre-driving circuit N 1 In response to the pulse signal PU d , a pre-driving circuit N 1 generates a pair of switching signals UH d and UL d .
- the pre-driving circuit N 2 In response to the pulse signal PV d , the pre-driving circuit N 2 generates a pair of switching signals VH d and VL d . In response to the pulse signal PW d , the pre-driving circuit N 3 generates a pair of switching signals WH d and WL d .
- the pre-driving circuits N 1 , N 2 , and N 3 not only enhances the driving ability but also creates the non-overlapping characteristic for the waveforms of each pair of the switching signals UH d and UL d , VH d and VL d , and WH d and WL d .
- a three-phase switching circuit 15 has a pair of switches S 1 and S 2 , a pair of switches S 3 and S 4 , and a pair of switches S 5 and S 6 , each pair being controlled by the switching signals UH d and UL d , VH d and VL d , and WH d and WL d , respectively. More specifically, the switch S 1 is coupled between a drive voltage source Vdd and the coil U while the switch S 2 is coupled between the coil U and a ground potential. The switching signal UH d is supplied to a terminal U 1 for controlling the switch S 1 while the switching signal UL d is supplied to a terminal U 2 for controlling the switch S 2 .
- a motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil U when the switch S 1 is turned ON and is allowed to flow from the coil U to the ground potential when the switch S 2 is turned ON.
- the switch S 3 is coupled between the drive voltage source Vdd and the coil V while the switch S 4 is coupled between the coil V and the ground potential.
- the switching signal VH d is supplied to a terminal V 1 for controlling the switch S 3 while the switching signal VL d is supplied to a terminal V 2 for controlling the switch S 4 . Therefore, the motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil V when the switch S 3 is turned ON and is allowed to flow from the coil V to the ground potential when the switch S 4 is turned ON.
- the switch S 5 is coupled between the drive voltage source Vdd and the coil W while the switch S 6 is coupled between the coil W and the ground potential.
- the switching signal WH d is supplied to a terminal W 1 for controlling the switch S 5 while the switching signal WL d is supplied to a terminal W 2 for controlling the switch S 6 . Therefore, the motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil W when the switch S 5 is turned ON and is allowed to flow from the coil W to the ground potential when the switch S 6 is turned ON.
- each of the switches S 1 , S 3 , and S 5 is implemented by a PMOS transistor while each of the switches S 2 , S 4 , and S 6 is implemented by an NMOS transistor. In another embodiment of the present invention, each of the switches S 1 to S 6 is implemented by a NMOS transistor.
- each pair of the switches S 1 and S 2 , S 3 and S 4 , and S 5 and S 6 is modulated in a hard chopping manner by the corresponding pair of the switching signals UH d and UL d , VH d and VL d , and WH d and WL d .
- the hard chopping modulation is referred to as that the upper-side switch S 1 , S 3 , or S 5 is turned ON/OFF when the lower-side switch S 2 , S 4 , or S 6 is synchronously, but oppositely, turned OFF/ON.
- each pair of the switches S 1 and S 2 , S 3 and S 4 , and S 5 and S 6 is modulated in a soft chopping manner by the corresponding pair of the switching signals UH d and UL d , VH d and VL d , and WH d and WL d .
- the soft chopping modulation is referred to as that the upper-side switch S 1 , S 3 , or S 5 is turned ON/OFF and the lower-side switch S 2 , S 4 , or S 6 keeps OFF during the positive half of the drive signals SU, SV, and SW, and the lower-side switch S 2 , S 4 , or S 6 is turned ON/OFF and the upper-side switch S 1 , S 3 , or S 5 keeps OFF during the negative half of the drive signals SU, SV, and SW.
- the hard and soft chopping modulations have already been disclosed in U.S. Pat. No. 6,710,572, which is incorporated herein by reference.
- a resistor Rs is series-connected between the common node of the lower-side switches S 2 , S 4 , and S 6 and the ground potential.
- the resistor Rs may be series-connected between the common node of the upper-side switches S 1 , S 3 , and S 5 and the drive voltage source Vdd.
- a voltage difference caused by the motor drive current Im flowing through the resistor Rs is supplied as a negative feedback to an inverting input terminal of an error amplifier EA.
- the error amplifier EA compares the voltage difference representative of the motor drive current Im with a current command signal Icom for generating a current error signal Ierr. Subsequently, the signal synthesizing circuit 12 adjusts the amplitudes of the drive signals SU, SV, and SW in accordance with the current error signal Ierr.
- the current error signal Ierr is applied to the signal synthesizing circuit 12 for adjusting the amplitudes of the drive signals SU, SV, and SW
- the present invention is not limited to this.
- the current error signal Ierr may be applied to the oscillating circuit 1 4 for adjusting the amplitude of the high-frequency reference signal T, thereby changing a relative relationship between the amplitudes of the drive signal and the reference signal.
- the current error signal Ierr may be applied to the Hall sensing circuit 11 for adjusting the amplitudes of the positional detection signals HU, HV, and HW, indirectly causing the amplitudes of the drive signals SU, SV, and SW to be adjusted.
- Such techniques regarding the adjustment of the relative relationship between the amplitudes have already been disclosed in U.S. Pat. No. 6,710,568, which is incorporated herein by reference.
- FIG. 3 ( a ) is a detailed circuit diagram showing a first embodiment of a PWM comparing circuit 20 - 1 and a duty-ratio limiting circuit 21 - 1 according to the present invention.
- FIG. 3 ( b ) is a waveform timing chart showing an operation of a first embodiment of a PWM comparing circuit 20 - 1 and a duty-ratio limiting circuit 21 - 1 according to the present invention.
- FIG. 3 ( b ) is a detailed circuit diagram showing a first embodiment of a PWM comparing circuit 20 - 1 and a duty-ratio limiting circuit 21 - 1 according to the present invention.
- FIG. 3 ( b ) is a waveform timing chart showing an operation of a first embodiment of a PWM comparing circuit 20 - 1 and a duty-ratio limiting circuit 21 - 1 according to the present invention.
- FIG. 3 ( b ) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and
- the drive signals SU, SV, and SW are supplied to the PWM comparing circuit 20 - 1 for being individually compared with respect to the high-frequency reference signal T.
- the PWM comparing circuit 20 - 1 includes three comparators CU, CV, and CW, each having an inverting input terminal for respectively receiving the drive signals SU, SV, and SW and a non-inverting terminal for receiving the high-frequency reference signal T.
- the comparator CU Based on the comparison of the drive signal SU with the high-frequency reference signal T, the comparator CU generates a pulse signal PU- 1 .
- the comparator CV Based on the comparison of the drive signal SV with the high-frequency reference signal T, the comparator CV generates a pulse signal PV- 1 .
- the comparator CW Based on the comparison of the drive signal SW with the high-frequency reference signal T, the comparator CW generates a pulse signal PW- 1 .
- the duty-ratio limiting circuit 21 - 1 is used for limiting the duty ratios of the pulse signals PU- 1 , PV- 1 , and PW- 1 .
- a comparator CL is adopted to compare the high-frequency reference signal T with a predetermined negative-half limit level V L for generating a negative-half duty-ratio limit signal PL.
- the negative-half limit level V L is set substantially equal to the valley of the high-frequency reference signal T and, preferably, slightly larger than the valley.
- a comparator CH is adopted to compare the high-frequency reference signal T with a predetermined positive-half limit level V H for generating a positive-half duty-ratio limit signal PH.
- the positive-half limit level V H is set substantially equal to the peak of the high-frequency reference signal T and, preferably, slightly smaller than the peak.
- each of the pulse signals PU- 1 , PV- 1 , and PW- 1 generated by the PWM comparing circuit 20 - 1 is constrained by both of the positive-half duty-ratio limit signal PH and the negative-half duty-ratio limit signal PL so as to limit the duty ratio of the complete cycle.
- the pulse signal PU- 1 is constrained at first by the negative-half duty-ratio limit signal PL through a NAND logic gate NL 1 to form an output signal PU I .
- the output signal PU I is further constrained by the positive-half duty-ratio limit signal PH through a NAND logic gate NH 1 .
- the desirable duty-ratio-limited pulse signal PU- 1 d is effectively achieved.
- the portion of the pulse signal PU- 1 d corresponding to the positive half of the drive signal SU has the duty ratio limited by the positive-half duty-ratio limit signal PH while the portion of the pulse signal PU- 1 d corresponding to the negative half of the drive signal SU has the duty ratio effectively limited by the negative-half duty-ratio limit signal PL.
- a reliable rotation of the motor M is effectively achieved even when the difference between the motor drive current Im and the current command signal Icom becomes too large.
- FIG. 4 ( a ) is a detailed circuit diagram showing a second embodiment of a PWM comparing circuit 20 - 2 and a duty-ratio limiting circuit 21 - 2 according to the present invention.
- FIG. 4 ( b ) is a waveform timing chart showing an operation of a second embodiment of a PWM comparing circuit 20 - 2 and a duty-ratio limiting circuit 21 - 2 according to the present invention.
- FIG. 4 ( b ) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and W of the motor M is operated with similar waveforms.
- the PWM comparing circuit 20 - 2 is implemented by three tri-input comparators CLU, CLV, and CLW.
- the tri-input comparator CLU has two non-inverting input terminals for respectively receiving the drive signal SU and a predetermined negative-half limit level V L , and an inverting input terminal for receiving the high-frequency reference signal T.
- the negative-half limit level V L is set substantially equal to the valley of the high-frequency reference signal T and, preferably, slightly larger than the valley. Once the high-frequency reference signal T becomes smaller than either of the drive signal SU and the negative-half limit level V L , the tri-input comparator CLU is triggered to output a high level.
- the tri-input comparator CLU effectively generates a pulse signal PU- 2 with limitation on the duty ratio during the negative half of the drive signal SU.
- the tri-input comparator CLV effectively generates a pulse signal PV- 2 with limitation on the duty ratio during the negative half of the drive signal SV.
- the tri-input comparator CLW effectively generates a pulse signal PW- 2 with limitation on the duty ratio during the negative half of the drive signal SW.
- the duty-ratio limiting circuit 21 - 2 is used for limiting the positive-half duty ratios of the pulse signals PU- 2 , PV- 2 , and PW- 2 .
- a comparator CH is adopted to compare the high-frequency reference signal T with a predetermined positive-half limit level V H for generating a positive-half duty-ratio limit signal PH.
- the positive-half limit level V H is set substantially equal to the peak of the high-frequency reference signal T and, preferably, slightly smaller than the peak.
- each of the pulse signals PU- 2 , PV- 2 , and PW- 2 generated by the PWM comparing circuit 20 - 2 is constrained by the positive-half duty-ratio limit signal PH so as to limit the duty ratio of the positive half.
- the pulse signal PU- 2 is constrained by the positive-half duty-ratio limit signal PH through a NAND logic gate NH 1 .
- the desirable duty-ratio-limited pulse signal PU- 2 d is effectively achieved.
- the portion of the pulse signal PU- 2 d corresponding to the positive half of the drive signal SU has the duty ratio limited by the positive-half duty-ratio limit signal PH while the portion of the pulse signal PU- 2 d corresponding to the negative half of the drive signal SU has the duty ratio effectively limited by the negative-half duty-ratio limit signal PL.
- a reliable rotation of the motor M is effectively achieved even when the difference between the motor drive current Im and the current command signal Icom becomes too large.
- FIG. 5 ( a ) is a detailed circuit diagram showing a third embodiment of a PWM comparing circuit 20 - 3 and a duty-ratio limiting circuit 21 - 3 according to the present invention.
- FIG. 5 ( b ) is a waveform timing chart showing an operation of a third embodiment of a PWM comparing circuit 20 - 3 and a duty-ratio limiting circuit 21 - 3 according to the present invention.
- FIG. 5 ( b ) is a detailed circuit diagram showing a third embodiment of a PWM comparing circuit 20 - 3 and a duty-ratio limiting circuit 21 - 3 according to the present invention.
- FIG. 5 ( b ) is a waveform timing chart showing an operation of a third embodiment of a PWM comparing circuit 20 - 3 and a duty-ratio limiting circuit 21 - 3 according to the present invention.
- FIG. 5 ( b ) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and
- the PWM comparing circuit 20 - 3 is implemented by three tri-input comparators CHU, CHV, and CHW.
- the tri-input comparator CHU has two inverting input terminals for respectively receiving the drive signal SU and a predetermined positive-half limit level V H , and a non-inverting input terminal for receiving the high-frequency reference signal T.
- the positive-half limit level V H is set substantially equal to the peak of the high-frequency reference signal T and, preferably, slightly smaller than the peak. Once the high-frequency reference signal T becomes larger than either of the drive signal SU and the positive-half limit level V H , the tri-input comparator CHU is triggered to output a high level.
- the tri-input comparator CHU effectively generates a pulse signal PU- 3 with limitation on the duty ratio during the positive half of the drive signal SU.
- the tri-input comparator CHV effectively generates a pulse signal PV- 3 with limitation on the duty ratio during the positive half of the drive signal SV.
- the tri-input comparator CHW effectively generates a pulse signal PW- 3 with limitation on the duty ratio during the positive half of the drive signal SW.
- the duty-ratio limiting circuit 21 - 3 is used for limiting the negative-half duty ratios of the pulse signals PU- 3 , PV- 3 , and PW- 3 .
- a comparator CL is adopted to compare the high-frequency reference signal T with a predetermined negative-half limit level V L for generating a negative-half duty-ratio limit signal PL.
- the negative-half limit level V L is set substantially equal to the valley of the high-frequency reference signal T and, preferably, slightly larger than the valley.
- each of the pulse signals PU- 3 , PV- 3 , and PW- 3 generated by the PWM comparing circuit 20 - 3 is constrained by the negative-half duty-ratio limit signal PL so as to limit the duty ratio of the negative half.
- the pulse signal PU- 3 is constrained by the negative-half duty-ratio limit signal PL through a NAND logic gate NL 1 .
- the desirable duty-ratio-limited pulse signal PU- 3 d is effectively achieved.
- the portion of the pulse signal PU- 3 d corresponding to the positive half of the drive signal SU has the duty ratio limited by the positive-half duty-ratio limit signal PH while the portion of the pulse signal PU- 3 d corresponding to the negative half of the drive signal SU has the duty ratio effectively limited by the negative-half duty-ratio limit signal PL.
- a reliable rotation of the motor M is effectively achieved even when the difference between the motor drive current Im and the current command signal Icom becomes too large.
- FIG. 6 ( a ) is a detailed circuit diagram showing a fourth embodiment of a PWM comparing circuit 20 - 4 and a duty-ratio limiting circuit 21 - 4 according to the present invention.
- FIG. 6 ( b ) is a waveform timing chart showing an operation of a fourth embodiment of a PWM comparing circuit 20 - 4 and a duty-ratio limiting circuit 21 - 4 according to the present invention.
- FIG. 6 ( b ) is a detailed circuit diagram showing a fourth embodiment of a PWM comparing circuit 20 - 4 and a duty-ratio limiting circuit 21 - 4 according to the present invention.
- FIG. 6 ( b ) is a waveform timing chart showing an operation of a fourth embodiment of a PWM comparing circuit 20 - 4 and a duty-ratio limiting circuit 21 - 4 according to the present invention.
- FIG. 6 ( b ) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and
- the PWM comparing circuit 20 - 4 is implemented by three tri-input comparators CLU, CLV, and CLW and three tri-input comparators CHU, CHV, and CHW.
- the PWM comparing circuit 20 - 4 is a combination of the PWM comparing circuit 20 - 2 of FIG. 4 ( a ) and the PWM comparing circuit 20 - 3 of FIG. 5 ( a ). Consequently, on one hand, the three tri-input comparators CLU, CLV, and CLW effectively generate three pulse signals PU- 4 a , PV- 4 a , and PW- 4 a with limitation on the duty ratio during the negative half of the drive signals SU, SV, and SW.
- the three tri-input comparators CHU, CHV, and CHW effectively generate three pulse signals PU- 4 b , PV- 4 b , and PW- 4 b with limitation on the duty ratio during the positive half of the drive signals SU, SV, and SW.
- the duty-ratio limiting circuit 21 - 4 is provided with three inverters 11 , 12 , and 13 for generating three inverted pulse signals PU- 4 a ′, PV- 4 a ′, and PW- 4 a ′. Additionally, the duty-ratio limiting circuit 21 - 4 is provided with three multiplexers M 1 , M 2 , and M 3 .
- the multiplexer M 1 has two source inputs for receiving the inverted pulse signal PU- 4 a ′ and the pulse signal PU- 4 b .
- the multiplexer M 1 further has one selection input for receiving a polarity selection signal PSU indicative of the polarity of the drive signal SU, i.e., the positive-half state or the negative-half state.
- the polarity selection signal PSU controls the multiplexer M 1 to output the inverted pulse signal PU- 4 a ′ as a duty-ratio-limited pulse signal PU- 4 d , thereby achieving the limitation on the duty ratio.
- the polarity selection signal PSU controls the multiplexer M 1 to output the pulse signal PU- 4 b as a duty-ratio-limited pulse signal PU- 4 d , thereby achieving the limitation on the duty ratio.
- the multiplexer M 2 has two source inputs for receiving the inverted pulse signal PV- 4 a ′ and the pulse signal PV- 4 b .
- the multiplexer M 2 further has one selection input for receiving a polarity selection signal PSV indicative of the polarity of the drive signal SV, i.e., the positive-half state or the negative-half state.
- a polarity selection signal PSV indicative of the polarity of the drive signal SV, i.e., the positive-half state or the negative-half state.
- the polarity selection signal PSV controls the multiplexer M 2 to output the inverted pulse signal PV- 4 a ′ as a duty-ratio-limited pulse signal PV- 4 d , thereby achieving the limitation on the duty ratio.
- the polarity selection signal PSV controls the multiplexer M 2 to output the pulse signal PV- 4 b as a duty-ratio-limited pulse signal PV- 4 d , thereby achieving the limitation on the duty ratio.
- the multiplexer M 3 has two source inputs for receiving the inverted pulse signal PW- 4 a ′ and the pulse signal PW- 4 b .
- the multiplexer M 2 further has one selection input for receiving a polarity selection signal PSW indicative of the polarity of the drive signal SW, i.e., the positive-half state or the negative-half state.
- the polarity selection signal PSW controls the multiplexer M 3 to output the inverted pulse signal PW- 4 a ′ as a duty-ratio-limited pulse signal PW- 4 d , thereby achieving the limitation on the duty ratio.
- the polarity selection signal PSW controls the multiplexer M 3 to output the pulse signal PW- 4 b as a duty-ratio-limited pulse signal PW- 4 d , thereby achieving the limitation on the duty ratio.
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- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
Description
- This application is a continuation-in-part of, and claims benefit of the filling date of, and hereby incorporates fully by reference, a parent application entitled “Brushless Motor Drive Device,” Ser. No. 10/711,235, filed Sep. 3, 2004, and assigned to the assignee of the present application.
- 1. Field of the Invention
- The present invention relates to a motor drive device and, more particularly, to a motor drive device for a brushless DC motor.
- 2. Description of the Prior Art
-
FIG. 1 (a) is a circuit block diagram showing a conventional brushless motor drive device. Referring toFIG. 1 (a), a motor M is a three-phase DC brushless motor having three phase coils U, V, and W. AHall sensing circuit 11 is arranged around the motor M for detecting a position of a rotor of the motor M, thereby generating three positional detection signals HU, HV, and HW. In response to the positional detection signals HU, HV, and HW, asignal synthesizing circuit 12 generates three sinusoidal drive signals SU, SV, and SW. Subsequently, the sinusoidal drive signals SU, SV, and SW are input to a pulse width modulation (PWM) comparingcircuit 13 for being individually compared with respect to a high-frequency triangular signal T generated by an oscillatingcircuit 1 4. Based on the comparison of the sinusoidal drive signals SU, SV, and SW individually with the high-frequency triangular signal T, thePWM comparing circuit 13 generates three pulse signals PU, PV, and PW to be supplied to three pre-drivers N1, N2, and N3. In response to the pulse signal PU, the pre-driver N1 generates a pair of switching signals UH and UL. In response to the pulse signal PV, the pre-driver N2 generates a pair of switching signals VH and VL. In response to the pulse signal PW, the pre-driver N3 generates a pair of switching signals WH and WL. - A three-
phase switching circuit 15 has a pair of switches S1 and S2, a pair of switches S3 and S4, and a pair of switches S5 and S6, each pair being controlled by one corresponding pair of the switching signals UH and UL, VH and VL, and WH and WL. A motor drive current Im is allowed to flow from a drive voltage source Vdd to the coil U when the switch S1 becomes short-circuited and to flow from the coil U to a ground potential when the switch S2 becomes short-circuited. The motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil V when the switch S3 becomes short-circuited and to flow from the coil V to the ground potential when the switch S4 becomes short-circuited. The motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil W when the switch S5 becomes short-circuited and to flow from the coil W to the ground potential when the switch S6 becomes short-circuited. - For detecting the motor drive current Im, a resistor Rs is series-connected between the common connecting point of the switches S2, S4, and S6 and the ground potential. A voltage difference caused by the motor drive current Im flowing through the resistor Rs is supplied as a negative feedback to an inverting input terminal of an error amplifier EA. The error amplifier EA compares the voltage difference representative of the motor drive current Im with a current command signal Icom for generating a current error signal Ierr. Subsequently, the
signal synthesizing circuit 12 adjusts the amplitudes of the sinusoidal drive signals SU, SV, and SW in accordance with the current error signal Ierr. -
FIG. 1 (b) is a waveform timing chart showing operations of the conventional brushless motor drive device. For the sake of simplicity, only is illustrated inFIG. 1 (b) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and W of the motor M is operated with similar waveforms. Referring toFIG. 1 (b), the pulse signal PU is generated from the comparison of the sinusoidal drive signal SU and the high-frequency triangular signal T through using thePWM comparing circuit 13. More specifically, the HIGH level of the pulse signal PU corresponds to an interval of time when the sinusoidal drive signal SU goes higher than the high-frequency triangular signal T and the LOW level of the pulse signal PU corresponds to an interval of time when the sinusoidal drive signal SU goes lower than the high-frequency triangular signal T. In response to the pulse signal PU, the pre-driver N1 generates the switching signals UH and UL for controlling the switches S1 and S2, respectively. - In order to regulate the motor drive current Im to follow the current command signal Icom, the error amplifier EA supplies the current error signal Ierr to the
signal synthesizing circuit 12 for adjusting the amplitude of the sinusoidal drive signal SU. For example, when the motor drive current Im is smaller than the current command signal Icom, the current error signal Ierr controls thesignal synthesizing circuit 12 to increase the amplitude of the sinusoidal drive signal SU so as to obtain a sinusoidal drive signal SU′. As clearly seen fromFIG. 1 (b), the sinusoidal drive signal SU′ with a larger amplitude causes thePWM comparing circuit 13 to generate a pulse signal PU′ with a larger duty ratio. In response to the pulse signal PU′ with the larger duty ratio, the three-phase switching circuit 15 causes an increase of the motor drive current Im and therefore the motor drive current Im approaches to the current command signal Icom. - However, when the difference between the motor drive current Im and the current command signal Icom becomes too large, for example, at the activation of the motor M the motor drive current Im starts from zero, the
signal synthesizing circuit 12 may even generate a sinusoidal drive signal SU″ with an amplitude larger than that of the high-frequency triangular T in response to an extremely great current error signal Ierr. As a result, thePWM comparing circuit 13 generates a pulse signal PU″ with a frequency lower than that of the high-frequency triangular signal T. The low-frequency pulse signal PU″ induces a large ripple to the motor torque and deteriorates the smooth rotation of the motor M. Moreover, the low-frequency pulse signal PU″ remains at the HIGH/LOW level each cycle for a relatively long time such that the three-phase switching circuit 15 supplies the motor drive current Im in the continuous mode other than the PWM mode. The long-time continuous supply of the motor drive current Im may damage the motor M and the three-phase switching circuit 15. Also, the temperature rising caused by the large heat dissipation may trigger the thermal shutdown mechanism. - In view of the above-mentioned problems, an object of the present invention is to provide a brushless motor drive device capable of limiting the duty ratio of the pulse signal.
- Another object of the present invention is to provide a brushless motor drive device capable of preventing the frequency of the pulse signal from becoming lower.
- Still another object of the present invention is to provide a brushless motor drive device capable of preventing the pulse signal from remaining at the HIGH/LOW level for a relatively long time.
- According to one aspect of the present invention, a brushless motor drive device is provided with a comparing circuit and a limiting circuit. The comparing circuit compares a drive signal and a reference signal to generate a pulse signal. The limiting circuit has a first circuit, a second circuit, a first logic circuit, and a second logic circuit. The first circuit generates a first-half duty-ratio limit signal. The second circuit generates a second-half duty-ratio limit signal. The first logic circuit constrains a duty ratio of the pulse signal by using the first-half duty-ratio limit signal and then generating an output signal. The second logic circuit constrains a duty ratio of the output signal of the first logic circuit by using the second-half duty-ratio limit signal.
- According to another aspect of the present invention, a brushless motor drive device is provided with a comparing circuit and a limiting circuit. The comparing circuit is implemented by at least one tri-input comparator for comparing a drive signal, a reference signal, and a first-half limit level to generate a pulse signal with limitation on a duty ratio of a first half of the pulse signal. The limiting circuit has a circuit for generating a second-half duty-ratio limit signal, and a logic circuit for constraining a duty ratio of a second half of the pulse signal by using the second-half duty-ratio limit signal.
- According to still another aspect of the present invention, a brushless motor drive device is provided with a comparing circuit and a limiting circuit. The comparing circuit is implemented by at least one first tri-input comparator and at least one second tri-input comparator. The first tri-input comparator compares a drive signal, a reference signal, and a first-half limit level to generate a first pulse signal with limitation on a duty ratio of a first half of the first pulse signal. The second tri-input comparator compares a drive signal, a reference signal, and a second-half limit level to generate a second pulse signal with limitation on a duty ratio of a second half of the second pulse signal.
- The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following descriptions and accompanying drawings, wherein:
-
FIG. 1 (a) is a circuit block diagram showing a conventional brushless motor drive device; -
FIG. 1 (b) is a waveform timing chart showing operations of a conventional brushless motor drive device; -
FIG. 2 is a circuit block diagram showing a brushless motor drive device according to the present invention; -
FIG. 3 (a) is a detailed circuit diagram showing a first embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention; -
FIG. 3 (b) is a waveform timing chart showing an operation of a first embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention; -
FIG. 4 (a) is a detailed circuit diagram showing a second embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention; -
FIG. 4 (b) is a waveform timing chart showing an operation of a second embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention; -
FIG. 5 (a) is a detailed circuit diagram showing a third embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention; -
FIG. 5 (b) is a waveform timing chart showing an operation of a third embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention; -
FIG. 6 (a) is a detailed circuit diagram showing a fourth embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention; and -
FIG. 6 (b) is a waveform timing chart showing an operation of a fourth embodiment of a PWM comparing circuit and a duty-ratio limiting circuit according to the present invention. - The preferred embodiments according to the present invention will be described in detail with reference to the drawings.
-
FIG. 2 is a circuit block diagram showing a brushless motor drive device according to the present invention. Referring toFIG. 2 , a motor M is a three-phase DC brushless motor having three phase coils U, V, and W. AHall sensing circuit 11 may include three Hall sensors and three Hall amplifiers for the three phase coils U, V, and W, respectively. TheHall sensing circuit 11 is arranged around the motor M for generating three positional detection signals HU, HV, and HW representative of the positional relationships between a rotor of the motor M and the three phase coils U, V, and W, respectively. Each of the positional detection signals HU, HV, and HW is a sinusoidal signal synchronous with the rotation of the motor M and is 120 degrees out of phase with respect to each other. In response to the positional detection signals HU, HV, and HW, asignal synthesizing circuit 12 generates three drive signals SU, SV, and SW. - In one embodiment of the present invention, the drive signals SU, SV, and SW may be implemented by shifting 30 degrees the phases of the corresponding positional detection signals HU, HV, and HW, and therefore the waveforms of the drive signals SU, SV, and SW still remain sinusoidal. In another embodiment of the present invention, the drive signals SU, SV, and SW may be implemented by superposing an appropriate correction signal for compensating the turn-on delay onto the corresponding positional detection signals HU, HV, and HW after the 30-degree phase shifting. Consequently, the waveforms of the drive signals SU, SV, and SW become the superposition of the sinusoidal signal and the correction signal. Many kinds of correction signals have already been disclosed in U.S. Pat. No. 5,811,949, which is incorporated herein by reference.
- In one embodiment of the present invention, a high-frequency reference signal T may be implemented by a single triangular signal in which an average value of an amplitude of the triangular signal substantially coincides with an average value of an amplitude of each of the drive signals SU, SV, and SW. In another embodiment of the present invention, the high-frequency reference signal T may be implemented by combining an upper triangular signal and a lower triangular signal, both of which have the same frequency. The valley of the upper triangular signal substantially corresponds in time to the peak of the lower triangular signal. The valley of the upper triangular signal substantially coincides with the average value of the amplitude of each of the drive signals SU, SV, and SW. The peak of the lower triangular signal substantially coincides with the average value of the amplitude of each of the drive signals SU, SV, and SW. Such upper and lower triangular signals have already been disclosed in U.S. Pat. No. 3,585,517, which is incorporated herein by reference.
- Based on comparison of the drive signals SU, SV, and SW and the high-frequency reference signal T, a
PWM comparing circuit 20 and a duty-ratio limiting circuit 21 are operated in coordination for generating three duty-ratio-limited pulse signals PUd, PVd, and PWd. (A variety of embodiments of thePWM comparing circuit 20 and the duty-ratio limiting circuit 21 will be described in detail later with reference to the drawings.) In response to the pulse signal PUd, a pre-driving circuit N1 generates a pair of switching signals UHd and ULd. In response to the pulse signal PVd, the pre-driving circuit N2 generates a pair of switching signals VHd and VLd. In response to the pulse signal PWd, the pre-driving circuit N3 generates a pair of switching signals WHd and WLd. The pre-driving circuits N1, N2, and N3 not only enhances the driving ability but also creates the non-overlapping characteristic for the waveforms of each pair of the switching signals UHd and ULd, VHd and VLd, and WHd and WLd. - A three-
phase switching circuit 15 has a pair of switches S1 and S2, a pair of switches S3 and S4, and a pair of switches S5 and S6, each pair being controlled by the switching signals UHd and ULd, VHd and VLd, and WHd and WLd, respectively. More specifically, the switch S1 is coupled between a drive voltage source Vdd and the coil U while the switch S2 is coupled between the coil U and a ground potential. The switching signal UHd is supplied to a terminal U1 for controlling the switch S1 while the switching signal ULd is supplied to a terminal U2 for controlling the switch S2. Therefore, a motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil U when the switch S1 is turned ON and is allowed to flow from the coil U to the ground potential when the switch S2 is turned ON. The switch S3 is coupled between the drive voltage source Vdd and the coil V while the switch S4 is coupled between the coil V and the ground potential. The switching signal VHd is supplied to a terminal V1 for controlling the switch S3 while the switching signal VLd is supplied to a terminal V2 for controlling the switch S4. Therefore, the motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil V when the switch S3 is turned ON and is allowed to flow from the coil V to the ground potential when the switch S4 is turned ON. The switch S5 is coupled between the drive voltage source Vdd and the coil W while the switch S6 is coupled between the coil W and the ground potential. The switching signal WHd is supplied to a terminal W1 for controlling the switch S5 while the switching signal WLd is supplied to a terminal W2 for controlling the switch S6. Therefore, the motor drive current Im is allowed to flow from the drive voltage source Vdd to the coil W when the switch S5 is turned ON and is allowed to flow from the coil W to the ground potential when the switch S6 is turned ON. - In one embodiment of the present invention, each of the switches S1, S3, and S5 is implemented by a PMOS transistor while each of the switches S2, S4, and S6 is implemented by an NMOS transistor. In another embodiment of the present invention, each of the switches S1 to S6 is implemented by a NMOS transistor.
- In one embodiment of the present invention, each pair of the switches S1 and S2, S3 and S4, and S5 and S6 is modulated in a hard chopping manner by the corresponding pair of the switching signals UHd and ULd, VHd and VLd, and WHd and WLd. The hard chopping modulation is referred to as that the upper-side switch S1, S3, or S5 is turned ON/OFF when the lower-side switch S2, S4, or S6 is synchronously, but oppositely, turned OFF/ON. In another embodiment of the present invention, each pair of the switches S1 and S2, S3 and S4, and S5 and S6 is modulated in a soft chopping manner by the corresponding pair of the switching signals UHd and ULd, VHd and VLd, and WHd and WLd. The soft chopping modulation is referred to as that the upper-side switch S1, S3, or S5 is turned ON/OFF and the lower-side switch S2, S4, or S6 keeps OFF during the positive half of the drive signals SU, SV, and SW, and the lower-side switch S2, S4, or S6 is turned ON/OFF and the upper-side switch S1, S3, or S5 keeps OFF during the negative half of the drive signals SU, SV, and SW. The hard and soft chopping modulations have already been disclosed in U.S. Pat. No. 6,710,572, which is incorporated herein by reference.
- For detecting the motor drive current Im, a resistor Rs is series-connected between the common node of the lower-side switches S2, S4, and S6 and the ground potential. In another embodiment of the present invention, the resistor Rs may be series-connected between the common node of the upper-side switches S1, S3, and S5 and the drive voltage source Vdd. A voltage difference caused by the motor drive current Im flowing through the resistor Rs is supplied as a negative feedback to an inverting input terminal of an error amplifier EA. The error amplifier EA compares the voltage difference representative of the motor drive current Im with a current command signal Icom for generating a current error signal Ierr. Subsequently, the
signal synthesizing circuit 12 adjusts the amplitudes of the drive signals SU, SV, and SW in accordance with the current error signal Ierr. - Although in
FIG. 2 the current error signal Ierr is applied to thesignal synthesizing circuit 12 for adjusting the amplitudes of the drive signals SU, SV, and SW, the present invention is not limited to this. In another embodiment of the present invention, the current error signal Ierr may be applied to theoscillating circuit 1 4 for adjusting the amplitude of the high-frequency reference signal T, thereby changing a relative relationship between the amplitudes of the drive signal and the reference signal. In still another embodiment of the present invention, the current error signal Ierr may be applied to theHall sensing circuit 11 for adjusting the amplitudes of the positional detection signals HU, HV, and HW, indirectly causing the amplitudes of the drive signals SU, SV, and SW to be adjusted. Such techniques regarding the adjustment of the relative relationship between the amplitudes have already been disclosed in U.S. Pat. No. 6,710,568, which is incorporated herein by reference. -
FIG. 3 (a) is a detailed circuit diagram showing a first embodiment of a PWM comparing circuit 20-1 and a duty-ratio limiting circuit 21-1 according to the present invention.FIG. 3 (b) is a waveform timing chart showing an operation of a first embodiment of a PWM comparing circuit 20-1 and a duty-ratio limiting circuit 21-1 according to the present invention. For the sake of simplicity, only is illustrated inFIG. 3 (b) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and W of the motor M is operated with similar waveforms. - The drive signals SU, SV, and SW are supplied to the PWM comparing circuit 20-1 for being individually compared with respect to the high-frequency reference signal T. More specifically, the PWM comparing circuit 20-1 includes three comparators CU, CV, and CW, each having an inverting input terminal for respectively receiving the drive signals SU, SV, and SW and a non-inverting terminal for receiving the high-frequency reference signal T. Based on the comparison of the drive signal SU with the high-frequency reference signal T, the comparator CU generates a pulse signal PU-1. Based on the comparison of the drive signal SV with the high-frequency reference signal T, the comparator CV generates a pulse signal PV-1. Based on the comparison of the drive signal SW with the high-frequency reference signal T, the comparator CW generates a pulse signal PW-1.
- The duty-ratio limiting circuit 21-1 is used for limiting the duty ratios of the pulse signals PU-1, PV-1, and PW-1. A comparator CL is adopted to compare the high-frequency reference signal T with a predetermined negative-half limit level VL for generating a negative-half duty-ratio limit signal PL. The negative-half limit level VL is set substantially equal to the valley of the high-frequency reference signal T and, preferably, slightly larger than the valley. A comparator CH is adopted to compare the high-frequency reference signal T with a predetermined positive-half limit level VH for generating a positive-half duty-ratio limit signal PH. The positive-half limit level VH is set substantially equal to the peak of the high-frequency reference signal T and, preferably, slightly smaller than the peak. Subsequently, each of the pulse signals PU-1, PV-1, and PW-1 generated by the PWM comparing circuit 20-1 is constrained by both of the positive-half duty-ratio limit signal PH and the negative-half duty-ratio limit signal PL so as to limit the duty ratio of the complete cycle. For example, the pulse signal PU-1 is constrained at first by the negative-half duty-ratio limit signal PL through a NAND logic gate NL1 to form an output signal PUI. Then, the output signal PUI is further constrained by the positive-half duty-ratio limit signal PH through a NAND logic gate NH1. As a result, the desirable duty-ratio-limited pulse signal PU-1 d is effectively achieved.
- Therefore, the portion of the pulse signal PU-1 d corresponding to the positive half of the drive signal SU has the duty ratio limited by the positive-half duty-ratio limit signal PH while the portion of the pulse signal PU-1 d corresponding to the negative half of the drive signal SU has the duty ratio effectively limited by the negative-half duty-ratio limit signal PL. According to the first embodiment of the present invention, a reliable rotation of the motor M is effectively achieved even when the difference between the motor drive current Im and the current command signal Icom becomes too large.
-
FIG. 4 (a) is a detailed circuit diagram showing a second embodiment of a PWM comparing circuit 20-2 and a duty-ratio limiting circuit 21-2 according to the present invention.FIG. 4 (b) is a waveform timing chart showing an operation of a second embodiment of a PWM comparing circuit 20-2 and a duty-ratio limiting circuit 21-2 according to the present invention. For the sake of simplicity, only is illustrated inFIG. 4 (b) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and W of the motor M is operated with similar waveforms. - The PWM comparing circuit 20-2 is implemented by three tri-input comparators CLU, CLV, and CLW. The tri-input comparator CLU has two non-inverting input terminals for respectively receiving the drive signal SU and a predetermined negative-half limit level VL, and an inverting input terminal for receiving the high-frequency reference signal T. The negative-half limit level VL is set substantially equal to the valley of the high-frequency reference signal T and, preferably, slightly larger than the valley. Once the high-frequency reference signal T becomes smaller than either of the drive signal SU and the negative-half limit level VL, the tri-input comparator CLU is triggered to output a high level. Therefore, the tri-input comparator CLU effectively generates a pulse signal PU-2 with limitation on the duty ratio during the negative half of the drive signal SU. Likely, the tri-input comparator CLV effectively generates a pulse signal PV-2 with limitation on the duty ratio during the negative half of the drive signal SV. The tri-input comparator CLW effectively generates a pulse signal PW-2 with limitation on the duty ratio during the negative half of the drive signal SW.
- The duty-ratio limiting circuit 21-2 is used for limiting the positive-half duty ratios of the pulse signals PU-2, PV-2, and PW-2. A comparator CH is adopted to compare the high-frequency reference signal T with a predetermined positive-half limit level VH for generating a positive-half duty-ratio limit signal PH. The positive-half limit level VH is set substantially equal to the peak of the high-frequency reference signal T and, preferably, slightly smaller than the peak. Subsequently, each of the pulse signals PU-2, PV-2, and PW-2 generated by the PWM comparing circuit 20-2 is constrained by the positive-half duty-ratio limit signal PH so as to limit the duty ratio of the positive half. For example, the pulse signal PU-2 is constrained by the positive-half duty-ratio limit signal PH through a NAND logic gate NH1. As a result, the desirable duty-ratio-limited pulse signal PU-2 d is effectively achieved.
- Therefore, the portion of the pulse signal PU-2 d corresponding to the positive half of the drive signal SU has the duty ratio limited by the positive-half duty-ratio limit signal PH while the portion of the pulse signal PU-2 d corresponding to the negative half of the drive signal SU has the duty ratio effectively limited by the negative-half duty-ratio limit signal PL. According to the second embodiment of the present invention, a reliable rotation of the motor M is effectively achieved even when the difference between the motor drive current Im and the current command signal Icom becomes too large.
-
FIG. 5 (a) is a detailed circuit diagram showing a third embodiment of a PWM comparing circuit 20-3 and a duty-ratio limiting circuit 21-3 according to the present invention.FIG. 5 (b) is a waveform timing chart showing an operation of a third embodiment of a PWM comparing circuit 20-3 and a duty-ratio limiting circuit 21 -3 according to the present invention. For the sake of simplicity, only is illustrated inFIG. 5 (b) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and W of the motor M is operated with similar waveforms. - The PWM comparing circuit 20-3 is implemented by three tri-input comparators CHU, CHV, and CHW. The tri-input comparator CHU has two inverting input terminals for respectively receiving the drive signal SU and a predetermined positive-half limit level VH, and a non-inverting input terminal for receiving the high-frequency reference signal T. The positive-half limit level VH is set substantially equal to the peak of the high-frequency reference signal T and, preferably, slightly smaller than the peak. Once the high-frequency reference signal T becomes larger than either of the drive signal SU and the positive-half limit level VH, the tri-input comparator CHU is triggered to output a high level. Therefore, the tri-input comparator CHU effectively generates a pulse signal PU-3 with limitation on the duty ratio during the positive half of the drive signal SU. Likely, the tri-input comparator CHV effectively generates a pulse signal PV-3 with limitation on the duty ratio during the positive half of the drive signal SV. The tri-input comparator CHW effectively generates a pulse signal PW-3 with limitation on the duty ratio during the positive half of the drive signal SW.
- The duty-ratio limiting circuit 21-3 is used for limiting the negative-half duty ratios of the pulse signals PU-3, PV-3, and PW-3. A comparator CL is adopted to compare the high-frequency reference signal T with a predetermined negative-half limit level VL for generating a negative-half duty-ratio limit signal PL. The negative-half limit level VL is set substantially equal to the valley of the high-frequency reference signal T and, preferably, slightly larger than the valley. Subsequently, each of the pulse signals PU-3, PV-3, and PW-3 generated by the PWM comparing circuit 20-3 is constrained by the negative-half duty-ratio limit signal PL so as to limit the duty ratio of the negative half. For example, the pulse signal PU-3 is constrained by the negative-half duty-ratio limit signal PL through a NAND logic gate NL1. As a result, the desirable duty-ratio-limited pulse signal PU-3 d is effectively achieved.
- Therefore, the portion of the pulse signal PU-3 d corresponding to the positive half of the drive signal SU has the duty ratio limited by the positive-half duty-ratio limit signal PH while the portion of the pulse signal PU-3 d corresponding to the negative half of the drive signal SU has the duty ratio effectively limited by the negative-half duty-ratio limit signal PL. According to the third embodiment of the present invention, a reliable rotation of the motor M is effectively achieved even when the difference between the motor drive current Im and the current command signal Icom becomes too large.
-
FIG. 6 (a) is a detailed circuit diagram showing a fourth embodiment of a PWM comparing circuit 20-4 and a duty-ratio limiting circuit 21-4 according to the present invention.FIG. 6 (b) is a waveform timing chart showing an operation of a fourth embodiment of a PWM comparing circuit 20-4 and a duty-ratio limiting circuit 21-4 according to the present invention. For the sake of simplicity, only is illustrated inFIG. 6 (b) the operational waveforms associated with the coil U of the motor M since each of the phase coils U, V, and W of the motor M is operated with similar waveforms. - The PWM comparing circuit 20-4 is implemented by three tri-input comparators CLU, CLV, and CLW and three tri-input comparators CHU, CHV, and CHW. In other words, the PWM comparing circuit 20-4 is a combination of the PWM comparing circuit 20-2 of
FIG. 4 (a) and the PWM comparing circuit 20-3 ofFIG. 5 (a). Consequently, on one hand, the three tri-input comparators CLU, CLV, and CLW effectively generate three pulse signals PU-4 a, PV-4 a, and PW-4 a with limitation on the duty ratio during the negative half of the drive signals SU, SV, and SW. On the other hand, the three tri-input comparators CHU, CHV, and CHW effectively generate three pulse signals PU-4 b, PV-4 b, and PW-4 b with limitation on the duty ratio during the positive half of the drive signals SU, SV, and SW. - The duty-ratio limiting circuit 21-4 is provided with three
inverters - Likely, the multiplexer M2 has two source inputs for receiving the inverted pulse signal PV-4 a′ and the pulse signal PV-4 b. The multiplexer M2 further has one selection input for receiving a polarity selection signal PSV indicative of the polarity of the drive signal SV, i.e., the positive-half state or the negative-half state. When the drive signal SV is at the positive-half state, the polarity selection signal PSV controls the multiplexer M2 to output the inverted pulse signal PV-4 a′ as a duty-ratio-limited pulse signal PV-4 d, thereby achieving the limitation on the duty ratio. When the drive signal SV is at the negative-half state, the polarity selection signal PSV controls the multiplexer M2 to output the pulse signal PV-4 b as a duty-ratio-limited pulse signal PV-4 d, thereby achieving the limitation on the duty ratio.
- Likely, the multiplexer M3 has two source inputs for receiving the inverted pulse signal PW-4 a′ and the pulse signal PW-4 b. The multiplexer M2 further has one selection input for receiving a polarity selection signal PSW indicative of the polarity of the drive signal SW, i.e., the positive-half state or the negative-half state. When the drive signal SW is at the positive-half state, the polarity selection signal PSW controls the multiplexer M3 to output the inverted pulse signal PW-4 a′ as a duty-ratio-limited pulse signal PW-4 d, thereby achieving the limitation on the duty ratio. When the drive signal SW is at the negative-half state, the polarity selection signal PSW controls the multiplexer M3 to output the pulse signal PW-4 b as a duty-ratio-limited pulse signal PW-4 d, thereby achieving the limitation on the duty ratio.
- While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.
Claims (19)
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US10/907,240 Expired - Fee Related US7015663B1 (en) | 2004-09-03 | 2005-03-25 | Brushless motor drive device |
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Cited By (2)
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US7164245B1 (en) * | 2006-01-24 | 2007-01-16 | Aimtron Technology Corp. | Brushless motor drive device |
US20120025746A1 (en) * | 2009-04-22 | 2012-02-02 | Mitsubishi Electric Corporation | Motor, electric equipment, and method of manufacturing motor |
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US8138710B2 (en) * | 2008-08-14 | 2012-03-20 | Sntech Inc. | Power drive of electric motor |
US8076877B2 (en) * | 2008-10-17 | 2011-12-13 | Oteman David G | System and method for controlling power balance in an electrical/mechanical system |
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US20120025746A1 (en) * | 2009-04-22 | 2012-02-02 | Mitsubishi Electric Corporation | Motor, electric equipment, and method of manufacturing motor |
US8912696B2 (en) * | 2009-04-22 | 2014-12-16 | Mitsubishi Electric Corporation | Motor, electric equipment, and method of manufacturing motor for reducing electric corosion of bearings |
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