US20050283975A1 - Circuit board - Google Patents

Circuit board Download PDF

Info

Publication number
US20050283975A1
US20050283975A1 US11/216,648 US21664805A US2005283975A1 US 20050283975 A1 US20050283975 A1 US 20050283975A1 US 21664805 A US21664805 A US 21664805A US 2005283975 A1 US2005283975 A1 US 2005283975A1
Authority
US
United States
Prior art keywords
circuit board
fibers
forming
thickness
core layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/216,648
Inventor
Tongbi Jiang
Yong Du
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US11/216,648 priority Critical patent/US20050283975A1/en
Publication of US20050283975A1 publication Critical patent/US20050283975A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Definitions

  • This invention relates to circuit boards, and more particularly, to increasing circuit board reliability.
  • FIG. 1 shows a cross-sectional view of a prior art ball-grid array (BGA) package 100 which includes printed circuit board 103 coupled to board 105 by solder balls 107 , and die 109 coupled to printed circuit board 103 by adhesive 111 and molding compound 112 .
  • BGA ball-grid array
  • a longstanding and unsolved problem with printed circuit boards in general and with BGA package 100 in particular is that printed circuit board 100 may develop a crack, such as crack 113 .
  • Crack 113 destroys the structural integrity of BGA package 100 .
  • electronic connectors such as electronic connectors 115 and 116 , and as a result, any product in which BGA package 100 is incorporated may malfunction.
  • One method of solving problems associated with printed circuit board cracking and the resulting electronic connection failures is to include a second printed circuit board in the design of an electronic system.
  • the second circuit board is a redundant printed circuit board which mirrors the operation of the primary board, so a system failure occurs only when both the redundant printed circuit board and the primary board fail at the same time.
  • this solution is very expensive and is cost effective only in systems, such as trains, airplanes, or spacecraft, where the cost of failure is high. For systems in which the cost of failure is low, redundant circuit boards are seldom used.
  • a circuit board that includes embedded fibers, which strengthen the board, and a surface layer having a certain thickness range that inhibits the formation of cracks in the circuit board.
  • the present invention provides, in one embodiment, a circuit board including a core layer and a surface layer.
  • a number of fibers are embedded in the core layer.
  • the surface layer has a thickness which is between about 10% and about 30% of the circuit board thickness. Embedding fibers in the core layer increases the strength of the circuit board.
  • a surface layer thickness of between about 10% and about 30% of the circuit board thickness inhibits the formation of cracks in the circuit board, which improves the reliability of circuits mounted on the circuit board and systems in which the circuit board is embedded.
  • the present invention provides a method of fabricating a circuit board having a circuit board thickness.
  • the method includes forming a core layer including a number of fibers, and forming a surface layer on the core layer.
  • the surface layer has a surface layer thickness that is between about 10% and about 30% of the circuit board thickness and is free of fibers.
  • FIG. 1 is an illustration cross-sectional view of a prior art ball-grid array (BGA) package including a circuit board.
  • BGA ball-grid array
  • FIG. 2A is a cross-sectional view of one embodiment of a circuit board assembly according to the teaching of the present invention.
  • FIG. 2B is a cross-sectional view of an alternate embodiment of a circuit board assembly according to the teaching of the present invention.
  • FIG. 2C is a cross-sectional view of a second alternate embodiment of a circuit board assembly according to the teaching of the present invention.
  • FIG. 3 is a block diagram of one embodiment of a computer system suitable for use in connection with the present invention.
  • FIG. 2A is a cross-sectional view of one embodiment of circuit board assembly 200 .
  • Circuit board assembly 200 includes die 201 , printed circuit board 202 , and board 203 .
  • Circuit board 202 is coupled to board 203 by solder balls 204
  • die 201 is coupled to printed circuit board 202 by adhesive 205 and molding compound 206 .
  • Circuit board assembly 200 is sometimes referred to as a ball-grid array, but the present invention is not limited to ball-grid array circuit board assemblies. Any circuit board assembly that includes a circuit board, such as printed circuit board 202 , which is described in more detail below, is suitable for use in connection with the present invention. For example, a circuit board assembly in which a first circuit board is coupled by edge connectors to a second circuit board is suitable for use in connection with the present invention.
  • Die 201 includes an integrated circuit, such as a memory circuit, a processor, an amplifier, or an application specific circuit (ASIC).
  • Memory circuits suitable for use in connection with the present invention include but are not limited to dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, erasable programmable memory (EPROM) circuits, and electrically erasable programmable memory (EEPROM) circuits.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • EPROM erasable programmable memory
  • EEPROM electrically erasable programmable memory
  • Processor circuits suitable for use in connection with the present invention include but are not limited to microprocessors, digital signal processors (DSPs), and reduced instruction set computing (RISC) processors.
  • Amplifier circuits suitable for use in connection with the present invention include but are not limited to operational amplifiers, differential amplifiers, and power amplifiers.
  • Die 201 is coupled to printed circuit board 202 by adhesive 205 , which is selected to maintain a low stress interface between die 201 and circuit board 202 .
  • Any adhesive that has a coefficient of thermal expansion which maintains a low stress interface between die 201 and circuit board 202 during the heating and cooling of circuit board assembly 200 is suitable for use in connection with the present invention.
  • a board 203 such as a circuit board, provides a substrate for mounting a number of circuit boards, such as circuit board 202 , and other electronic or electro-mechanical components.
  • board 203 is a computer system circuit board including a processor.
  • Board 203 may also provide a substrate suitable for securing circuit assembly 200 to a larger package or other housing, such as a cabinet or case.
  • Board 203 is fabricated from materials commonly used in the fabrication of circuit boards, such as polymeric composite materials.
  • a polymeric composite material is phenolic.
  • board 203 is not limited to polymeric composite materials, and other materials, particularly insulating materials, may also be used in the fabrication of board 203 .
  • Solder balls 204 provide a number of signal paths to electronically couple circuit board 202 to board 203 .
  • the number of signal paths permit communication between components mounted on circuit board 202 and on board 203 .
  • Any material that is a good conductor is suitable for use in fabricating solder balls 204 .
  • Tin, gold, copper, silver, and alloys of tin, gold, copper, and silver, are examples of materials suitable for use fabricating solder balls 204 .
  • Circuit board 202 provides a substrate for mounting die 201 and coupling signals to board 203 .
  • circuit board 202 is formed from a polymeric composite material.
  • Circuit board 202 is coupled to die 201 by adhesive 205 .
  • FIG. 2B is a detailed cross-sectional view of one embodiment of circuit board 202 .
  • circuit board 202 includes core layer 208 and surface layer 209 , which is a first layer or a first resin layer.
  • Circuit board 202 may also include slot 211 for routing conductive connectors, such as conductive connectors 207 and 208 shown in FIG. 2A , from above circuit board 202 to below circuit board 202 .
  • Core layer 208 includes one or more fibers 213 embedded in an insulator.
  • Core layer 208 in one embodiment, is fabricated from a resin and has a thickness 212 of between about 0.006 inches and about 0.012 inches.
  • the one or more fibers 213 in one embodiment, are glass fibers having a diameter of between about 0.0005 inches and about 0.001 inches.
  • the one or more fibers 213 are woven fibers, such as woven glass fibers, and have a diameter of between about 0.001 inches and about 0.002 inches.
  • Surface layer 209 in one embodiment, is fabricated from a resin that is free of fibers. In an alternate embodiment, surface layer 209 is fabricated from a resin that is essentially free of fibers. Surface layer 209 is essentially free of fibers when any fibers embedded in surface layer 209 do not significantly increase the likelihood of cracking in circuit board 202 . The inventors discovered that cracks in circuit board 202 frequently occur on the surface of circuit board 202 at stress concentration points located above fiber hills, such as fiber hills 215 and 217 , and that cracks are less likely to occur at stress concentration points located above fiber valleys.
  • stress concentration points occur along an edge of an interface between two surfaces, such as along the edge of adhesive 205 at the interface between adhesive 205 and circuit board 202 , as shown in FIG. 2A .
  • the inventors also discovered that cracks at stress concentration points were most likely to occur during the solder reflow process, when temperature gradients are formed in board assembly 200 .
  • a surface crack such as surface crack 219 intersects with a fiber, such as the one or more fibers 213
  • the crack proceeds along the interfacial interface between the one or more fibers 213 and the material in which the one or more fibers 213 is embedded.
  • the inventors also discovered that by increasing thickness 210 of surface layer 209 to between about 10% and 30% of circuit board thickness 221 , the likelihood of crack formation on the surface of circuit board 202 is decreased. Therefore, in the novel circuit board of the present invention, the thickness 210 is preferably between about 10% and about 30% of circuit board thickness 221 .
  • FIG. 2C is a detailed cross-sectional view of an alternate embodiment of circuit board 202 .
  • circuit board 202 includes core layer 223 , first surface layer 225 , and second surface layer 227 .
  • Core layer 223 is located between first surface layer 225 and second surface layer 227 .
  • Core layer 223 includes one or more fibers 231 embedded in core layer 223 .
  • Core layer 223 in one embodiment, is fabricated from a resin and has a thickness 229 of between about 0.006 inches and about 0.012 inches. Core layer 223 also has greater mechanical strength than first surface layer 225 or second surface layer 227 .
  • the one or more fibers 231 in one embodiment, embedded in core layer 223 , are glass fibers having a diameter of between about 0.0005 inches and about 0.001 inches. In an alternate embodiment, the one or more fibers 231 are woven fibers, such as woven glass fibers, and have a diameter of between about 0.001 inches and about 0.002 inches.
  • First and second surface layers 225 and 227 are fabricated from a resin that is free of fibers. In an alternate embodiment, first and second surface layers 225 and 227 are fabricated from a resin that is essentially free of fibers. First and second surface layers 225 and 227 are essentially free of fibers when any fibers embedded in first and second surface layers 225 and 227 do not significantly increase the likelihood of cracking in circuit board 202 .
  • the inventors in addition to discovering the source of cracks in circuit boards having a single surface layer, have also discovered that cracks in a circuit board having two surface layers, such as circuit board 202 shown in FIG.
  • first surface layer thickness 237 is preferably between about 10% and about 15% of circuit board thickness 241 and second surface layer thickness 239 are preferably between about 10% and about 15% of circuit board thickness 241 .
  • FIG. 3 is a block diagram of one embodiment of a computer system 300 suitable for use in connection with the present invention.
  • System 300 comprises processor 305 and memory board assembly 310 including one or more circuit boards shown in FIGS. 2B and 2C according to the teachings of the present invention.
  • Memory board assembly 310 comprises memory array 315 , address circuitry 320 , and read circuitry 330 , and is coupled to processor 305 by address bus 335 , data bus 340 , and control bus 345 .
  • Processor 305 through address bus 335 , data bus 340 , and control bus 345 communicates with memory board assembly 310 .
  • address information, data information, and control information are provided to memory board assembly 310 through busses 335 , 340 , and 345 .
  • This information is decoded by addressing circuitry 320 , including a row decoder and a column decoder, and read circuitry 330 .
  • Successful completion of the read operation results in information from memory array 315 being communicated to processor 305 over data bus 340 .
  • the circuit boards include a number of layers including a core layer and one or more surface layers.
  • the core layer includes a number of embedded fibers to increase the strength of the core layer. Cracking is reduced in the surface layer or layers by fabricating the surface layers with a thickness sufficient to reduce the probability of stress concentration points inducing cracks during the heating and cooling of the circuit board.
  • the methods described for fabricating a circuit board include forming a core layer including a number of fibers, and forming a surface layer on the core layer, such that the surface layer is free of fibers and has thickness that is between about 10% and 30% of the circuit board thickness. Cracking is reduced in the surface layer or layers of circuit boards fabricated using the methods of the present invention.

Abstract

This invention relates to circuit boards and methods of fabricating circuit boards. A circuit board includes a core layer and a surface layer. The core layer includes a number of fibers and the surface layer has a thickness that is between about 10% and about 30% of the circuit board thickness. Including fibers in the core layer increases the strength of the circuit board. The surface layer is essentially free of fibers and relatively thick. The thickness of the surface layer inhibits the formation of cracks in the circuit board, which improves the reliability of circuits and systems coupled to the circuit board.

Description

  • This application is a Divisional of U.S. application Ser. No. 10/857,738, filed May 28, 2004, which is a Divisional of U.S. application Ser. No. 09/643,526, filed Aug. 22, 2000, now U.S. Pat. No. 6,757,176, both of which are incorporated herein by reference.
    • FIELD OF THE INVENTION
  • This invention relates to circuit boards, and more particularly, to increasing circuit board reliability.
    • BACKGROUND OF THE INVENTION
  • Printed circuit boards, which are used in the manufacture of electrical, mechanical, electromechanical, and other kinds of products, provide a substrate for mounting a die on which integrated circuits, such as processors, memories, and amplifiers, are fabricated. FIG. 1 shows a cross-sectional view of a prior art ball-grid array (BGA) package 100 which includes printed circuit board 103 coupled to board 105 by solder balls 107, and die 109 coupled to printed circuit board 103 by adhesive 111 and molding compound 112.
  • A longstanding and unsolved problem with printed circuit boards in general and with BGA package 100 in particular is that printed circuit board 100 may develop a crack, such as crack 113. Crack 113 destroys the structural integrity of BGA package 100. Once the structural integrity of BGA package 100 is destroyed, unforseen stresses may break or damage electronic connectors, such as electronic connectors 115 and 116, and as a result, any product in which BGA package 100 is incorporated may malfunction. One method of solving problems associated with printed circuit board cracking and the resulting electronic connection failures is to include a second printed circuit board in the design of an electronic system. The second circuit board is a redundant printed circuit board which mirrors the operation of the primary board, so a system failure occurs only when both the redundant printed circuit board and the primary board fail at the same time. Unfortunately, this solution is very expensive and is cost effective only in systems, such as trains, airplanes, or spacecraft, where the cost of failure is high. For systems in which the cost of failure is low, redundant circuit boards are seldom used.
  • For these and other reasons there is a need for the present invention.
    • SUMMARY OF THE INVENTION
  • The above mentioned problems with cracking in circuit boards and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A circuit board is described that includes embedded fibers, which strengthen the board, and a surface layer having a certain thickness range that inhibits the formation of cracks in the circuit board.
  • The present invention provides, in one embodiment, a circuit board including a core layer and a surface layer. A number of fibers are embedded in the core layer. The surface layer has a thickness which is between about 10% and about 30% of the circuit board thickness. Embedding fibers in the core layer increases the strength of the circuit board. A surface layer thickness of between about 10% and about 30% of the circuit board thickness inhibits the formation of cracks in the circuit board, which improves the reliability of circuits mounted on the circuit board and systems in which the circuit board is embedded.
  • In an alternate embodiment, the present invention provides a method of fabricating a circuit board having a circuit board thickness. The method includes forming a core layer including a number of fibers, and forming a surface layer on the core layer. The surface layer has a surface layer thickness that is between about 10% and about 30% of the circuit board thickness and is free of fibers.
  • These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an illustration cross-sectional view of a prior art ball-grid array (BGA) package including a circuit board.
  • FIG. 2A is a cross-sectional view of one embodiment of a circuit board assembly according to the teaching of the present invention.
  • FIG. 2B is a cross-sectional view of an alternate embodiment of a circuit board assembly according to the teaching of the present invention.
  • FIG. 2C is a cross-sectional view of a second alternate embodiment of a circuit board assembly according to the teaching of the present invention.
  • FIG. 3 is a block diagram of one embodiment of a computer system suitable for use in connection with the present invention.
    • DETAILED DESCRIPTION
  • In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
  • FIG. 2A is a cross-sectional view of one embodiment of circuit board assembly 200. Circuit board assembly 200 includes die 201, printed circuit board 202, and board 203. Circuit board 202 is coupled to board 203 by solder balls 204, and die 201 is coupled to printed circuit board 202 by adhesive 205 and molding compound 206.
  • Circuit board assembly 200 is sometimes referred to as a ball-grid array, but the present invention is not limited to ball-grid array circuit board assemblies. Any circuit board assembly that includes a circuit board, such as printed circuit board 202, which is described in more detail below, is suitable for use in connection with the present invention. For example, a circuit board assembly in which a first circuit board is coupled by edge connectors to a second circuit board is suitable for use in connection with the present invention.
  • Die 201 includes an integrated circuit, such as a memory circuit, a processor, an amplifier, or an application specific circuit (ASIC). Memory circuits suitable for use in connection with the present invention include but are not limited to dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, erasable programmable memory (EPROM) circuits, and electrically erasable programmable memory (EEPROM) circuits. Processor circuits suitable for use in connection with the present invention include but are not limited to microprocessors, digital signal processors (DSPs), and reduced instruction set computing (RISC) processors. Amplifier circuits suitable for use in connection with the present invention include but are not limited to operational amplifiers, differential amplifiers, and power amplifiers. Application specific integrated circuits (ASICs) suitable for use in connection with the present invention include telecommunication circuits, such as telecommunication interface circuits. Die 201 is coupled to printed circuit board 202 by adhesive 205, which is selected to maintain a low stress interface between die 201 and circuit board 202. Any adhesive that has a coefficient of thermal expansion which maintains a low stress interface between die 201 and circuit board 202 during the heating and cooling of circuit board assembly 200 is suitable for use in connection with the present invention.
  • A board 203, such as a circuit board, provides a substrate for mounting a number of circuit boards, such as circuit board 202, and other electronic or electro-mechanical components. In one embodiment, board 203 is a computer system circuit board including a processor. Board 203 may also provide a substrate suitable for securing circuit assembly 200 to a larger package or other housing, such as a cabinet or case. Board 203 is fabricated from materials commonly used in the fabrication of circuit boards, such as polymeric composite materials. One example of a polymeric composite material is phenolic. However, board 203 is not limited to polymeric composite materials, and other materials, particularly insulating materials, may also be used in the fabrication of board 203.
  • Solder balls 204 provide a number of signal paths to electronically couple circuit board 202 to board 203. The number of signal paths permit communication between components mounted on circuit board 202 and on board 203. Any material that is a good conductor is suitable for use in fabricating solder balls 204. Tin, gold, copper, silver, and alloys of tin, gold, copper, and silver, are examples of materials suitable for use fabricating solder balls 204.
  • Circuit board 202, as shown in FIG. 2A, provides a substrate for mounting die 201 and coupling signals to board 203. In one embodiment, circuit board 202 is formed from a polymeric composite material. Circuit board 202 is coupled to die 201 by adhesive 205.
  • FIG. 2B is a detailed cross-sectional view of one embodiment of circuit board 202. In this embodiment, circuit board 202 includes core layer 208 and surface layer 209, which is a first layer or a first resin layer. Circuit board 202 may also include slot 211 for routing conductive connectors, such as conductive connectors 207 and 208 shown in FIG. 2A, from above circuit board 202 to below circuit board 202.
  • Core layer 208 includes one or more fibers 213 embedded in an insulator. Core layer 208, in one embodiment, is fabricated from a resin and has a thickness 212 of between about 0.006 inches and about 0.012 inches. The one or more fibers 213, in one embodiment, are glass fibers having a diameter of between about 0.0005 inches and about 0.001 inches. In an alternate embodiment, the one or more fibers 213 are woven fibers, such as woven glass fibers, and have a diameter of between about 0.001 inches and about 0.002 inches.
  • Surface layer 209, in one embodiment, is fabricated from a resin that is free of fibers. In an alternate embodiment, surface layer 209 is fabricated from a resin that is essentially free of fibers. Surface layer 209 is essentially free of fibers when any fibers embedded in surface layer 209 do not significantly increase the likelihood of cracking in circuit board 202. The inventors discovered that cracks in circuit board 202 frequently occur on the surface of circuit board 202 at stress concentration points located above fiber hills, such as fiber hills 215 and 217, and that cracks are less likely to occur at stress concentration points located above fiber valleys. In board assembly 200, stress concentration points occur along an edge of an interface between two surfaces, such as along the edge of adhesive 205 at the interface between adhesive 205 and circuit board 202, as shown in FIG. 2A. The inventors also discovered that cracks at stress concentration points were most likely to occur during the solder reflow process, when temperature gradients are formed in board assembly 200. Once a surface crack, such as surface crack 219 intersects with a fiber, such as the one or more fibers 213, the crack proceeds along the interfacial interface between the one or more fibers 213 and the material in which the one or more fibers 213 is embedded. According to the teachings of the present invention, the inventors also discovered that by increasing thickness 210 of surface layer 209 to between about 10% and 30% of circuit board thickness 221, the likelihood of crack formation on the surface of circuit board 202 is decreased. Therefore, in the novel circuit board of the present invention, the thickness 210 is preferably between about 10% and about 30% of circuit board thickness 221.
  • FIG. 2C is a detailed cross-sectional view of an alternate embodiment of circuit board 202. In this embodiment, circuit board 202 includes core layer 223, first surface layer 225, and second surface layer 227. Core layer 223 is located between first surface layer 225 and second surface layer 227.
  • Core layer 223 includes one or more fibers 231 embedded in core layer 223. Core layer 223, in one embodiment, is fabricated from a resin and has a thickness 229 of between about 0.006 inches and about 0.012 inches. Core layer 223 also has greater mechanical strength than first surface layer 225 or second surface layer 227. The one or more fibers 231, in one embodiment, embedded in core layer 223, are glass fibers having a diameter of between about 0.0005 inches and about 0.001 inches. In an alternate embodiment, the one or more fibers 231 are woven fibers, such as woven glass fibers, and have a diameter of between about 0.001 inches and about 0.002 inches.
  • First and second surface layers 225 and 227, in one embodiment, are fabricated from a resin that is free of fibers. In an alternate embodiment, first and second surface layers 225 and 227 are fabricated from a resin that is essentially free of fibers. First and second surface layers 225 and 227 are essentially free of fibers when any fibers embedded in first and second surface layers 225 and 227 do not significantly increase the likelihood of cracking in circuit board 202. The inventors, in addition to discovering the source of cracks in circuit boards having a single surface layer, have also discovered that cracks in a circuit board having two surface layers, such as circuit board 202 shown in FIG. 2C, frequently occur on one of the surfaces of circuit board 202 at stress concentration points located above fiber hills, such as fiber hills 233 and 235, and that cracks are less likely to occur at stress concentration points located above fiber valleys. In board assembly 200, which is shown in FIG. 2A, stress concentration points occur along an edge of an interface between two surfaces, such as along the edge of adhesive 205 at the interface between adhesive 205 and circuit board 202. The inventors also discovered that cracks at stress concentration points were most likely to occur during the solder reflow process when temperature gradients are being formed in board assembly 200. Referring again to FIG. 2C, once a surface crack intersects a fiber, such as one of the number of fibers 231, the crack proceeds along the interfacial interface between one of the number of fibers 231 and the material in which one of the number of fibers 235 is embedded. The inventors also discovered that by increasing the thickness 237 of surface layer 225 to between about 10% and 15% of circuit board thickness 241 and the thickness 239 of surface layer 227 to between about 10% and 15% of circuit board thickness 241, the likelihood of crack formation on the surface of circuit board 202 is decreased. Therefore, first surface layer thickness 237 is preferably between about 10% and about 15% of circuit board thickness 241 and second surface layer thickness 239 are preferably between about 10% and about 15% of circuit board thickness 241.
  • FIG. 3 is a block diagram of one embodiment of a computer system 300 suitable for use in connection with the present invention. System 300 comprises processor 305 and memory board assembly 310 including one or more circuit boards shown in FIGS. 2B and 2C according to the teachings of the present invention. Memory board assembly 310 comprises memory array 315, address circuitry 320, and read circuitry 330, and is coupled to processor 305 by address bus 335, data bus 340, and control bus 345. Processor 305, through address bus 335, data bus 340, and control bus 345 communicates with memory board assembly 310. In a read operation initiated by processor 305, address information, data information, and control information are provided to memory board assembly 310 through busses 335, 340, and 345. This information is decoded by addressing circuitry 320, including a row decoder and a column decoder, and read circuitry 330. Successful completion of the read operation results in information from memory array 315 being communicated to processor 305 over data bus 340.
    • CONCLUSION
  • A number of circuit boards, circuit board assemblies, and methods of fabricating circuit boards and circuit board assemblies have been described. The circuit boards include a number of layers including a core layer and one or more surface layers. The core layer includes a number of embedded fibers to increase the strength of the core layer. Cracking is reduced in the surface layer or layers by fabricating the surface layers with a thickness sufficient to reduce the probability of stress concentration points inducing cracks during the heating and cooling of the circuit board. The methods described for fabricating a circuit board include forming a core layer including a number of fibers, and forming a surface layer on the core layer, such that the surface layer is free of fibers and has thickness that is between about 10% and 30% of the circuit board thickness. Cracking is reduced in the surface layer or layers of circuit boards fabricated using the methods of the present invention.
  • Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (25)

1. A method of fabricating a circuit board having a circuit board thickness, the method comprising:
forming a core layer including a number of fibers; and
forming a surface layer on the core layer, the surface layer having a surface layer thickness that is between about 10% and about 30% of the circuit board thickness, the surface layer being free of fibers.
2. The method of claim 1, wherein forming a core layer including a number of fibers comprises embedding the number of fibers in a resin.
3. The method of claim 1, wherein forming a core layer including a number of fibers comprises embedding the number of fibers in a polymeric composite material.
4. The method of claim 1, forming a core layer including a number of fibers comprises embedding the number of fibers in phenolic.
5. A method of fabricating a circuit board having a circuit board thickness, the method comprising:
forming a core layer including a number of fibers; and
forming a surface resin layer on the core layer, the surface layer having a surface layer thickness that is between about 10% to 30% of the circuit board thickness.
6. The method of claim 5, further comprising forming a number of slots in the circuit board.
7. The method of claim 5, further comprising mounting a die using an adhesive over each of the number of slots.
8. A method of fabricating a circuit board having a circuit board thickness comprising:
forming a core layer including a number of fibers;
forming a first layer on the core layer, the first layer having a thickness between about 10% and about 15% of the circuit board thickness and the first layer being free of fibers; and
forming a second layer on the core layer, the second having a thickness that is between about 10% and about 15% of the circuit board thickness.
9. The method of claim 8, wherein forming a core layer including a number of fibers comprises embedding the number of fibers in a resin.
10. The method of claim 8, wherein forming a core layer including a number of fibers comprises embedding the number of fibers in a polymeric composite material.
11. The method of claim 8, forming a core layer including a number of fibers comprises embedding the number of fibers in phenolic.
12. A method of fabricating a circuit board having a circuit board thickness comprising:
forming a core layer including a number of fibers;
forming a first layer on a first side of the core layer, the first layer having a thickness between about 10% and about 15% of the circuit board thickness and the first layer being free of fibers; and
forming a second layer on a second side of the core layer, the second having a thickness that is between about 10% and about 15% of the circuit board thickness.
13. The method of claim 1, wherein forming a core layer including a number of fibers comprises embedding the number of fibers in one of a group consisting of a resin, a polymeric composite material, and phenolic.
14. A method of fabricating a circuit board having a circuit board thickness comprising:
forming a core layer including a number of fibers;
forming a first resin layer on the core layer, the first resin layer having a thickness between about 10% and about 15% of the circuit board thickness; and
forming a second resin layer on the core layer, the second resin layer having a thickness that is between about 10% and about 15% of the circuit board thickness.
15. The method of claim 14, wherein forming the core layer includes embedding the fibers in a resin layer.
16. The method of claim 14, wherein forming a core layer including a number of fibers comprises embedding the number of fibers in one of a group consisting of a polymeric composite material and phenolic material.
17. A method of fabricating a circuit board having a circuit board thickness, the method comprising:
forming a core layer including a number of fibers; and
forming a surface layer on the core layer, the surface layer having a surface layer thickness that is about 20% of the circuit board thickness, the surface layer being free of fibers.
18. The method of claim 16, wherein forming a core layer including a number of fibers comprises embedding the number of fibers in one of a group consisting of a resin, a polymeric composite material, and phenolic material.
19. A method of fabricating a circuit board having a circuit board thickness, the method comprising:
forming a core layer including a number of fibers having a diameter of between about 0.0005 inch and about 0.001 inch and a second dimension; and
forming a surface layer on the core layer, the surface layer having a surface layer thickness that is between about 10% and about 30% of the circuit board thickness, the surface layer being free of fibers.
20. The method of claim 19, wherein the core layer has a thickness of between about 0.006 inch and about 0.012 inch.
21. The method of claim 20, wherein the surface layer is about 20% of the circuit board thickness.
22. The method of claim 21, wherein the surface layer includes a first resin layer on the core layer and a second resin layer.
23. A method of fabricating a circuit board having a circuit board thickness, the method comprising:
forming a core layer including a number of fibers;
forming a surface resin layer on the core layer, the surface layer having a surface layer thickness that is between about 10% and 30% of the circuit board thickness;
forming a number of slots in the circuit board; and
mounting a die using an adhesive over each of the number of slots.
24. The method of claim 23, wherein mounting the die includes mounting a memory over the slots.
25. The method of claim 24, wherein the memory includes a dynamic random access memory.
US11/216,648 2000-08-22 2005-08-31 Circuit board Abandoned US20050283975A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/216,648 US20050283975A1 (en) 2000-08-22 2005-08-31 Circuit board

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/643,526 US6757176B1 (en) 2000-08-22 2000-08-22 Circuit board
US10/857,738 US20040217463A1 (en) 2000-08-22 2004-05-28 Circuit board
US11/216,648 US20050283975A1 (en) 2000-08-22 2005-08-31 Circuit board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/857,738 Division US20040217463A1 (en) 2000-08-22 2004-05-28 Circuit board

Publications (1)

Publication Number Publication Date
US20050283975A1 true US20050283975A1 (en) 2005-12-29

Family

ID=32508352

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/643,526 Expired - Lifetime US6757176B1 (en) 2000-08-22 2000-08-22 Circuit board
US10/857,738 Abandoned US20040217463A1 (en) 2000-08-22 2004-05-28 Circuit board
US11/216,648 Abandoned US20050283975A1 (en) 2000-08-22 2005-08-31 Circuit board

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/643,526 Expired - Lifetime US6757176B1 (en) 2000-08-22 2000-08-22 Circuit board
US10/857,738 Abandoned US20040217463A1 (en) 2000-08-22 2004-05-28 Circuit board

Country Status (1)

Country Link
US (3) US6757176B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050063637A1 (en) * 2003-09-22 2005-03-24 Mershon Jayne L. Connecting a component with an embedded optical fiber
US20050063638A1 (en) * 2003-09-24 2005-03-24 Alger William O. Optical fibers embedded in a printed circuit board
US7215204B2 (en) * 2004-12-29 2007-05-08 Agere Systems Inc. Intelligent high-power amplifier module
US7433192B2 (en) * 2004-12-29 2008-10-07 Agere Systems Inc. Packaging for electronic modules
JP2016004888A (en) * 2014-06-17 2016-01-12 イビデン株式会社 Printed wiring board and method for manufacturing printed wiring board

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2695351A (en) * 1950-01-12 1954-11-23 Beck S Inc Electric circuit components and methods of preparing the same
US3617613A (en) * 1968-10-17 1971-11-02 Spaulding Fibre Co Punchable printed circuit board base
US4195110A (en) * 1973-11-12 1980-03-25 United States Gypsum Company Glass-reinforced composite gypsum board
US4550051A (en) * 1983-05-05 1985-10-29 Dynamit Nobel Aktiengesellschaft Laminate based on epoxy resin for printed circuits
US4594284A (en) * 1983-05-30 1986-06-10 Kanai Juyo Kogyo Co., Ltd. Foundation for card clothing
US4886699A (en) * 1987-10-26 1989-12-12 Rogers Corporation Glass fiber reinforced fluoropolymeric circuit laminate
US4915983A (en) * 1985-06-10 1990-04-10 The Foxboro Company Multilayer circuit board fabrication process
US6096411A (en) * 1997-03-14 2000-08-01 Matsushita Electric Industrial Co., Ltd. Conductive paste composition for via hole filling and printed circuit board using the same
US6127728A (en) * 1999-06-24 2000-10-03 Lsi Logic Corporation Single reference plane plastic ball grid array package
US6165629A (en) * 1991-10-29 2000-12-26 International Business Machines Corporation Structure for thin film interconnect
US6303500B1 (en) * 1999-02-24 2001-10-16 Micron Technology, Inc. Method and apparatus for electroless plating a contact pad
US6338195B1 (en) * 1996-07-23 2002-01-15 Hitachi Chemical Company, Ltd. Connection sheet and electrode connection structure for electrically interconnecting electrodes facing each other, and method using the connection sheet
US6423579B2 (en) * 1999-08-30 2002-07-23 Micron Technology, Inc. Apparatus and methods for providing substrate structures having metallic layers for microelectronics devices
US6477286B1 (en) * 1999-07-16 2002-11-05 Canon Kabushiki Kaisha Integrated optoelectronic device, and integrated circuit device
US6532651B1 (en) * 1998-05-14 2003-03-18 Matsushita Electric Industrial Co., Ltd. Circuit board and method of manufacturing the same
US6594153B1 (en) * 2000-06-27 2003-07-15 Intel Corporation Circuit package for electronic systems
US6651149B1 (en) * 1998-12-10 2003-11-18 Kabushiki Kaisha Toshiba Data storage medium with certification data
US6781064B1 (en) * 1996-08-20 2004-08-24 International Business Machines Corporation Printed circuit boards for electronic device packages having glass free non-conductive layers and method of forming same
US6944945B1 (en) * 2000-05-12 2005-09-20 Shipley Company, L.L.C. Sequential build circuit board

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2695351A (en) * 1950-01-12 1954-11-23 Beck S Inc Electric circuit components and methods of preparing the same
US3617613A (en) * 1968-10-17 1971-11-02 Spaulding Fibre Co Punchable printed circuit board base
US4195110A (en) * 1973-11-12 1980-03-25 United States Gypsum Company Glass-reinforced composite gypsum board
US4550051A (en) * 1983-05-05 1985-10-29 Dynamit Nobel Aktiengesellschaft Laminate based on epoxy resin for printed circuits
US4594284A (en) * 1983-05-30 1986-06-10 Kanai Juyo Kogyo Co., Ltd. Foundation for card clothing
US4915983A (en) * 1985-06-10 1990-04-10 The Foxboro Company Multilayer circuit board fabrication process
US4886699A (en) * 1987-10-26 1989-12-12 Rogers Corporation Glass fiber reinforced fluoropolymeric circuit laminate
US6165629A (en) * 1991-10-29 2000-12-26 International Business Machines Corporation Structure for thin film interconnect
US6338195B1 (en) * 1996-07-23 2002-01-15 Hitachi Chemical Company, Ltd. Connection sheet and electrode connection structure for electrically interconnecting electrodes facing each other, and method using the connection sheet
US6781064B1 (en) * 1996-08-20 2004-08-24 International Business Machines Corporation Printed circuit boards for electronic device packages having glass free non-conductive layers and method of forming same
US6096411A (en) * 1997-03-14 2000-08-01 Matsushita Electric Industrial Co., Ltd. Conductive paste composition for via hole filling and printed circuit board using the same
US6532651B1 (en) * 1998-05-14 2003-03-18 Matsushita Electric Industrial Co., Ltd. Circuit board and method of manufacturing the same
US6651149B1 (en) * 1998-12-10 2003-11-18 Kabushiki Kaisha Toshiba Data storage medium with certification data
US6303500B1 (en) * 1999-02-24 2001-10-16 Micron Technology, Inc. Method and apparatus for electroless plating a contact pad
US6127728A (en) * 1999-06-24 2000-10-03 Lsi Logic Corporation Single reference plane plastic ball grid array package
US6477286B1 (en) * 1999-07-16 2002-11-05 Canon Kabushiki Kaisha Integrated optoelectronic device, and integrated circuit device
US6423579B2 (en) * 1999-08-30 2002-07-23 Micron Technology, Inc. Apparatus and methods for providing substrate structures having metallic layers for microelectronics devices
US6944945B1 (en) * 2000-05-12 2005-09-20 Shipley Company, L.L.C. Sequential build circuit board
US6594153B1 (en) * 2000-06-27 2003-07-15 Intel Corporation Circuit package for electronic systems

Also Published As

Publication number Publication date
US6757176B1 (en) 2004-06-29
US20040217463A1 (en) 2004-11-04

Similar Documents

Publication Publication Date Title
US7632127B2 (en) Socket and method for compensating for differing coefficients of thermal expansion
US4574331A (en) Multi-element circuit construction
US4581679A (en) Multi-element circuit construction
US4474292A (en) Carrier element for an IC-chip
US20010005042A1 (en) Method of manufacturing a surface mount package
KR960006982B1 (en) Stepped multilayer interconnection apparatus and the method for making the same
US20050283975A1 (en) Circuit board
US20050139980A1 (en) High density integrated circuit module
EP0343400A2 (en) Electronic package assembly with flexible carrier and method of making it
JPH0738222A (en) Rigid-flexible circuit board and preparation thereof
JPS5856447A (en) Identification card and method of producing same
JPH0636463B2 (en) Printed circuit board
US5776662A (en) Method for fabricating a chip carrier with migration barrier, and resulating chip carrier
JPH0532090A (en) Noncollapsible ic card
EP0429689B1 (en) Printed circuit board
JP2652107B2 (en) Electrical connection structure
US6674155B2 (en) Chip carrier film, method of manufacturing the chip carrier film and liquid crystal display using the chip carrier film
JP2693618B2 (en) Electronic circuit board
JP2000077798A (en) Printed wiring board, semiconductor device and liquid crystal display device provided therewith
JP2000323628A (en) Semiconductor device, manufacture thereof and electronic device using the same
US20070249209A1 (en) Circuit Arrangement for Coupling a Voltage Supply to a Semiconductor Component, Method for Producing the Circuit Arrangement, and Data Processing Device Comprising the Circuit Arrangement
JPS62101053A (en) Thin type electronic circuit unit
US6750537B2 (en) Substrate structure
JPH05235498A (en) Printed circuit board having protruding electrode and bonding method therefor
JPH0348671Y2 (en)

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION