US20040227233A1

US20040227233A1 - Interconnection pattern design

Info

Publication number: US20040227233A1
Application number: US10/439,489
Authority: US
Inventors: Esa Hussa
Original assignee: Nokia Oyj
Current assignee: Nokia Oyj
Priority date: 2003-05-16
Filing date: 2003-05-16
Publication date: 2004-11-18
Also published as: CN1791978A; EP1625619A1; KR100780869B1; WO2004102661A1; US20040251544A1; KR20060019541A; US7223681B2; US20070165388A1

Abstract

An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.

Description

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, such as a cell phone or a computer. More particularly, the present invention relates to a method for extending life time and reliability of a semiconductor device and to reduce field failure rate (FFR) of the device. Furthermore, the present invention relates to an interconnection pattern design of a semiconductor component.

BACKGROUND OF THE INVENTION

Semiconductor components, such as ball grid array (BGA) and chip scale packaging (CSP) components, are one significant source of field failures in semiconductor devices, especially in portable and hand held devices such as cell phones. CSPs and BGAs will fail as a consequence of shock impact from mechanical shock and fatigue from thermal and bending cycling. CSPs and BGAs fail mainly due to failure in interconnection between a component and a printed wiring board (PWB) i.e. in an interconnection or PWB built up failure. Furthermore, high loading of interconnections may cause component internal failures, e.g. substrate or die cracking.

General examples of a prior art semiconductor components are illustrated in FIGS. 1 a-1 e. Specifically, FIGS. 1a-1 e illustrate an integrated circuit component 20 that has interconnections 10 arranged in some two-dimensional layout in order to form an interconnection pattern. The interconnections 10 allow the component 20 to be electrically connected to other external devices, other peripherals, or other integrated circuits over conductive traces of a printed wiring board (PWB) or other substrate whereby larger electrical systems may be created (e.g. a computer, cell phone, television, etc.). In the prior art FIGS. 1a-1 e, the interconnections 10 are aligned into rows and columns to form an interconnection pattern which has a rectangular shape with sharp corners. All interconnections 10 are of the same size but it is possible that some of the interconnections could have smaller or larger diameter.

One significant cause for failures is that loading is not distributed evenly between interconnections of the component. Typically corner interconnections meet the highest load and fail first.

Coefficient of thermal expansion (CTE) mismatch and temperature differences cause a component and a printed wiring board (PWB) to expand at different rate and magnitude. FIG. 2 illustrates in a simplified manner a cross sectional view of the ball

grid array package

30 mounted on a printed wiring board 31 before deformation and FIG. 3 illustrates the same after deformation. It can be seen that the longer the distance from the component 32 center point is the higher deformation and stress an interconnection 33 have to undergo. Therefore, the corner solder joints 33′ have to deform the most and are thus typically the most critical ones.

As a consequence of shock impact from mechanical shock, a printed wiring board (PWB) is deformed. Deformation is dependent on supporting structures and loading. Due to an acceleration, PWB is bent up- or downward in the area between screws. A component mounted on the PWB tends to follow said deformation. This leads to uneven loading of the interconnections and the corner solder joints of the component are loaded the most. FIGS. 4 and 5 illustrate a simplified example of the

PWB

40 during a shock impact. During the shock impact the PWB 40 is bent downwards forming kind of a flat bowl. A component 41 attached to the PWB 40 can be imagined as a piece of glass, which is put into the bowl as in FIG. 4. A weight 42 is put on the glass, which represents the phenomena that glass (component) should be able to follow the deformation of bowl (PWB). A first place of breakage is dependent on the bottom area of the weight while in a component it is dependent on die size (rigid area). In any case, the most likely locations for failure are the corners of the glass. Another potential failure locations would be the corners of the weight.

When the class is round as illustrated in FIG. 5, the glass is supported from the whole edge area. There, stress is even, and the most critical locations would probably be the corners of the weight i.e. the solder joints close to the die edge. Thus, rounded bailout would distribute loading more evenly between the interconnections and thus reduce stresses in critical solder joints, and, furthermore, improve reliability.

Therefore, a need exists in the industry for a method of designing an interconnection pattern whereby overall product reliability is greatly improved while the compactness of CSP and BGA devices is not substantially and adversely affected.

SUMMARY OF THE INVENTION

A primary object of the invention is to provide an interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. The interconnection pattern in accordance with the present invention has substantially rounded or chamfered corners. Thus, reliability of the interconnections is improved by smaller loading and more even stress distribution between the connections.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of an example and is not limited in the accompanying figures, in which alike references indicate similar elements, and in which; [0010]
FIGS. 1[0011] a-1 e illustrate a plan view of a prior art interconnection pattern,
FIG. 2 illustrates a cross sectional view of the ball grid array package mounted on a printed wiring board, [0012]
FIG. 3 illustrates a cross sectional view of the ball grid array package mounted on a printed wiring board after thermal deformation, [0013]
FIG. 4 illustrates a simplified example of the PWB during a shock impact, [0014]
FIG. 5 illustrates a simplified example of the PWB comprising a component in accordance of the present invention during a shock impact, [0015]
FIG. 6 illustrates a plan view of an interconnection pattern in accordance with the first preferred embodiment of the present invention, [0016]
FIG. 7 illustrates a plan view of an interconnection pattern in accordance with the second preferred embodiment of the present invention, [0017]
FIG. 8 illustrates a plan view of an interconnection pattern in accordance with the third preferred embodiment of the present invention, [0018]
FIG. 9 illustrates a plan view of an interconnection pattern in accordance with the fourth preferred embodiment of the present invention, [0019]
FIG. 10 illustrates a plan view of an interconnection pattern in accordance with the fifth preferred embodiment of the present invention, and [0020]
FIG. 11 illustrates a flow chart of a method for designing an interconnection pattern in accordance with one embodiment of the present invention.[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Generally, the present invention provides a semiconductor component, a ball grid array (BGA) device and a method for designing a semiconductor component with solder joints having extended thermal fatigue life. Fatigue life is extended by designing an interconnection pattern to be substantially rounded or chamfered from the corners. Reliability of the interconnections is improved by smaller loading and more even stress distribution between the interconnections. Rounded or chamfered interconnection patterns are formed by designing a semiconductor component by aligning the interconnections such that the pattern formed by the interconnections has rounded or chamfered corners. [0022]
A semiconductor component according to the present invention can be achieved e.g. by modifying a prior art component by transferring multiple electrically connecting solder joints from the corners of an interconnection pattern to the sides of the pattern or to the center of the pattern or near to the center of the pattern. A semiconductor component according to the present invention can be achieved also by modifying a prior art component by adding multiple solder joints to the periphery of the pattern in order to design a pattern with rounded or chamfered pattern design. It is also self-evident that it is possible to design a novel semiconductor component having an interconnection pattern according to the present invention without amendment or modification of the prior art component. [0023]
The present invention may be useful in any type of packaging technology that includes interconnections such as, for example, solder balls or solder bumps, like, for example, BGA, CSP (chip scale package) and flip chip. The present invention may also be useful in different types of bump forming technology, such as, for example, the C4 (Controlled Collapse Chip Connection) bump process or the E3 (Extended Eutectic Evaporative) bump process. Furthermore, the present invention may also be utilized in other kinds of connection techniques between a semiconductor component and its base, like gluing. Thus it should be noted that the invention is not limited to used connection technique. The present invention will be further described with reference to FIGS. 6-10. [0024]
FIGS. 6-10 illustrate a plan view of an interconnection pattern in accordance with some alternative embodiments of the present invention. In FIGS. 6-10, the [0025] interconnections 10 are formed on a component 20. The interconnections are generally any number of conductive contact regions that are exposed at a surface of the component 20 in order to enable electrical contact to electrical circuitry formed on the component 20. The component 20 may be any device requiring solder balls and/or bumps to physically and electrically connect the component 20 to a printed wiring board. For example, the component 20 may be a substrate portion of a BGA package, or it may be a semiconductor material having metal pads for directly connecting to a PWB, such as in flip chip technology. The component 20 may be any kind of surface-mountable component, e.g. flip chip component or LGA, multi-chip module (MCM), a wafer scale integrated product, or the like integrated circuit devices. The interconnections 10 may be formed from a conductive metal such as aluminum or copper, and serve as terminals for external connections of the component 20. Note, that in the illustrated embodiments, the conductive contact regions are generally circular in shape. However, in other embodiments, the conductive contact regions may have other shapes, such as, for example, square or rectangular.
In the first preferred embodiment of the present invention illustrated in FIG. 6, the interconnection pattern according to the prior art as illustrated in FIG. 1[0026] a is modified and designed according to the present invention by transferring one interconnection from each corner to the corners inside the inner circle of the joints. Thus, one electrically connecting joint at each outer corner is missing, but total number of the joints is equal to the prior art pattern as illustrated in FIG. 1a, the outermost rows and the outermost columns of the grid array having less electrically connecting joints than the second outermost rows and columns with the result of a pattern with chamfered corners. In other words, an outer loop comprising the joints in the periphery of the pattern has substantially chamfered corners. The interconnections illustrated in FIG. 6 and also in FIGS. 7-10 are solder joints. But as the invention is not limited to any specific connecting technique, they represent an example on one possible type of the used interconnection.
In the second preferred embodiment of the present invention illustrated in FIG. 7, the interconnection pattern according to the prior art as illustrated in FIG. 1[0027] b is modified and designed according to the present invention by changing the position of six solder joints in each corner. Two solder joints are transferred to the corners inside the inner circle of the joints. Four solder joints are transferred to open spaces at the sides of the pattern. Thus, plurality of electrically connecting joints at each outer corner is missing but the total number of the joints is equal to the prior art pattern as illustrated in FIG. 1b, the outermost rows and the outermost columns of the grid array having less electrically connecting joints than the second outermost rows and columns and the second outermost columns of the grid having equal amount or fewer electrically connecting joints than the third outermost rows and the third outermost columns of the grid with the result of a pattern with chamfered corners.
In the third preferred embodiment of the present invention illustrated in FIG. 8, the interconnection pattern according to the prior art as illustrated in FIG. 1[0028] c is modified and designed according to the present invention by transferring one interconnection from each outermost corner to the side of the pattern.
In the fourth preferred embodiment of the present invention illustrated in FIG. 9, the interconnection pattern according to the prior art as illustrated in FIG. 1[0029] d is modified and designed according to the present invention by removing six support joints (that is not electrically connecting joints) from each corner and by transferring electrically connecting joints from corners to the sides of the original joint pattern. Thus, the joints of the interconnection pattern are arranged such that the pattern has rounded corners, close to round design. In some embodiments it is actually possible to design a pattern so that it has a round design.
In the fifth preferred embodiment of the present invention illustrated in FIG. 10, the interconnection pattern according to the prior art as illustrated in FIG. 1[0030] e is modified and designed according to the present invention by adding additional not electrically connecting solder joints which are arranged such that the joint pattern has rounded corners. In other words, additional joints are added so that the constructed outer loop of the pattern comprising the joints in the periphery of the pattern has substantially rounded corners. As illustrated in FIG. 1e, a die of the component extends significantly outside the interconnecting pattern. This has induced breakage of the die when handling the component, e.g. in manufacturing, and in mechanical shock situations. FIG. 1e illustrates support joints at the corners of the pattern without which the component is unstable in manufacturing line and it may tilt during processing, e.g. in a reflow oven. Tilting of the component may cause unsuccessful solder joint. However, placing of the additional support joints transmits deformation of PWB to the die of the component, whereupon the die will fracture. This problem is reduced with the joint pattern according to the present invention by adding additional support joints which are placed such that the joint pattern has rounded corners.
FIG. 11 illustrates a flow chart of a method for designing an interconnection pattern in accordance with one embodiment of the present invention. At [0031] step 30, a prior art semiconductor BGA design is analyzed to determine which are the “worst case” solder joints, i.e., which interconnections of the design have the lowest reliability or which otherwise reduce the component or the component-PWB assembly reliability. At step 32, N interconnections as determined in step 30 are transferred from the interconnection corners to the sides of the pattern or to the center of the pattern or near to the center, where N is any size subset of the total number of interconnections on the corner. Alternatively at step 32, N solder joints are added at the vicinity of the “worst case” solder joints to create a pattern with chamfered or rounded corners. At step 34, the modified interconnection pattern is tested to determine component or the component-PWB assembly reliability. In the illustrated embodiment, the design is modeled using finite element method (FEM) analysis. If the reliability is improved by an acceptable amount, then the product can be accepted to manufacturing as in step 36. However, if the reliability has not been improved by the required amount, then steps 30 through 34 are repeated until the required reliability is demonstrated. This method can be used to design for example embodiments of the inventions as illustrated in FIGS. 6-10.
The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented. [0032]
While the invention has been described in the context of preferred embodiments, which are not in order of superiority, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true scope of the invention. [0033]

Claims

1. A semiconductor component comprising a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners.

2. The semiconductor component as claimed in claim 1, wherein the interconnection pattern is formed as a ball grid array in which at least two electrically connecting joints at each corner of the array are missing.

3. The semiconductor component as claimed in claim 1, wherein the interconnection pattern is formed as a ball grid in which at least the outermost rows and the outermost columns of the grid have less electrically connecting joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have equal amount electrically connecting joints or less than the third outermost rows and the third outermost columns of the grid.

4. The semiconductor component as claimed in claim 1, wherein the interconnection pattern is formed as a ball grid array in which at least two joints at each corner of the array are missing.

5. The semiconductor component as claimed in claim 1, wherein the interconnection pattern is formed as a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have equal or fewer amount of joints than the third outermost rows and the third outermost columns of the grid.

6. A semiconductor component as claimed in claim 1, wherein a plurality of bonding joints are located about the periphery of the component in an array arrangement, wherein the bonding joints are positioned in first, second and at least in one third loops, the first, second and third loops comprising respectively an outer loop, a middle loop, and an inner loop along the sides of the component, the joints in the outer loop being positioned such that the outer loop has substantially rounded or chamfered corners.

7. A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as a pattern between the PWB and at least one component are aligned such that the pattern has substantially rounded or chamfered corners.

8. A semiconductor device as claimed in claim 7, wherein the semiconductor device is a portable device.

9. A semiconductor device as claimed in claim 7, wherein the interconnection pattern is formed as a ball grid array in which at least two electrically connecting joints at each corner of the array are missing.

10. A semiconductor device as claimed in claim 7, wherein the interconnection pattern is formed as a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of electrically connecting joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have equal or fewer amount of electrically connecting joints than the third outermost rows and the third outermost columns of the grid.

11. A semiconductor device as claimed in claim 7, wherein a plurality of bonding joints are located about the periphery of the component in an array arrangement, wherein the bonding joints are positioned in first, second and at least one third loops, the first, second and third loops comprising respectively an outer loop, a middle loop, and an inner loop along the sides of the component, the joints in the outer loop being positioned such that the outer loop has substantially rounded or chamfered corners.

12. A method for designing a semiconductor component comprising an interconnection pattern formed as a ball grid, wherein the interconnections are designed to align such that the pattern has substantially rounded or chamfered corners.

13. A method as claimed in claim 12, wherein joint pattern is designed to a form of a ball grid array in which at least two electrically connecting joints at each corner of the array are missing.

14. A method as claimed in claim 12, wherein the interconnection pattern is designed to a form of a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of electrically connecting joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have fewer amount of electrically connecting joints than the third outermost rows and the third outermost columns of the grid.

15. A method as claimed in claim 12, wherein joint pattern is designed to a form of a ball grid array in which at least two joints at each corner of the array are missing.

16. A method as claimed in claim 12, wherein the interconnection pattern is designed to a form of a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer amount of joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have fewer amount of joints than the third outermost rows and the third outermost columns of the grid.

17. A method as claimed in claim 12, wherein a plurality of bonding joints is located about the periphery of the component in an array arrangement in which at least joints of the outermost loop of the array are positioned such that the loop has substantially rounded or chamfered corners.

18. A method as claimed in claim 12, wherein the joint pattern is designed to comprise a plurality of additional non electrically connecting joints forming at least a part of the substantially rounded or chamfered corners of the pattern.