US20040224533A1 - Method for increasing polysilicon granin size - Google Patents

Method for increasing polysilicon granin size Download PDF

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Publication number
US20040224533A1
US20040224533A1 US10/431,120 US43112003A US2004224533A1 US 20040224533 A1 US20040224533 A1 US 20040224533A1 US 43112003 A US43112003 A US 43112003A US 2004224533 A1 US2004224533 A1 US 2004224533A1
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United States
Prior art keywords
furnace
flow
nitrogen
grain size
polysilicon
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Abandoned
Application number
US10/431,120
Inventor
Yao-Hui Huang
Tung-Li Lee
Chih-Hao Lin
Yen-Fei Lin
James Sun
Bu-Fun Chen
David Huang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to US10/431,120 priority Critical patent/US20040224533A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, BU-FUN, HUANG, DAVID, LIN, YEN-FEI, SUN, JAMES, HUANG, YAO-HUI, LEE, TUNG-LI, LIN, CHIH-HAO
Priority to TW093112939A priority patent/TWI231532B/en
Publication of US20040224533A1 publication Critical patent/US20040224533A1/en
Priority to US11/293,709 priority patent/US7446056B2/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0209—Pretreatment of the material to be coated by heating
    • C23C16/0218—Pretreatment of the material to be coated by heating in a reactive atmosphere
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material

Definitions

  • the present invention relates generally to semiconductor device manufacturing, and, more particularly, to a method for controlling device speed by adjusting polysilicon grain size.
  • wafers such as silicon wafers
  • the processing steps include depositing or forming layers, patterning the layers, and removing portions of the layers to define features on the wafer.
  • One such process used to form the layers is a procedure known as chemical vapor deposition (CVD), where reactive gases are introduced into a vessel containing the semiconductor wafers. The reactive gases facilitate a chemical reaction that causes a layer to form on the wafers.
  • CVD chemical vapor deposition
  • One deposition process involves the formation of polycrystalline silicon (polysilicon) layers on the wafer by decomposing SiH 4 molecules to Si atoms, which in turn combine to form Si grains, or “polysilicon.”.
  • polysilicon polycrystalline silicon
  • Polysilicon furnaces both within and without a nitrogen box may play an important role in controlling polysilicon grain size, thereby governing device speed.
  • An important consideration is the actual N 2 (nitrogen) flow which continuously treats the silicon wafer surface in the N 2 box.
  • N 2 nitrogen
  • the present invention relates to a method for increasing the grain size of a polysilicon layer in a furnace, which includes exposing a silicon oxide wafer in a deposition chamber to an amount, effective for the purpose, of nitrogen at a flow rate of at least about 240 standard liters per minute (slm).
  • FIG. 1 is a graph of the effect of increased nitrogen flow in a furnace.
  • FIG. 2 is a graph of polysilicon film volume fraction versus control wafer resistivity in a furnace.
  • a maximizing of polysilicon grain size results in an increase in device speed.
  • an oxide wafer i.e., a surface capped with a thin O 2 boundary layer
  • the wafer was exposed to bulk N 2 flow, with absorbed O 2 being removed as a result.
  • absorbed oxygen bonded with oxide molecules, and the oxygen depletion site was filled with N 2 molecules.
  • a prototypical furnace includes four tube furnaces, which are used for curing polymers, sintering, and growing oxides and nitrides on silicon wafers. There are also four gas flow timers for the furnace. The orientation of the timers matches the orientation of the tubes with which they correspond; with a maximum time of twelve hours, the flow timers are used to control the time the gas flows in the furnaces. The minimum amount of time for the process to function correctly is about two hours. When the timer reaches zero, the gas discontinues to flow.
  • each of the flow meters There are three flow meters located just below the gas flow timers. Beneath each of the flow meters are two flow meter valves. The cut-off valves are the valves closest to the flow meters. The handles are at a 90° angle when the flow meters are closed. When the handles are parallel with the flow meter, they are open. The lower valves are the needle valves, which control the gas flow into the flow meters. To the right of the flow meters is the three-way valve. This valve controls which gas flows into the middle flow meter (tube 2 ). The two selectable gases are oxygen and nitrogen. The narrow, pointed end of the handle points to the gas that is being used. When tube 2 is not in use, the valve is turned to the off position.
  • the oxygen cylinder in the chase behind the furnace is on. Note that in order to check that the gas pressure is sufficient, the cylinder gauge closest to the cylinder is read. The gauge to the left indicates the gas line pressure; it is set to approximately 25 psi.
  • the furnace temperature is controlled by a programmable temperature control unit. There is one control for every furnace; there are programmable temperature controllers on each of the temperature control units. These controllers monitor each of the furnace zone heaters, and allow the programming of several process steps. Thus, in order to operate the furnaces, the following steps are performed: (1) set the appropriate atmosphere, (2) load the furnace, (3) set the temperature program, (4) run the process, (5) end the run.
  • the first step in setting the atmosphere is to set the gas flow timer to the length of the particular run. This prevents the waste of gas in the system.
  • the next step is to set the flow of gas using the flow meters.
  • the first step in loading the furnace is to place a sample into a quartz boat, which is found in the nitrogen box next to the furnace.
  • the cap on the end of the tube is removed, and the boat placed just inside the opening.
  • a metal rod is used in order to carefully push the boat to the middle of the furnace tube.
  • the desired temperature in degrees Celsius is set for the controllers, and the temperature cooled to about room temperature when the program is done. In order to remove the boat from the furnace, the loading procedure is reversed.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The present invention relates to a method for increasing the grain size of a polysilicon layer, which includes exposing a silicon oxide wafer in a deposition chamber to an amount, effective for the purpose, of nitrogen at a flow rate of at least about 240 standard liters per minute (slm).

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a method for controlling device speed by adjusting polysilicon grain size. [0001]
    • BACKGROUND OF THE INVENTION
  • In the manufacture of semiconductor devices, wafers, such as silicon wafers, are subjected to a number of processing steps. The processing steps include depositing or forming layers, patterning the layers, and removing portions of the layers to define features on the wafer. One such process used to form the layers is a procedure known as chemical vapor deposition (CVD), where reactive gases are introduced into a vessel containing the semiconductor wafers. The reactive gases facilitate a chemical reaction that causes a layer to form on the wafers. [0002]
  • One deposition process involves the formation of polycrystalline silicon (polysilicon) layers on the wafer by decomposing SiH[0003] 4 molecules to Si atoms, which in turn combine to form Si grains, or “polysilicon.”. There are numerous factors that affect the deposition rate and deposition polysilicon film characteristics of a deposition tool. These factors include, e.g., the flow rate of reactive gases through the chamber and the temperature/pressure of the chamber.
  • Polysilicon furnaces both within and without a nitrogen box (the furnace wafer loading area immediately below the furnace main body) may play an important role in controlling polysilicon grain size, thereby governing device speed. An important consideration is the actual N[0004] 2 (nitrogen) flow which continuously treats the silicon wafer surface in the N2 box. A continual need exists for effective mechanisms for increasing the grain size of a silicon wafer.
    • SUMMARY OF THE INVENTION
  • The present invention relates to a method for increasing the grain size of a polysilicon layer in a furnace, which includes exposing a silicon oxide wafer in a deposition chamber to an amount, effective for the purpose, of nitrogen at a flow rate of at least about 240 standard liters per minute (slm).[0005]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which: [0006]
  • FIG. 1 is a graph of the effect of increased nitrogen flow in a furnace; and [0007]
  • FIG. 2 is a graph of polysilicon film volume fraction versus control wafer resistivity in a furnace.[0008]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • According to the method of the present invention, a maximizing of polysilicon grain size results in an increase in device speed. In the method of the present invention, when an oxide wafer (i.e., a surface capped with a thin O[0009] 2 boundary layer) was placed in an N2 box, the wafer was exposed to bulk N2 flow, with absorbed O2 being removed as a result. Upon treatment with the N2 flow, absorbed oxygen bonded with oxide molecules, and the oxygen depletion site was filled with N2 molecules. Nitrogen molecules “interfere” with silicon in forming a polysilicon seed; therefore fewer seeds, and a larger grain size was the result.
  • A prototypical furnace includes four tube furnaces, which are used for curing polymers, sintering, and growing oxides and nitrides on silicon wafers. There are also four gas flow timers for the furnace. The orientation of the timers matches the orientation of the tubes with which they correspond; with a maximum time of twelve hours, the flow timers are used to control the time the gas flows in the furnaces. The minimum amount of time for the process to function correctly is about two hours. When the timer reaches zero, the gas discontinues to flow. [0010]
  • There are three flow meters located just below the gas flow timers. Beneath each of the flow meters are two flow meter valves. The cut-off valves are the valves closest to the flow meters. The handles are at a 90° angle when the flow meters are closed. When the handles are parallel with the flow meter, they are open. The lower valves are the needle valves, which control the gas flow into the flow meters. To the right of the flow meters is the three-way valve. This valve controls which gas flows into the middle flow meter (tube [0011] 2). The two selectable gases are oxygen and nitrogen. The narrow, pointed end of the handle points to the gas that is being used. When tube 2 is not in use, the valve is turned to the off position. When furnace tube 2 is used, which performs oxidation, the oxygen cylinder in the chase behind the furnace is on. Note that in order to check that the gas pressure is sufficient, the cylinder gauge closest to the cylinder is read. The gauge to the left indicates the gas line pressure; it is set to approximately 25 psi.
  • The furnace temperature is controlled by a programmable temperature control unit. There is one control for every furnace; there are programmable temperature controllers on each of the temperature control units. These controllers monitor each of the furnace zone heaters, and allow the programming of several process steps. Thus, in order to operate the furnaces, the following steps are performed: (1) set the appropriate atmosphere, (2) load the furnace, (3) set the temperature program, (4) run the process, (5) end the run. [0012]
  • The first step in setting the atmosphere is to set the gas flow timer to the length of the particular run. This prevents the waste of gas in the system. The next step is to set the flow of gas using the flow meters. [0013]
  • The first step in loading the furnace is to place a sample into a quartz boat, which is found in the nitrogen box next to the furnace. The cap on the end of the tube is removed, and the boat placed just inside the opening. A metal rod is used in order to carefully push the boat to the middle of the furnace tube. The desired temperature in degrees Celsius is set for the controllers, and the temperature cooled to about room temperature when the program is done. In order to remove the boat from the furnace, the loading procedure is reversed. [0014]
  • In the testing of the present invention, an analysis of the effect of an increase in nitrogen flow, via nitrogen shower or other acceptable method was conducted in a furnace. As shown in FIG. 1, the V[0015] f (the polysilicon film volume fraction, which is an index of polysilicon grain size) trends down (i.e., larger grain size, as nitrogen flow increased). In FIG. 2, note that Rs (control wafer resistivity) trends down (i.e., higher speed) as Vf trends down (i.e., a larger grain size). Therefore, it is apparent that device speed is significantly enhanced by the amount of the N2 flow rate in a furnace.
  • While this invention has been described with respect to particular embodiments thereof, it is apparent that numerous other forms and modifications of this invention will be obvious to those skilled in the art. The appended claims and this invention generally should be construed to cover all such obvious forms and modifications which are within the true spirit and scope of the present invention. [0016]

Claims (3)

What is claimed is:
1. In the manufacture of semiconductor devices, a method for increasing the grain size of a polysilicon layer in a furnace, which comprises exposing a silicon oxide wafer in a deposition chamber of the furnace to an amount, effective for the purpose, of nitrogen at a flow rate of at least about 240 standard liters per minute.
2. The method as recited in claim 1, wherein the flow of nitrogen is achieved through nitrogen shower.
3. The method as recited in claim 1, wherein the increasing of grain size results in an increase in semiconductor device speed.
US10/431,120 2003-05-07 2003-05-07 Method for increasing polysilicon granin size Abandoned US20040224533A1 (en)

Priority Applications (3)

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US10/431,120 US20040224533A1 (en) 2003-05-07 2003-05-07 Method for increasing polysilicon granin size
TW093112939A TWI231532B (en) 2003-05-07 2004-05-07 Method for enhancing the speed of semiconductor device
US11/293,709 US7446056B2 (en) 2003-05-07 2005-12-01 Method for increasing polysilicon grain size

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US10/431,120 US20040224533A1 (en) 2003-05-07 2003-05-07 Method for increasing polysilicon granin size

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Publication number Priority date Publication date Assignee Title
TWI711728B (en) * 2016-08-29 2020-12-01 聯華電子股份有限公司 Method for forming lattice structures
US9852912B1 (en) 2016-09-20 2017-12-26 United Microelectronics Corp. Method of manufacturing semiconductor device for reducing grain size of polysilicon

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242855A (en) * 1991-09-30 1993-09-07 Nec Corporation Method of fabricating a polycrystalline silicon film having a reduced resistivity
US5804473A (en) * 1995-09-26 1998-09-08 Fujitsu Limited Thin film semiconductor device having a polycrystal active region and a fabrication process thereof
US6514879B2 (en) * 1999-12-17 2003-02-04 Intel Corporation Method and apparatus for dry/catalytic-wet steam oxidation of silicon

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US5447893A (en) * 1994-08-01 1995-09-05 Dow Corning Corporation Preparation of high density titanium carbide ceramics with preceramic polymer binders
US6287988B1 (en) * 1997-03-18 2001-09-11 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and semiconductor device
US20030049372A1 (en) * 1997-08-11 2003-03-13 Cook Robert C. High rate deposition at low pressures in a small batch reactor
US6450116B1 (en) * 1999-04-22 2002-09-17 Applied Materials, Inc. Apparatus for exposing a substrate to plasma radicals
US6812081B2 (en) * 2001-03-26 2004-11-02 Semiconductor Energy Laboratory Co.,.Ltd. Method of manufacturing semiconductor device
US6803330B2 (en) * 2001-10-12 2004-10-12 Cypress Semiconductor Corporation Method for growing ultra thin nitrided oxide
US7005160B2 (en) * 2003-04-24 2006-02-28 Asm America, Inc. Methods for depositing polycrystalline films with engineered grain structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242855A (en) * 1991-09-30 1993-09-07 Nec Corporation Method of fabricating a polycrystalline silicon film having a reduced resistivity
US5804473A (en) * 1995-09-26 1998-09-08 Fujitsu Limited Thin film semiconductor device having a polycrystal active region and a fabrication process thereof
US6514879B2 (en) * 1999-12-17 2003-02-04 Intel Corporation Method and apparatus for dry/catalytic-wet steam oxidation of silicon

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US20060134926A1 (en) 2006-06-22
TW200425308A (en) 2004-11-16
US7446056B2 (en) 2008-11-04
TWI231532B (en) 2005-04-21

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Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, YAO-HUI;LEE, TUNG-LI;LIN, CHIH-HAO;AND OTHERS;REEL/FRAME:014053/0466;SIGNING DATES FROM 20030415 TO 20030416

STCB Information on status: application discontinuation

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