US20040222512A1 - Method and system to manufacture stacked chip devices - Google Patents

Method and system to manufacture stacked chip devices Download PDF

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Publication number
US20040222512A1
US20040222512A1 US10/869,176 US86917604A US2004222512A1 US 20040222512 A1 US20040222512 A1 US 20040222512A1 US 86917604 A US86917604 A US 86917604A US 2004222512 A1 US2004222512 A1 US 2004222512A1
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component
pad
electronic package
laser
face
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US10/869,176
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Boyd Coomer
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Intel Corp
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Intel Corp
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Definitions

  • This invention relates generally to packaging of integrated circuits. More specifically, this invention relates to a method and system for electrically interconnecting semiconductor devices.
  • FIG. 1 illustrates a package 100 .
  • Package 100 is a stacked chip composite device that includes a substrate 101 , a semiconductor die 110 stacked atop substrate 101 , and a semiconductor die 120 stacked atop die 110 .
  • Solder bumps 150 are typically employed to assemble the stacked chip composite device to a printed wiring board (not shown).
  • Each die 110 , 120 and substrate 101 are electrically interconnected. via wire bond technology.
  • each die 110 , 120 is electrically connected to substrate 101 via gold wires 130 .
  • Die 110 and die 120 also may be electrically interconnected via gold wire connections (not shown).
  • An. encapsulant or mold 140 in package 100 protects gold wires 130 .
  • die 120 and substrate 101 are electrically interconnected via gold wires, and die 110 and substrate 101 are electrically interconnected using solder bumps.
  • the entire package is then encapsulated with an encapsulant.
  • FIG. 1 Prior Art
  • FIG. 1 illustrates a package that includes gold wires and an encapsulant.
  • FIG. 2 (Prior Art) illustrates a system for depositing a conductor via a laser.
  • FIG. 3 illustrates a system that includes stacked semiconductor devices that are electrically interconnected according to an embodiment of the present invention.
  • FIGS. 4A and 4B are top and side views, respectively, of stacked semiconductor devices that are electrically interconnected according to an embodiment of the present invention.
  • FIG. 5 is a high-level flow diagram illustrating a process for electrically interconnecting semiconductor devices according to an embodiment of the present invention.
  • a method and system for electrically interconnecting a semiconductor device and a component involve a semiconductor device and a component, such as another semiconductor device or a carrier substrate.
  • the device and component include respective dielectric portions on at least one respective face thereof.
  • the device and component are constructed and arranged to be stacked and bonded together.
  • a first laser selectively ablates the respective dielectric portions of the device and component. The ablating creates a starting pad on the device or component and a destination pad on the device or component.
  • a second laser deposits a conductor along a path between the starting pad and destination pad.
  • smaller, more condensed electronic packages may be fabricated, and gold wires and associated encapsulants may be eliminated from electronic package designs.
  • FIG. 2 illustrates a system 200 in which a conductor is deposited onto an electrical device using the energy of a laser beam and conductor precursor chemistries.
  • a laser beam such as a laser 201
  • Laser 201 may ablate—that is, remove—dielectric material from a substrate 220 to prepare the substrate for conductor deposition.
  • Laser 201 is then focused through an aperture 230 .
  • An aerosol generator 210 propels dissolved metal through aperture 230 .
  • the dissolved metal comes into contact with air 240 and is applied by laser 201 to substrate 220 .
  • a surface of a substrate is flooded with a solution, which a laser decomposes to generate a conductor.
  • FIG. 3 illustrates a system 300 of stacked, electrically interconnected semiconductor devices according to an embodiment of the present invention.
  • System 300 includes various semiconductor devices 310 that are stacked and bonded together.
  • Semiconductor devices 310 may be bonded and stacked together by artisans of ordinary skill in accordance with methods well known in the art.
  • Semiconductor devices 310 may be stacked on a substrate 301 , which is connected to a base printed wiring board or other interconnect device 330 via connection mechanisms, such as solder bumps 320 .
  • Semiconductor devices 310 and substrate 301 may include a dielectric portion, such as a coating, on at least one face thereof For instance, a top face of a semiconductor device 310 and an edge face thereof may include such an insulating coating.
  • the dielectric portion may comprise, for example, silicon oxide (SiOx) or a polyimide-type polymeric compound. The dielectric portion insulates existing base material and circuitry of semiconductor devices 310 from laser-formed conductors, thus preventing short circuits.
  • a dielectric material is applied to a semiconductor device, such as semiconductor device 310 in system 300 .
  • a dielectric material need not be applied.
  • a fabricated substrate, such as substrate 301 may include a dielectric material by design.
  • Each semiconductor device 310 is electrically connected, via laser-formed conductors 320 , to another semiconductor device 310 and/or to a package substrate 301 .
  • Each conductor 320 may be deposited by a laser along a path that begins at a starting pad on one of the devices 310 and ends at a destination pad on another device or substrate 301 .
  • a laser may selectively ablate respective dielectric portions of the semiconductor devices 310 that are to be electrically interconnected. Specifically, the ablating may create a starting pad on one such device and a destination pad on another such device. A laser may then deposit a conductor along a path between the starting pad and destination pad. The path may traverse, for instance, top surfaces and edges of semiconductor devices 310 .
  • laser control software may control the drawing of the path. In particular, such software may define the location of the starting pad, turn the laser on, move the laser or the bed on which the device is resting, stop the movement of the laser at the destination pad, and turn off the laser.
  • control software may then move the device or the laser to the next starting pad to begin the process again. It is to be appreciated that in some embodiments, the same laser or different lasers may be used for various processes, such as the ablation or deposition processes.
  • Connections between a device and the carrier substrate may enable signal transmission to and from other devices on printed wiring board 330 . Moreover, wire bonding or encapsulants need not be employed in embodiments of the present invention. Thus, the overall height of the stacked semiconductor devices is reduced. The number of interconnections possible among semiconductor devices and/or a carrier substrate may depend on a number of factors, including the amount of surface area available in a given implementation, as well as the width of the laser beam employed in the assembly process.
  • FIGS. 4A and 4B illustrate top and side views, respectively, of a system 400 according to an embodiment of the present invention.
  • semiconductor devices 440 A, 440 B and substrate 401 are stacked together.
  • Device 440 A and device 440 B are electrically interconnected via conductors 420 , which are deposited with a laser.
  • Device 440 A and substrate 401 are electrically interconnected via conductors 410 .
  • Device 440 B and substrate 401 are electrically interconnected via conductors 430 .
  • the height of such a stacked configuration is relatively small, and gold wire and encapsulant materials need not be incorporated into the design.
  • FIG. 5 is a high-level flow diagram of a process 500 for electrically interconnecting semiconductor devices according to an embodiment of the present invention.
  • a semiconductor device and a component are provided.
  • a dielectric material is applied, if not already present, to the semiconductor device and component.
  • the device and component are stacked and bonded in tasks 520 and 530 , respectively, to provide mechanical interconnections therebetween. It is to be appreciated that various steps, such as stacking and bonding, may occur as one task or multiple tasks within an overall package assembly process.
  • a laser selectively ablates dielectric material from the device and component to create a starting pad and a destination pad.
  • the starting pad may reside on the device, and the destination pad may reside on the component. Alternatively, the starting pad may reside on the component, and the destination pad may reside on the device.
  • a laser deposits a conductor along a path between the starting pad and destination pad.
  • process 500 may include a task wherein an assembly device locates at least two registration fiducials on the component and the device, and orients a laser or lasers based at least in part on the locating. It is to be appreciated that one laser or multiple lasers may be used for various tasks in process 500 .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

A method and system for electrically interconnecting a semiconductor device and a component is presented. The semiconductor device includes a dielectric portion on at least one face thereof. Similarly, the component includes a dielectric portion on at least one face thereof The device and component are constructed and arranged to be stacked and bonded together. A first laser selectively ablates the respective dielectric portions of the device and component. The ablating creates a starting pad on the device or component and a destination pad on the device or component. A second laser deposits a conductor along a path between the starting pad and destination pad. As such, smaller, more condensed electronic packages may be fabricated.

Description

    BACKGROUND
  • 1. Field [0001]
  • This invention relates generally to packaging of integrated circuits. More specifically, this invention relates to a method and system for electrically interconnecting semiconductor devices. [0002]
  • 2. Background and Related Art [0003]
  • In electronic packages, semiconductor devices may be stacked together atop package substrates. FIG. 1 (Prior Art) illustrates a [0004] package 100. Package 100 is a stacked chip composite device that includes a substrate 101, a semiconductor die 110 stacked atop substrate 101, and a semiconductor die 120 stacked atop die 110. Solder bumps 150 are typically employed to assemble the stacked chip composite device to a printed wiring board (not shown). Each die 110, 120 and substrate 101 are electrically interconnected. via wire bond technology. Specifically, each die 110, 120 is electrically connected to substrate 101 via gold wires 130. Die 110 and die 120 also may be electrically interconnected via gold wire connections (not shown). An. encapsulant or mold 140 in package 100 protects gold wires 130.
  • In other arrangements (not shown), die [0005] 120 and substrate 101 are electrically interconnected via gold wires, and die 110 and substrate 101 are electrically interconnected using solder bumps. The entire package is then encapsulated with an encapsulant.
  • The inclusion of gold wires and encapsulants within packages such as [0006] package 100 leads to a large total package height, which places constraints on application design. Moreover, the inclusion of gold wires and encapsulants makes such packages relatively difficult and expensive to fabricate.
  • Therefore, what is needed is an improved method and system for electrically interconnecting semiconductor devices.[0007]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 (Prior Art) illustrates a package that includes gold wires and an encapsulant. [0008]
  • FIG. 2 (Prior Art) illustrates a system for depositing a conductor via a laser. [0009]
  • FIG. 3 illustrates a system that includes stacked semiconductor devices that are electrically interconnected according to an embodiment of the present invention. [0010]
  • FIGS. 4A and 4B are top and side views, respectively, of stacked semiconductor devices that are electrically interconnected according to an embodiment of the present invention. [0011]
  • FIG. 5 is a high-level flow diagram illustrating a process for electrically interconnecting semiconductor devices according to an embodiment of the present invention.[0012]
    • DETAILED DESCRIPTION
  • A method and system for electrically interconnecting a semiconductor device and a component, as disclosed herein, involve a semiconductor device and a component, such as another semiconductor device or a carrier substrate. The device and component include respective dielectric portions on at least one respective face thereof. The device and component are constructed and arranged to be stacked and bonded together. A first laser selectively ablates the respective dielectric portions of the device and component. The ablating creates a starting pad on the device or component and a destination pad on the device or component. A second laser deposits a conductor along a path between the starting pad and destination pad. In accordance with embodiments of the present invention, smaller, more condensed electronic packages may be fabricated, and gold wires and associated encapsulants may be eliminated from electronic package designs. [0013]
  • FIG. 2 (Prior Art) illustrates a [0014] system 200 in which a conductor is deposited onto an electrical device using the energy of a laser beam and conductor precursor chemistries. A laser beam, such as a laser 201, may ablate—that is, remove—dielectric material from a substrate 220 to prepare the substrate for conductor deposition. Laser 201 is then focused through an aperture 230. An aerosol generator 210 propels dissolved metal through aperture 230. The dissolved metal comes into contact with air 240 and is applied by laser 201 to substrate 220. In another system (not shown), a surface of a substrate is flooded with a solution, which a laser decomposes to generate a conductor.
  • FIG. 3 illustrates a [0015] system 300 of stacked, electrically interconnected semiconductor devices according to an embodiment of the present invention. System 300 includes various semiconductor devices 310 that are stacked and bonded together. Semiconductor devices 310 may be bonded and stacked together by artisans of ordinary skill in accordance with methods well known in the art. Semiconductor devices 310 may be stacked on a substrate 301, which is connected to a base printed wiring board or other interconnect device 330 via connection mechanisms, such as solder bumps 320.
  • [0016] Semiconductor devices 310 and substrate 301 may include a dielectric portion, such as a coating, on at least one face thereof For instance, a top face of a semiconductor device 310 and an edge face thereof may include such an insulating coating. The dielectric portion may comprise, for example, silicon oxide (SiOx) or a polyimide-type polymeric compound. The dielectric portion insulates existing base material and circuitry of semiconductor devices 310 from laser-formed conductors, thus preventing short circuits.
  • In some embodiments, a dielectric material is applied to a semiconductor device, such as [0017] semiconductor device 310 in system 300. In other embodiments, a dielectric material need not be applied. For instance, a fabricated substrate, such as substrate 301, may include a dielectric material by design.
  • Each [0018] semiconductor device 310 is electrically connected, via laser-formed conductors 320, to another semiconductor device 310 and/or to a package substrate 301. Each conductor 320 may be deposited by a laser along a path that begins at a starting pad on one of the devices 310 and ends at a destination pad on another device or substrate 301.
  • To fabricate each [0019] conductor 320, a laser may selectively ablate respective dielectric portions of the semiconductor devices 310 that are to be electrically interconnected. Specifically, the ablating may create a starting pad on one such device and a destination pad on another such device. A laser may then deposit a conductor along a path between the starting pad and destination pad. The path may traverse, for instance, top surfaces and edges of semiconductor devices 310. In an exemplary implementation, laser control software may control the drawing of the path. In particular, such software may define the location of the starting pad, turn the laser on, move the laser or the bed on which the device is resting, stop the movement of the laser at the destination pad, and turn off the laser. For a subsequent conductor, the control software may then move the device or the laser to the next starting pad to begin the process again. It is to be appreciated that in some embodiments, the same laser or different lasers may be used for various processes, such as the ablation or deposition processes.
  • Connections between a device and the carrier substrate may enable signal transmission to and from other devices on printed [0020] wiring board 330. Moreover, wire bonding or encapsulants need not be employed in embodiments of the present invention. Thus, the overall height of the stacked semiconductor devices is reduced. The number of interconnections possible among semiconductor devices and/or a carrier substrate may depend on a number of factors, including the amount of surface area available in a given implementation, as well as the width of the laser beam employed in the assembly process.
  • FIGS. 4A and 4B illustrate top and side views, respectively, of a [0021] system 400 according to an embodiment of the present invention. As shown, semiconductor devices 440A, 440B and substrate 401 are stacked together. Device 440A and device 440B are electrically interconnected via conductors 420, which are deposited with a laser. Device 440A and substrate 401 are electrically interconnected via conductors 410. Device 440B and substrate 401 are electrically interconnected via conductors 430. The height of such a stacked configuration is relatively small, and gold wire and encapsulant materials need not be incorporated into the design.
  • FIG. 5 is a high-level flow diagram of a [0022] process 500 for electrically interconnecting semiconductor devices according to an embodiment of the present invention. In task 501, a semiconductor device and a component are provided. In task 510, a dielectric material is applied, if not already present, to the semiconductor device and component. The device and component are stacked and bonded in tasks 520 and 530, respectively, to provide mechanical interconnections therebetween. It is to be appreciated that various steps, such as stacking and bonding, may occur as one task or multiple tasks within an overall package assembly process.
  • In [0023] task 540, during a first scan, a laser selectively ablates dielectric material from the device and component to create a starting pad and a destination pad. The starting pad may reside on the device, and the destination pad may reside on the component. Alternatively, the starting pad may reside on the component, and the destination pad may reside on the device. In task 550, during a second scan, a laser deposits a conductor along a path between the starting pad and destination pad.
  • Though not shown in FIG. 5, [0024] process 500 may include a task wherein an assembly device locates at least two registration fiducials on the component and the device, and orients a laser or lasers based at least in part on the locating. It is to be appreciated that one laser or multiple lasers may be used for various tasks in process 500.
  • The foregoing description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments are possible, and the generic principles presented herein may be applied to other embodiments as well. As such, the present invention is not intended to be limited to the embodiments shown above but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein. [0025]

Claims (10)

1-17 (Cancelled).
18. An electronic package including interconnected chips, comprising:
a semiconductor device including a dielectric portion on at least one face thereof;
a component stacked with and bonded to the semiconductor device, the component including a dielectric portion on at least one face thereof; and
at least one interconnection between the device and component, the interconnection comprising a conductor along a path between a starting pad on one of the device and component and a destination pad on the other of the device and component, the starting pad and destination pad being created by selectively ablating, by at least a first laser, the respective dielectric portions of the device and component, and the conductor being deposited along the path by at least a second laser.
19. The electronic package of claim 18, further comprising a second semiconductor device constructed and arranged to interpose the device and component and to be stacked with and bonded to the device and component.
20. The electronic package of claim 18, wherein the dielectric portion of the device comprises silicon oxide (SiOx).
21. The electronic package of claim 18, wherein the dielectric portion of the device comprises a polyimide-type polymeric compound.
22. The electronic package of claim 18, wherein the at least one face of the device comprises a top face or an edge face.
23. The electronic package of claim 18, wherein the component is a semiconductor device.
24. The electronic package of claim 18, wherein the component is a carrier substrate.
25. The electronic package of claim 18, wherein the at least one interconnection is exclusive of a wire bond interconnection.
26. The electronic package of claim 18, wherein the at least one interconnection is exclusive of an encapsulant.
US10/869,176 2002-01-11 2004-06-16 Method and system to manufacture stacked chip devices Abandoned US20040222512A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009117882A1 (en) * 2008-03-27 2009-10-01 Hong Kong Applied Science and Technology Research Institute Co. Ltd Pulse-laser bonding method for through-silicon-via based stacking of electronic components

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004008135A1 (en) * 2004-02-18 2005-09-22 Infineon Technologies Ag Semiconductor device with a stack of semiconductor chips and method for producing the same
US7429785B2 (en) 2005-10-19 2008-09-30 Littelfuse, Inc. Stacked integrated circuit chip assembly
JP2009141169A (en) * 2007-12-07 2009-06-25 Shinko Electric Ind Co Ltd Semiconductor device

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4555720A (en) * 1982-03-03 1985-11-26 U.S. Philips Corporation Infra-red radiation detectors and their manufacture
US4613891A (en) * 1984-02-17 1986-09-23 At&T Bell Laboratories Packaging microminiature devices
US5355102A (en) * 1990-04-05 1994-10-11 General Electric Company HDI impedance matched microwave circuit assembly
US5391516A (en) * 1991-10-10 1995-02-21 Martin Marietta Corp. Method for enhancement of semiconductor device contact pads
US5410179A (en) * 1990-04-05 1995-04-25 Martin Marietta Corporation Microwave component having tailored operating characteristics and method of tailoring
US5653019A (en) * 1995-08-31 1997-08-05 Regents Of The University Of California Repairable chip bonding/interconnect process
US5970319A (en) * 1997-10-14 1999-10-19 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6251488B1 (en) * 1999-05-05 2001-06-26 Optomec Design Company Precision spray processes for direct write electronic components
US6268584B1 (en) * 1998-01-22 2001-07-31 Optomec Design Company Multiple beams and nozzles to increase deposition rate
US6365975B1 (en) * 1997-04-02 2002-04-02 Tessera, Inc. Chip with internal signal routing in external element
US20030116859A1 (en) * 1997-03-10 2003-06-26 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6627531B2 (en) * 2000-03-22 2003-09-30 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6650019B2 (en) * 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
US6885092B1 (en) * 1997-09-29 2005-04-26 Hitachi, Ltd. Semiconductor device and a memory system including a plurality of IC chips in a common package

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4555720A (en) * 1982-03-03 1985-11-26 U.S. Philips Corporation Infra-red radiation detectors and their manufacture
US4613891A (en) * 1984-02-17 1986-09-23 At&T Bell Laboratories Packaging microminiature devices
US5355102A (en) * 1990-04-05 1994-10-11 General Electric Company HDI impedance matched microwave circuit assembly
US5410179A (en) * 1990-04-05 1995-04-25 Martin Marietta Corporation Microwave component having tailored operating characteristics and method of tailoring
US5391516A (en) * 1991-10-10 1995-02-21 Martin Marietta Corp. Method for enhancement of semiconductor device contact pads
US5653019A (en) * 1995-08-31 1997-08-05 Regents Of The University Of California Repairable chip bonding/interconnect process
US20030116859A1 (en) * 1997-03-10 2003-06-26 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6365975B1 (en) * 1997-04-02 2002-04-02 Tessera, Inc. Chip with internal signal routing in external element
US6885092B1 (en) * 1997-09-29 2005-04-26 Hitachi, Ltd. Semiconductor device and a memory system including a plurality of IC chips in a common package
US5970319A (en) * 1997-10-14 1999-10-19 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6268584B1 (en) * 1998-01-22 2001-07-31 Optomec Design Company Multiple beams and nozzles to increase deposition rate
US6251488B1 (en) * 1999-05-05 2001-06-26 Optomec Design Company Precision spray processes for direct write electronic components
US6627531B2 (en) * 2000-03-22 2003-09-30 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6650019B2 (en) * 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009117882A1 (en) * 2008-03-27 2009-10-01 Hong Kong Applied Science and Technology Research Institute Co. Ltd Pulse-laser bonding method for through-silicon-via based stacking of electronic components
US20090243046A1 (en) * 2008-03-27 2009-10-01 Xunqing Shi Pulse-Laser Bonding Method for Through-Silicon-Via Based Stacking of Electronic Components
US8138577B2 (en) 2008-03-27 2012-03-20 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Pulse-laser bonding method for through-silicon-via based stacking of electronic components

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