US20040211517A1 - Method of etching with NH3 and fluorine chemistries - Google Patents
Method of etching with NH3 and fluorine chemistries Download PDFInfo
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- US20040211517A1 US20040211517A1 US10/847,695 US84769504A US2004211517A1 US 20040211517 A1 US20040211517 A1 US 20040211517A1 US 84769504 A US84769504 A US 84769504A US 2004211517 A1 US2004211517 A1 US 2004211517A1
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- containing gas
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- 238000005530 etching Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 33
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910052731 fluorine Inorganic materials 0.000 title claims abstract description 25
- 239000011737 fluorine Substances 0.000 title claims abstract description 25
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 66
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 62
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000005086 pumping Methods 0.000 abstract description 2
- 210000002381 plasma Anatomy 0.000 description 47
- 239000007789 gas Substances 0.000 description 36
- 239000006117 anti-reflective coating Substances 0.000 description 25
- 235000012431 wafers Nutrition 0.000 description 19
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 14
- 239000002245 particle Substances 0.000 description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- 229920005573 silicon-containing polymer Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C15/00—Surface treatment of glass, not in the form of fibres or filaments, by etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Definitions
- the present invention relates to the fabrication of semiconductor-based devices. More particularly, the present invention relates to improved techniques for fabricating semiconductor-based devices with low dielectric constant materials.
- dual damascene structures may be used in conjunction with copper conductor material to reduce the RC delays associated with signal propagation in aluminum based materials used in previous generation technologies.
- dual damascene instead of etching the conductor material, vias, and trenches may be etched into the dielectric material and filled with copper. The excess copper may be removed by chemical mechanical polishing (CMP) leaving copper lines connected by vias for signal transmission.
- CMP chemical mechanical polishing
- Low dielectric constant materials are here defined as materials with a dielectric constant of less than about 3.7.
- These low dielectric constant materials may include organo-silicate-glass (OSG) materials, such as CoralTM and Black DiamondTM, or may be purely organic materials, such as SILKTM or FlareTM.
- OSG materials may be silicon dioxide doped with organic components such as methyl groups. Etching these materials and stripping the photoresist on these materials may be significantly different and much more challenging than when conventional oxide materials are used. Oxygen containing plasmas may not be suitable for stripping resist on OSG materials, since oxygen plasmas may oxidize the organic content of low k OSG materials or may cause bowing during the etch of purely organic low k materials.
- FIG. 1A is a cross-sectional view of a stack 100 on a wafer 110 used in the damascene process of the prior art.
- a contact 104 may be placed in a dielectric layer 108 over the wafer 110 .
- a barrier layer 112 which may be of silicon nitride or silicon carbide, may be placed over the contact 104 to prevent the copper diffusion.
- a via level low k material layer 116 may be placed over the barrier layer 112 and dielectric layer 108 .
- a trench stop layer 120 may be placed over the via level low k layer 116 .
- a trench level low k material layer 124 may be placed over the trench stop layer 120 .
- a hard mask and/or an antireflective coating (ARC) layer 128 may be placed over the trench level low k material layer 124 .
- a patterned resist layer 132 may be placed over the hard mask and/or an antireflective coating (ARC) layer 128 .
- the via level low k material layer 116 and the trench level low k material layer 124 may be formed from a low dielectric constant OSG material or organic material.
- the trench etch stop layer 120 may be formed from silicon carbide or silicon nitride. SiON or organic anti reflective coating (BARC) may be used to form the ARC layer 128 .
- FIG. 1B is a cross-sectional view of the stack 100 after a via 136 and a trench 140 have been etched.
- ARC antireflective coating
- the etch stop layer 120 and the barrier layer 112 it may be desirable to use a fluorine containing gas as a gas source for an etching plasma.
- an ammonia (NH 3 ) containing gas it may be desirable to use an ammonia (NH 3 ) containing gas as a gas source for an etching plasma.
- a fluorine source may be added to NH 3 to remove any unwanted polymeric residue from the open areas of the wafer.
- a fluorine source may be added to NH 3 to remove any unwanted polymeric residue from the open areas of the wafer.
- a fluorine containing gas similar to the gas used to etch the ARC layer 128 , the etch stop layer 120 and barrier layer 112 .
- NH 3 gas To strip the photo resist after via, trench, or barrier etch, it may be desirable to use NH 3 gas.
- a polymer crust 144 may be deposited over the patterned resist layer 132 and side walls of the trench 140 and via 140 .
- a fluorine containing etchant gas in combination with NH3.
- an etchant gas with a fluorine containing gas and an ammonia containing gas either together or in alternating steps, such attempts in the prior art resulted in the formation of particles, which may contaminate the plasma processing chamber and may increase defects in the resulting semiconductor structure. Thus such processes, which used ammonia and fluorine in the same chamber were avoided.
- the stack is placed in a plasma processing chamber.
- a fluorine containing gas is flowed into the plasma processing chamber.
- An ammonia containing gas is flowed into the plasma processing chamber.
- a plasma is generated.
- the stack is then etched.
- the present invention provides a device for etching stacks on a substrate.
- the device comprises: a plasma chamber with chamber walls; a plasma confinement device for reducing plasma contact with the chamber walls; a gas source; plasma generation and energizing device; and an exhaust system for pumping plasma away.
- the gas source comprises a fluorine containing gas source and an ammonia containing gas source.
- FIGS. 1 A-B are cross-sectional views of a stack on a wafer used in the damascene process of the prior art.
- FIG. 2 is a schematic view of a plasma processing chamber that may be used in a preferred embodiment of the invention.
- FIG. 3 is a flow chart of a process that uses the plasma processing chamber.
- FIGS. 4 A-B are cross-sectional views of a stack on a wafer used in the damascene process in a preferred embodiment of the invention.
- FIG. 5 is a more detailed flow chart for the step of etching the via.
- FIGS. 6 A-C are cross-sectional views of a stack on a wafer used in the damascene process in a preferred embodiment of the invention after a via has been etched.
- FIG. 7 is a more detailed flow chart for the step of etching the trench.
- FIG. 8 is a graph of the number of particles over 0.16 microns versus the number of wafers processed found during a test.
- FIG. 2 is a schematic view of a plasma processing chamber 200 that may be used in a preferred embodiment of the invention.
- the plasma processing chamber 200 comprising confinement rings 202 , an upper electrode 204 , a lower electrode 208 , a gas source 210 , and an exhaust pump 220 .
- the gas source 210 comprises a fluorine containing gas source 212 and an ammonia containing gas source 216 .
- the gas source 210 may comprise additional gas sources.
- a substrate 224 is positioned upon the lower electrode 208 .
- the lower electrode 208 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding the substrate 224 .
- a suitable substrate chucking mechanism e.g., electrostatic, mechanical clamping, or the like
- the reactor top 228 incorporates the upper electrode 204 disposed immediately opposite the lower electrode 208 .
- the upper electrode 204 , lower electrode 208 , and confinement rings 202 define the confined plasma volume 240 .
- Gas is supplied to the confined plasma volume 240 by gas source 210 and is exhausted from the confined plasma volume 240 through the confinement rings 202 and an exhaust port by the exhaust pump 220 .
- a first RF source 244 is electrically connected to the upper electrode 204 .
- a second RF source 248 is electrically connected to the lower electrode 208 .
- Different combinations of connecting RF power to the electrode are possible. In case of Exelan HP both the RF sources are connected to the lower electrode and the upper electrode is grounded.
- Chamber walls 252 surround the confinement rings 202 , the upper electrode 204 , and the lower electrode 208 .
- Both the first RF source 244 and the second RF source 248 may comprise a 27 MHz power source and a 2 MHz power source.
- the upper electrode 204 and the lower electrode are spaced are preferably spaced apart by a distance of about 1.35 cm but may have a spacing up to 2.0 cm.
- FIG. 3 is a flow chart of a process that uses the plasma processing chamber 200 .
- a stack 400 is formed on a wafer 224 (step 304 ), as shown in FIG. 4A.
- a contact 404 may be placed in a dielectric layer 408 over a wafer 224 .
- a barrier layer 412 which may be of silicon nitride or silicon carbide, may be placed over the contact 404 to prevent a copper or metal diffusion.
- a via level low k material layer 416 may be placed over the barrier layer 412 .
- a trench stop layer 420 may be placed over the via level low k layer 416 .
- the trench stop layer 420 may be made of silicon nitride (SiN).
- a trench level low k material layer 424 may be placed over the trench stop layer 420 .
- a hard mask and/or an antireflective coating (ARC) layer 428 may be placed over the trench level low k material layer 424 .
- a patterned resist layer 432 patterned for etching a via may be placed over the hard mask and/or an antireflective coating (ARC) layer 428 .
- the via level low k material layer 416 and the trench level low k material layer 424 may be formed from a low dielectric constant OSG material or organic material.
- the trench etch stop layer 420 may be formed from silicon carbide, instead of silicon nitride, and the hard mask layer may be formed from SiN.
- the ARC layer 428 may be formed from SiON or organic anti reflective coating.
- the patterned resist layer 432 may be made of a photo resist layer with the ARC layer 428 acting as an antireflective coating.
- the stack 400 may be placed over other layers over the wafer 224 .
- the wafer 224 may then be placed in the plasma processing chamber 200 (step 308 ).
- a via is then etched (step 312 ).
- a gas is flowed from the gas source 210 .
- Energy is provided by the first RF source 244 and the second RF source 248 , which energizes and ionizes the gas generating a plasma.
- the plasma is partially confined to the confined plasma volume 240 , where the plasma is able to etch the stack 400 on the wafer 224 .
- the plasma is then vented past the confinement rings 202 to the exhaust pump 220 .
- the confinement rings 202 reduce plasma interaction with the chamber walls 252 .
- FIG. 4B is a schematic view of the stack 400 with an etched via 440 .
- the via 440 the hard mask and or ARC layer 428 , the trench level low k material layer 424 , the trench stop layer 420 , and the via level low k material layer 416 are etched.
- FIG. 5 is a more detailed flow chart for the step of etching the via (step 312 ) where the trench level low k material 424 and the via level low k material 416 are organic.
- First the via is etched through the hard mask/ARC layer 428 (step 504 ).
- One recipe set of parameters for etching the hard mask/ARC layer 428 is provided in Table I where sccm stands for Standard Cubic Centimeters per minute.
- the flow rate of pressure was approximately 70 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 1,000 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 160 sccm; the flow rate of oxygen (O 2 ) was approximately 15 sccm; the flow rate of CF 4 was approximately 40 sccm; the flow rate of C 4 F 8 was approximately 5 sccm.
- the via level organic low k material layer 424 is etched (step 508 ).
- One recipe set of parameters for etching the trench level low k material layer 424 is provided in Table II.
- Table II MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 0-300 100-200 140-160 (mTorr) Flow rate of NH 3 500-1500 750-1250 900-1100 (sccm) Power at 27 MHz 250-750 300-700 450-550 (Watts) Power at 2 MHz 0-500 0-250 0 (Watts)
- the flow rate of pressure was approximately 150 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 0 Watts was provided at 2 MHz; the flow rate of NH 3 was approximately 1,000 sccm.
- the via etch of the organic low k material using NH 3 plasma all the resist material to form the via pattern is removed. After via etch the stack is repatterned with photo resist trench pattern to form trench pattern on the wafers.
- the trench stop layer 420 is etched (step 512 ).
- One recipe set of parameters for etching an SiN trench stop layer 420 is provided in Table III. TABLE III MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 0-180 60-120 80-100 (mTorr) Flow rate of Ar 75-300 100-200 130-170 (sccm) Flow rate of CHF 3 6-18 9-15 11-13 (sccm) Flow rate of CF 4 10-40 15-35 20-30 (sccm) Flow rate of O 2 5-15 7-13 9-11 (sccm) Flow rate of N 2 15-45 20-40 25-35 (sccm) Power at 27 MHz 300-1200 450-750 550-650 (Watts) Power at 2 MHz 50-200 75-125 90-110 (Watts)
- the flow rate of pressure was approximately 90 mTorr; approximately 600 Watts was provided at 27 MHz; approximately 100 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 150 sccm; the flow rate of oxygen (O 2 ) was approximately 10 sccm; the flow rate of CF 4 was approximately 25 sccm; the flow rate of CHF 3 was approximately 12 sccm; the flow rate of N 2 was approximately 30 sccm.
- the trench level low k material layer 424 is etched (step 516 ).
- One recipe set of parameters for etching the trench level low k material layer 424 is provided in Table IV.
- Table IV TABLE IV MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 0-300 100-200 140-160 (mTorr) Flow rate of NH 3 500-1500 750-1250 900-1100 (sccm) Power at 27 MHz 250-750 300-700 450-550 (Watts) Power at 2 MHz 0-500 0-250 0 (Watts)
- the flow rate of pressure was approximately 150 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 0 Watts was provided at 2 MHz; the flow rate of NH 3 was approximately 1,000 sccm;.
- etching via 440 in the OSG low k materials to the barrier layer 412 may be stopped.
- a silicon containing polymer crust 444 may be deposited over the patterned resist layer 432 and the sidewalls of the via 440 as a result of the via etching.
- the plasma chamber 200 may be used to strip the polymer crust 444 , when etching OSG low k materials, and the patterned resist layer 432 , when etching either OSG low k materials or organic low k materials (step 316 ).
- a recipe for stripping the polymer crust 444 and patterned resist layer 432 may use NH 3 as a plasma source gas for stripping the photoresist.
- the wafer 224 may be removed from the plasma chamber 200 to allow the depositing of a new patterned resist layer 504 (step 320 ), as shown in FIG. 6A.
- the wafer 224 may be placed back in the plasma chamber 200 (step 324 ).
- a trench 604 is etched (step 328 ), as shown in FIG. 6B.
- FIG. 7 is a more detailed flow chart for the step of etching the trench (step 328 ) when the trench level layer 424 is an organic low k material.
- the trench is etched through the hard mask/ARC layer 428 (step 704 ).
- One recipe set of parameters for etching the hard mask/ARC layer 428 is provided in Table I above.
- the flow rate of pressure was approximately 70 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 1,000 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 160 sccm; the flow rate of oxygen (O 2 ) was approximately 15 sccm; the flow rate of CF 4 was approximately 40 sccm; the flow rate of C 4 F 8 was approximately 5 sccm.
- the trench level organic low k material layer 424 is etched (step 708 ).
- One recipe set of parameters for etching the trench level organic low k material layer 424 is provided in Table II.
- the flow rate of pressure was approximately 150 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 0 Watts was provided at 2 MHz; the flow rate of NH 3 was approximately 1,000 sccm.
- the trench etching may be stopped.
- the barrier layer 412 may then be etched (step 332 ).
- One recipe set of parameters for etching the barrier layer 412 is provided in Table V.
- the flow rate of pressure was approximately 158 mTorr; approximately 400 Watts was provided at 27 MHz; approximately 200 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 300 sccm; the flow rate of CHF 3 was approximately 20 sccm; the flow rate of N 2 was approximately 100 sccm.
- a silicon containing polymer crust 608 may be deposited over the patterned resist layer 432 and the sidewalls of the via 440 and trench 604 as a result of the trench etching, as shown in FIG. 6B.
- the plasma chamber 200 may be used to strip the polymer crust 608 and patterned resist layer 504 (step 336 ).
- a recipe for stripping the polymer crust 608 and patterned resist layer 504 may use NH 3 as a plasma source gas for stripping the photoresist.
- the wafer 224 as shown in FIG. 6C, may be removed from the plasma chamber 200 (step 340 ).
- FIG. 8 is a graph of the number of particles over 0.16 microns (Particle count) versus the number of wafers processed (0-500) found during the test.
- the level of particle generation is below 30, which is normal for the chamber, indicating that the confinement rings 202 , small plasma volume 240 , and exhaust pump 220 speed help to minimize plasma contact with the walls of the chamber so that formed ammonium fluoride does not have a chance to condense onto the walls of the chamber to form a higher number of particles.
- the trench level low k material layer 424 and the via level low k material 416 are made of an OSG material
- the trench level low k material 424 , the via level low k material 416 , the ARC layer 428 , barrier layer 412 , and the trench stop layer 420 may be all etched with fluorine containing etchant gases.
- an NH 3 stripping gas may be used. More preferably an NH 3 gas combined with a CF 4 gas may be used to strip the patterned resist layer.
- an ammonia containing gas and a fluorine containing gas are used at the same time within the same plasma chamber and at alternating times.
- plasma confinement devices which keep plasma from the chamber walls may be used in place of the confinement rings.
- Other types of plasma generation and energizing systems may be used in place of the upper and lower electrodes 204 , 208 and the first and second RF sources 244 , 248 , which may generate and energize a plasma in a small plasma volume.
- Another embodiment of the invention may use a combined resist strip and barrier etch step to reduced etching damage as described in U.S. patent application Ser. No. ______ (Attorney Docket Number LAM1P158) entitled “A Combined Resist Strip And Barrier Etch Process For Dual Damascene Structures” by Rao Annapragada and Reza Sadjadi, with the same filing date, and which is incorporated by reference.
Abstract
A method of etching a stack using a fluorine containing gas and an ammonia containing gas is provided. Generally, the stack is placed in a plasma processing chamber. A fluorine containing gas is flowed into the plasma processing chamber. An ammonia containing gas is flowed into the plasma processing chamber. A plasma is generated. The stack is then etched.
In addition, a device for etching stacks on a substrate is provided. The device comprises: a plasma chamber with chamber walls; a plasma confinement device for reducing plasma contact with the chamber walls; a gas source; plasma generation and energizing device; and an exhaust system for pumping plasma away. The gas source comprises a fluorine containing gas source and an ammonia containing gas source.
Description
- The present invention relates to the fabrication of semiconductor-based devices. More particularly, the present invention relates to improved techniques for fabricating semiconductor-based devices with low dielectric constant materials.
- In semiconductor-based device (e.g., integrated circuits or flat panel displays) manufacturing, dual damascene structures may be used in conjunction with copper conductor material to reduce the RC delays associated with signal propagation in aluminum based materials used in previous generation technologies. In dual damascene, instead of etching the conductor material, vias, and trenches may be etched into the dielectric material and filled with copper. The excess copper may be removed by chemical mechanical polishing (CMP) leaving copper lines connected by vias for signal transmission. To reduce the RC delays even further, low dielectric constant materials may be used. Low dielectric constant materials are here defined as materials with a dielectric constant of less than about 3.7. These low dielectric constant materials may include organo-silicate-glass (OSG) materials, such as Coral™ and Black Diamond™, or may be purely organic materials, such as SILK™ or Flare™. OSG materials may be silicon dioxide doped with organic components such as methyl groups. Etching these materials and stripping the photoresist on these materials may be significantly different and much more challenging than when conventional oxide materials are used. Oxygen containing plasmas may not be suitable for stripping resist on OSG materials, since oxygen plasmas may oxidize the organic content of low k OSG materials or may cause bowing during the etch of purely organic low k materials.
- To facilitate discussion, FIG. 1A is a cross-sectional view of a
stack 100 on awafer 110 used in the damascene process of the prior art. Acontact 104 may be placed in adielectric layer 108 over thewafer 110. Abarrier layer 112, which may be of silicon nitride or silicon carbide, may be placed over thecontact 104 to prevent the copper diffusion. A via level lowk material layer 116 may be placed over thebarrier layer 112 anddielectric layer 108. Atrench stop layer 120 may be placed over the via levellow k layer 116. A trench level lowk material layer 124 may be placed over thetrench stop layer 120. A hard mask and/or an antireflective coating (ARC)layer 128 may be placed over the trench level lowk material layer 124. A patternedresist layer 132 may be placed over the hard mask and/or an antireflective coating (ARC)layer 128. The via level lowk material layer 116 and the trench level lowk material layer 124 may be formed from a low dielectric constant OSG material or organic material. The trenchetch stop layer 120 may be formed from silicon carbide or silicon nitride. SiON or organic anti reflective coating (BARC) may be used to form theARC layer 128. - FIG. 1B is a cross-sectional view of the
stack 100 after avia 136 and atrench 140 have been etched. To etch through the hard mask and/or an antireflective coating (ARC)layer 128, theetch stop layer 120 and thebarrier layer 112 it may be desirable to use a fluorine containing gas as a gas source for an etching plasma. To etch through the via level organic lowk material layer 116 and the trench level organic lowk material layer 124, it may be desirable to use an ammonia (NH3) containing gas as a gas source for an etching plasma. In addition, for organic low k materials, a fluorine source may be added to NH3 to remove any unwanted polymeric residue from the open areas of the wafer. To etch through the via level OSG lowk material layer 116 and the trench level OSG lowk material layer 124, it may be desirable to use a fluorine containing gas similar to the gas used to etch theARC layer 128, theetch stop layer 120 andbarrier layer 112. To strip the photo resist after via, trench, or barrier etch, it may be desirable to use NH3 gas. After the trench and via etches of OSG materials apolymer crust 144 may be deposited over the patternedresist layer 132 and side walls of thetrench 140 and via 140. To remove a silicon containingpolymer crust 144 it may be desirable to use a fluorine containing etchant gas in combination with NH3. Although it is desirable to use an etchant gas with a fluorine containing gas and an ammonia containing gas either together or in alternating steps, such attempts in the prior art resulted in the formation of particles, which may contaminate the plasma processing chamber and may increase defects in the resulting semiconductor structure. Thus such processes, which used ammonia and fluorine in the same chamber were avoided. - It is desirable to provide an efficient etching with minimal particle contamination.
- To achieve the foregoing and other objectives and in accordance with the purpose of the present invention for etching a stack, generally, the stack is placed in a plasma processing chamber. A fluorine containing gas is flowed into the plasma processing chamber. An ammonia containing gas is flowed into the plasma processing chamber. A plasma is generated. The stack is then etched.
- In addition, the present invention provides a device for etching stacks on a substrate. The device comprises: a plasma chamber with chamber walls; a plasma confinement device for reducing plasma contact with the chamber walls; a gas source; plasma generation and energizing device; and an exhaust system for pumping plasma away. The gas source comprises a fluorine containing gas source and an ammonia containing gas source.
- These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
- The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
- FIGS.1A-B are cross-sectional views of a stack on a wafer used in the damascene process of the prior art.
- FIG. 2 is a schematic view of a plasma processing chamber that may be used in a preferred embodiment of the invention.
- FIG. 3 is a flow chart of a process that uses the plasma processing chamber.
- FIGS.4A-B are cross-sectional views of a stack on a wafer used in the damascene process in a preferred embodiment of the invention.
- FIG. 5 is a more detailed flow chart for the step of etching the via.
- FIGS.6A-C are cross-sectional views of a stack on a wafer used in the damascene process in a preferred embodiment of the invention after a via has been etched.
- FIG. 7 is a more detailed flow chart for the step of etching the trench.
- FIG. 8 is a graph of the number of particles over 0.16 microns versus the number of wafers processed found during a test.
- The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
- To facilitate discussion, FIG. 2 is a schematic view of a
plasma processing chamber 200 that may be used in a preferred embodiment of the invention. Theplasma processing chamber 200 comprising confinement rings 202, anupper electrode 204, alower electrode 208, agas source 210, and anexhaust pump 220. Thegas source 210 comprises a fluorine containinggas source 212 and an ammonia containinggas source 216. Thegas source 210 may comprise additional gas sources. Withinplasma processing chamber 200, asubstrate 224 is positioned upon thelower electrode 208. Thelower electrode 208 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding thesubstrate 224. Thereactor top 228 incorporates theupper electrode 204 disposed immediately opposite thelower electrode 208. Theupper electrode 204,lower electrode 208, and confinement rings 202 define the confinedplasma volume 240. Gas is supplied to the confinedplasma volume 240 bygas source 210 and is exhausted from the confinedplasma volume 240 through the confinement rings 202 and an exhaust port by theexhaust pump 220. Afirst RF source 244 is electrically connected to theupper electrode 204. Asecond RF source 248 is electrically connected to thelower electrode 208. Different combinations of connecting RF power to the electrode are possible. In case of Exelan HP both the RF sources are connected to the lower electrode and the upper electrode is grounded.Chamber walls 252 surround the confinement rings 202, theupper electrode 204, and thelower electrode 208. Both thefirst RF source 244 and thesecond RF source 248 may comprise a 27 MHz power source and a 2 MHz power source. Theupper electrode 204 and the lower electrode are spaced are preferably spaced apart by a distance of about 1.35 cm but may have a spacing up to 2.0 cm. - FIG. 3 is a flow chart of a process that uses the
plasma processing chamber 200. Astack 400 is formed on a wafer 224 (step 304), as shown in FIG. 4A. Acontact 404 may be placed in adielectric layer 408 over awafer 224. Abarrier layer 412, which may be of silicon nitride or silicon carbide, may be placed over thecontact 404 to prevent a copper or metal diffusion. A via level lowk material layer 416 may be placed over thebarrier layer 412. Atrench stop layer 420 may be placed over the via levellow k layer 416. In a preferred embodiment, thetrench stop layer 420 may be made of silicon nitride (SiN). A trench level lowk material layer 424 may be placed over thetrench stop layer 420. A hard mask and/or an antireflective coating (ARC)layer 428 may be placed over the trench level lowk material layer 424. A patterned resistlayer 432 patterned for etching a via may be placed over the hard mask and/or an antireflective coating (ARC)layer 428. The via level lowk material layer 416 and the trench level lowk material layer 424 may be formed from a low dielectric constant OSG material or organic material. The trenchetch stop layer 420 may be formed from silicon carbide, instead of silicon nitride, and the hard mask layer may be formed from SiN. TheARC layer 428 may be formed from SiON or organic anti reflective coating. The patterned resistlayer 432 may be made of a photo resist layer with theARC layer 428 acting as an antireflective coating. Thestack 400 may be placed over other layers over thewafer 224. - The
wafer 224 may then be placed in the plasma processing chamber 200 (step 308). A via is then etched (step 312). Generally, to provide etching in the plasma processing chamber 200 a gas is flowed from thegas source 210. Energy is provided by thefirst RF source 244 and thesecond RF source 248, which energizes and ionizes the gas generating a plasma. The plasma is partially confined to the confinedplasma volume 240, where the plasma is able to etch thestack 400 on thewafer 224. The plasma is then vented past the confinement rings 202 to theexhaust pump 220. The confinement rings 202 reduce plasma interaction with thechamber walls 252. FIG. 4B is a schematic view of thestack 400 with an etched via 440. To etch the via 440 the hard mask and orARC layer 428, the trench level lowk material layer 424, thetrench stop layer 420, and the via level lowk material layer 416 are etched. - FIG. 5 is a more detailed flow chart for the step of etching the via (step312) where the trench level
low k material 424 and the via levellow k material 416 are organic. First the via is etched through the hard mask/ARC layer 428 (step 504). One recipe set of parameters for etching the hard mask/ARC layer 428 is provided in Table I where sccm stands for Standard Cubic Centimeters per minute.TABLE I MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 0-140 35-105 60-80 (mTorr) Flow rate of Ar 80-320 120-200 150-170 (sccm) Flow rate of C4F8 1-9 3-7 5 (sccm) Flow rate of CF4 10-80 30-50 35-45 (sccm) Flow rate of O2 4-26 10-20 13-17 (sccm) Power at 27 MHz 250-750 300-700 450-550 (Watts) Power at 2 MHz 500-1500 750-1250 900-1100 (Watts) - In a preferred embodiment for etching the hard mask/ARC layer428: the flow rate of pressure was approximately 70 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 1,000 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 160 sccm; the flow rate of oxygen (O2) was approximately 15 sccm; the flow rate of CF4 was approximately 40 sccm; the flow rate of C4F8 was approximately 5 sccm.
- Next the via level organic low
k material layer 424 is etched (step 508). One recipe set of parameters for etching the trench level lowk material layer 424 is provided in Table II.TABLE II MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 0-300 100-200 140-160 (mTorr) Flow rate of NH3 500-1500 750-1250 900-1100 (sccm) Power at 27 MHz 250-750 300-700 450-550 (Watts) Power at 2 MHz 0-500 0-250 0 (Watts) - In the preferred embodiment for etching the trench level low k material layer424: the flow rate of pressure was approximately 150 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 0 Watts was provided at 2 MHz; the flow rate of NH3 was approximately 1,000 sccm. During the via etch of the organic low k material using NH3 plasma, all the resist material to form the via pattern is removed. After via etch the stack is repatterned with photo resist trench pattern to form trench pattern on the wafers.
- Next the
trench stop layer 420 is etched (step 512). One recipe set of parameters for etching an SiNtrench stop layer 420 is provided in Table III.TABLE III MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 0-180 60-120 80-100 (mTorr) Flow rate of Ar 75-300 100-200 130-170 (sccm) Flow rate of CHF3 6-18 9-15 11-13 (sccm) Flow rate of CF4 10-40 15-35 20-30 (sccm) Flow rate of O2 5-15 7-13 9-11 (sccm) Flow rate of N2 15-45 20-40 25-35 (sccm) Power at 27 MHz 300-1200 450-750 550-650 (Watts) Power at 2 MHz 50-200 75-125 90-110 (Watts) - In the preferred embodiment for etching the trench stop layer420: the flow rate of pressure was approximately 90 mTorr; approximately 600 Watts was provided at 27 MHz; approximately 100 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 150 sccm; the flow rate of oxygen (O2) was approximately 10 sccm; the flow rate of CF4 was approximately 25 sccm; the flow rate of CHF3 was approximately 12 sccm; the flow rate of N2 was approximately 30 sccm.
- Next the trench level low
k material layer 424 is etched (step 516). One recipe set of parameters for etching the trench level lowk material layer 424 is provided in Table IV.TABLE IV MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 0-300 100-200 140-160 (mTorr) Flow rate of NH3 500-1500 750-1250 900-1100 (sccm) Power at 27 MHz 250-750 300-700 450-550 (Watts) Power at 2 MHz 0-500 0-250 0 (Watts) - In the preferred embodiment for etching the via level low k material layer416: the flow rate of pressure was approximately 150 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 0 Watts was provided at 2 MHz; the flow rate of NH3 was approximately 1,000 sccm;.
- While etching via440 in the OSG low k materials to the
barrier layer 412 the via etching may be stopped. A silicon containing polymer crust 444 may be deposited over the patterned resistlayer 432 and the sidewalls of the via 440 as a result of the via etching. Theplasma chamber 200 may be used to strip the polymer crust 444, when etching OSG low k materials, and the patterned resistlayer 432, when etching either OSG low k materials or organic low k materials (step 316). A recipe for stripping the polymer crust 444 and patterned resistlayer 432 may use NH3 as a plasma source gas for stripping the photoresist. Once the polymer crust 444 and patterned resistlayer 432 have been stripped, thewafer 224 may be removed from theplasma chamber 200 to allow the depositing of a new patterned resist layer 504 (step 320), as shown in FIG. 6A. - The
wafer 224 may be placed back in the plasma chamber 200 (step 324). Atrench 604 is etched (step 328), as shown in FIG. 6B. FIG. 7 is a more detailed flow chart for the step of etching the trench (step 328) when thetrench level layer 424 is an organic low k material. First, the trench is etched through the hard mask/ARC layer 428 (step 704). One recipe set of parameters for etching the hard mask/ARC layer 428 is provided in Table I above. In a preferred embodiment for etching the hard mask/ARC layer 428: the flow rate of pressure was approximately 70 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 1,000 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 160 sccm; the flow rate of oxygen (O2) was approximately 15 sccm; the flow rate of CF4 was approximately 40 sccm; the flow rate of C4F8 was approximately 5 sccm. - Next the trench level organic low
k material layer 424 is etched (step 708). One recipe set of parameters for etching the trench level organic lowk material layer 424 is provided in Table II. In the preferred embodiment for etching the trench level low k material layer 424: the flow rate of pressure was approximately 150 mTorr; approximately 500 Watts was provided at 27 MHz; approximately 0 Watts was provided at 2 MHz; the flow rate of NH3 was approximately 1,000 sccm. - Once the
trench 604 has been etched to thetrench stop layer 420 the trench etching may be stopped. Thebarrier layer 412 may then be etched (step 332). One recipe set of parameters for etching thebarrier layer 412 is provided in Table V.TABLE V MORE PREFERRED PREFERRED PARAMETERS BROAD RANGE RANGE RANGE PRESSURE 100-220 130-190 150-170 (mTorr) Flow rate of Ar 100-500 200-400 250-350 (sccm) Flow rate of CHF3 5-40 10-30 15-25 (sccm) Flow rate of N2 40-200 60-140 80-120 (sccm) Power at 27 MHz 300-800 500-600 400 (Watts) Power at 2 MHz 50-400 100-300 200 (Watts) - In the preferred embodiment for etching the barrier layer412: the flow rate of pressure was approximately 158 mTorr; approximately 400 Watts was provided at 27 MHz; approximately 200 Watts was provided at 2 MHz; the flow rate of Argon (Ar) was approximately 300 sccm; the flow rate of CHF3 was approximately 20 sccm; the flow rate of N2 was approximately 100 sccm.
- A silicon containing
polymer crust 608 may be deposited over the patterned resistlayer 432 and the sidewalls of the via 440 andtrench 604 as a result of the trench etching, as shown in FIG. 6B. Theplasma chamber 200 may be used to strip thepolymer crust 608 and patterned resist layer 504 (step 336). A recipe for stripping thepolymer crust 608 and patterned resistlayer 504 may use NH3 as a plasma source gas for stripping the photoresist. Once thepolymer crust 608 and patterned resistlayer 504 have been stripped, thewafer 224, as shown in FIG. 6C, may be removed from the plasma chamber 200 (step 340). - In an Exelan HP, made by LAM Research Corporation™ of Fremont, Calif., a test was performed using the above recipes for 500 wafers. An O2 clean was done every 60 seconds. Particles were collected periodically in 25 or 50 wafer intervals. A particle count was taken using an NH3 recipe as described above for 10 seconds, where the particle size monitored was 0.16 to 9,000 microns with 6 mm edge exclusion. The test temperature was about 0° C. FIG. 8 is a graph of the number of particles over 0.16 microns (Particle count) versus the number of wafers processed (0-500) found during the test. It can be seen that the level of particle generation is below 30, which is normal for the chamber, indicating that the confinement rings 202,
small plasma volume 240, andexhaust pump 220 speed help to minimize plasma contact with the walls of the chamber so that formed ammonium fluoride does not have a chance to condense onto the walls of the chamber to form a higher number of particles. - In another embodiment of the invention, where the trench level low
k material layer 424 and the via levellow k material 416 are made of an OSG material the trench levellow k material 424, the via levellow k material 416, theARC layer 428,barrier layer 412, and thetrench stop layer 420 may be all etched with fluorine containing etchant gases. For stripping the patterned resistlayer 432 an NH3 stripping gas may be used. More preferably an NH3 gas combined with a CF4 gas may be used to strip the patterned resist layer. In such an embodiment an ammonia containing gas and a fluorine containing gas are used at the same time within the same plasma chamber and at alternating times. - In other embodiments other types of plasma confinement devices, which keep plasma from the chamber walls may be used in place of the confinement rings. Other types of plasma generation and energizing systems may be used in place of the upper and
lower electrodes second RF sources - Another embodiment of the invention may use a combined resist strip and barrier etch step to reduced etching damage as described in U.S. patent application Ser. No. ______ (Attorney Docket Number LAM1P158) entitled “A Combined Resist Strip And Barrier Etch Process For Dual Damascene Structures” by Rao Annapragada and Reza Sadjadi, with the same filing date, and which is incorporated by reference.
- Sidewalls formed by the crust may be removed during the stripping of the resist or may be removed using a separate wet stripping as described in U.S. patent application Ser. No. ______ (Attorney Docket Number LAM1P156) entitled “Method of Preventing Damage To Organo-Silicate-Glass Materials During Resist Stripping” by Rao Anapragada, with the same filing date, and which is incorporated by reference.
- While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, and substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and substitute equivalents as fall within the true spirit and scope of the present invention.
Claims (20)
1-15. (Canceled)
16. A method of etching a stack, comprising:
placing the stack in a plasma processing chamber;
flowing a fluorine containing gas into the plasma processing chamber;
flowing an ammonia containing gas into the plasma processing chamber;
generating a plasma; and
etching the stack.
17. The method, as recited in claim 15, further comprising confining the plasma to reduce plasma contact with chamber walls.
18. The method, as recited in claim 15, wherein the stack comprises a low dielectric constant layer and an etch stop layer over a substrate.
19. The method, as recited in claim 16 , wherein the fluorine containing gas and the ammonia containing gas are provided in an alternating manner and wherein a plasma is generated from the fluorine containing gas and a plasma is generated from the ammonia containing gas.
20. The method, as recited in claim 16 , wherein the confining the plasma comprises providing a plurality of spaced apart plasma rings.
21. The method, as recited in claim 20 , further comprising providing a pressure below 300 mTorr during the etching.
22. The method, as recited in claim 15, wherein the stack comprises a low dielectric constant material layer and an etch stop layer, wherein the low dielectric constant layer is etched by plasma generated from the ammonia containing gas and the etch stop layer is etched plasma generated from the fluorine containing gas.
23. The method, as recited in claim 15, further comprising stripping a photoresist mask within the plasma processing chamber wherein the stripping uses a plasma generated from an ammonia containing stripping gas.
24. A method of etching a stack with at least one organic low dielectric constant layer, comprising:
placing the stack in a plasma processing chamber comprising a plasma chamber wall, a gas source, a plasma generation and energizing device, confinement rings and an exhaust system;
flowing an ammonia containing gas into the plasma processing chamber;
generating a plasma from the ammonia containing gas;
performing a first etch from the ammonia containing gas;
flowing a fluorine containing gas into the plasma processing chamber;
generating a plasma from the fluorine containing gas; and
performing a second etch from the fluorine containing gas.
25. The method, as recited in claim 24 , wherein the first etch etches the at least one organic low dielectric constant layer.
26. The method, as recited in claim 25 , wherein the stack further comprises an etch stop layer, wherein the second etch etches the etch stop layer.
27. The method, as recited in claim 26 , further comprising:
flowing an ammonia containing stripping gas into the plasma processing chamber;
generating a plasma from the ammonia containing gas; and
stripping a photoresist mask over the stack.
28. The method, as recited in claim 27 , wherein the ammonia containing stripping gas contains a fluorine containing gas.
29. The method, as recited in claim 28 , further comprising confining the plasma to reduce plasma contact with chamber walls wherein the confinement rings are used to confine the plasma.
30. The method, as recited in claim 24 , further comprising:
flowing an ammonia containing stripping gas into the plasma processing chamber;
generating a plasma from the ammonia containing gas; and
stripping a photoresist mask over the stack.
31. The method, as recited in claim 30 , wherein the ammonia containing stripping gas contains a fluorine containing gas.
32. The method, as recited in claim 24 , further comprising confining the plasma to reduce plasma contact with chamber walls wherein the confinement rings are used to confine the plasma.
33. A method of etching a stack with at least one organic low dielectric constant layer, comprising:
placing the stack in a plasma processing chamber comprising a plasma chamber wall, a gas source, a plasma generation and energizing device, a plurality of spaced apart confinement rings, and an exhaust system;
flowing a fluorine containing gas into the plasma processing chamber;
flowing an ammonia containing gas into the plasma processing chamber;
generating a plasma;
confining the plasma with the confinement rings;
maintaining the pressure below 300 mTorr; and
etching the stack with the generated plasma.
34. The method, as recited in claim 33 , wherein a the organic low dielectric constant material is below a photoresist mask, further comprising stripping the photoresist mask, wherein the stripping comprises
Priority Applications (1)
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US10/847,695 US20040211517A1 (en) | 2000-12-22 | 2004-05-17 | Method of etching with NH3 and fluorine chemistries |
Applications Claiming Priority (2)
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US09/746,900 US20020121500A1 (en) | 2000-12-22 | 2000-12-22 | Method of etching with NH3 and fluorine chemistries |
US10/847,695 US20040211517A1 (en) | 2000-12-22 | 2004-05-17 | Method of etching with NH3 and fluorine chemistries |
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US09/746,900 Division US20020121500A1 (en) | 2000-12-22 | 2000-12-22 | Method of etching with NH3 and fluorine chemistries |
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