US20040196171A1 - Switched-capacitor frequency-to-current converter - Google Patents
Switched-capacitor frequency-to-current converter Download PDFInfo
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- US20040196171A1 US20040196171A1 US10/405,191 US40519103A US2004196171A1 US 20040196171 A1 US20040196171 A1 US 20040196171A1 US 40519103 A US40519103 A US 40519103A US 2004196171 A1 US2004196171 A1 US 2004196171A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
- H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
- H03K9/06—Demodulating pulses which have been modulated with a continuously-variable signal of frequency- or rate-modulated pulses
Definitions
- the invention relates to the field of electronics, and more specifically to circuits for frequency to current conversion.
- Frequency-to-voltage and frequency-to-current converters are employed in numerous types of applications.
- One such application is the field of analog-to-digital conversion, in which power consumption by analog-digital processors is a persistent and increasingly complicated issue.
- Applications such as Analog-to-Digital converters (ADCs), require features such as an adaptive bias current, which enable analog-to-digital conversion while saving power consumption.
- Tools such as a frequency-to-current converter may be employed in such applications to supply an adaptive bias current.
- Frequency-to-current converters are often implemented by coupling a frequency-to-voltage converter to a voltage-to-current converter.
- Many conventional frequency-to-voltage and voltage-to-current converters are well known in the art. This combination of circuits, however, is often inadequate for the purposes outlined above; in particular, such combinations are complicated to be embedded in a single integrated circuit, and demand too much power for host applications, such as an ADC converter.
- the invention comprises a frequency-to-current converter operative to convert a clock frequency to an output current, such that the output current increases linearly with the clock frequency.
- the frequency-to-current converter is designed to minimize power consumption in hardware applications. Examples of hardware applications which may incorporate the converter of the present invention include digital-to-analog converters (DAC) or analog-to-digital converters (ADC). These applications may be driven by clocks with variable frequencies.
- DAC digital-to-analog converters
- ADC analog-to-digital converters
- the frequency-to-current converter employs an integrator circuit, which is used to compare an input reference voltage and a current feedback into a sampling capacitor.
- the feedback current is just sufficient to discharge the sampling capacitor to a fixed voltage.
- the current only depends on the clock frequency, the sampling capacitor value and the reference voltage. The current is linearly proportional to each of the factors listed above.
- the clock frequency driving the circuit is variable.
- the clock frequency may vary from 7.5 MHz to 22 MHz.
- the variable clock frequency is accommodated by biasing the amplifiers in the frequency-to-current converter with currents proportional to the clock frequency, thereby ensuring that the unity-gain bandwidth of the amplifiers is adaptively adjusted to track the clock frequency, and saving power concurrently.
- Circuits employed by embodiments of the invention are simple in design, particularly by comparison to standard frequency-to-current converters.
- the core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches.
- the elegant design facilitates lower cost, complexity, and power consumption in the host application, and allows the frequency-to-current converter to be resident with the host application on a single integrated circuit.
- FIG. 1 schematically illustrates a circuit diagram for a frequency-to-current converter according to embodiments of the invention.
- FIG. 2 illustrates a plurality of clock phases employed by the frequency-to-current converter according to embodiments of the invention.
- FIG. 3 illustrates a linear relationship between an input clock frequency of a frequency-to-current converter, and an output current of the frequency-to-current converter according to embodiments of the invention.
- FIG. 4 schematically illustrates a clock detection circuit used by the frequency-to-current converter in embodiments of the invention.
- the invention comprises a frequency-to-current converter operative to convert a clock frequency to an output current, such that the output current increases linearly with the clock frequency.
- the frequency-to-current converter uses an integrator to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just enough to discharge the sampling capacitor to a fixed voltage. Thus, the current only depends on the clock frequency, the sampling capacitor value and the reference voltage.
- This circuit employed is simple in design, particularly by comparison to standard frequency-to-current converters.
- the core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches.
- An output current of the frequency-to-current converter linearly increases with the clock frequency. The simplicity of the design facilitates lower cost, complexity, and power consumption in the host application.
- the frequency-to-current converter is designed for use in applications such as an analog-to-digital converter, which are intended to operate at low power.
- the frequency-to-current converter may be used to reduce power consumption in an analog-to-digital converter with a varying clock frequency.
- An illustrative, non-limiting example of such an analog-to-digital converter is the Max 1195TM ADC, produced by Maxim Integrated Products, Inc. of Sunnyvale, Calif. This ADC comprises a dual, 8-bit, ADC optimized for low power, operating at a 2.7 v to 3.6 v power supply, and which consumes 87 mW, and has a sampling rate of 40 Msps.
- the frequency-to-current converter ensures that the current in critical analog blocks in the analog-to-digital converter varies proportionally to a sample clock frequency.
- FIG. 1 schematically illustrates an example of a circuit 100 used to implement the frequency-to-current converter according to embodiments of the invention.
- the circuit 100 includes a first opamp op 1 102 , which receives a first reference voltage VREF 1 104 at a positive input.
- the circuit further includes a sampling capacitor C s 128 , and a feedback capacitor C f 130 .
- the feedback capacitor C f 130 is operatively coupled to the negative input of a second opamp OP 2 125 .
- a second reference voltage V ref2 132 is operatively coupled to the positive input of the second op amp OP 2 125 .
- the circuit 100 further includes multiple switches, SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , SW 8 , SW 9 , SW 10 , SW 11 , which are operated by clock pulses from a clock generator 116 coupled to a master clock 118 ; these clock pulses include phi 1 120 , phi 2 122 , phi 3 124 , NCK, and NCK bar, which are further described herein.
- the circuit also includes several MOSFET transistors M 1 134 , M 2 138 , M 3 140 .
- the opamp op 1 102 is used as a buffer for a first reference voltage, VREF 1 104 .
- a resistor R 1 106 and a capacitor C 1 108 are specifically used to relax the driving capability of the opamp op 1 102 .
- a clock detector 110 is used to turn off the frequency-to-current converter when a clock 114 stops. This ensures that the circuit 100 will not be biased at high current. When the clock detector 110 detects that the clock has stopped, the signal NCK 112 drops to a low state, and all switches in the circuit 100 which are controlled by NCK SW 10 SW 9 are subsequently opened.
- a clock generator 116 is also illustrated in FIG. 1.
- the clock generator 116 receives input from a master clock MASTER CLK 118 , and produces three timing waveforms, phi 1 120 , phi 2 122 , and phi 3 124 .
- FIG. 2 illustrates the clock timing of phi 1 202 , phi 2 204 , and phi 3 206 , relative to that of the master clock 200 .
- phi 2 204 has a pulse width which is twice that of ph 1 202 and phi 3 206 .
- the clock pulse phi 3 206 has a period T 208 equal to four periods of the master clock MASTER CLK 200 .
- a second opamp op 2 125 , a sampling capacitor C s 128 , and a feedback capacitor C f 130 comprise an integrator.
- the sampling capacitor C s 128 is coupled via a switch SW 7 to the negative input of the second op amp OP 2 125 .
- the positive input of the second op amp 125 receives a second reference voltage VREF 2 132 .
- the feedback capacitor C f 130 forms a feedback to the second op amp OP 2 125 .
- the sampling capacitor Cs 128 is shorted.
- the top plate of the sampling capacitor C s 128 is connected to the first reference voltage VREF 1 104 , and the bottom plate of the sampling capacitor C s 128 is discharged by a drain current of a transistor M 1 130 .
- the voltage across the sampling capacitor C s 128 is reduced to a voltage V x .
- the sampling capacitor C s 128 is connected to the negative input of the opamp op 2 125 .
- the opamp Op 2 125 compares the voltage V 5 with the reference voltage VREF 2 132 and adjusts the output Vout accordingly. At steady state, the voltage V x is identical to the reference voltage VREF 2 132 .
- f master is the master clock frequency 200 , as shown in FIG. 2.
- the current I varies linearly with the frequency of the master clock, f master 200 .
- the output voltage Vout 136 is low-pass filtered by a passive filter 150 .
- the current of M 1 134 is mirrored to M 2 138 .
- the transistors M 2 138 and M 3 140 form a high impedance current source, which can be used, in embodiments of the invention, to bias other circuitry in the respective application. Since the current is proportional to the clock frequency 200 , the bandwidth (or the g m /C) of the circuit 100 is proportional to the square root of the clock frequency 200 . This implies that the circuit 100 saves power when the clock frequency 200 is low, and speeds up as the clock frequency 200 increases.
- Z ⁇ 1 corresponds to a delay of period T 208 ; in the illustrative example shown in FIG. 2, the period T comprises four periods of the master clock 200 .
- the factor g m1 represents the transconductance of M 1 134 , as shown in FIG. 1. Since the factor g m1 is proportional to the square root of the current, g m1 ⁇ ⁇ ⁇ I ⁇ ⁇ and ⁇ ⁇ I ⁇ ⁇ ⁇ ⁇ f , B ⁇ ⁇ ⁇ ⁇ 1 f .
- FIG. 3 illustrates the output current 302 as a function of the master clock frequency 200 .
- the non-linearity is within a threshold of 0.5% with a 3 ⁇ frequency variation.
- FIG. 4 A schematic diagram illustrating the clock detection circuit 450 is shown in FIG. 4.
- the clock detection circuit 450 includes a plurality of Schmidt triggers 440 442 , which comprise the input to a NOR gate.
- Capacitors C 1 400 and C 2 402 are charged and discharged periodically by the clock signal phi 2 404 . As the clock frequency decreases, the peak voltages on node A 406 and node B 408 increase.
- the peak voltage on either node A 406 or node B 408 is high enough to trigger one of a plurality of Schmidt triggers 440 442 , and the output signal NCK 410 decreases accordingly.
- NCK 410 When NCK 410 is sufficiently low, the opamp op 2 125 of the frequency-to-current converter 100 is tied in a voltage follower configuration, the switch SWI 1 160 is opened, and the output current goes to zero.
- the clock frequency 200 may be variable.
- ADC Analog-to-Digital converter
- the frequency-to-current converter described herein is particularly well suited to low power applications, of which analog-to-digital converters are one -non-limiting example.
- the embodiments described herein are for illustrative purposes only; many equivalents and variants will be apparent to those skilled in the art.
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Abstract
Description
- The invention relates to the field of electronics, and more specifically to circuits for frequency to current conversion.
- Frequency-to-voltage and frequency-to-current converters are employed in numerous types of applications. One such application is the field of analog-to-digital conversion, in which power consumption by analog-digital processors is a persistent and increasingly complicated issue. Applications such as Analog-to-Digital converters (ADCs), require features such as an adaptive bias current, which enable analog-to-digital conversion while saving power consumption. Tools such as a frequency-to-current converter may be employed in such applications to supply an adaptive bias current.
- Standard implementations of frequency-to-current converters, however, are inadequate to such tasks. Frequency-to-current converters are often implemented by coupling a frequency-to-voltage converter to a voltage-to-current converter. Many conventional frequency-to-voltage and voltage-to-current converters are well known in the art. This combination of circuits, however, is often inadequate for the purposes outlined above; in particular, such combinations are complicated to be embedded in a single integrated circuit, and demand too much power for host applications, such as an ADC converter.
- As such, there is a need for a frequency-to-current converter which is simple in implementation, and which ensures that a linear relationship is maintained between output current and input clock frequency, for suitability in host applications.
- The invention comprises a frequency-to-current converter operative to convert a clock frequency to an output current, such that the output current increases linearly with the clock frequency. The frequency-to-current converter is designed to minimize power consumption in hardware applications. Examples of hardware applications which may incorporate the converter of the present invention include digital-to-analog converters (DAC) or analog-to-digital converters (ADC). These applications may be driven by clocks with variable frequencies.
- In embodiments of the invention, the frequency-to-current converter employs an integrator circuit, which is used to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just sufficient to discharge the sampling capacitor to a fixed voltage. Thus, the current only depends on the clock frequency, the sampling capacitor value and the reference voltage. The current is linearly proportional to each of the factors listed above.
- In many applications employing the frequency-to-current converter—such as, by way of non-limiting example, the analog-to-digital converter—the clock frequency driving the circuit is variable. In one version of the analog-to-digital converter, the clock frequency may vary from 7.5 MHz to 22 MHz. In embodiments of the invention, the variable clock frequency is accommodated by biasing the amplifiers in the frequency-to-current converter with currents proportional to the clock frequency, thereby ensuring that the unity-gain bandwidth of the amplifiers is adaptively adjusted to track the clock frequency, and saving power concurrently.
- Circuits employed by embodiments of the invention are simple in design, particularly by comparison to standard frequency-to-current converters. In embodiments of the invention, the core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches. The elegant design facilitates lower cost, complexity, and power consumption in the host application, and allows the frequency-to-current converter to be resident with the host application on a single integrated circuit. These and other embodiments are described in further detail infra.
- FIG. 1 schematically illustrates a circuit diagram for a frequency-to-current converter according to embodiments of the invention.
- FIG. 2 illustrates a plurality of clock phases employed by the frequency-to-current converter according to embodiments of the invention.
- FIG. 3 illustrates a linear relationship between an input clock frequency of a frequency-to-current converter, and an output current of the frequency-to-current converter according to embodiments of the invention.
- FIG. 4 schematically illustrates a clock detection circuit used by the frequency-to-current converter in embodiments of the invention.
- The invention comprises a frequency-to-current converter operative to convert a clock frequency to an output current, such that the output current increases linearly with the clock frequency. In embodiments of the invention, the frequency-to-current converter uses an integrator to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just enough to discharge the sampling capacitor to a fixed voltage. Thus, the current only depends on the clock frequency, the sampling capacitor value and the reference voltage.
- This circuit employed is simple in design, particularly by comparison to standard frequency-to-current converters. In embodiments of the invention, the core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches. An output current of the frequency-to-current converter linearly increases with the clock frequency. The simplicity of the design facilitates lower cost, complexity, and power consumption in the host application.
- The frequency-to-current converter is designed for use in applications such as an analog-to-digital converter, which are intended to operate at low power. As a non-limiting example, the frequency-to-current converter may be used to reduce power consumption in an analog-to-digital converter with a varying clock frequency. An illustrative, non-limiting example of such an analog-to-digital converter is the Max 1195™ ADC, produced by Maxim Integrated Products, Inc. of Sunnyvale, Calif. This ADC comprises a dual, 8-bit, ADC optimized for low power, operating at a 2.7 v to 3.6 v power supply, and which consumes 87 mW, and has a sampling rate of 40 Msps. By providing an adaptive bias current, the frequency-to-current converter ensures that the current in critical analog blocks in the analog-to-digital converter varies proportionally to a sample clock frequency.
- FIG. 1 schematically illustrates an example of a
circuit 100 used to implement the frequency-to-current converter according to embodiments of the invention. Thecircuit 100 includes afirst opamp op1 102, which receives a firstreference voltage VREF1 104 at a positive input. The circuit further includes asampling capacitor C s 128, and afeedback capacitor C f 130. Thefeedback capacitor C f 130 is operatively coupled to the negative input of asecond opamp OP2 125. A secondreference voltage V ref2 132 is operatively coupled to the positive input of the secondop amp OP2 125. Thecircuit 100 further includes multiple switches, SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, which are operated by clock pulses from aclock generator 116 coupled to amaster clock 118; these clock pulses includephi1 120,phi2 122,phi3 124, NCK, and NCK bar, which are further described herein. The circuit also includes several MOSFET transistors M1 134, M2 138, M3 140. - In embodiments of the invention, the
opamp op1 102 is used as a buffer for a first reference voltage,VREF1 104. Aresistor R 1 106 and acapacitor C 1 108 are specifically used to relax the driving capability of theopamp op1 102. Aclock detector 110 is used to turn off the frequency-to-current converter when a clock 114 stops. This ensures that thecircuit 100 will not be biased at high current. When theclock detector 110 detects that the clock has stopped, thesignal NCK 112 drops to a low state, and all switches in thecircuit 100 which are controlled by NCK SW 10 SW9 are subsequently opened. - A
clock generator 116 is also illustrated in FIG. 1. Theclock generator 116 receives input from a masterclock MASTER CLK 118, and produces three timing waveforms,phi1 120,phi2 122, andphi3 124. FIG. 2 illustrates the clock timing ofphi1 202, phi2 204, andphi3 206, relative to that of themaster clock 200. Note that in the embodiments shown in FIG. 2, phi2 204 has a pulse width which is twice that ofph1 202 andphi3 206. Theclock pulse phi3 206 has aperiod T 208 equal to four periods of the masterclock MASTER CLK 200. These clock pulses operate various switches in the integrator circuit, as elaborated further herein. - With reference to FIG. 1, a
second opamp op2 125, asampling capacitor C s 128, and afeedback capacitor C f 130 comprise an integrator. Thesampling capacitor C s 128 is coupled via a switch SW7 to the negative input of the secondop amp OP2 125. The positive input of thesecond op amp 125 receives a secondreference voltage VREF2 132. Thefeedback capacitor C f 130 forms a feedback to the secondop amp OP2 125. - During the
clock pulse phi1 120, thesampling capacitor Cs 128 is shorted. During theclock pulse phi2 122, the top plate of thesampling capacitor C s 128 is connected to the firstreference voltage VREF1 104, and the bottom plate of thesampling capacitor C s 128 is discharged by a drain current of atransistor M1 130. At the end of thepulse phi2 122, the voltage across thesampling capacitor C s 128 is reduced to a voltage Vx. During the clock pulse phi3, thesampling capacitor C s 128 is connected to the negative input of the opamp op2 125. Theopamp Op2 125 compares the voltage V5 with thereference voltage VREF2 132 and adjusts the output Vout accordingly. At steady state, the voltage Vx is identical to thereference voltage VREF2 132. The drain current ofM1 134 is given by therelation Equation 1 below: -
- and fmaster is the
master clock frequency 200, as shown in FIG. 2. - Thus, per the relation given by
Equation 1, the current I varies linearly with the frequency of the master clock,f master 200. Theoutput voltage Vout 136 is low-pass filtered by apassive filter 150. The current ofM1 134 is mirrored toM2 138. Thetransistors M2 138 andM3 140 form a high impedance current source, which can be used, in embodiments of the invention, to bias other circuitry in the respective application. Since the current is proportional to theclock frequency 200, the bandwidth (or the gm/C) of thecircuit 100 is proportional to the square root of theclock frequency 200. This implies that thecircuit 100 saves power when theclock frequency 200 is low, and speeds up as theclock frequency 200 increases. -
-
- When the
frequency 200 increases, the pole will asymptotically rise to Z=1 but will never reach Z=1. When thefrequency 200 decreases and B≧2, the pole will go outside the unity circle. This indicates the existence of a minimum clock frequency, below which the circuit will be unstable. - Simulations demonstrate that the frequency-to-current converter has a substantially linear relationship between the
master clock frequency 200 and the output current. FIG. 3 illustrates the output current 302 as a function of themaster clock frequency 200. In such embodiments, the non-linearity is within a threshold of 0.5% with a 3× frequency variation. - To prevent the circuit from generating a large output current when the clock stops, embodiments of the invention also employ a
clock detection circuit 450. A schematic diagram illustrating theclock detection circuit 450 is shown in FIG. 4. Theclock detection circuit 450 includes a plurality of Schmidt triggers 440 442, which comprise the input to a NOR gate.Capacitors C1 400 andC2 402 are charged and discharged periodically by theclock signal phi2 404. As the clock frequency decreases, the peak voltages onnode A 406 andnode B 408 increase. - In embodiments of the invention, when the frequency is below a threshold frequency, the peak voltage on either
node A 406 ornode B 408 is high enough to trigger one of a plurality of Schmidt triggers 440 442, and theoutput signal NCK 410 decreases accordingly. The Schmidt triggers 440 442 bistable device used to square-up waveforms with slow rise and fall times; the operation characteristics of the Schmidt triggers 440 442 shall be apparent to those skilled in the art. - When
NCK 410 is sufficiently low, the opamp op2 125 of the frequency-to-current converter 100 is tied in a voltage follower configuration, theswitch SWI1 160 is opened, and the output current goes to zero. - In many of the applications which may employ the frequency-to-current converter—such as, by way of non-limiting example, an Analog-to-Digital converter (ADC)—the
clock frequency 200 may be variable. In such embodiments, by biasing the amplifiers with currents proportional to theclock frequency 200, the unity-gain bandwidth of the amplifiers is adaptively adjusted to track theclock frequency 200 and to save power concurrently. - The frequency-to-current converter described herein is particularly well suited to low power applications, of which analog-to-digital converters are one -non-limiting example. The embodiments described herein are for illustrative purposes only; many equivalents and variants will be apparent to those skilled in the art.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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EP1679575A2 (en) * | 2005-01-11 | 2006-07-12 | Fujitsu Limited | Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus |
US20070172013A1 (en) * | 2006-01-24 | 2007-07-26 | Cadence Design Systems, Inc. | Frequency-to-current converter |
US20220116196A1 (en) * | 2020-10-12 | 2022-04-14 | Invensense, Inc. | Adaptive control of bias settings in a digital microphone |
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US7479812B1 (en) | 2005-05-27 | 2009-01-20 | National Semiconductor Corporation | Producing a frequency-representative signal with rapid adjustment to frequency changes |
US7627053B2 (en) * | 2005-06-29 | 2009-12-01 | Texas Instruments Incorporated | Apparatus and method for driving a pulse width modulation reference signal |
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US8742685B1 (en) | 2010-04-05 | 2014-06-03 | Maxim Integrated Products, Inc. | Magnetic amplifier assisted LED constant current sink overhead voltage regulation |
CN102170290B (en) * | 2011-03-11 | 2014-05-14 | 中国航天科技集团公司第九研究院第七七一研究所 | Current mode analogue-to-digital converter capable of improving conversion accuracy |
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US5457458A (en) * | 1993-12-21 | 1995-10-10 | Honeywell Inc. | High resolution analog current-to-frequency converter |
-
2003
- 2003-04-01 US US10/405,191 patent/US6798372B1/en not_active Expired - Lifetime
Patent Citations (1)
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US5457458A (en) * | 1993-12-21 | 1995-10-10 | Honeywell Inc. | High resolution analog current-to-frequency converter |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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EP1679575A2 (en) * | 2005-01-11 | 2006-07-12 | Fujitsu Limited | Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus |
EP1679575A3 (en) * | 2005-01-11 | 2008-10-01 | Fujitsu Limited | Signal detection device, frequency detection device, power consumption control device, corresponding methods and electronic apparatus using the same |
US20070172013A1 (en) * | 2006-01-24 | 2007-07-26 | Cadence Design Systems, Inc. | Frequency-to-current converter |
US7627072B2 (en) * | 2006-01-24 | 2009-12-01 | Cadence Design Systems, Inc. | Frequency-to-current converter |
US20220116196A1 (en) * | 2020-10-12 | 2022-04-14 | Invensense, Inc. | Adaptive control of bias settings in a digital microphone |
US11811904B2 (en) * | 2020-10-12 | 2023-11-07 | Invensense, Inc. | Adaptive control of bias settings in a digital microphone |
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