US20040153583A1 - Serial communication device with dynamic allocation of acceptance masks using serial implementation - Google Patents
Serial communication device with dynamic allocation of acceptance masks using serial implementation Download PDFInfo
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- US20040153583A1 US20040153583A1 US09/957,062 US95706201A US2004153583A1 US 20040153583 A1 US20040153583 A1 US 20040153583A1 US 95706201 A US95706201 A US 95706201A US 2004153583 A1 US2004153583 A1 US 2004153583A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
- H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Definitions
- the present invention relates to a serial communication device, in particular a Controller Area Network (CAN) device. Furthermore, the present invention relates to a microcontroller with a serial communication device and a method of operating a serial communication device.
- CAN Controller Area Network
- Controller Area Network is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. Applications of CAN range from high speed digital communications networks to low cost multiplex wiring.
- CAN is a high-integrity serial data communications bus for real-time applications. CAN operates at data rates of up to 1 Megabits per second, has excellent error detection and confinement capabilities, and was originally developed for use in automobiles. The interface between the CAN bus and the CPU is usually called the CAN controller.
- the motivation behind CAN was to make automobiles more reliable, safe and fuel-efficient by improving the interoperability of automotive electronics, engine control units, sensors, anti-skid brake systems, etc., while decreasing wiring harness weight and complexity.
- CAN Since CAN's inception, the CAN protocol has gained widespread popularity in industrial automation and automotive/truck applications. The robustness of the CAN bus in noisy environments and the ability to detect and recover from fault conditions makes CAN suitable for use with, industrial control equipment, medical equipment, test equipment, mobile and portable machines, appliances, etc.
- CAN is an asynchronous serial bus system with one logical bus line. It has an open, linear bus structure with equal bus nodes.
- a CAN bus consists of two or more nodes. The number of nodes on the bus may be changed dynamically without disturbing the communication of the other nodes.
- the CAN logic bus corresponds to a “wired-AND” mechanism, “recessive” bits (mostly, but not necessarily equivalent to the logic level “1“) are overwritten by “dominant” bits (mostly logic level “0”). As long as no bus node is sending a dominant bit, the bus line is in the recessive state, but a dominant bit from any bus node generates the dominant bus state. Therefore, for the CAN bus line, a medium is chosen that is able to transmit the two possible bit states (dominant and recessive). A common physical medium used is a twisted wire pair.
- the bus lines are then called “CANH” and “CANL,” and may be connected directly to the CAN controller nodes or via a connector thereto.
- CAN bus protocol In the CAN bus protocol it is not bus nodes that are addressed, but rather the address information is contained in the messages that are transmitted. This is done via an identifier (part of each message) which identifies the message content, e.g., engine speed, oil temperature, etc.
- the identifier additionally indicates the priority of the message. The lower the binary value of the identifier, the higher the priority of the message (more dominant bits).
- the original CAN specifications (Versions 1.0, 1.2 and 2.0A) defined the message identifier as having a length of 11 bits, giving a possible 2048 message identifiers.
- An “extended CAN” specification Version 2.0B allows message identifier lengths of 11 and/or 29 bits to be used (an identifier length of 29 bits allows over 536 Million message identifiers).
- the CAN specifications (all versions) are incorporated by reference herein for all purposes.
- the BasicCAN controller architecture is similar to simple UART, except that complete frames are sent instead of characters.
- a microcontroller puts a frame in the transmit buffer, and receives an interrupt when the frame is sent.
- the microcontroller receives an interrupt to empty the receive buffer and empties the frame from the receive buffer before a subsequent frame is received.
- the microcontroller In the BasicCAN controller architecture the microcontroller must manage the transmission and reception, and handle the storage of the frames.
- the FullCAN controller architecture stores frames in the controller itself. A limited number of frames may be dealt with. Each frame buffer is tagged with the identifier of the frame mapped to the buffer. The microcontroller can update a frame in the buffer and mark it for transmission. Receive buffers can be examined to see if a frame with a matching identifier has been received. In addition, filters may be used to pre-screen a received frame so that only those frames intended for use by the particular CAN controller is stored in a receive buffer.
- the CAN protocol usually comes in two versions: CAN 1.0 and CAN 2.0.
- CAN 2.0 is backwardly compatible with CAN 1.0, and most new controllers are built according to CAN 2.0.
- part A and part B There are two parts to the CAN 2.0 standard: part A and part B.
- CAN 1.0 and CAN 2.0A identifiers must be 11-bits long.
- CAN 2.0B identifiers can be 11-bits (a “standard” identifier) or 29-bits (an “extended” identifier).
- CAN 2.0B active controllers will send and accept both standard and extended frames.
- CAN 2.0B passive controllers will send and receive standard frames, and will discard extended frames without error.
- a BasicCAN controller the architecture is similar to a simple UART, except that complete frames are sent instead of characters: there is (typically) a single transmit buffer, and a double-buffered receive buffer.
- the CPU puts a frame in the transmit buffer, and takes an interrupt when the frame is sent; the CPU receives a frame in the receive buffer, takes an interrupt and empties the buffer (before a subsequent frame is received).
- the CPU must manage the transmission and reception, and handle the storage of the frames.”
- a FullCAN controller the frames are stored in the controller.
- a limited number of frames can be dealt with (typically 16); because there can be many more frames on the network, each buffer is tagged with the identifier of the frame mapped to the buffer.
- the CPU can update a frame in the buffer and mark it for transmission; buffers can be examined to see if a frame with a matching identifier has been received.”
- the intention with the FulICAN design is to provide a set of “shared variables” in the network; the CPU periodically updates the variables (i.e., the contents of frames in the buffer); the CPU also can examine the variables.
- variables i.e., the contents of frames in the buffer
- the CPU also can examine the variables.
- things are not so simple (of course) because of concurrency difficulties: while reading a set of bytes from a frame, the controller could overwrite the data with the contents of a new frame, and in many controllers this is signaled only by a status flag.”
- “Basic CAN” implementations there is generally one double buffered receive channel with one or more associated message acceptance filters. Having but one double buffered message channel means that the processor must be capable of handling the previous message within this time.
- “Full CAN” implementations there are generally up to 15 message buffers or channels, each with one associated message acceptance filter. Having a large number of receive-buffers can be helpful in dealing with bursts of message traffic if the processor is very slow, however, if the total message traffic is such that it overwhelms the processor capability, no amount of buffering can prevent the eventual loss of a message. If a processor's CPU is very slow, to receive many different addressed messages requires separate receive buffers and acceptance filters.
- each receive buffer has associated a plurality of mask registers and filter registers as well as associated comparators. This requires a large amount of silicon real estate.
- the invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by a CAN module or a microcontroller comprising a CAN module which receives a serial bit stream.
- the CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.
- a further enhancement can comprise a mask register with a bit select input and a single bit output and a mask unit receiving the mask single bit output and the comparison result and generating a result signal being fed to the register.
- at least two mask registers with a bit select input and a single bit output and a multiplexer for selecting one of the mask register single bit outputs can be provided .
- the multiplexer comprises an input which is coupled with the single bit output of a further filter register and/or an input which is coupled with a constant signal indicating no mask function.
- the multiplexer can be controlled by at least one bit from the filter register.
- the filter register comprises two additional bits to control the multiplexer.
- the comparator is an EXCLUSIVE NOR gate
- the mask unit is a NOR gate
- the register is a D-Flip-Flop.
- a method of operating a CAN module comprises the steps of:
- An enhancement of this method comprises the step of masking the comparison result on a bit by bit base. Furthermore, a mask value can be selected from a plurality of mask values. In yet another enhancement the filter value provides additional data information for selecting the mask value. For example, the mask values is selected from a plurality of mask registers and filter registers and one mask value can provide a non-masking function.
- FIG. 1 is a schematic diagram of the receive buffers and their associated filters according to the prior art.
- FIG. 2 is a schematic diagram of the receive buffers and their associated filters and comparators according to a first exemplary embodiment of the present invention
- FIG. 3 shows details of the CAN protocol engine according to the exemplary embodiment shown in FIG. 2;
- FIG. 4 shows details of a serial bit comparator unit according to FIG. 2.
- FIG. 5 shows another embodiment of a serial bit comparator according to FIG. 2.
- Buffer 120 designated as a message assembly buffer (MAB), functions only to monitor the CAN logic bus (not shown) for incoming messages.
- the MAB 120 holds a de-stuffed bit stream from the bus line.
- the bit stream consists of a message, i.e. a data frame, remote frame, or other frame, comprising an identifier and data field (not shown).
- the MAB 120 allows receive buffers 118 and 122 parallel access to the message.
- MAB 120 also allows acceptance filters 106 and 116 access to the identifier portion of the message. Parallel transfer of the bit stream message to receive buffers 118 or 122 is not allowed until acceptance masks 102 and 108 and acceptance filters 104 , 106 , 110 , 112 , 114 , and 116 apply an acceptance match test to the message.
- Programmable acceptance filter masks 102 and 108 are used to select which bits of the unstuffed bit-stream message should be compared with the contents of acceptance filters 104 and 106 , and 110 , 112 , 114 , and 116 .
- the acceptance match test proceeds as follows: Filters 104 , 106 , 110 , 112 , 114 , and 116 receive the identifier field of the message and compare that field to filter values. If there is a match between the identifier field and a filter value, then the message is loaded into the matching filter's corresponding receive buffer 118 or 122 . Filters 104 and 106 are connected to buffer 118 , filters 110 , 112 , 114 , and 116 to buffer 122 .
- Buffer 118 is the higher priority buffer and has message acceptance filters 104 and 106 associated with it.
- Buffer 122 is the lower priority buffer and has acceptance filters 110 , 112 , 114 , and 116 associated with it. That fewer filters are associated with buffer 118 than with buffer 122 means that buffer 118 is more restrictive than buffer 122 . The more restrictive buffer 118 has, by implication, the higher criticality associated with it.
- receive buffer 118 designated as the first high-priority buffer
- receive buffer 118 will receive the first high-priority message.
- MAB 120 finds that buffer 118 is currently occupied by a high-priority message.
- MAB 120 then directs buffer 122 , designated as the second high-priority buffer, to receive the second high-priority message.
- Buffers 118 and 122 are ranked, respectively, as the first high-priority buffer and the second high-priority buffer in this scenario.
- the central processing unit (CPU) (not shown) may operate on one of the receive buffers 118 and 122 , while the other is available for reception or holding a previously received message.
- bit7 Message Ready Status
- Bit is only set by CAN module, bit is only cleared by CPU.
- bit6-5 Receive Buffer Operating Mode
- bit4 Message Reception Interrupt Enable
- bit2 (BUKT) Enable Overflow to Receive Buffer 122
- bit1 Read Only Copy of bit2 (BUKT)
- bit0 Indicates which acceptance filter enabled the message reception
- [0066] 1 acceptance filter associated with Buffer 122
- the BUKT bit implements the priority-based protocol of the present invention.
- Table II depicts and explains the control register of receive buffer 122 . TABLE II bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
- bit7 Message Ready Status
- Bit is only set by CAN module, bit is only cleared by CPU.
- bit6-5 Receive Buffer Operating Mode [these bits are optional]
- bit4 Message Reception Interrupt Enable
- bit2-0 Indicates which acceptance filter enabled the message reception
- 000 acceptance filter 104 [only if BUKT bit set to “1” in control register for buffer 118 ]
- FIG. 2 shows an exemplary embodiment of the present invention with a serial comparison according to the present invention.
- a first and second mask register 415 and 420 are bit-wise addressable and comprise a single output bit.
- a plurality of filter registers 0 . . . N (only two are shown) are designated by numerals 425 and 430 .
- the filter registers 425 , 430 also comprise a single output bit and are bit-wise addressable.
- mask registers 415 and 420 as well as all filter registers 425 , 430 are read and write-able in a parallel mode by a central processing unit 497 (connection not shown in FIG. 2).
- a sequencer and control unit 410 operates as a bit select unit and generates address signals which are fed to mask register 415 and 420 and all filter registers 425 , 430 .
- Each filter register 425 , 430 comprises an associated bit comparator unit 435 , 440 .
- the bit output signal of mask register 415 and 420 are fed to first and second inputs of bit comparator units 435 , 440 .
- each bit output of the filter registers 425 , 430 is fed to a third input of their associated bit comparator unit 435 , 440 .
- a bit stream signal from a CAN bus is provided by a CAN protocol engine 495 and fed to a fourth input of each bit comparator unit 435 , 440 .
- Filter registers 425 , 430 can provided additional storage bits which are coupled with a fifth input of each associated bit comparator unit.
- the output of each bit comparator unit 435 , 440 carries the acceptance signal and is coupled with a control input of an associated buffer pointer 445 , 450 .
- An OR gate 455 is provided having as many inputs as the number of filter registers. Each input receives an acceptance signal from a respective bit comparator unit 435 , 440 .
- the outputs of each buffer pointer 445 and 450 are coupled with a buffer pointer bus 462 which is connected to an address input of a multiple function address register 460 .
- the output of OR gate 455 is coupled with a control input of multiple function register 460 .
- Multiple function register 460 further comprises a mode control input 465 , a first status output 475 indicating whether a buffer memory 485 is full, a second status output 480 indicating whether a buffer memory 485 is empty, and an up/down control input for a counter function of the multiple function address register 460 .
- An address output 464 of multiple function address register 460 is coupled with the address input of buffer memory 485 .
- Buffer memory 485 is preferably a dual port memory whose first port is coupled with a message assembly buffer shift register 490 receiving the serial data stream from the CAN protocol engine 495 .
- the second port of is coupled with central processing unit 497 which is furthermore coupled with a memory 496 for storing program and data information.
- this embodiment provides two options to write data from a serial data stream into the buffer memory 485 . Both options can be implemented as a stand alone embodiment or combined as shown in FIG. 2 with the features of the present invention.
- the comparison of filter values stored in filter registers 425 , 430 and transmitted identifiers is done in a bit-wise fashion rather than in parallel. Thus, parallel comparators, which need a relatively big amount of silicon real estate, are avoided.
- a serial data stream provided by CAN protocol engine 495 comprises an identifier which is fed directly to all bit comparator units 435 , 440 .
- Sequencer and control unit 410 address the mask registers 415 , 420 and all filter registers 425 , 430 to output a corresponding bit to the bit comparator units 435 , 440 .
- the bit comparator units 435 , 440 compare all filter register bits with the respective identifier bit within a frame. The result is further processed by comparing it to the respective mask register bit. To this end, the additional storage bits of each filter register 425 , 430 can indicate which mask register should be used for this comparison. This function will be explained in more detail below.
- the final comparison result will be accumulated for all bits of each identifier within a frame. If a single comparison fails the acceptance signal will not be generated. If every bit comparison is positive the acceptance signal will be fed to the respective buffer pointer 445 , 450 and to a respective input of OR gate 455 .
- a central processing unit can control the multiple function address register 460 in the following manner. Two modes can be selected through mode signal 465 . In the first mode the buffer pointer 445 , 450 work in the same way as described above in conjunction with FIG. 2. Multiple function address register 460 latches an address which has been put on address bus 462 and addresses buffer memory 485 stores data in parallel that has been assembled by message assembly buffer shift register 490 .
- a second mode can be selected by means of control signal 465 .
- the buffer pointers 445 , 450 are not needed and therefore their output signals will be neglected.
- the actual address register within multiple function address register is, for example, set to “Fh” and the status signal 480 will signal an empty buffer. Every time a bit comparator unit 435 , 440 generates an acceptance signal this triggers an increment function of the multiple function address register 460 and its content will therefore be incremented by 1.
- the first data assembled by message assembly buffer shift register 490 will be stored at memory location 0 .
- This function provides a so called FIFO functionality of the CAN module in which no buffer is associated with any bit comparator.
- the buffer memory 485 will be sequentially written until the address reaches “Fh” again which indicates that the buffer is full unless the CPU has read previous entries. A full buffer memory 485 will be indicated by control signal 475 .
- control signal 470 can select between a incrementing and decrementing function of the address register. Additional signals can be provided by the CPU to indicate whether a buffer value has been read for generating the proper status signals 475 , and 480 and to ensure that no value will be overwritten before it has been fetched by the CPU.
- FIG. 3 shows the CAN protocol engine 495 from FIG. 2 in more detail.
- the protocol engine 495 combines several functional blocks.
- the heart of the engine 495 is the protocol finite state machine 310 (FSM).
- FSM protocol finite state machine
- This state machine sequences through the messages on a bit by bit basis, changing states of the machine as various fields of various frame types are transmitted or received.
- the FSM 310 is a sequencer controlling the sequential data stream between the RX/TX shift register 320 , 325 , the CRC Register 330 , and the receive bus line 350 and transmit bus line 360 , respectively.
- the shift registers 320 , 325 can be part of the message assembly register 270 .
- Additional components 355 and 365 are provided to convert the data streams and adapt to the respective timing on the bus lines 350 and 360 .
- the FSM also controls the Error Management Logic 340 (EML) and the parallel data stream RecData between the TX/RX shift register 320 , 325 and other components of the CAN module. The processes of reception arbitration, transmission, and error signaling are performed according to the CAN protocol.
- the FSM 310 also handles any automatic transmission of messages on the bus line.
- the data interface to the protocol engine 495 consists of byte wide transmit and receive data. Rather than assembling and shifting an entire frame, the frames are broken into bytes.
- a receive or transmit address from the protocol FSM 310 signifies which byte of the frame is current.
- the appropriate byte from the transmit buffer is selected and presented to the engine, which then uses an 8-bit shift register to serialize the data.
- an 8-bit shift register assembles a byte which is then loaded within the appropriate byte in the message assembly buffer 270 .
- the cyclic redundancy check register 330 generates the Cyclic Redundancy Check (CRC) code to be transmitted over the data bytes and checks the CRC code of incoming messages.
- the Error Management Logic (EML) 340 is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit stream processor. According to the values of the error counters, the CAN controller is set into states error active, error passive or bus off.
- the Bit Timing Logic (BTL) within unit 355 monitors the bus line input and handles the bus line related bit timing according to the CAN protocol.
- the BTL synchronizes on a recessive to dominant bus line transition at Start of Frame and on any further recessive to dominant bus line transition, if the CAN controller itself does not transmit a dominant bit.
- the BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and in defining the position of the Sample Point in the bit time.
- the programming of the BTL depends on the baud rate and on external physical delay times.
- FIG. 4 an exemplary embodiment of a comparator unit according to the present invention is shown. The details are shown for a single Bit comparator unit but apply for all other bit comparator units accordingly.
- Numeral 600 indicates a unit providing a CAN serial data stream which is fed to a message assembly buffer register 680 and the first input of an Exclusive NOR gate 690 .
- the single bit output of a filter register 620 is coupled with the second input of Exclusive NOR gate 690 whose output is connected with the first input of a NOR gate 650 .
- the second input of NOR gate 650 receives the single bit output signal from mask register 630 .
- NOR gate 650 is coupled with the first input of an AND gate 660 whose output is coupled with the control input of a D-Flip-Flop 670 .
- Input D of D-Flip-Flop 670 is coupled with a logical “low” signal such as Vcc.
- the inverting output of D-Flip-Flop 670 is coupled with the first input of AND gate 640 whose output provides the acceptance signal.
- AND gates 640 and 660 comprises second inputs ACC_RDY and BIT_RDY, respectively, which are used for synchronization with the respective input signals.
- a Bit Select Logic 610 is coupled with filter register 620 and mask register 630 to select the respective bits which will be used for comparison within each frame.
- bit select logic 610 selects the respective bit in filter register 620 and mask register 630 that corresponds to the incoming bit of the serial bit stream.
- the actual comparator is formed by Exclusive NOR gate 690 which only generates a logic “high” at its output if both input signals are identical.
- NOR gate 650 is used as a mask unit to mask out a result if a respective bit within the mask register 630 is set.
- D-Flip-Flop 670 is used as a register to accumulate the results within a chain of comparisons and is preset to “1” at the start of a frame.
- FIG. 5 shows another exemplary embodiment of a bit comparator unit 435 , 440 with even more functionality in more detail. Again, the details are shown for Bit comparator unit 0 but apply for all other bit comparator units accordingly.
- the outputs of mask register 415 and 420 are coupled with first and second inputs of a 4:1 multiplexer 520 .
- Additional input 560 and 570 can be provided at the third and fourth input of multiplexer 520 .
- input 560 is coupled with the output of filter register 15 which is designated by numeral 580 .
- Filter register 425 comprises, for example, two additional outputs which are coupled with the select input of multiplexer 520 .
- Multiplexer 520 can have any size, for example, can be expanded to a N:1 multiplexer increasing the number of masks to N.
- the output of multiplexer 520 is connected to the first input of a NOR gate 530 .
- NOR gate 530 operates as a validation unit indicating whether a comparison result will be used or ignored.
- the second input of NOR gate 530 is coupled with the output of an Exclusive NOR gate 510 whose first input receives the bit output signal from filter register 425 and whose second input receives the serial data stream from CAN protocol engine 495 .
- the output of NOR gate 530 is coupled with the control input of a D-Flip-Flop 540 .
- the D-input of D-Flip-Flop 540 receives a logical low signal.
- the acceptance signal is carried at the negating output 550 of D-Flip-Flop 540 .
- the first comparison stage is formed by Exclusive NOR gate 510 .
- Exclusive NOR gate 510 In this stage the identifier bits of the serial bit stream are compared with the respective bits of filter register 425 .
- Exclusive NOR gate 510 only generates a logic “high” at its output if both input signals are identical.
- Sequencer unit 410 selects the respective bits within filter register 425 .
- Filter register 425 comprises additional data bits which indicate which mask register should be used. In this exemplary embodiment four different values can be selected. Either one of the mask registers 415 or 420 can be selected or a third value can be provided by another filter register, for example filter register 15 .
- the fourth possible selection 570 can be used to indicate that no mask will be used by providing a respective level, for example, a logical “1”.
- each filter register 425 , 430 can be assigned an individual mask function.
- the selected mask value will be put at the first input of NOR gate 530 . If the mask value indicates that the respective bit in filter register 425 should be used NOR gate 530 will operate as a controllable switch and feed the comparison result of Exclusive NOR gate 510 to the control input D-Flip-Flop 540 .
- D-Flip-Flop 540 is used as a register which is preset to “1”. If the result of one comparison is negative indicating no match and the respective mask bit is valid D-Flip-Flop 540 will be cleared and no acceptance signal 550 will be generated. D-Flip-Flop 540 thus will be reset to “0”. D-Flip-Flop 540 will be preset to “1” again beginning with the next frame to compare another identifier as described above.
- any other type of appropriate logic can be used to implement the comparator.
- controllable switches, equivalent Boolean operators, etc. can be used.
- the validation unit can be either put in front of the comparator or after the comparator. The essential function of a validation unit is to either incorporate selected bits or exclude them from comparison.
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Abstract
A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.
Description
- The present invention relates to a serial communication device, in particular a Controller Area Network (CAN) device. Furthermore, the present invention relates to a microcontroller with a serial communication device and a method of operating a serial communication device.
- Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. Applications of CAN range from high speed digital communications networks to low cost multiplex wiring. CAN is a high-integrity serial data communications bus for real-time applications. CAN operates at data rates of up to 1 Megabits per second, has excellent error detection and confinement capabilities, and was originally developed for use in automobiles. The interface between the CAN bus and the CPU is usually called the CAN controller. The motivation behind CAN was to make automobiles more reliable, safe and fuel-efficient by improving the interoperability of automotive electronics, engine control units, sensors, anti-skid brake systems, etc., while decreasing wiring harness weight and complexity. Since CAN's inception, the CAN protocol has gained widespread popularity in industrial automation and automotive/truck applications. The robustness of the CAN bus in noisy environments and the ability to detect and recover from fault conditions makes CAN suitable for use with, industrial control equipment, medical equipment, test equipment, mobile and portable machines, appliances, etc.
- CAN is an asynchronous serial bus system with one logical bus line. It has an open, linear bus structure with equal bus nodes. A CAN bus consists of two or more nodes. The number of nodes on the bus may be changed dynamically without disturbing the communication of the other nodes.
- The CAN logic bus corresponds to a “wired-AND” mechanism, “recessive” bits (mostly, but not necessarily equivalent to the logic level “1“) are overwritten by “dominant” bits (mostly logic level “0”). As long as no bus node is sending a dominant bit, the bus line is in the recessive state, but a dominant bit from any bus node generates the dominant bus state. Therefore, for the CAN bus line, a medium is chosen that is able to transmit the two possible bit states (dominant and recessive). A common physical medium used is a twisted wire pair. The bus lines are then called “CANH” and “CANL,” and may be connected directly to the CAN controller nodes or via a connector thereto.
- In the CAN bus protocol it is not bus nodes that are addressed, but rather the address information is contained in the messages that are transmitted. This is done via an identifier (part of each message) which identifies the message content, e.g., engine speed, oil temperature, etc. The identifier additionally indicates the priority of the message. The lower the binary value of the identifier, the higher the priority of the message (more dominant bits).
- The original CAN specifications (Versions 1.0, 1.2 and 2.0A) defined the message identifier as having a length of 11 bits, giving a possible 2048 message identifiers. An “extended CAN” specification Version 2.0B allows message identifier lengths of 11 and/or 29 bits to be used (an identifier length of 29 bits allows over 536 Million message identifiers). The CAN specifications (all versions) are incorporated by reference herein for all purposes.
- Generally, two approaches may be used for CAN since an architecture for the CAN controller is not covered by the CAN standard, these two approaches are: “BasicCAN” and “FullCAN” (not to be confused with CAN 1 and CAN 2, or standard identifiers and extended identifiers); they differ in the buffering of messages.
- The BasicCAN controller architecture is similar to simple UART, except that complete frames are sent instead of characters. Typically, there is a single transmit buffer and a double-buffered receive buffer. For example, a microcontroller puts a frame in the transmit buffer, and receives an interrupt when the frame is sent. When a frame is received in the receive buffer, the microcontroller receives an interrupt to empty the receive buffer and empties the frame from the receive buffer before a subsequent frame is received. In the BasicCAN controller architecture the microcontroller must manage the transmission and reception, and handle the storage of the frames.
- The FullCAN controller architecture stores frames in the controller itself. A limited number of frames may be dealt with. Each frame buffer is tagged with the identifier of the frame mapped to the buffer. The microcontroller can update a frame in the buffer and mark it for transmission. Receive buffers can be examined to see if a frame with a matching identifier has been received. In addition, filters may be used to pre-screen a received frame so that only those frames intended for use by the particular CAN controller is stored in a receive buffer.
- Standard CAN vs Extended CAN
- The CAN protocol usually comes in two versions: CAN 1.0 and CAN 2.0. CAN 2.0 is backwardly compatible with CAN 1.0, and most new controllers are built according to CAN 2.0. There are two parts to the CAN 2.0 standard: part A and part B. With CAN 1.0 and CAN 2.0A, identifiers must be 11-bits long. With CAN 2.0B identifiers can be 11-bits (a “standard” identifier) or 29-bits (an “extended” identifier). To comply with CAN 2.0 a controller must be either 2.0 part B passive, or 2.0 part B active. If it is passive, then it must ignore extended frames (CAN 1.0 controllers will generate error frames when they see frames with 29-bit identifiers). If it is active then it must allow extended frames to be received and transmitted. There are some compatibility rules for sending and receiving the two types of frames:
- CAN 2.0B active controllers will send and accept both standard and extended frames.
- CAN 2.0B passive controllers will send and receive standard frames, and will discard extended frames without error.
- CAN 1.0 controllers will generate errors when they see extended frames.
- So a network where there is a single CAN 1.0 controller on the network cannot live with extended frames on the network; all the controllers must send using standard frames.”
- Controller Architectures
- The architecture of controllers isn't covered by the CAN standard, so there is a variation in how they are used. There are, though, two general approaches: BasicCAN and FullCAN (not to be confused with CAN 1.0 and 2.0, or standard identifiers and extended identifiers); they differ in the buffering of messages.”
- In a BasicCAN controller the architecture is similar to a simple UART, except that complete frames are sent instead of characters: there is (typically) a single transmit buffer, and a double-buffered receive buffer. The CPU puts a frame in the transmit buffer, and takes an interrupt when the frame is sent; the CPU receives a frame in the receive buffer, takes an interrupt and empties the buffer (before a subsequent frame is received). The CPU must manage the transmission and reception, and handle the storage of the frames.”
- In a FullCAN controller the frames are stored in the controller. A limited number of frames can be dealt with (typically 16); because there can be many more frames on the network, each buffer is tagged with the identifier of the frame mapped to the buffer. The CPU can update a frame in the buffer and mark it for transmission; buffers can be examined to see if a frame with a matching identifier has been received.”
- The intention with the FulICAN design is to provide a set of “shared variables” in the network; the CPU periodically updates the variables (i.e., the contents of frames in the buffer); the CPU also can examine the variables. In practice, things are not so simple (of course) because of concurrency difficulties: while reading a set of bytes from a frame, the controller could overwrite the data with the contents of a new frame, and in many controllers this is signaled only by a status flag.”
- In “Basic CAN” implementations, there is generally one double buffered receive channel with one or more associated message acceptance filters. Having but one double buffered message channel means that the processor must be capable of handling the previous message within this time. In “Full CAN” implementations, there are generally up to 15 message buffers or channels, each with one associated message acceptance filter. Having a large number of receive-buffers can be helpful in dealing with bursts of message traffic if the processor is very slow, however, if the total message traffic is such that it overwhelms the processor capability, no amount of buffering can prevent the eventual loss of a message. If a processor's CPU is very slow, to receive many different addressed messages requires separate receive buffers and acceptance filters. With a faster processor, it is possible to use a more limited number of receive buffers with flexibility in the programming of the acceptance filters. In short, the processor must have the bandwidth to service the total traffic on the bus. A plurality of buffers is usually implemented as a compromise. However, each receive buffer has associated a plurality of mask registers and filter registers as well as associated comparators. This requires a large amount of silicon real estate.
- There is, therefore, a need in the art for a CAN implementation that does not require a large amount of silicon area.
- The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by a CAN module or a microcontroller comprising a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.
- A further enhancement can comprise a mask register with a bit select input and a single bit output and a mask unit receiving the mask single bit output and the comparison result and generating a result signal being fed to the register. In addition, at least two mask registers with a bit select input and a single bit output and a multiplexer for selecting one of the mask register single bit outputs can be provided .
- In yet another enhancement, the multiplexer comprises an input which is coupled with the single bit output of a further filter register and/or an input which is coupled with a constant signal indicating no mask function. The multiplexer can be controlled by at least one bit from the filter register. For example, the filter register comprises two additional bits to control the multiplexer. In an exemplary embodiment, the comparator is an EXCLUSIVE NOR gate, the mask unit is a NOR gate, and the register is a D-Flip-Flop.
- A method of operating a CAN module comprises the steps of:
- receiving a data stream;
- generating an identifier and data out of the data stream;
- comparing said identifier with a filter value on a bit by bit base;
- generating an acceptance signal if the comparison is positive;
- storing associated data in a buffer upon generation of the acceptance signal.
- An enhancement of this method comprises the step of masking the comparison result on a bit by bit base. Furthermore, a mask value can be selected from a plurality of mask values. In yet another enhancement the filter value provides additional data information for selecting the mask value. For example, the mask values is selected from a plurality of mask registers and filter registers and one mask value can provide a non-masking function.
- The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
- FIG. 1 is a schematic diagram of the receive buffers and their associated filters according to the prior art.
- FIG. 2 is a schematic diagram of the receive buffers and their associated filters and comparators according to a first exemplary embodiment of the present invention;
- FIG. 3 shows details of the CAN protocol engine according to the exemplary embodiment shown in FIG. 2;
- FIG. 4 shows details of a serial bit comparator unit according to FIG. 2; and
- FIG. 5 shows another embodiment of a serial bit comparator according to FIG. 2.
- Referring to FIG. 1, receive
buffers mask registers Buffer 120, designated as a message assembly buffer (MAB), functions only to monitor the CAN logic bus (not shown) for incoming messages. TheMAB 120 holds a de-stuffed bit stream from the bus line. The bit stream consists of a message, i.e. a data frame, remote frame, or other frame, comprising an identifier and data field (not shown). TheMAB 120 allows receivebuffers MAB 120 also allows acceptance filters 106 and 116 access to the identifier portion of the message. Parallel transfer of the bit stream message to receivebuffers - Programmable acceptance filter masks102 and 108, respectively, are used to select which bits of the unstuffed bit-stream message should be compared with the contents of acceptance filters 104 and 106, and 110, 112, 114, and 116.
- The acceptance match test proceeds as follows:
Filters buffer Filters filters - There is an implied priority to the receive buffers.
Buffer 118 is the higher priority buffer and has message acceptance filters 104 and 106 associated with it.Buffer 122 is the lower priority buffer and has acceptance filters 110, 112, 114, and 116 associated with it. That fewer filters are associated withbuffer 118 than withbuffer 122 means thatbuffer 118 is more restrictive thanbuffer 122. The morerestrictive buffer 118 has, by implication, the higher criticality associated with it. - On the occasion when two “high-priority” messages are received by
MAB 120 in quick succession, receivebuffer 118, designated as the first high-priority buffer, will receive the first high-priority message. Upon receipt of the second high-priority message,MAB 120 finds thatbuffer 118 is currently occupied by a high-priority message.MAB 120 then directsbuffer 122, designated as the second high-priority buffer, to receive the second high-priority message.Buffers - The central processing unit (CPU) (not shown) may operate on one of the receive
buffers - The protocol in the case of the arrival of two high-priority messages is effected by the BUKT bit in the control registers (not shown) of receive
buffers buffer 118, wherein R/W means Readable/Writable bit, and wherein R means Read-only bit.TABLE I bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R R/W - bit7: Message Ready Status
-
-
- Bit is only set by CAN module, bit is only cleared by CPU.
- bit6-5: Receive Buffer Operating Mode
-
-
-
-
- bit4: Message Reception Interrupt Enable
-
-
- bit3: Received Remote Transfer Request
-
-
- bit2: (BUKT) Enable Overflow to Receive
Buffer 122 -
Buffer 118 Overflow Will Write to Buffer 122 -
- bit1: Read Only Copy of bit2 (BUKT)
- bit0: Indicates which acceptance filter enabled the message reception
-
Buffer 122 -
Buffer 118 - If set to “1,” the BUKT bit implements the priority-based protocol of the present invention.
- Table II depicts and explains the control register of receive
buffer 122.TABLE II bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W R/W R/W R/W R/W R/W R/W R/W - bit7: Message Ready Status
-
-
- Bit is only set by CAN module, bit is only cleared by CPU.
- bit6-5: Receive Buffer Operating Mode [these bits are optional]
-
-
-
-
- bit4: Message Reception Interrupt Enable
-
-
- bit3: Received Remote Transfer Request
-
-
- bit2-0: Indicates which acceptance filter enabled the message reception
-
acceptance filter 116 -
acceptance filter 114 -
acceptance filter 112 -
acceptance filter 110 -
-
- FIG. 2 shows an exemplary embodiment of the present invention with a serial comparison according to the present invention. A first and
second mask register filter registers 0 . . . N (only two are shown) are designated bynumerals control unit 410 operates as a bit select unit and generates address signals which are fed to mask register 415 and 420 and all filterregisters filter register comparator unit 435, 440. The bit output signal ofmask register comparator units 435, 440. Furthermore, each bit output of the filter registers 425, 430 is fed to a third input of their associated bitcomparator unit 435, 440. A bit stream signal from a CAN bus is provided by aCAN protocol engine 495 and fed to a fourth input of eachbit comparator unit 435, 440. Filter registers 425, 430 can provided additional storage bits which are coupled with a fifth input of each associated bit comparator unit. The output of eachbit comparator unit 435, 440 carries the acceptance signal and is coupled with a control input of an associatedbuffer pointer gate 455 is provided having as many inputs as the number of filter registers. Each input receives an acceptance signal from a respective bitcomparator unit 435, 440. The outputs of eachbuffer pointer buffer pointer bus 462 which is connected to an address input of a multiplefunction address register 460. The output of ORgate 455 is coupled with a control input ofmultiple function register 460.Multiple function register 460 further comprises amode control input 465, afirst status output 475 indicating whether abuffer memory 485 is full, asecond status output 480 indicating whether abuffer memory 485 is empty, and an up/down control input for a counter function of the multiplefunction address register 460. An address output 464 of multiplefunction address register 460 is coupled with the address input ofbuffer memory 485.Buffer memory 485 is preferably a dual port memory whose first port is coupled with a message assemblybuffer shift register 490 receiving the serial data stream from theCAN protocol engine 495. The second port of is coupled withcentral processing unit 497 which is furthermore coupled with amemory 496 for storing program and data information. - Even this is not crucial to the present invention, this embodiment provides two options to write data from a serial data stream into the
buffer memory 485. Both options can be implemented as a stand alone embodiment or combined as shown in FIG. 2 with the features of the present invention. The comparison of filter values stored in filter registers 425, 430 and transmitted identifiers is done in a bit-wise fashion rather than in parallel. Thus, parallel comparators, which need a relatively big amount of silicon real estate, are avoided. A serial data stream provided byCAN protocol engine 495 comprises an identifier which is fed directly to all bitcomparator units 435, 440. Sequencer andcontrol unit 410 address the mask registers 415, 420 and all filterregisters bit comparator units 435, 440. Thebit comparator units 435, 440 compare all filter register bits with the respective identifier bit within a frame. The result is further processed by comparing it to the respective mask register bit. To this end, the additional storage bits of eachfilter register respective buffer pointer gate 455. - A central processing unit can control the multiple
function address register 460 in the following manner. Two modes can be selected throughmode signal 465. In the first mode thebuffer pointer address bus 462 and addressesbuffer memory 485 stores data in parallel that has been assembled by message assemblybuffer shift register 490. - A second mode can be selected by means of
control signal 465. In this mode thebuffer pointers status signal 480 will signal an empty buffer. Every time abit comparator unit 435, 440 generates an acceptance signal this triggers an increment function of the multiplefunction address register 460 and its content will therefore be incremented by 1. Thus, the first data assembled by message assemblybuffer shift register 490 will be stored atmemory location 0. This function provides a so called FIFO functionality of the CAN module in which no buffer is associated with any bit comparator. Thebuffer memory 485 will be sequentially written until the address reaches “Fh” again which indicates that the buffer is full unless the CPU has read previous entries. Afull buffer memory 485 will be indicated bycontrol signal 475. In an additionalmode control signal 470 can select between a incrementing and decrementing function of the address register. Additional signals can be provided by the CPU to indicate whether a buffer value has been read for generating the proper status signals 475, and 480 and to ensure that no value will be overwritten before it has been fetched by the CPU. - FIG. 3 shows the
CAN protocol engine 495 from FIG. 2 in more detail. Theprotocol engine 495 combines several functional blocks. The heart of theengine 495 is the protocol finite state machine 310 (FSM). This state machine sequences through the messages on a bit by bit basis, changing states of the machine as various fields of various frame types are transmitted or received. TheFSM 310 is a sequencer controlling the sequential data stream between the RX/TX shift register CRC Register 330, and the receivebus line 350 and transmitbus line 360, respectively. The shift registers 320, 325 can be part of the message assembly register 270.Additional components bus lines RX shift register FSM 310 also handles any automatic transmission of messages on the bus line. - The data interface to the
protocol engine 495 consists of byte wide transmit and receive data. Rather than assembling and shifting an entire frame, the frames are broken into bytes. A receive or transmit address from theprotocol FSM 310 signifies which byte of the frame is current. For transmission, the appropriate byte from the transmit buffer is selected and presented to the engine, which then uses an 8-bit shift register to serialize the data. For reception, an 8-bit shift register assembles a byte which is then loaded within the appropriate byte in the message assembly buffer 270. - The cyclic
redundancy check register 330 generates the Cyclic Redundancy Check (CRC) code to be transmitted over the data bytes and checks the CRC code of incoming messages. The Error Management Logic (EML) 340 is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit stream processor. According to the values of the error counters, the CAN controller is set into states error active, error passive or bus off. - The Bit Timing Logic (BTL) within
unit 355 monitors the bus line input and handles the bus line related bit timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant bus line transition at Start of Frame and on any further recessive to dominant bus line transition, if the CAN controller itself does not transmit a dominant bit. The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and in defining the position of the Sample Point in the bit time. The programming of the BTL depends on the baud rate and on external physical delay times. - In FIG. 4 an exemplary embodiment of a comparator unit according to the present invention is shown. The details are shown for a single Bit comparator unit but apply for all other bit comparator units accordingly.
Numeral 600 indicates a unit providing a CAN serial data stream which is fed to a messageassembly buffer register 680 and the first input of an Exclusive NORgate 690. The single bit output of afilter register 620 is coupled with the second input of Exclusive NORgate 690 whose output is connected with the first input of a NORgate 650. The second input of NORgate 650 receives the single bit output signal frommask register 630. The output of NORgate 650 is coupled with the first input of an ANDgate 660 whose output is coupled with the control input of a D-Flip-Flop 670. Input D of D-Flip-Flop 670 is coupled with a logical “low” signal such as Vcc. The inverting output of D-Flip-Flop 670 is coupled with the first input of ANDgate 640 whose output provides the acceptance signal. ANDgates Bit Select Logic 610 is coupled withfilter register 620 and mask register 630 to select the respective bits which will be used for comparison within each frame. - The incoming CAN bit stream is synchronized with the bit
select logic 610. In other words, bitselect logic 610 selects the respective bit infilter register 620 and mask register 630 that corresponds to the incoming bit of the serial bit stream. The actual comparator is formed by Exclusive NORgate 690 which only generates a logic “high” at its output if both input signals are identical. NORgate 650 is used as a mask unit to mask out a result if a respective bit within themask register 630 is set. D-Flip-Flop 670 is used as a register to accumulate the results within a chain of comparisons and is preset to “1” at the start of a frame. Only if all comparisons within a frame are successful, then the acceptance signal AccN at the output of ANDgate 640 will be generated. Otherwise the D-Flip-Flop 670 is set to “0” by a false comparison result and stays “0” until the end of the frame. The two control signals ACC_RDY and BIT_RDY are used to synchronize and activate the respective signals. - FIG. 5 shows another exemplary embodiment of a
bit comparator unit 435, 440 with even more functionality in more detail. Again, the details are shown forBit comparator unit 0 but apply for all other bit comparator units accordingly. The outputs ofmask register multiplexer 520.Additional input multiplexer 520. For example,input 560 is coupled with the output of filter register 15 which is designated bynumeral 580.Filter register 425 comprises, for example, two additional outputs which are coupled with the select input ofmultiplexer 520.Multiplexer 520 can have any size, for example, can be expanded to a N:1 multiplexer increasing the number of masks to N. The output ofmultiplexer 520 is connected to the first input of a NORgate 530. NORgate 530 operates as a validation unit indicating whether a comparison result will be used or ignored. The second input of NORgate 530 is coupled with the output of an Exclusive NORgate 510 whose first input receives the bit output signal fromfilter register 425 and whose second input receives the serial data stream fromCAN protocol engine 495. The output of NORgate 530 is coupled with the control input of a D-Flip-Flop 540. The D-input of D-Flip-Flop 540 receives a logical low signal. The acceptance signal is carried at the negatingoutput 550 of D-Flip-Flop 540. - The first comparison stage is formed by Exclusive NOR
gate 510. In this stage the identifier bits of the serial bit stream are compared with the respective bits offilter register 425. Exclusive NORgate 510 only generates a logic “high” at its output if both input signals are identical.Sequencer unit 410 selects the respective bits withinfilter register 425.Filter register 425 comprises additional data bits which indicate which mask register should be used. In this exemplary embodiment four different values can be selected. Either one of the mask registers 415 or 420 can be selected or a third value can be provided by another filter register, forexample filter register 15. The fourthpossible selection 570 can be used to indicate that no mask will be used by providing a respective level, for example, a logical “1”. Thus, eachfilter register gate 530. If the mask value indicates that the respective bit infilter register 425 should be used NORgate 530 will operate as a controllable switch and feed the comparison result of Exclusive NORgate 510 to the control input D-Flip-Flop 540. D-Flip-Flop 540 is used as a register which is preset to “1”. If the result of one comparison is negative indicating no match and the respective mask bit is valid D-Flip-Flop 540 will be cleared and noacceptance signal 550 will be generated. D-Flip-Flop 540 thus will be reset to “0”. D-Flip-Flop 540 will be preset to “1” again beginning with the next frame to compare another identifier as described above. - Any other type of appropriate logic can be used to implement the comparator. For example, controllable switches, equivalent Boolean operators, etc. can be used. Furthermore, the validation unit can be either put in front of the comparator or after the comparator. The essential function of a validation unit is to either incorporate selected bits or exclude them from comparison.
- The invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While the invention has been depicted, described, and is defined by reference to particular preferred embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts. The depicted and described preferred embodiments of the invention are exemplary only, and are not exhaustive of the scope of the invention. Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.
Claims (26)
1. A CAN module receiving a serial bit stream comprising:
a filter register having a bit select input and a single bit output;
a bit select unit for selecting a bit of said filter register in accordance with said serial bit stream;
a comparator coupled with said single bit output and with said serial bit stream for generating a comparison signal;
a register receiving said comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.
2. CAN module according to claim 1 , further comprising
a mask register having a bit select input and a single bit output;
a mask unit receiving said mask single bit output and said comparison result and generating a result signal being fed to said register.
3. CAN module according to claim 2 , further comprising
at least two mask register s having a bit select input and a single bit output;
a multiplexer for selecting one of said mask register single bit output s .
4. CAN module according to claim 3 , wherein said multiplexer comprises an input which is coupled with the single bit output of a further filter register.
5. CAN module according to claim 3 , wherein said multiplexer comprises an input which is coupled with a constant signal indicating no mask function.
6. CAN module according to claim 3 , wherein said multiplexer is controlled by at least one bit from said filter register.
7. CAN module according to claim 6 , wherein said filter register comprises two additional bits to control said multiplexer.
8. CAN module according to claim 1 , wherein said comparator is an EXCLUSIVE NOR gate.
9. CAN module according to claim 1 , wherein said mask unit is a NOR gate.
10. CAN module according to claim 1 , wherein said register is a D-Flip-Flop.
11. A microcontroller comprising:
a central processing unit;
a random access memory connected to said central processing unit; and
a CAN module coupled with said central processing unit, wherein said CAN module comprises:
a filter register having a bit select input and a single bit output;
a bit select unit for selecting a bit of said filter register in accordance with said serial bit stream;
a comparator coupled with said single bit output and with said serial bit stream for generating a comparison signal;
a register receiving said comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.
12. The microcontroller according to claim 11 , further comprising:
a mask register having a bit select input and a single bit output;
a mask unit receiving said mask single bit output and said comparison result and generating a result signal being fed to said register.
13. The microcontroller according to claim 12 , further comprising:
at least two mask registers having a bit select input and a single bit output;
a multiplexer for selecting one of said mask register single bit outputs.
14. The microcontroller according to claim 13 , wherein said multiplexer comprises an input which is coupled with the single bit output of a further filter register.
15. The microcontroller according to claim 13 , wherein said multiplexer comprises an input which is coupled with a constant signal indicating no mask function.
16. The microcontroller according to claim 13 , wherein said multiplexer is controlled by at least one bit from said filter register.
17. The microcontroller according to claim 16 , wherein said filter register comprises two additional bits to control said multiplexer.
18. The microcontroller according to claim 11 , wherein said comparator is an EXCLUSIVE NOR gate.
19. The microcontroller according to claim 11 , wherein said mask unit is a NOR gate.
20. The microcontroller according to claim 11 , wherein said register is a D-Flip-Flop.
21. A method of operating a CAN module comprising the steps of:
receiving a data stream;
generating an identifier and data out of said data stream;
comparing said identifier with a filter value on a bit by bit base;
generating an acceptance signal if said comparison is positive;
storing associated data in a buffer upon generation of said acceptance signal.
22. A method according to claim 21 , further comprising the step of masking said comparison result on a bit by bit base.
23. A method according to claim 22 , further comprising the step selecting a mask value from a plurality of mask values.
24. A method according to claim 23 , wherein said filter value provides additional data information for selecting said mask value.
25. A method according to claim 23 , wherein said mask values is selected from a plurality of mask registers and filter registers.
26. A method according to claim 23 , wherein one mask value provides a non-masking function.
Priority Applications (9)
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US09/957,062 US20040153583A1 (en) | 2001-09-20 | 2001-09-20 | Serial communication device with dynamic allocation of acceptance masks using serial implementation |
AU2002331837A AU2002331837A1 (en) | 2001-09-20 | 2002-09-10 | Serial communication device with dynamic filter allocation |
AT02768828T ATE448614T1 (en) | 2001-09-20 | 2002-09-10 | DEVICE FOR SERIAL COMMUNICATION SYSTEM WITH ASSIGNMENT OF DYNAMIC FILTERS |
PCT/US2002/028661 WO2003025740A2 (en) | 2001-09-20 | 2002-09-10 | Serial communication device with dynamic filter allocation |
CN02822749A CN100586092C (en) | 2001-09-20 | 2002-09-10 | Serial communication device with dynamic filter allocation |
KR1020047004106A KR100660437B1 (en) | 2001-09-20 | 2002-09-10 | Serial communication device with dynamic filter allocation |
DE60234357T DE60234357D1 (en) | 2001-09-20 | 2002-09-10 | NUNG OF DYNAMIC FILTERS |
EP02768828A EP1430653B1 (en) | 2001-09-20 | 2002-09-10 | Serial communication device with dynamic filter allocation |
US12/504,268 US7979594B2 (en) | 2001-09-20 | 2009-07-16 | Serial communications device with dynamic allocation of acceptance masks using serial implementation |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030051061A1 (en) * | 2001-09-04 | 2003-03-13 | Peter Hank | Acceptance filter |
US20040057432A1 (en) * | 2002-09-20 | 2004-03-25 | Allen William E. | Method for setting masks for message filtering |
US7296312B2 (en) * | 2002-09-06 | 2007-11-20 | Hill-Rom Services, Inc. | Hospital bed |
US20110125855A1 (en) * | 2008-03-10 | 2011-05-26 | Florian Hartwich | Method and filter system for filtering messages received via a serial data bus of a communication network by a user of the network |
US9009893B2 (en) | 1999-12-29 | 2015-04-21 | Hill-Rom Services, Inc. | Hospital bed |
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EP2330791B1 (en) * | 2009-11-30 | 2012-10-17 | Fujitsu Semiconductor Limited | Message reception |
CN103248520A (en) * | 2013-04-28 | 2013-08-14 | 安徽江淮汽车股份有限公司 | Processing method and system for bus-off fault of CAN bus |
FR3089729B1 (en) * | 2018-12-05 | 2021-08-06 | Renault Sas | Frame selection system, communication node and associated implementation method |
CN110808891B (en) * | 2019-09-30 | 2021-10-12 | 深圳市道通合创新能源有限公司 | CAN filter merging method and device and CAN controller |
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Also Published As
Publication number | Publication date |
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US20100017490A1 (en) | 2010-01-21 |
US7979594B2 (en) | 2011-07-12 |
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