US20040106287A1 - Method for making a semiconductor device having a high-k gate dielectric - Google Patents
Method for making a semiconductor device having a high-k gate dielectric Download PDFInfo
- Publication number
- US20040106287A1 US20040106287A1 US10/618,226 US61822603A US2004106287A1 US 20040106287 A1 US20040106287 A1 US 20040106287A1 US 61822603 A US61822603 A US 61822603A US 2004106287 A1 US2004106287 A1 US 2004106287A1
- Authority
- US
- United States
- Prior art keywords
- layer
- dielectric layer
- gate dielectric
- oxide
- titanium nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 claims description 2
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 claims description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- -1 e.g. Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910001510 metal chloride Inorganic materials 0.000 description 1
- 239000012702 metal oxide precursor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/906—Cleaning of wafer as interim step
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/974—Substrate surface preparation
Definitions
- the present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include high-k gate dielectric layers.
- MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, in place of silicon dioxide, can reduce gate leakage. Such a dielectric may not, however, be compatible with polysilicon—the preferred material for making the device's gate electrode. Placing a thin layer of titanium nitride, which is compatible with many high-k gate dielectrics, between a high-k gate dielectric and a polysilicon-based gate electrode may enable such a dielectric to be used with such a gate electrode. Unfortunately, the presence of such a layer may increase the transistor's threshold voltage, which is undesirable.
- FIGS. 1 a - 1 d represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
- a method for making a semiconductor device comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. That dielectric layer is modified so that it will be compatible with a gate electrode to be formed on it. A gate electrode is then formed on the dielectric layer.
- dielectric layer 101 is formed on substrate 100 .
- Substrate 100 may include isolation regions, p-type wells and n-type wells that have been formed in a bulk silicon or silicon-on-insulator substructure.
- Substrate 100 may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
- germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
- Dielectric layer 101 comprises a material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide.
- Dielectric layer 101 preferably has a dielectric constant that is at least about twice that of silicon dioxide, i.e., a dielectric constant that is greater than about 8.
- dielectric layer 101 When serving as the gate dielectric for the semiconductor device, dielectric layer 101 is a “high-k gate dielectric.”
- Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide.
- that layer may be made from other materials that serve to reduce gate leakage from the level present in devices that include silicon dioxide gate dielectrics.
- Dielectric layer 101 may be formed on substrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process.
- a conventional atomic layer CVD process is used.
- a metal oxide precursor e.g., a metal chloride
- steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate 100 and dielectric layer 101 .
- the CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications, dielectric layer 101 should be less than about 100 angstroms thick, and more preferably between about 20 angstroms and about 60 angstroms thick.
- dielectric layer 101 will include undesirable impurities, e.g., hydrogen and/or unreacted metal (represented by dots in FIG. 1 a ), which render that layer incompatible with polysilicon.
- dielectric layer 101 is modified so that it will be compatible with a gate electrode to be formed on it.
- FIGS. 1 a - 1 c illustrate steps that may be applied to modify dielectric layer 101 .
- sacrificial layer 102 is formed on dielectric layer 101 to generate the structure represented by FIG. 1 a .
- Sacrificial layer 102 preferably is made from a material that may getter impurities from dielectric layer 101 .
- An example of a suitable material is titanium nitride.
- Such a titanium nitride layer may be formed on dielectric layer 101 using a conventional CVD or PVD process. In a preferred embodiment, such a process is used to form a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick.
- sacrificial layer 102 is formed on dielectric layer 101 , undesirable impurities are transported from dielectric layer 101 to sacrificial layer 102 .
- impurities may be transported from high-k gate dielectric layer 101 to titanium nitride layer 102 by annealing titanium nitride layer 102 .
- Titanium nitride layer 102 may be annealed using a rapid thermal anneal process or by heating that layer in a furnace at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes.
- FIG. 1 b represents a structure in which undesirable impurities, e.g., hydrogen and unreacted metal (represented by dots in FIG. 1 b ), have been transferred from high-k dielectric layer 101 into titanium nitride layer 102 .
- FIG. 1 b is not meant to suggest that annealing titanium nitride layer 102 will cause all undesirable impurities, initially present in high-k dielectric layer 101 , to be moved into layer 102 . Rather, the annealing step is performed to cause a sufficient number of those impurities to move from high-k dielectric layer 101 into titanium nitride layer 102 to modify high-k dielectric layer 101 such that it will be compatible with a gate electrode to be formed on that layer.
- a method that applies an annealing step which does not remove all—or even substantially all—of the undesirable impurities from high-k dielectric layer 101 , may still fall within the spirit and scope of the present invention.
- sacrificial layer 102 is removed.
- sacrificial layer 102 is made from titanium nitride and dielectric layer 101 comprises a high-k gate dielectric layer
- titanium nitride layer 102 may be removed from high-k gate dielectric layer 101 using a conventional wet etch process, which uses a chemistry that is selective for titanium nitride over the material used to form the high-k gate dielectric layer.
- a gate electrode may be formed on dielectric layer 101 .
- the gate electrode may be formed by initially depositing polysilicon layer 103 on high-k gate dielectric layer 101 —generating the FIG. 1 c structure.
- Polysilicon layer 103 may be deposited using conventional methods and preferably is between about 2,000 angstroms and about 4,000 angstroms thick.
- additional steps that are generally used to complete the gate electrode e.g., forming a silicide (not shown) on the upper part of etched polysilicon structure 104 ) may be applied. As such steps are well known to those skilled in the art, they will not be described in more detail here.
- a sacrificial titanium nitride layer may enable a high-k gate dielectric to be used with a polysilicon-based gate electrode.
- a titanium nitride layer may be formed on a high-k gate dielectric layer, annealing and then removing that layer to remove undesirable impurities from the high-k gate dielectric, the embodiment described above enables the resulting device to benefit from the temporary presence of the titanium nitride layer without experiencing the work function shifts that permanent placement of that layer between the high-k gate dielectric and the gate electrode may cause.
- the present invention is not limited to this particular embodiment, but instead contemplates other processes for modifying dielectric layers to ensure compatibility with gate electrodes.
Abstract
A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
Description
- The present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include high-k gate dielectric layers.
- MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, in place of silicon dioxide, can reduce gate leakage. Such a dielectric may not, however, be compatible with polysilicon—the preferred material for making the device's gate electrode. Placing a thin layer of titanium nitride, which is compatible with many high-k gate dielectrics, between a high-k gate dielectric and a polysilicon-based gate electrode may enable such a dielectric to be used with such a gate electrode. Unfortunately, the presence of such a layer may increase the transistor's threshold voltage, which is undesirable.
- Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric. There is a need for such a process in which a polysilicon-based gate electrode is formed on such a gate dielectric to create a functional device—without causing undesirable work function shifts. The method of the present invention provides such a process.
- FIGS. 1a-1 d represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
- A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. That dielectric layer is modified so that it will be compatible with a gate electrode to be formed on it. A gate electrode is then formed on the dielectric layer. In the following description, a number of details are set forth to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art, however, that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below.
- In an embodiment of the method of the present invention, as illustrated by FIGS. 1a-1 d,
dielectric layer 101 is formed onsubstrate 100.Substrate 100 may include isolation regions, p-type wells and n-type wells that have been formed in a bulk silicon or silicon-on-insulator substructure.Substrate 100 may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although several examples of materials from whichsubstrate 100 may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention. -
Dielectric layer 101 comprises a material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide.Dielectric layer 101 preferably has a dielectric constant that is at least about twice that of silicon dioxide, i.e., a dielectric constant that is greater than about 8. When serving as the gate dielectric for the semiconductor device,dielectric layer 101 is a “high-k gate dielectric.” Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide. Although a few examples of materials that may be used to formdielectric layer 101 are described here, that layer may be made from other materials that serve to reduce gate leakage from the level present in devices that include silicon dioxide gate dielectrics. -
Dielectric layer 101 may be formed onsubstrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process. Preferably, a conventional atomic layer CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface betweensubstrate 100 anddielectric layer 101. The CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications,dielectric layer 101 should be less than about 100 angstroms thick, and more preferably between about 20 angstroms and about 60 angstroms thick. - As deposited,
dielectric layer 101 will include undesirable impurities, e.g., hydrogen and/or unreacted metal (represented by dots in FIG. 1a), which render that layer incompatible with polysilicon. In the method of the present invention,dielectric layer 101 is modified so that it will be compatible with a gate electrode to be formed on it. FIGS. 1a-1 c illustrate steps that may be applied to modifydielectric layer 101. First,sacrificial layer 102 is formed ondielectric layer 101 to generate the structure represented by FIG. 1a.Sacrificial layer 102 preferably is made from a material that may getter impurities fromdielectric layer 101. An example of a suitable material is titanium nitride. Such a titanium nitride layer may be formed ondielectric layer 101 using a conventional CVD or PVD process. In a preferred embodiment, such a process is used to form a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick. - After
sacrificial layer 102 is formed ondielectric layer 101, undesirable impurities are transported fromdielectric layer 101 tosacrificial layer 102. Whensacrificial layer 102 is made from titanium nitride anddielectric layer 101 comprises a high-k gate dielectric layer, impurities may be transported from high-k gatedielectric layer 101 totitanium nitride layer 102 by annealingtitanium nitride layer 102.Titanium nitride layer 102 may be annealed using a rapid thermal anneal process or by heating that layer in a furnace at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes. - FIG. 1b represents a structure in which undesirable impurities, e.g., hydrogen and unreacted metal (represented by dots in FIG. 1b), have been transferred from high-k
dielectric layer 101 intotitanium nitride layer 102. FIG. 1b is not meant to suggest that annealingtitanium nitride layer 102 will cause all undesirable impurities, initially present in high-kdielectric layer 101, to be moved intolayer 102. Rather, the annealing step is performed to cause a sufficient number of those impurities to move from high-kdielectric layer 101 intotitanium nitride layer 102 to modify high-kdielectric layer 101 such that it will be compatible with a gate electrode to be formed on that layer. Thus, a method that applies an annealing step, which does not remove all—or even substantially all—of the undesirable impurities from high-kdielectric layer 101, may still fall within the spirit and scope of the present invention. - After the undesirable impurities have been transported from
dielectric layer 101 tosacrificial layer 102, e.g., by annealing the sacrificial layer,sacrificial layer 102 is removed. Whensacrificial layer 102 is made from titanium nitride anddielectric layer 101 comprises a high-k gate dielectric layer,titanium nitride layer 102 may be removed from high-k gatedielectric layer 101 using a conventional wet etch process, which uses a chemistry that is selective for titanium nitride over the material used to form the high-k gate dielectric layer. - Following the removal of
sacrificial layer 102, a gate electrode may be formed ondielectric layer 101. In a preferred embodiment, the gate electrode may be formed by initially depositingpolysilicon layer 103 on high-k gatedielectric layer 101—generating the FIG. 1c structure.Polysilicon layer 103 may be deposited using conventional methods and preferably is between about 2,000 angstroms and about 4,000 angstroms thick. After etching bothlayers - As described above, a sacrificial titanium nitride layer may enable a high-k gate dielectric to be used with a polysilicon-based gate electrode. By forming a titanium nitride layer on a high-k gate dielectric layer, annealing and then removing that layer to remove undesirable impurities from the high-k gate dielectric, the embodiment described above enables the resulting device to benefit from the temporary presence of the titanium nitride layer without experiencing the work function shifts that permanent placement of that layer between the high-k gate dielectric and the gate electrode may cause. Although the embodiment described above is an example of a process for modifying a dielectric layer to enable it to be compatible with a gate electrode, the present invention is not limited to this particular embodiment, but instead contemplates other processes for modifying dielectric layers to ensure compatibility with gate electrodes.
- Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims.
Claims (20)
1. A method for making a semiconductor device comprising:
forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide;
modifying the dielectric layer so that it will be compatible with a gate electrode to be formed on the dielectric layer; and then
forming a gate electrode on the dielectric layer.
2. The method of claim 1 wherein the dielectric layer is modified by:
forming a sacrificial layer on the dielectric layer;
transporting impurities from the dielectric layer to the sacrificial layer; then
removing the sacrificial layer.
3. The method of claim 2 wherein the dielectric layer is a high-k gate dielectric layer that has a dielectric constant that is greater than about 8.
4. The method of claim 3 wherein the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition, and wherein the high-k gate dielectric layer comprises a material selected from the group consisting of hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
5. The method of claim 4 wherein the sacrificial layer comprises a titanium nitride layer.
6. The method of claim 5 wherein the titanium nitride layer is annealed to cause the impurities to be transported from the dielectric layer to the titanium nitride layer.
7. The method of claim 6 wherein the gate electrode comprises polysilicon.
8. A method for making a semiconductor device comprising:
forming a high-k gate dielectric layer on a substrate, the high-k gate dielectric layer including impurities;
forming a sacrificial layer on the high-k gate dielectric layer;
transporting the impurities from the high-k gate dielectric layer to the sacrificial layer; then removing the sacrificial layer; and
forming a layer that comprises polysilicon on the high-k gate dielectric layer.
9. The method of claim 8 wherein the sacrificial layer comprises a titanium nitride layer, and wherein the impurities are transported from the high-k gate dielectric layer to the titanium nitride layer by annealing the titanium nitride layer to getter the impurities from the high-k gate dielectric layer.
10. The method of claim 9 wherein the substrate comprises silicon.
11. The method of claim 10 wherein the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition, and is between about 20 angstroms and about 60 angstroms thick.
12. The method of claim 11 wherein the high-k gate dielectric layer comprises a material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide.
13. The method of claim 12 wherein the titanium nitride layer is between about 10 angstroms and about 50 angstroms thick.
14. The method of claim 13 wherein the titanium nitride layer is annealed by heating that layer at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes.
15. The method of claim 14 wherein the titanium nitride layer is removed using a wet etch process that is selective for titanium nitride over the material used to make the high-k dielectric layer.
16. The method of claim 15 wherein the layer that comprises polysilicon is between about 2,000 angstroms and about 4,000 angstroms thick.
17. A method for making a semiconductor device comprising:
forming a high-k gate dielectric layer on a substrate, the high-k gate dielectric layer being less than about 100 angstroms thick and comprising a material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide;
forming a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick on the high-k gate dielectric layer;
annealing the titanium nitride layer at a temperature of between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes; then removing the titanium nitride layer;
forming a layer that comprises polysilicon on the high-k gate dielectric layer; and
etching the polysilicon containing layer and the high-k gate dielectric layer.
18. The method of claim 17 wherein the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition and is between about 20 angstroms and about 60 angstroms thick.
19. The method of claim 18 wherein the titanium nitride layer is removed using a wet etch process that is selective for titanium nitride over the material used to make the high-k dielectric layer.
20. The method of claim 19 wherein the layer that comprises polysilicon is between about 2,000 angstroms and about 4,000 angstroms thick.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/618,226 US20040106287A1 (en) | 2002-02-22 | 2003-07-11 | Method for making a semiconductor device having a high-k gate dielectric |
US10/943,661 US7166505B2 (en) | 2002-02-22 | 2004-09-16 | Method for making a semiconductor device having a high-k gate dielectric |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/082,530 US6617209B1 (en) | 2002-02-22 | 2002-02-22 | Method for making a semiconductor device having a high-k gate dielectric |
US10/618,226 US20040106287A1 (en) | 2002-02-22 | 2003-07-11 | Method for making a semiconductor device having a high-k gate dielectric |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/082,530 Continuation US6617209B1 (en) | 2002-02-22 | 2002-02-22 | Method for making a semiconductor device having a high-k gate dielectric |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/943,661 Division US7166505B2 (en) | 2002-02-22 | 2004-09-16 | Method for making a semiconductor device having a high-k gate dielectric |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040106287A1 true US20040106287A1 (en) | 2004-06-03 |
Family
ID=27753118
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/082,530 Expired - Fee Related US6617209B1 (en) | 2002-02-22 | 2002-02-22 | Method for making a semiconductor device having a high-k gate dielectric |
US10/618,226 Abandoned US20040106287A1 (en) | 2002-02-22 | 2003-07-11 | Method for making a semiconductor device having a high-k gate dielectric |
US10/943,661 Expired - Fee Related US7166505B2 (en) | 2002-02-22 | 2004-09-16 | Method for making a semiconductor device having a high-k gate dielectric |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/082,530 Expired - Fee Related US6617209B1 (en) | 2002-02-22 | 2002-02-22 | Method for making a semiconductor device having a high-k gate dielectric |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/943,661 Expired - Fee Related US7166505B2 (en) | 2002-02-22 | 2004-09-16 | Method for making a semiconductor device having a high-k gate dielectric |
Country Status (1)
Country | Link |
---|---|
US (3) | US6617209B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060017112A1 (en) * | 2004-07-21 | 2006-01-26 | Chih-Hao Wang | Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof |
US7235847B2 (en) | 2004-09-17 | 2007-06-26 | Freescale Semiconductor, Inc. | Semiconductor device having a gate with a thin conductive layer |
US20070176227A1 (en) * | 2006-01-30 | 2007-08-02 | Chun-Li Liu | MOS device with nano-crystal gate structure |
US20070187725A1 (en) * | 2004-12-23 | 2007-08-16 | Chih-Hao Wang | Method and apparatus for a semiconductor device with a high-k gate dielectric |
US8581352B2 (en) | 2006-08-25 | 2013-11-12 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
Families Citing this family (64)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6617209B1 (en) * | 2002-02-22 | 2003-09-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
JP4089469B2 (en) * | 2002-03-14 | 2008-05-28 | セイコーエプソン株式会社 | Motor drive device and recording device |
JP2003282873A (en) * | 2002-03-22 | 2003-10-03 | Sony Corp | Semiconductor device and its fabricating method |
US7339187B2 (en) * | 2002-05-21 | 2008-03-04 | State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University | Transistor structures |
US7189992B2 (en) * | 2002-05-21 | 2007-03-13 | State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University | Transistor structures having a transparent channel |
US7115479B2 (en) * | 2002-11-26 | 2006-10-03 | Intel Corporation | Sacrificial annealing layer for a semiconductor device and a method of fabrication |
US6787440B2 (en) * | 2002-12-10 | 2004-09-07 | Intel Corporation | Method for making a semiconductor device having an ultra-thin high-k gate dielectric |
US7196013B2 (en) * | 2002-12-12 | 2007-03-27 | Intel Corporation | Capping layer for a semiconductor device and a method of fabrication |
US6709911B1 (en) * | 2003-01-07 | 2004-03-23 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
JP2004241612A (en) * | 2003-02-06 | 2004-08-26 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
US6716707B1 (en) * | 2003-03-11 | 2004-04-06 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US6890807B2 (en) * | 2003-05-06 | 2005-05-10 | Intel Corporation | Method for making a semiconductor device having a metal gate electrode |
US6806146B1 (en) * | 2003-05-20 | 2004-10-19 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US7037845B2 (en) * | 2003-08-28 | 2006-05-02 | Intel Corporation | Selective etch process for making a semiconductor device having a high-k gate dielectric |
US6939815B2 (en) * | 2003-08-28 | 2005-09-06 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US7129182B2 (en) * | 2003-11-06 | 2006-10-31 | Intel Corporation | Method for etching a thin metal layer |
US6974764B2 (en) * | 2003-11-06 | 2005-12-13 | Intel Corporation | Method for making a semiconductor device having a metal gate electrode |
KR100568256B1 (en) * | 2003-12-11 | 2006-04-07 | 삼성전자주식회사 | Method for cleaning fabrication apparatus of semiconductor device |
US7160767B2 (en) * | 2003-12-18 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US7220635B2 (en) * | 2003-12-19 | 2007-05-22 | Intel Corporation | Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer |
US7153734B2 (en) | 2003-12-29 | 2006-12-26 | Intel Corporation | CMOS device with metal and silicide gate electrodes and a method for making it |
US7183184B2 (en) * | 2003-12-29 | 2007-02-27 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US6893927B1 (en) | 2004-03-22 | 2005-05-17 | Intel Corporation | Method for making a semiconductor device with a metal gate electrode |
US7208361B2 (en) * | 2004-03-24 | 2007-04-24 | Intel Corporation | Replacement gate process for making a semiconductor device that includes a metal gate electrode |
US7153784B2 (en) * | 2004-04-20 | 2006-12-26 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US20050250258A1 (en) * | 2004-05-04 | 2005-11-10 | Metz Matthew V | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US8119210B2 (en) | 2004-05-21 | 2012-02-21 | Applied Materials, Inc. | Formation of a silicon oxynitride layer on a high-k dielectric material |
US7045428B2 (en) * | 2004-05-26 | 2006-05-16 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction |
US20050272191A1 (en) * | 2004-06-03 | 2005-12-08 | Uday Shah | Replacement gate process for making a semiconductor device that includes a metal gate electrode |
US6887800B1 (en) | 2004-06-04 | 2005-05-03 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction |
US7425490B2 (en) * | 2004-06-24 | 2008-09-16 | Intel Corporation | Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics |
US7157378B2 (en) * | 2004-07-06 | 2007-01-02 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US7148548B2 (en) * | 2004-07-20 | 2006-12-12 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
US7074680B2 (en) * | 2004-09-07 | 2006-07-11 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US7176090B2 (en) * | 2004-09-07 | 2007-02-13 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US7390709B2 (en) | 2004-09-08 | 2008-06-24 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US7507629B2 (en) * | 2004-09-10 | 2009-03-24 | Gerald Lucovsky | Semiconductor devices having an interfacial dielectric layer and related methods |
US7384880B2 (en) * | 2004-10-12 | 2008-06-10 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US20060094180A1 (en) * | 2004-11-02 | 2006-05-04 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode |
US20060091483A1 (en) * | 2004-11-02 | 2006-05-04 | Doczy Mark L | Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode |
US20060121742A1 (en) * | 2004-12-07 | 2006-06-08 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US7064066B1 (en) * | 2004-12-07 | 2006-06-20 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode |
US7381608B2 (en) * | 2004-12-07 | 2008-06-03 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode |
US7160779B2 (en) * | 2005-02-23 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US20060220090A1 (en) * | 2005-03-23 | 2006-10-05 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
JP2008536312A (en) * | 2005-04-08 | 2008-09-04 | サッチェム, インコーポレイテッド | Selective wet etching of metal nitride |
US7449756B2 (en) * | 2005-06-13 | 2008-11-11 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
US7501336B2 (en) * | 2005-06-21 | 2009-03-10 | Intel Corporation | Metal gate device with reduced oxidation of a high-k gate dielectric |
JP4598639B2 (en) * | 2005-09-27 | 2010-12-15 | Okiセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
US7226831B1 (en) | 2005-12-27 | 2007-06-05 | Intel Corporation | Device with scavenging spacer layer |
US7645710B2 (en) | 2006-03-09 | 2010-01-12 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
US7678710B2 (en) | 2006-03-09 | 2010-03-16 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
US7837838B2 (en) | 2006-03-09 | 2010-11-23 | Applied Materials, Inc. | Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus |
US20070262399A1 (en) * | 2006-05-10 | 2007-11-15 | Gilbert Dewey | Sealing spacer to reduce or eliminate lateral oxidation of a high-k gate dielectric |
WO2008039845A2 (en) | 2006-09-26 | 2008-04-03 | Applied Materials, Inc. | Fluorine plasma treatment of high-k gate stack for defect passivation |
US8030163B2 (en) * | 2007-12-26 | 2011-10-04 | Intel Corporation | Reducing external resistance of a multi-gate device using spacer processing techniques |
US7763943B2 (en) * | 2007-12-26 | 2010-07-27 | Intel Corporation | Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin |
US20090206404A1 (en) * | 2008-02-15 | 2009-08-20 | Ravi Pillarisetty | Reducing external resistance of a multi-gate device by silicidation |
US9048186B2 (en) * | 2009-10-08 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming integrated circuits |
JP5757628B2 (en) * | 2009-12-01 | 2015-07-29 | 国立研究開発法人物質・材料研究機構 | Interface layer reduction method, high dielectric constant gate insulating film forming method, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film |
US8574990B2 (en) | 2011-02-24 | 2013-11-05 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gate |
US8802524B2 (en) | 2011-03-22 | 2014-08-12 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gates |
US9716160B2 (en) | 2014-08-01 | 2017-07-25 | International Business Machines Corporation | Extended contact area using undercut silicide extensions |
CN113287187A (en) | 2019-01-11 | 2021-08-20 | 弗萨姆材料美国有限责任公司 | Hafnium oxide corrosion inhibitors |
Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6020024A (en) * | 1997-08-04 | 2000-02-01 | Motorola, Inc. | Method for forming high dielectric constant metal oxides |
US6121094A (en) * | 1998-07-21 | 2000-09-19 | Advanced Micro Devices, Inc. | Method of making a semiconductor device with a multi-level gate structure |
US6184072B1 (en) * | 2000-05-17 | 2001-02-06 | Motorola, Inc. | Process for forming a high-K gate dielectric |
US6234594B1 (en) * | 1997-02-20 | 2001-05-22 | Unilever Patent Holdings Bv | Housing for freezer cabinets, and housing system |
US6297539B1 (en) * | 1999-07-19 | 2001-10-02 | Sharp Laboratories Of America, Inc. | Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same |
US6365450B1 (en) * | 2001-03-15 | 2002-04-02 | Advanced Micro Devices, Inc. | Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate |
US6365467B1 (en) * | 1998-12-30 | 2002-04-02 | Hyundai Electronics Industries Co., Ltd. | Method of forming gate oxide layer in semiconductor device |
US6406945B1 (en) * | 2001-01-26 | 2002-06-18 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a transistor gate dielectric with high-K and low-K regions |
US6420279B1 (en) * | 2001-06-28 | 2002-07-16 | Sharp Laboratories Of America, Inc. | Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate |
US6436777B1 (en) * | 2000-10-19 | 2002-08-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US20020120797A1 (en) * | 2001-02-28 | 2002-08-29 | Fabre B. Scott | Adaptive run-time data transfer optimization |
US20020137317A1 (en) * | 2001-03-20 | 2002-09-26 | Kaushik Vidya S. | High K dielectric film and method for making |
US20020197790A1 (en) * | 1997-12-22 | 2002-12-26 | Kizilyalli Isik C. | Method of making a compound, high-K, gate and capacitor insulator layer |
US6514828B2 (en) * | 2001-04-20 | 2003-02-04 | Micron Technology, Inc. | Method of fabricating a highly reliable gate oxide |
US20030032303A1 (en) * | 2001-08-13 | 2003-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ozone-enhanced oxidation for high-k dielectric semiconductor devices |
US20030045080A1 (en) * | 2001-08-31 | 2003-03-06 | Visokay Mark R. | Gate structure and method |
US6544906B2 (en) * | 2000-12-21 | 2003-04-08 | Texas Instruments Incorporated | Annealing of high-k dielectric materials |
US6617210B1 (en) * | 2002-05-31 | 2003-09-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US6617209B1 (en) * | 2002-02-22 | 2003-09-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US6806146B1 (en) * | 2003-05-20 | 2004-10-19 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU5669794A (en) | 1992-12-11 | 1994-07-04 | Intel Corporation | A mos transistor having a composite gate electrode and method of fabrication |
JPH07179622A (en) * | 1993-12-22 | 1995-07-18 | Tipton Mfg Corp | Barrel-polishing stone containing compound and its production |
US5753560A (en) * | 1996-10-31 | 1998-05-19 | Motorola, Inc. | Method for fabricating a semiconductor device using lateral gettering |
US5891798A (en) | 1996-12-20 | 1999-04-06 | Intel Corporation | Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit |
US6063698A (en) * | 1997-06-30 | 2000-05-16 | Motorola, Inc. | Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits |
US6087261A (en) * | 1997-09-30 | 2000-07-11 | Fujitsu Limited | Method for production of semiconductor device |
CN1247777C (en) * | 1997-12-16 | 2006-03-29 | 诺沃奇梅兹有限公司 | Polypeptides having aminopepyidase activity and nucleic acids encoding same |
US6235594B1 (en) * | 1999-01-13 | 2001-05-22 | Agere Systems Guardian Corp. | Methods of fabricating an integrated circuit device with composite oxide dielectric |
FR2797999B1 (en) * | 1999-08-31 | 2003-08-08 | St Microelectronics Sa | METHOD FOR MANUFACTURING AN INTEGRATED CAPACITY ON A SILICON SUBSTRATE |
SE515806C2 (en) * | 2000-01-19 | 2001-10-08 | Avesta Polarit Ab Publ | Long-term stable urea containing urea as well as ways of making it |
US6407435B1 (en) | 2000-02-11 | 2002-06-18 | Sharp Laboratories Of America, Inc. | Multilayer dielectric stack and method |
JP2002198441A (en) * | 2000-11-16 | 2002-07-12 | Hynix Semiconductor Inc | Method for forming dual metal gate of semiconductor element |
US6475874B2 (en) * | 2000-12-07 | 2002-11-05 | Advanced Micro Devices, Inc. | Damascene NiSi metal gate high-k transistor |
US20020102797A1 (en) * | 2001-02-01 | 2002-08-01 | Muller David A. | Composite gate dielectric layer |
US6410376B1 (en) * | 2001-03-02 | 2002-06-25 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration |
US6642131B2 (en) * | 2001-06-21 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film |
US6667246B2 (en) * | 2001-12-04 | 2003-12-23 | Matsushita Electric Industrial Co., Ltd. | Wet-etching method and method for manufacturing semiconductor device |
-
2002
- 2002-02-22 US US10/082,530 patent/US6617209B1/en not_active Expired - Fee Related
-
2003
- 2003-07-11 US US10/618,226 patent/US20040106287A1/en not_active Abandoned
-
2004
- 2004-09-16 US US10/943,661 patent/US7166505B2/en not_active Expired - Fee Related
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6234594B1 (en) * | 1997-02-20 | 2001-05-22 | Unilever Patent Holdings Bv | Housing for freezer cabinets, and housing system |
US6020024A (en) * | 1997-08-04 | 2000-02-01 | Motorola, Inc. | Method for forming high dielectric constant metal oxides |
US20020197790A1 (en) * | 1997-12-22 | 2002-12-26 | Kizilyalli Isik C. | Method of making a compound, high-K, gate and capacitor insulator layer |
US6121094A (en) * | 1998-07-21 | 2000-09-19 | Advanced Micro Devices, Inc. | Method of making a semiconductor device with a multi-level gate structure |
US6365467B1 (en) * | 1998-12-30 | 2002-04-02 | Hyundai Electronics Industries Co., Ltd. | Method of forming gate oxide layer in semiconductor device |
US6297539B1 (en) * | 1999-07-19 | 2001-10-02 | Sharp Laboratories Of America, Inc. | Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same |
US6184072B1 (en) * | 2000-05-17 | 2001-02-06 | Motorola, Inc. | Process for forming a high-K gate dielectric |
US6436777B1 (en) * | 2000-10-19 | 2002-08-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US6544906B2 (en) * | 2000-12-21 | 2003-04-08 | Texas Instruments Incorporated | Annealing of high-k dielectric materials |
US6406945B1 (en) * | 2001-01-26 | 2002-06-18 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a transistor gate dielectric with high-K and low-K regions |
US20020120797A1 (en) * | 2001-02-28 | 2002-08-29 | Fabre B. Scott | Adaptive run-time data transfer optimization |
US6365450B1 (en) * | 2001-03-15 | 2002-04-02 | Advanced Micro Devices, Inc. | Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate |
US20020137317A1 (en) * | 2001-03-20 | 2002-09-26 | Kaushik Vidya S. | High K dielectric film and method for making |
US6514828B2 (en) * | 2001-04-20 | 2003-02-04 | Micron Technology, Inc. | Method of fabricating a highly reliable gate oxide |
US6420279B1 (en) * | 2001-06-28 | 2002-07-16 | Sharp Laboratories Of America, Inc. | Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate |
US20030032303A1 (en) * | 2001-08-13 | 2003-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ozone-enhanced oxidation for high-k dielectric semiconductor devices |
US20030045080A1 (en) * | 2001-08-31 | 2003-03-06 | Visokay Mark R. | Gate structure and method |
US6617209B1 (en) * | 2002-02-22 | 2003-09-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US6617210B1 (en) * | 2002-05-31 | 2003-09-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US6806146B1 (en) * | 2003-05-20 | 2004-10-19 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060017112A1 (en) * | 2004-07-21 | 2006-01-26 | Chih-Hao Wang | Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof |
US7279756B2 (en) | 2004-07-21 | 2007-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof |
US7235847B2 (en) | 2004-09-17 | 2007-06-26 | Freescale Semiconductor, Inc. | Semiconductor device having a gate with a thin conductive layer |
US20070218640A1 (en) * | 2004-09-17 | 2007-09-20 | Freescale Semiconductor, Inc. | Semiconductor device having a gate with a thin conductive layer |
US20070187725A1 (en) * | 2004-12-23 | 2007-08-16 | Chih-Hao Wang | Method and apparatus for a semiconductor device with a high-k gate dielectric |
US7332407B2 (en) | 2004-12-23 | 2008-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for a semiconductor device with a high-k gate dielectric |
US20070176227A1 (en) * | 2006-01-30 | 2007-08-02 | Chun-Li Liu | MOS device with nano-crystal gate structure |
US7700438B2 (en) | 2006-01-30 | 2010-04-20 | Freescale Semiconductor, Inc. | MOS device with nano-crystal gate structure |
US20100155825A1 (en) * | 2006-01-30 | 2010-06-24 | Freescale Semiconductor, Inc. | Transistor devices with nano-crystal gate structures |
US7928502B2 (en) | 2006-01-30 | 2011-04-19 | Freescale Semiconductor, Inc. | Transistor devices with nano-crystal gate structures |
US8581352B2 (en) | 2006-08-25 | 2013-11-12 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
US9202686B2 (en) | 2006-08-25 | 2015-12-01 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
Also Published As
Publication number | Publication date |
---|---|
US20030162377A1 (en) | 2003-08-28 |
US20050032318A1 (en) | 2005-02-10 |
US7166505B2 (en) | 2007-01-23 |
US6617209B1 (en) | 2003-09-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6617209B1 (en) | Method for making a semiconductor device having a high-k gate dielectric | |
US6617210B1 (en) | Method for making a semiconductor device having a high-k gate dielectric | |
US6709911B1 (en) | Method for making a semiconductor device having a high-k gate dielectric | |
US11031482B2 (en) | Gate electrode having a capping layer | |
US7442983B2 (en) | Method for making a semiconductor device having a high-k gate dielectric | |
US6713358B1 (en) | Method for making a semiconductor device having a high-k gate dielectric | |
EP1668706B1 (en) | Method for metal replacement gate of high performance device | |
US20080076216A1 (en) | Method to fabricate high-k/metal gate transistors using a double capping layer process | |
US20100052079A1 (en) | Semiconductor devices and fabrication process thereof | |
US20050272270A1 (en) | Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction | |
TW200843110A (en) | Semiconductor device manufacturing method and semiconductor device | |
KR20070050494A (en) | A method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode | |
JP5127694B2 (en) | Semiconductor device and manufacturing method thereof | |
US6867102B2 (en) | Method for making a semiconductor device having a high-k gate dielectric | |
US7820538B2 (en) | Method of fabricating a MOS device with non-SiO2 gate dielectric | |
US20050250258A1 (en) | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode | |
JP3646718B2 (en) | Manufacturing method of semiconductor device | |
US7425490B2 (en) | Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics | |
US7071038B2 (en) | Method of forming a semiconductor device having a dielectric layer with high dielectric constant | |
US20050287746A1 (en) | Facilitating removal of sacrificial layers to form replacement metal gates | |
JP2006245306A (en) | Method of manufacturing semiconductor device | |
US20230377879A1 (en) | Barrier layer for preventing aluminum diffusion | |
KR20040107427A (en) | Semiconductor device and manufacturing method thereof | |
US20040135218A1 (en) | MOS transistor with high k gate dielectric |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |