US20030234670A1 - Frequency doubling two-phase clock generation circuit - Google Patents
Frequency doubling two-phase clock generation circuit Download PDFInfo
- Publication number
- US20030234670A1 US20030234670A1 US10/177,323 US17732302A US2003234670A1 US 20030234670 A1 US20030234670 A1 US 20030234670A1 US 17732302 A US17732302 A US 17732302A US 2003234670 A1 US2003234670 A1 US 2003234670A1
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- clock
- latch
- generation circuit
- transition
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
Definitions
- This invention relates to chip clock distribution, generation and repowering circuits.
- IBM is a registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A.. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
- Microprocessor frequencies are scaling with CMOS device speed and are outpacing the capabilities of global chip clock distribution.
- the problem is two fold.
- First, the number of circuits per chip is growing roughly as the square of the lithography improvement and thus the clock needs to be distributed to more circuits.
- the thickest wiring layers which are generally used to route the global clocks behave as a low pass filter with a cutoff frequency which does not improve with device speed. Previously this cutoff frequency limit has been extended through the use of very wide wires. It would be advantageous to extend the global clock distribution frequency limit without reducing the number of wiring tracks available to I/O and signals. It would also be advantageous to reduce the power associated with generating and globally distributing the clock.
- the invention provides a frequency doubling two-phase clock generation circuit which avoids the above described frequency limitation.
- our clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit.
- the preferred circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks.
- a rising edge detection circuit generates a pulse in response to a rising edge of the global clock.
- a falling edge detection circuit generates a pulse in response to a falling edge of the global clock.
- a master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse.
- a delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch.
- the master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.
- FIG. 1 illustrates a prior art clock block and master/slave latch.
- FIG. 2 illustrates the prior art clock circuit input and output waveforms.
- FIG. 3 illustrates the frequency doubling clock circuit in accordance with our preferred embodiment.
- FIG. 4 illustrates the delay/shaping sub-circuit.
- FIG. 5 illustrates the invention clock circuit input and output waveforms.
- the prior-art clock block simply distributes and repowers a global clock to master and slave latches.
- the global clock 10 is repowered by inverters 11 , 12 and 13 to create a local c1 clock 14 which is inverted with respect to the global clock 10 .
- Global clock 10 is also repowered by inverters 15 and 16 to create a local c2 clock 17 which is not inverted with respect to the global clock 10 .
- the local c1 clock 14 is driven through local wires to the local master latches 18 .
- the local c2 clock 17 is driven through local wires to the local slave latches 19 .
- the prior-art clock block outputs two local clocks.
- the local c1 clock 14 and local c2 clock 17 have different phases than the global clock 10 ; but these output clocks have the same period (and frequency) as the global clock 10 .
- the preferred embodiment of the invention provides a clock generation circuit having a frequency-doubling clock block which receives a global clock and doubles its frequency to generate two out-of-phase local clocks.
- the edge detect subcircuit 30 monitors the global clock 10 .
- the edge detect subcircuit 30 consists of a delay circuit 31 which outputs global clock delay in-phase signal 32 and out-of-phase signal 33 , an inverter 34 which generates an inverted clock signal 35 , a NAND gate 36 which generates a falling edge detection signal 40 and a NAND gate 37 which generates a rising edge detection signal 41 .
- the operation of this edge detect subcircuit 30 is as follows.
- the global clock 10 is low such that the clock delay in-phase signal 32 is low, the clock delay out-of-phase signal 33 is high, the inverted clock signal 35 is high, the falling edge detection signal 40 is high (inactive) and the rising edge detection signal 41 is high (inactive.)
- a rising transition on the global clock 10 sets both inputs into NAND gate 37 high and causes the rising edge detection signal 41 to drop low (activate.)
- the clock delay out-of-phase signal 33 will drop low which causes the rising edge detection signal 41 to return to high (inactivate).
- the rising edge detection signal 41 pulses low in response to a rising transition on global clock 10 .
- the clock delay in-phase signal 32 will switch high, and the inverted clock signal 35 will switch low. Now a falling transition on the global clock 10 sets both inputs into NAND gate 36 high and causes the falling edge detection signal 40 to drop low (activate.) A fixed amount of delay after global clock 10 falls, the clock delay in-phase signal 32 will drop low which causes the falling edge detection signal 40 to return to high (inactivate). Thus, the falling edge detection signal 40 pulses low in response to a falling transition on global clock 10 .
- the falling edge detection signal 40 and rising edge detection signal 41 are driven to slave clock SR (set/reset) latch subcircuit 50 and master clock SR (set/reset) latch subcircuit 60 .
- the master clock SR latch 60 consists of cross-coupled NANDs 65 and 66 and operates as follows. Activation of either falling edge detection signal 40 or rising edge detection signal 41 causes the master clock SR latch internal node 61 to transition high and the master clock SR latch internal node 62 to transition low. This effectively resets the master clock SR latch 60 output which is repowered through buffer 63 to drive the c1 clock 64 low (or inactive).
- the slave clock SR latch 50 consists of cross-coupled NANDs 55 and 56 and operates as follows.
- the master clock SR latch output node 70 drives a delay/shaping subcircuit 80 .
- the operation of the delay/shaping subcircuit 80 is as follows.
- the delay/shaping input 70 is delayed through two chain of inverters 71 and 72 .
- the output of these inverter chains 71 and 72 are driven to a AND gate 73 to drive output 74 .
- Initially input 70 is high, the output of inverter chain 71 is low, the output of inverter chain 72 is high and the output 74 is high (inactive).
- When input 70 switches low the output of inverter chain 72 switches high after three inverter delays.
- Both inputs to NAND gate 73 are high thus the output 74 is switched low.
- the output of inverter chain 72 is switched low and thus the NAND gate 73 output switches back to high.
- the delay/shaping circuit 80 thus produces a delayed pulsed low output 74 in response to a falling transition on input 70 .
- a falling transition on delay/shaping subcircuit output 74 causes the master clock SR latch internal node 62 to transition high and the master clock SR latch internal node 61 to transition low. This effectively sets the master clock SR latch 60 output which is repowered through buffer 63 to drive the c1 clock 64 high (or active).
- a falling transition on delay/shaping subcircuit output 74 also causes the slave clock SR latch internal node 52 to transition high and the slave clock SR latch internal node 51 to transition low. This effectively resets the slave clock SR latch 50 output which is repowered through buffer 53 to drive the c2 clock 54 low (or inactive).
- the delay of delay/shaping subcircuit 80 thus determines the c1 clock 64 and c2 clock 54 pulse widths.
- the global clock 10 falling transition 10 a causes a falling transition 64 a on c1 clock 64 and a rising transition 54 a on c2 clock 54 .
- the delay/shaping circuit 80 causes the rising transition 64 b on c1 clock 64 and falling transition 54 b on c2 clock 54 .
- the global clock 10 falling transition 10 b causes a falling transition 64 c on c1 clock 64 and a rising transition 54 c on c2 clock 54 .
- the delay/shaping circuit 80 causes the rising transition 64 d on c1 clock 64 and falling transition 54 d on c2 clock 54 .
- the periods of c1 clock 64 and c2 clock 54 are half the period of the global clock 10 .
- the frequency of c1 clock 64 and c2 clock 54 is doubled with respect to the frequency of the global clock 10 .
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
- This invention relates to chip clock distribution, generation and repowering circuits.
- IBM is a registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A.. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
- Microprocessor frequencies are scaling with CMOS device speed and are outpacing the capabilities of global chip clock distribution. The problem is two fold. First, the number of circuits per chip is growing roughly as the square of the lithography improvement and thus the clock needs to be distributed to more circuits. Second, the wire performance is relatively constant. The thickest wiring layers which are generally used to route the global clocks behave as a low pass filter with a cutoff frequency which does not improve with device speed. Previously this cutoff frequency limit has been extended through the use of very wide wires. It would be advantageous to extend the global clock distribution frequency limit without reducing the number of wiring tracks available to I/O and signals. It would also be advantageous to reduce the power associated with generating and globally distributing the clock.
- The invention provides a frequency doubling two-phase clock generation circuit which avoids the above described frequency limitation. In accordance with the preferred embodiment of the invention our clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit. The preferred circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks. A rising edge detection circuit generates a pulse in response to a rising edge of the global clock. A falling edge detection circuit generates a pulse in response to a falling edge of the global clock. A master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse. A delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch. The master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.
- FIG. 1 illustrates a prior art clock block and master/slave latch.
- FIG. 2 illustrates the prior art clock circuit input and output waveforms.
- FIG. 3 illustrates the frequency doubling clock circuit in accordance with our preferred embodiment.
- FIG. 4 illustrates the delay/shaping sub-circuit.
- FIG. 5 illustrates the invention clock circuit input and output waveforms.
- Our detailed description explains the preferred embodiments of our invention, together with advantages and features, by way of example with reference to the drawings.
- Referring to FIG. 1, the prior-art clock block simply distributes and repowers a global clock to master and slave latches. The
global clock 10 is repowered byinverters local c1 clock 14 which is inverted with respect to theglobal clock 10.Global clock 10 is also repowered byinverters local c2 clock 17 which is not inverted with respect to theglobal clock 10. Thelocal c1 clock 14 is driven through local wires to thelocal master latches 18. Thelocal c2 clock 17 is driven through local wires to thelocal slave latches 19. - Referring to FIG. 2, the prior-art clock block outputs two local clocks. The
local c1 clock 14 andlocal c2 clock 17 have different phases than theglobal clock 10; but these output clocks have the same period (and frequency) as theglobal clock 10. - Referring to FIG. 3, the preferred embodiment of the invention provides a clock generation circuit having a frequency-doubling clock block which receives a global clock and doubles its frequency to generate two out-of-phase local clocks. The edge detect
subcircuit 30 monitors theglobal clock 10. Theedge detect subcircuit 30 consists of adelay circuit 31 which outputs global clock delay in-phase signal 32 and out-of-phase signal 33, aninverter 34 which generates an invertedclock signal 35, aNAND gate 36 which generates a fallingedge detection signal 40 and aNAND gate 37 which generates a risingedge detection signal 41. The operation of this edge detectsubcircuit 30 is as follows. Initially theglobal clock 10 is low such that the clock delay in-phase signal 32 is low, the clock delay out-of-phase signal 33 is high, the invertedclock signal 35 is high, the fallingedge detection signal 40 is high (inactive) and the risingedge detection signal 41 is high (inactive.) Now a rising transition on theglobal clock 10 sets both inputs intoNAND gate 37 high and causes the risingedge detection signal 41 to drop low (activate.) A fixed amount of delay afterglobal clock 10 rises, the clock delay out-of-phase signal 33 will drop low which causes the risingedge detection signal 41 to return to high (inactivate). Thus, the risingedge detection signal 41 pulses low in response to a rising transition onglobal clock 10. - Also in response to the rising transition on
global clock 10, the clock delay in-phase signal 32 will switch high, and the invertedclock signal 35 will switch low. Now a falling transition on theglobal clock 10 sets both inputs intoNAND gate 36 high and causes the fallingedge detection signal 40 to drop low (activate.) A fixed amount of delay afterglobal clock 10 falls, the clock delay in-phase signal 32 will drop low which causes the fallingedge detection signal 40 to return to high (inactivate). Thus, the fallingedge detection signal 40 pulses low in response to a falling transition onglobal clock 10. - The falling
edge detection signal 40 and risingedge detection signal 41 are driven to slave clock SR (set/reset)latch subcircuit 50 and master clock SR (set/reset)latch subcircuit 60. The masterclock SR latch 60 consists ofcross-coupled NANDs edge detection signal 40 or risingedge detection signal 41 causes the master clock SR latchinternal node 61 to transition high and the master clock SR latchinternal node 62 to transition low. This effectively resets the masterclock SR latch 60 output which is repowered throughbuffer 63 to drive thec1 clock 64 low (or inactive). The slaveclock SR latch 50 consists ofcross-coupled NANDs edge detection signal 40 or risingedge detection signal 41 causes the slave clock SR latchinternal node 51 to transition high and the slave clock SR latchinternal node 52 to transition low. This effectively sets the slaveclock SR latch 50 output which is repowered throughbuffer 53 to drive thec2 clock 54 high (or active). - The master clock SR
latch output node 70 drives a delay/shapingsubcircuit 80. Referring to FIG. 4, the operation of the delay/shapingsubcircuit 80 is as follows. The delay/shaping input 70 is delayed through two chain ofinverters 71 and 72. The output of theseinverter chains 71 and 72 are driven to aAND gate 73 to driveoutput 74. Initiallyinput 70 is high, the output of inverter chain 71 is low, the output ofinverter chain 72 is high and theoutput 74 is high (inactive). Wheninput 70 switches low the output ofinverter chain 72 switches high after three inverter delays. Both inputs toNAND gate 73 are high thus theoutput 74 is switched low. After three more inverter delays the output ofinverter chain 72 is switched low and thus theNAND gate 73 output switches back to high. The delay/shaping circuit 80 thus produces a delayed pulsedlow output 74 in response to a falling transition oninput 70. - Referring back to FIG. 3, a falling transition on delay/shaping
subcircuit output 74 causes the master clock SR latchinternal node 62 to transition high and the master clock SR latchinternal node 61 to transition low. This effectively sets the masterclock SR latch 60 output which is repowered throughbuffer 63 to drive thec1 clock 64 high (or active). A falling transition on delay/shapingsubcircuit output 74 also causes the slave clock SR latchinternal node 52 to transition high and the slave clock SR latchinternal node 51 to transition low. This effectively resets the slaveclock SR latch 50 output which is repowered throughbuffer 53 to drive thec2 clock 54 low (or inactive). The delay of delay/shapingsubcircuit 80 thus determines thec1 clock 64 andc2 clock 54 pulse widths. - Referring to FIG. 5, the
global clock 10 fallingtransition 10 a causes a fallingtransition 64 a onc1 clock 64 and a risingtransition 54 a onc2 clock 54. The delay/shaping circuit 80 causes the risingtransition 64 b onc1 clock 64 and fallingtransition 54 b onc2 clock 54. Theglobal clock 10 fallingtransition 10 b causes a fallingtransition 64 c onc1 clock 64 and a risingtransition 54 c onc2 clock 54. The delay/shaping circuit 80 causes the risingtransition 64 d onc1 clock 64 and fallingtransition 54 d onc2 clock 54. The periods ofc1 clock 64 andc2 clock 54 are half the period of theglobal clock 10. Thus the frequency ofc1 clock 64 andc2 clock 54 is doubled with respect to the frequency of theglobal clock 10. - While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Claims (10)
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US10/177,323 US6661262B1 (en) | 2002-06-20 | 2002-06-20 | Frequency doubling two-phase clock generation circuit |
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US10/177,323 US6661262B1 (en) | 2002-06-20 | 2002-06-20 | Frequency doubling two-phase clock generation circuit |
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US20030234670A1 true US20030234670A1 (en) | 2003-12-25 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102487272A (en) * | 2010-12-01 | 2012-06-06 | Arm有限公司 | Integrated circuit, clock gate control circuit and method |
US8222916B2 (en) * | 2010-11-17 | 2012-07-17 | Aeroflex Colorado Springs Inc. | Single event transient direct measurement methodology and circuit |
WO2019040323A1 (en) * | 2017-08-23 | 2019-02-28 | Teradyne, Inc. | Adjusting signal timing |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US7313210B2 (en) * | 2003-02-28 | 2007-12-25 | Hewlett-Packard Development Company, L.P. | System and method for establishing a known timing relationship between two clock signals |
DE10320793B4 (en) * | 2003-04-30 | 2005-04-21 | Infineon Technologies Ag | Latch or phase detector circuit for DRAM data storage uses flip flop stage and cascaded NAND gates to give output depending on clock and data state change phase |
US7424046B2 (en) * | 2004-10-15 | 2008-09-09 | Altera Corporation | Spread spectrum clock signal generation system and method |
TWI638521B (en) * | 2017-09-19 | 2018-10-11 | 新唐科技股份有限公司 | Clock filter circuit and filtering method |
US10389335B1 (en) * | 2018-05-04 | 2019-08-20 | Apple Inc. | Clock pulse generation circuit |
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US5359232A (en) * | 1992-05-08 | 1994-10-25 | Cyrix Corporation | Clock multiplication circuit and method |
US5365181A (en) * | 1993-03-15 | 1994-11-15 | Texas Instruments Incorporated | Frequency doubler having adaptive biasing |
DE10036722C1 (en) * | 2000-07-27 | 2002-02-28 | Infineon Technologies Ag | Frequency doubling circuit for data transmission bus has input signal and processed input signal combined via Exclusive-OR gate |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8222916B2 (en) * | 2010-11-17 | 2012-07-17 | Aeroflex Colorado Springs Inc. | Single event transient direct measurement methodology and circuit |
US8854076B2 (en) | 2010-11-17 | 2014-10-07 | Aeroflex Colorado Springs Inc. | Single event transient direct measurement methodology and circuit |
CN102487272A (en) * | 2010-12-01 | 2012-06-06 | Arm有限公司 | Integrated circuit, clock gate control circuit and method |
US20120139590A1 (en) * | 2010-12-01 | 2012-06-07 | James Edward Myers | Integrated circuit, clock gating circuit, and method |
US8604831B2 (en) * | 2010-12-01 | 2013-12-10 | Cambridge | Integrated circuit, clock gating circuit, and method |
GB2486003B (en) * | 2010-12-01 | 2016-09-14 | Advanced Risc Mach Ltd | Intergrated circuit, clock gating circuit, and method |
WO2019040323A1 (en) * | 2017-08-23 | 2019-02-28 | Teradyne, Inc. | Adjusting signal timing |
US10276229B2 (en) | 2017-08-23 | 2019-04-30 | Teradyne, Inc. | Adjusting signal timing |
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