US20030198119A1 - Simultaneous function dynamic random access memory device technique - Google Patents
Simultaneous function dynamic random access memory device technique Download PDFInfo
- Publication number
- US20030198119A1 US20030198119A1 US10/125,758 US12575802A US2003198119A1 US 20030198119 A1 US20030198119 A1 US 20030198119A1 US 12575802 A US12575802 A US 12575802A US 2003198119 A1 US2003198119 A1 US 2003198119A1
- Authority
- US
- United States
- Prior art keywords
- memory banks
- read
- integrated circuit
- memory
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/108—Wide data ports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2281—Timing of a read operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/229—Timing of a write operation
Definitions
- the present invention relates, in general, to the field of integrated circuit (“IC”) memory devices and other ICs incorporating embedded memory. More particularly, the present invention relates to a simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like.
- DRAM simultaneous function dynamic random access memory
- a memory architecture that allows for simultaneous “read” and “write” operations (used primarily for read-modify-write cycles) may use a “write” address first-in, first-out (“FIFO”) register to capture a “read” address to be used later as a “write” address. See Hardee, K.
- the technique of the present invention advantageously enables the execution of “read”, “write”, “active” and “precharge” commands to a memory array on a single clock cycle.
- the technique disclosed herein is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts.
- the present invention provides for the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.
- simultaneous commands are supported through the use of separate bank addresses.
- parallel “active”, “read”, “write” and “precharge” commands can be executed on the same clock (“CLK”) cycle with only simultaneous “active” and “precharge” commands being unable to be executed to the same bank during any given clock cycle.
- each “active”, “read”, “write” and “precharge” command has its own dedicated address field, including bank addresses. In this manner, each command can be simultaneously and independently executed during the same clock cycle resulting in much improved memory control bus utilization through this high level of parallel operation.
- BAA ⁇ 0,1> bank address for “active” or row select
- BAR ⁇ 0,1> bank address for “read” commands
- BAW ⁇ 0,1> bank address for “write” commands
- BAP ⁇ 0,1> bank address for “precharge”
- RA ⁇ 0:X> row address
- CAR ⁇ 0:X> column address for “read” commands
- CAW ⁇ 0:X> columnumn address for “write” commands
- the conventional row address strobe (“/RAS”); column address strobe (“/CAS”); write enable (“/WE”) and chip select (“/CE”) signals may be then replaced with “read”, “write”, “active” and “precharge” commands with the input/outputs (“I/Os”; “DATA IN” and “DATA OUT”) not being common.
- I/Os input/outputs
- DATA IN input/outputs
- DATA OUT input/outputs
- an integrated circuit device including a memory array comprising a plurality of memory banks and wherein the memory array receives a clock signal and a number of memory array command signals and is configured for reading data therefrom and writing data thereto.
- the memory array comprises: a row address input for specifying a row address within the memory array; at least one column address input for specifying a column address within the memory array; a bank address read input for specifying one of the memory banks from which data may be read at the specified row and column address; and a bank address write input for substantially concurrently specifying another one of the memory banks to which data may be written at the specified row and column address.
- an integrated circuit device including a memory array comprising a plurality of memory banks.
- the integrated circuit device comprises: a clock input for sequencing operations of said memory array; a command input for receiving at least read, write, active and precharge commands for the memory array; a row address input for specifying a row address within the memory array; first and second column address inputs for specifying independent column addresses for respectively reading data from and writing data to the memory array; and a plurality of bank address inputs, with each of the bank address inputs corresponding to one of the read, write, active and precharge commands.
- a method for accessing data in an integrated circuit device including a memory array comprising a plurality of memory banks.
- the method comprises the steps of: activating a first of the plurality of memory banks on a first clock cycle and activating a second of the plurality of memory banks while substantially concurrently reading data from the first of said plurality of memory banks on a second clock cycle.
- FIG. 1 is a simplified functional block diagram of a prior art integrated circuit device incorporating an embedded memory array having, for example, four banks of memory accessible through conventional address fields for the bank, row and column addresses;
- FIG. 2 is a representative timing diagram illustrative of the interrelationship among the clock (“CLK”), command (“CMD”), bank address (“BA ⁇ 0,1>”), row address (“RA ⁇ 0:1>”), column address (“CA ⁇ 0:1>”), DATA IN and DATA OUT signals in a prior art integrated circuit device similar to that shown in the preceding figure and wherein the device does not include a “precharge all” capability;
- FIG. 3 is a further representative timing diagram illustrative of the interrelationship among the CLK, CMD, BA ⁇ 0,1>, RA ⁇ 0:X>, CA ⁇ 0:X>, DATA IN and DATA OUT signals in a prior art integrated circuit device similar to that shown in FIG. 1 and wherein the device does include a “precharge all” capability;
- FIG. 4 is a simplified functional block diagram of an exemplary integrated circuit device incorporating an embedded memory array accessible in accordance with the present invention having, for example, four banks of memory and including separate bank addresses for active (“ACTB”) (or row select), read (“READB“), write (“WRITEB”) and precharge (“PREB”) commands as well as row address (“RA ⁇ 0:X>”), and column address fields for “read” and “write” command (“CAR ⁇ 0:X>” and “CAW ⁇ 0:X>”); and
- FIG. 5 is a representative timing diagram illustrative of the interrelationship among the various signals indicated in the exemplary embodiment of the present invention of the preceding figure including the bank address for active (or row select) commands (“BAA ⁇ 0,1>”), bank address for “read” commands (“BAR ⁇ 0,1>”), bank address for “write” commands (“BAW ⁇ 0,1>”) and bank address for precharge commands (“IBAP ⁇ 0,1>”) and showing how each command can be simultaneously and independently executed during the same clock cycle thereby improving memory control bus utilization.
- BAA ⁇ 0,1> bank address for active (or row select) commands
- BAR ⁇ 0,1> bank address for “read” commands
- BAW ⁇ 0,1> bank address for “write” commands
- IBAP ⁇ 0,1> bank address for precharge commands
- FIG. 1 a simplified functional block diagram of a prior art integrated circuit device 10 is shown incorporating an embedded memory array.
- the memory array comprises, for example, four memory banks 12 0 through 12 3 (Bank 0 through Bank 3 respectively).
- a clock signal (“CLK”) is supplied to the device 10 to synchronize memory accesses and a number of commands may be provided on various inputs shown as a single line 16 which, in a conventional DRAM or SDRAM device 10 can include an active low row address strobe (“/RAS”), column address strobe (“I/CAS”), write enable (“/WE”), chip select (“/CS”) signals and the like.
- Data to be written to the memory banks 12 0 through 12 3 may be input in serial or parallel format as shown by line 18 while data read from the device 10 may likewise be output as indicated by line 20 .
- the memory banks 120 through 123 are accessible through conventional address fields for the bank, row and column addresses which, in the simplified embodiment of the device 10 shown may comprise bank address field BA ⁇ 0,1> on line 24 , row address field RA ⁇ 0:1> on line 26 and column address field CA ⁇ 0:1> on line 28 .
- FIG. 2 a representative timing diagram illustrative of the interrelationship among CLK, command (“CMD”), bank address (“BA ⁇ 0 , 1 >”), row address (“RA ⁇ 0:1>”), column address (“CA ⁇ 0:1>”), DATA IN and DATA OUT signals is shown, for example, in a prior art integrated circuit device similar to that shown in the preceding figure.
- the device does not include a “precharge all” capability and the commands illustrated are: “active” (“ACT”), “read” (“RD”), “write” (“WT”) and “precharge” (“PRE”).
- the bank address field BA ⁇ 0,1> in this four memory bank example can have any one of four values representative of the corresponding memory banks 12 0 through 12 3 .
- the row address field RA ⁇ 0:X> is illustrated as having four values: A, B, C and D while the column address field CA ⁇ 0:X> also has four values: M, N, 0 and P.
- a “write” command is issued to bank 0 , row A and column M followed by another “write” to bank 1 , row B, column N at CLK pulse 8 .
- a “read” operation is directed to bank 2 , row C, column 0 followed by another “read” command to bank 3 , row D, column P at CLK pulse 10 .
- the data output (”Q”) for bank 2 , row C, column O appears at the DATA OUT line coincident with the tenth CLK pulse while the data output for bank 3 , row D, column P appears on the following CLK pulse 11 .
- FIG. 3 a further representative timing diagram illustrative of the interrelationship among the conventional CLK, CMD, BA ⁇ 0,1>, RA ⁇ 0:X>, CA ⁇ 0:X>, DATA IN and DATA OUT signals is shown in a prior art integrated circuit device similar to that shown in FIG. 1.
- the functionality illustrated is substantially the same as that previously illustrated and described with respect to the timing diagram for an interleaved bank read/write (read-modify-write) operation of FIG. 2, but in this instance, the device does include a “precharge all” capability. Consequently, the relationship between the CLK, CMD and bank, row and column address fields is the same from CLK pulse 1 through CLK pulse 12 .
- the device 50 includes an embedded memory array comprising, for example, four memory banks 52 0 through 52 3 inclusive (Bank 0 through Bank 3 ).
- a clock signal (“CLK”) is supplied to the device 50 to synchronize memory accesses and a number of commands may be provided on various inputs shown as a single line 54 including active “low”: “active” (“ACTB”) (or row select), “read” (“READB”), “write” (“WRITEB”) and “precharge” (“PREB”) commands.
- CLK clock signal
- ACTB active”
- READB read”
- WRITEB write”
- PREB precharge
- a number of novel bank address fields 60 are supplied to enable access operations to the device 50 including, for example, the bank address for active (or row select) commands (“BAA ⁇ 0,1>”) on line 62 , the bank address for “read” commands (“BAR ⁇ 0,1>”) on line 64 , the bank address for “write” commands (“BAW ⁇ 0,1>”) on line 66 and the bank address for precharge commands (“BAP ⁇ 0,1>”) on line 68 .
- a row address (“RA ⁇ 0:X>”) is supplied on line 70 while a pair of column address fields 72 are furnished for “read” and “write” commands (“CAR ⁇ 0:X>” and “CAW ⁇ 0:X>”) on lines 74 and 76 respectively.
- FIG. 5 a representative timing diagram is shown illustrative of the interrelationship among the various signals indicated in the exemplary embodiment of the device 50 of the preceding FIG. 4.
- the timing diagram presented represents how each command can be simultaneously and independently executed during the same clock cycle thereby improving memory control bus utilization over the conventional implementations shown with respect to FIGS. 1 - 3 .
- the ACTB command is asserted for bank 0 , row A as shown.
- the ACTB is asserted for bank 1 , row B while a concurrent READB command is issued for bank 0 , row A, column M which bank and row were made “active” on the prior CLK pulse 1 .
- the ACTB command is again asserted for bank 2 , row C while a concurrent READB command issued for bank 1 , row B, column N as this bank and row were made “active” on the preceding CLK pulse 2 .
- data output (“Q”) for bank 0 , row A, column M is provided on the DATA OUT line 58 .
- the ACTB command is again asserted for bank 3 , row D while a READB command is issued for bank 2 , row C, column O.
- Data red from bank 1 , row B, column N is also output on line 58 while a WRITEB command takes data from the DATA IN line 56 and writes it to bank 0 , row A, column M, which bank, row and column were previously read from at CLK pulse 2 .
- a PREB command is issued to precharge bank 0 while a READB command reads data from bank 3 , row D, column P while data from bank 2 , row C, column O is provided on the DATA OUT line 58 .
- a WRITEB command takes data on the DATA IN line 56 and writes it to bank 1 , row B, column N. Bank 1 , row B, column N were previously read from on CLK pulse 3 .
- Bank 1 is next precharged at CLK pulse 6 while data is output from bank 3 , row D, column P and data is written to bank 2 , row C, column O which was read from at CLK pulse 4 .
- bank 2 is precharged while data is written to bank 3 , row D, column P which was previously read from at CLK pulse 5 .
- bank 3 is precharged and the interleaved bank read/write operation is completed in only eight clock cycles as opposed to the thirteen of FIG. 3 or the sixteen of FIG. 2. This high level of parallel operation greatly improves memory control bus utilization.
Landscapes
- Dram (AREA)
Abstract
Description
- The present invention relates, in general, to the field of integrated circuit (“IC”) memory devices and other ICs incorporating embedded memory. More particularly, the present invention relates to a simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like.
- It has long been a goal of memory design to increase the performance of DRAM in order to support higher speed processors. One method of increasing DRAM performance is to increase the “read” and “write” data rate across the memory bus. SDRAM access times and burst data rates are constantly improving by manufacturing process “shrinks” and improved interconnect technology. Additionally, improved command bus utilization has been achieved by reducing the number of instructions needed to perform certain memory-operations. In general, the fewer command cycles which are required for the execution of memory commands results in more bus cycles which are then available for memory data transfers.
- To date, several approaches have been used to minimize the number of command cycles needed to access SDRAM devices and embedded arrays. One example is the use of “burst accesses” which utilize a single “read” or “write” command execution in order to read or write to multiple sequential words. Another technique for reducing the number of command cycles required to access SDRAMs is the use of an “auto-precharge” mode of operation. Auto-precharge is a programmable mode wherein a “precharge” operation automatically occurs at the end of a predetermined number of burst “read” or “write” cycles without requiring the assertion of an external “precharge” command. Similarly, the execution of a “refresh” command in SDRAMs results in the device automatically precharging at the end of the “refresh” operation.
- Nevertheless, there are a number of applications, such as in conjunction with graphics processors, where performance could be greatly enhanced if the associated memory supported multiple command executions on a single clock cycle. As an example, a memory architecture that allows for simultaneous “read” and “write” operations (used primarily for read-modify-write cycles) may use a “write” address first-in, first-out (“FIFO”) register to capture a “read” address to be used later as a “write” address. See Hardee, K. et al.; “A 1.43 GHz Per Data I/
O 16 Mb DDR Low-Power Embedded DRAM Macro for a 3D Graphics Engine”;2001 IEEE International Solid-State Circuits Conference Digest of Technical Papers; pp 386-387 and ISSCC Visuals Supplement pp 316-317. Further, the concept of capturing the “read” address and using it at a later time via a pipeline is described in U.S. Pat. No. 5,996,052 issued Nov. 30, 1999 to Taniguchi et al. for: “Method and Circuit for Enabling a Clock-Synchronized Read-Modify-Write Operation on a Memory Array”. - While simultaneous “read” and “write” operations have been reported in specialty memories (and certain embedded memories) using posted “write” addresses as mentioned above, simultaneous “read”, “write”, “active” and “precharge” operations in response to external memory commands have apparently not been previously reported.
- In this regard, the technique of the present invention advantageously enables the execution of “read”, “write”, “active” and “precharge” commands to a memory array on a single clock cycle. The technique disclosed herein is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the present invention provides for the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.
- In accordance with the disclosure of the present invention, simultaneous commands are supported through the use of separate bank addresses. As a consequence, parallel “active”, “read”, “write” and “precharge” commands can be executed on the same clock (“CLK”) cycle with only simultaneous “active” and “precharge” commands being unable to be executed to the same bank during any given clock cycle.
- In a particular representative embodiment disclosed herein, each “active”, “read”, “write” and “precharge” command has its own dedicated address field, including bank addresses. In this manner, each command can be simultaneously and independently executed during the same clock cycle resulting in much improved memory control bus utilization through this high level of parallel operation.
- Through the use of separate “read” and “write” addresses together with separate bank addresses for “precharge” operations as well, multiple commands may be captured on one edge (e.g. the rising edge) of the clock signal and performed internally to the memory array in parallel. For example, in a conventional four bank memory the address fields are: BA<0,1> (bank address); RA<0:X> (row address) and CA<0:X> (column address). By contrast, and in accordance with the technique of the present invention, the following new address fields may be utilized: BAA<0,1> (bank address for “active” or row select); BAR<0,1> (bank address for “read” commands); BAW<0,1> (bank address for “write” commands); BAP<0,1> (bank address for “precharge”); RA<0:X> (row address); CAR<0:X> (column address for “read” commands) and CAW<0:X> (column address for “write” commands).
- In this regard, the conventional row address strobe (“/RAS”); column address strobe (“/CAS”); write enable (“/WE”) and chip select (“/CE”) signals may be then replaced with “read”, “write”, “active” and “precharge” commands with the input/outputs (“I/Os”; “DATA IN” and “DATA OUT”) not being common. Used together with the aforementioned address commands, fully parallel memory operation results. While this internally parallel operation adds some extra address bussing over prior art techniques and results in a small increase in DRAM periphery area, it nevertheless allows for a two, three or four (or more) times increase in memory bandwidth.
- Particularly disclosed herein is an integrated circuit device including a memory array comprising a plurality of memory banks and wherein the memory array receives a clock signal and a number of memory array command signals and is configured for reading data therefrom and writing data thereto. The memory array comprises: a row address input for specifying a row address within the memory array; at least one column address input for specifying a column address within the memory array; a bank address read input for specifying one of the memory banks from which data may be read at the specified row and column address; and a bank address write input for substantially concurrently specifying another one of the memory banks to which data may be written at the specified row and column address.
- Also disclosed herein is an integrated circuit device including a memory array comprising a plurality of memory banks. The integrated circuit device comprises: a clock input for sequencing operations of said memory array; a command input for receiving at least read, write, active and precharge commands for the memory array; a row address input for specifying a row address within the memory array; first and second column address inputs for specifying independent column addresses for respectively reading data from and writing data to the memory array; and a plurality of bank address inputs, with each of the bank address inputs corresponding to one of the read, write, active and precharge commands.
- Further disclosed herein is a method for accessing data in an integrated circuit device including a memory array comprising a plurality of memory banks. The method comprises the steps of: activating a first of the plurality of memory banks on a first clock cycle and activating a second of the plurality of memory banks while substantially concurrently reading data from the first of said plurality of memory banks on a second clock cycle.
- The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:
- FIG. 1 is a simplified functional block diagram of a prior art integrated circuit device incorporating an embedded memory array having, for example, four banks of memory accessible through conventional address fields for the bank, row and column addresses;
- FIG. 2 is a representative timing diagram illustrative of the interrelationship among the clock (“CLK”), command (“CMD”), bank address (“BA<0,1>”), row address (“RA<0:1>”), column address (“CA<0:1>”), DATA IN and DATA OUT signals in a prior art integrated circuit device similar to that shown in the preceding figure and wherein the device does not include a “precharge all” capability;
- FIG. 3 is a further representative timing diagram illustrative of the interrelationship among the CLK, CMD, BA<0,1>, RA<0:X>, CA<0:X>, DATA IN and DATA OUT signals in a prior art integrated circuit device similar to that shown in FIG. 1 and wherein the device does include a “precharge all” capability;
- FIG. 4 is a simplified functional block diagram of an exemplary integrated circuit device incorporating an embedded memory array accessible in accordance with the present invention having, for example, four banks of memory and including separate bank addresses for active (“ACTB”) (or row select), read (“READB“), write (“WRITEB”) and precharge (“PREB”) commands as well as row address (“RA<0:X>”), and column address fields for “read” and “write” command (“CAR<0:X>” and “CAW<0:X>”); and
- FIG. 5 is a representative timing diagram illustrative of the interrelationship among the various signals indicated in the exemplary embodiment of the present invention of the preceding figure including the bank address for active (or row select) commands (“BAA<0,1>”), bank address for “read” commands (“BAR<0,1>”), bank address for “write” commands (“BAW<0,1>”) and bank address for precharge commands (“IBAP<0,1>”) and showing how each command can be simultaneously and independently executed during the same clock cycle thereby improving memory control bus utilization.
- With reference now to FIG. 1, a simplified functional block diagram of a prior art
integrated circuit device 10 is shown incorporating an embedded memory array. The memory array comprises, for example, fourmemory banks 12 0 through 12 3 (Bank 0 throughBank 3 respectively). A clock signal (“CLK”) is supplied to thedevice 10 to synchronize memory accesses and a number of commands may be provided on various inputs shown as asingle line 16 which, in a conventional DRAM orSDRAM device 10 can include an active low row address strobe (“/RAS”), column address strobe (“I/CAS”), write enable (“/WE”), chip select (“/CS”) signals and the like. Data to be written to thememory banks 12 0 through 12 3 may be input in serial or parallel format as shown byline 18 while data read from thedevice 10 may likewise be output as indicated byline 20. - In general, the
memory banks 120 through 123 are accessible through conventional address fields for the bank, row and column addresses which, in the simplified embodiment of thedevice 10 shown may comprise bank address field BA<0,1> online 24, row address field RA<0:1> online 26 and column address field CA<0:1> online 28. - With reference additionally now to FIG. 2, a representative timing diagram illustrative of the interrelationship among CLK, command (“CMD”), bank address (“BA<0,1>”), row address (“RA<0:1>”), column address (“CA<0:1>”), DATA IN and DATA OUT signals is shown, for example, in a prior art integrated circuit device similar to that shown in the preceding figure. In this example, the device does not include a “precharge all” capability and the commands illustrated are: “active” (“ACT”), “read” (“RD”), “write” (“WT”) and “precharge” (“PRE”).
- The bank address field BA<0,1> in this four memory bank example can have any one of four values representative of the
corresponding memory banks 12 0 through 12 3. The row address field RA<0:X> is illustrated as having four values: A, B, C and D while the column address field CA<0:X> also has four values: M, N, 0 and P. - On the positive transition of CLK pulse “1”,
bank 0, row A is made “active” followed bybank 1, row B at CLK pulse “2”,bank 2, row C at CLK pulse “3” andbank 2, row D at CLK pulse “4”. A “read” command is issued atCLK pulse 5 tobank 0 and column M of the already active row A followed by another “read” command atCLK pulse 6 tobank 1, column N of the active row B. The data output (“Q”) forbank 0, row A, column M appears at the DATA OUT line coincident with the sixth CLK pulse while the data output forbank 1, row B, column N appears on the followingCLK pulse 7. - Also at CLK
pulse 7, a “write” command is issued tobank 0, row A and column M followed by another “write” tobank 1, row B, column N atCLK pulse 8. AtCLK pulse 9, a “read” operation is directed tobank 2, row C,column 0 followed by another “read” command tobank 3, row D, column P atCLK pulse 10. The data output (”Q”) forbank 2, row C, column O appears at the DATA OUT line coincident with the tenth CLK pulse while the data output forbank 3, row D, column P appears on the followingCLK pulse 11. - Also at CLK
pulse 11, another “write” command is issued tobank 2, row C and column O followed by another “write” tobank 3, row D, column P atCLK pulse 12. Thereafter, at CLKpulse 13, a PRECHARGE command is issued tobank 0, followed by separate PRECHARGE commands issued tobanks CLK pulses - With reference additionally now to FIG. 3, a further representative timing diagram illustrative of the interrelationship among the conventional CLK, CMD, BA<0,1>, RA<0:X>, CA<0:X>, DATA IN and DATA OUT signals is shown in a prior art integrated circuit device similar to that shown in FIG. 1. The functionality illustrated is substantially the same as that previously illustrated and described with respect to the timing diagram for an interleaved bank read/write (read-modify-write) operation of FIG. 2, but in this instance, the device does include a “precharge all” capability. Consequently, the relationship between the CLK, CMD and bank, row and column address fields is the same from
CLK pulse 1 throughCLK pulse 12. Because a “precharge all” capability is present, atCLK pulse 13, all four banks are precharged concurrently. In this illustrative example, the interleaved bank read/write (read-modify-write) operation including a “precharge all” capability requires thirteen CLK cycles to complete, which, while requiring less device memory control bus utilization than the example of the preceding figure is still undesirably long. - With reference additionally now to FIG. 4, a simplified functional block diagram of an exemplary
integrated circuit device 50 in accordance with the present invention is shown. Thedevice 50 includes an embedded memory array comprising, for example, four memory banks 52 0 through 52 3 inclusive (Bank 0 through Bank 3). A clock signal (“CLK”) is supplied to thedevice 50 to synchronize memory accesses and a number of commands may be provided on various inputs shown as asingle line 54 including active “low”: “active” (“ACTB”) (or row select), “read” (“READB”), “write” (“WRITEB”) and “precharge” (“PREB”) commands. Data to be written to the memory banks 52 0 through 52 3 may be input in serial or parallel format as shown byline 56 while data read from thedevice 50 may likewise be output as indicated byline 58. - A number of novel bank address fields60 are supplied to enable access operations to the
device 50 including, for example, the bank address for active (or row select) commands (“BAA<0,1>”) online 62, the bank address for “read” commands (“BAR<0,1>”) online 64, the bank address for “write” commands (“BAW<0,1>”) online 66 and the bank address for precharge commands (“BAP<0,1>”) online 68. A row address (“RA<0:X>”) is supplied online 70 while a pair of column address fields 72 are furnished for “read” and “write” commands (“CAR<0:X>” and “CAW<0:X>”) onlines - With reference additionally now to FIG. 5, a representative timing diagram is shown illustrative of the interrelationship among the various signals indicated in the exemplary embodiment of the
device 50 of the preceding FIG. 4. The timing diagram presented represents how each command can be simultaneously and independently executed during the same clock cycle thereby improving memory control bus utilization over the conventional implementations shown with respect to FIGS. 1-3. - At
CLK pulse 1, the ACTB command is asserted forbank 0, row A as shown. On thenext CLK pulse 2, the ACTB is asserted forbank 1, row B while a concurrent READB command is issued forbank 0, row A, column M which bank and row were made “active” on theprior CLK pulse 1. AtCLK pulse 3, the ACTB command is again asserted forbank 2, row C while a concurrent READB command issued forbank 1, row B, column N as this bank and row were made “active” on the precedingCLK pulse 2. Concurrently, data output (“Q”) forbank 0, row A, column M is provided on theDATA OUT line 58. - At
CLK pulse 4, the ACTB command is again asserted forbank 3, row D while a READB command is issued forbank 2, row C, column O. Data red frombank 1, row B, column N is also output online 58 while a WRITEB command takes data from the DATA INline 56 and writes it tobank 0, row A, column M, which bank, row and column were previously read from atCLK pulse 2. Subsequently, atCLK pulse 5, a PREB command is issued toprecharge bank 0 while a READB command reads data frombank 3, row D, column P while data frombank 2, row C, column O is provided on theDATA OUT line 58. Concurrently, a WRITEB command takes data on the DATA INline 56 and writes it tobank 1, row B,column N. Bank 1, row B, column N were previously read from onCLK pulse 3. -
Bank 1 is next precharged atCLK pulse 6 while data is output frombank 3, row D, column P and data is written tobank 2, row C, column O which was read from atCLK pulse 4. AtCLK pulse 7,bank 2 is precharged while data is written tobank 3, row D, column P which was previously read from atCLK pulse 5. AtCLK pulse 8,bank 3 is precharged and the interleaved bank read/write operation is completed in only eight clock cycles as opposed to the thirteen of FIG. 3 or the sixteen of FIG. 2. This high level of parallel operation greatly improves memory control bus utilization. - While there have been described above the principles of the present invention in conjunction with specific address fields, including bank addresses for “read” and “write” commands and separate bank addresses for “active” and “precharge” commands, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
Claims (26)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/125,758 US6643212B1 (en) | 2002-04-18 | 2002-04-18 | Simultaneous function dynamic random access memory device technique |
JP2002250520A JP3949543B2 (en) | 2002-04-18 | 2002-08-29 | Integrated circuit device and method for accessing data in an integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/125,758 US6643212B1 (en) | 2002-04-18 | 2002-04-18 | Simultaneous function dynamic random access memory device technique |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030198119A1 true US20030198119A1 (en) | 2003-10-23 |
US6643212B1 US6643212B1 (en) | 2003-11-04 |
Family
ID=29214848
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/125,758 Expired - Lifetime US6643212B1 (en) | 2002-04-18 | 2002-04-18 | Simultaneous function dynamic random access memory device technique |
Country Status (2)
Country | Link |
---|---|
US (1) | US6643212B1 (en) |
JP (1) | JP3949543B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050018521A1 (en) * | 2003-07-24 | 2005-01-27 | Byong-Kwon Lee | Methods and devices for accessing a memory using multiple separate address mapped temporary storage areas |
US20060132337A1 (en) * | 2004-12-02 | 2006-06-22 | Nokia Corporation | Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal |
EP2034488A1 (en) * | 2007-09-07 | 2009-03-11 | Nokia Siemens Networks Oy | Method to improve the performance of memory operations |
US20100110747A1 (en) * | 2005-08-10 | 2010-05-06 | Liquid Design Systems, Inc. | Semiconductor memory device |
US20140362656A1 (en) * | 2013-06-06 | 2014-12-11 | Etron Technology, Inc. | Memory with low current consumption and method for reducing current consumption of a memory |
US9452147B2 (en) | 2005-07-14 | 2016-09-27 | Neothetics, Inc. | Lipolytic methods |
WO2020086379A1 (en) * | 2018-10-23 | 2020-04-30 | Etron Technology America, Inc. | Superscalar memory ic, bus and system for use therein |
US20240126476A1 (en) * | 2022-10-13 | 2024-04-18 | Micron Technology, Inc. | Activate information on preceding command |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8233322B2 (en) * | 2003-10-10 | 2012-07-31 | Micron Technology, Inc. | Multi-partition memory with separated read and algorithm datalines |
US8595459B2 (en) | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
US7283418B2 (en) * | 2005-07-26 | 2007-10-16 | Micron Technology, Inc. | Memory device and method having multiple address, data and command buses |
US20070260841A1 (en) | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
WO2008048770A1 (en) * | 2006-10-17 | 2008-04-24 | Lipothera, Inc. | Methods, compositions, and formulations for the treatment of thyroid eye disease |
KR100894252B1 (en) | 2007-01-23 | 2009-04-21 | 삼성전자주식회사 | Semiconductor memory device and method for controlling operation of the same |
US20090140024A1 (en) * | 2007-11-29 | 2009-06-04 | Mclemore Don | Multi-use cargo carrier adaptor and assemblies including the same |
US9132084B2 (en) * | 2009-05-27 | 2015-09-15 | Neothetics, Inc. | Methods for administration and formulations for the treatment of regional adipose tissue |
US20110224176A1 (en) * | 2010-01-15 | 2011-09-15 | Lithera, Inc. | Lyophilized Cake Formulations |
EA201270784A1 (en) | 2010-11-24 | 2013-04-30 | ОБЩЕСТВО С ОГРАНИЧЕННОЙ ОТВЕТСТВЕННОСТЬЮ "НоваМедика" | MONOTHERAPE TREATMENT COMPOSITIONS OF SELECTIVE LIPOPHIL AND BETA-AGONIST OF LONG ACTION AND METHODS OF COSMETIC TREATMENT FOR OBESITY AND COUNTER-ROOTING |
US11630605B1 (en) | 2022-08-10 | 2023-04-18 | Recogni Inc. | Methods and systems for processing read-modify-write requests |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5636173A (en) * | 1995-06-07 | 1997-06-03 | Micron Technology, Inc. | Auto-precharge during bank selection |
JPH1064257A (en) | 1996-08-20 | 1998-03-06 | Sony Corp | Semiconductor storage |
-
2002
- 2002-04-18 US US10/125,758 patent/US6643212B1/en not_active Expired - Lifetime
- 2002-08-29 JP JP2002250520A patent/JP3949543B2/en not_active Expired - Lifetime
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050018521A1 (en) * | 2003-07-24 | 2005-01-27 | Byong-Kwon Lee | Methods and devices for accessing a memory using multiple separate address mapped temporary storage areas |
US7340560B2 (en) * | 2003-07-24 | 2008-03-04 | Samsung Electronics Co., Ltd. | Methods and devices for accessing a memory using multiple separate address mapped temporary storage areas |
US20060132337A1 (en) * | 2004-12-02 | 2006-06-22 | Nokia Corporation | Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal |
US7280054B2 (en) * | 2004-12-02 | 2007-10-09 | Nokia Corporation | Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal |
US9452147B2 (en) | 2005-07-14 | 2016-09-27 | Neothetics, Inc. | Lipolytic methods |
US20100110747A1 (en) * | 2005-08-10 | 2010-05-06 | Liquid Design Systems, Inc. | Semiconductor memory device |
EP2034488A1 (en) * | 2007-09-07 | 2009-03-11 | Nokia Siemens Networks Oy | Method to improve the performance of memory operations |
US20140362656A1 (en) * | 2013-06-06 | 2014-12-11 | Etron Technology, Inc. | Memory with low current consumption and method for reducing current consumption of a memory |
US9773533B2 (en) * | 2013-06-06 | 2017-09-26 | Etron Technology, Inc. | Memory with low current consumption and method for reducing current consumption of a memory |
WO2020086379A1 (en) * | 2018-10-23 | 2020-04-30 | Etron Technology America, Inc. | Superscalar memory ic, bus and system for use therein |
US20240126476A1 (en) * | 2022-10-13 | 2024-04-18 | Micron Technology, Inc. | Activate information on preceding command |
Also Published As
Publication number | Publication date |
---|---|
JP3949543B2 (en) | 2007-07-25 |
JP2003317474A (en) | 2003-11-07 |
US6643212B1 (en) | 2003-11-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6643212B1 (en) | Simultaneous function dynamic random access memory device technique | |
US10388337B2 (en) | Memory with deferred fractional row activation | |
JP4077874B2 (en) | Dynamic random access memory system | |
US5392239A (en) | Burst-mode DRAM | |
US8547776B2 (en) | Multi-port memory based on DRAM core | |
US5883855A (en) | High speed semiconductor memory with burst mode | |
US6005823A (en) | Memory device with pipelined column address path | |
US8045416B2 (en) | Method and memory device providing reduced quantity of interconnections | |
USRE37316E1 (en) | Synchronous LSI memory device | |
US7447109B2 (en) | Semiconductor storage device | |
US6477631B1 (en) | Memory device with pipelined address path | |
WO1997032307A1 (en) | Simplified clocked dram with a fast command input | |
US20040088472A1 (en) | Multi-mode memory controller | |
JP4097165B2 (en) | Reduction circuit and method for reducing the number of data input / output, and semiconductor device | |
JP4744777B2 (en) | Semiconductor memory device having divided cell array and memory cell access method of the device | |
US6545936B1 (en) | Pipeline structure of memory for high-fast row-cycle | |
US6501701B2 (en) | Semiconductor memory device | |
JP3957421B2 (en) | Semiconductor memory device | |
JP2001035153A (en) | Semiconductor memory | |
US6151273A (en) | Synchronous semiconductor memory device | |
JP4997663B2 (en) | Multiport memory and control method thereof | |
US6504767B1 (en) | Double data rate memory device having output data path with different number of latches | |
US20050289293A1 (en) | Dual-port DRAM cell with simultaneous access | |
US20070171735A1 (en) | Latency circuit for semiconductor memories | |
US20220188022A1 (en) | Memory system and electronic system including the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED MEMORIES, INC., COLORADO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JONES, OSCAR FREDERICK, JR.;PARRIS, MICHAEL C.;REEL/FRAME:012827/0343 Effective date: 20020417 Owner name: SONY CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JONES, OSCAR FREDERICK, JR.;PARRIS, MICHAEL C.;REEL/FRAME:012827/0343 Effective date: 20020417 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: UNITED MEMORIES, INC.,COLORADO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONY CORPORATION;REEL/FRAME:024185/0267 Effective date: 20100226 |
|
AS | Assignment |
Owner name: TESSERA INTELLECTUAL PROPERTIES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNITED MEMORIES, INC.;REEL/FRAME:025596/0520 Effective date: 20101119 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: INVENSAS CORPORATION, CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:TESSERA INTELLECTUAL PROPERTIES, INC.;REEL/FRAME:026423/0286 Effective date: 20110425 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001 Effective date: 20161201 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., NORTH CAROLINA Free format text: SECURITY INTEREST;ASSIGNORS:ROVI SOLUTIONS CORPORATION;ROVI TECHNOLOGIES CORPORATION;ROVI GUIDES, INC.;AND OTHERS;REEL/FRAME:053468/0001 Effective date: 20200601 |
|
AS | Assignment |
Owner name: INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.), CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: DTS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: DTS LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: TESSERA ADVANCED TECHNOLOGIES, INC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: PHORUS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: IBIQUITY DIGITAL CORPORATION, MARYLAND Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: INVENSAS CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS), CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: TESSERA, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 |