US20030085432A1 - High frequency signal isolation in a semiconductor device - Google Patents
High frequency signal isolation in a semiconductor device Download PDFInfo
- Publication number
- US20030085432A1 US20030085432A1 US10/003,535 US353501A US2003085432A1 US 20030085432 A1 US20030085432 A1 US 20030085432A1 US 353501 A US353501 A US 353501A US 2003085432 A1 US2003085432 A1 US 2003085432A1
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- United States
- Prior art keywords
- well
- semiconductor device
- isolated
- composite
- plugs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000002955 isolation Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000002131 composite material Substances 0.000 claims description 30
- 239000007943 implant Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Definitions
- the present invention relates generally to semiconductor devices, and more particularly, to high frequency signal isolation in a semiconductor device.
- the NMOS signal isolation is accomplished using a deep n+ implant (DNW) with an n-well to create an isolated p-well (IPW) pocket, and is sometimes referred to as a triple well process.
- DGW deep n+ implant
- IPW isolated p-well
- Implanted wells as used to approximate a Faraday cage in integrated circuits, reduce the effect of noise. However, the use of implanted wells fails to provide adequate signal isolation at higher RF frequencies.
- FIG. 1 illustrates a top view of a prior art semiconductor device 10 .
- FIG. 2 illustrates a cross-sectional view of the prior art semiconductor device 10 of FIG. 1.
- Semiconductor device 10 has a p substrate 18 .
- a deep n-well implant 16 together with a n-well ring 15 creates an isolated p-well pocket 12 .
- a plurality of p+ well ties 14 is implanted in the surface of the isolated p-well 12 .
- Electronic circuits are built into the surface of the isolated p-well (not shown).
- the isolated p-well 12 functions to isolate the circuits implemented in the well from circuits that are implemented outside of the well.
- the deep n-well implant 16 has a relatively high resistance that is undesirable for signal isolation in the RF frequency range.
- FIG. 1 illustrates a top view of a prior art semiconductor device.
- FIG. 2 illustrates a cross-sectional view of the prior art semiconductor device of FIG. 1.
- FIG. 3 illustrates a top view of a semiconductor device in accordance with the present invention.
- FIG. 4 illustrates a cross-sectional view of the semiconductor device of FIG. 3.
- the present invention provides a semiconductor device 20 having a substrate 21 , a buried n-well 25 , and an n-well ring 24 .
- the n-well ring 24 extends from a surface of the semiconductor device 20 to the buried n-well 25 .
- the n-well ring 24 and the buried n-well 25 form an isolated p-well 22 .
- the isolated p-well 22 includes a plurality of n-well plugs 27 extending from the surface into the isolated p-well 22 and contacting the buried n-well 25 .
- the plurality of n-well plugs 27 reduces an n-well resistance to provide better isolation for high frequency signals.
- FIG. 3 illustrates a top view of a portion of a semiconductor device 20 in accordance with the present invention.
- FIG. 4 illustrates a cross-sectional view of semiconductor device 20 of FIG. 3 along the line 4 - 4 .
- semiconductor device 20 includes a substrate 21 , deep n-well 25 , composite well ring 23 , and composite well ties 34 and 44 .
- An isolated p well 22 is formed by deep n-well 25 and n-well ring 24 .
- Composite well ring 23 includes n-well ring 24 , inter-well STI (shallow trench isolation) 26 , intra-well STI 30 , n+ active 29 , and p+ active 28 .
- inter-well STI shallow trench isolation
- Composite well tie 34 includes n-well plug 27 , p+ active 36 , inter-well STI 38 , n+ active 40 , and intra-well STI 42 .
- a plurality of composite well ties, similar to composite well tie 34 are spaced throughout isolated p-well 22 . However, for the purpose of illustration, only one other composite well tie, composite well tie 44 , is illustrated in FIGS. 3 and 4.
- Deep n-well 25 is first implanted in substrate 21 . Then, n-well ring 24 is implanted over deep n-well 25 to construct isolated p-well 22 . Inter-well STI 26 , intra-well STI 30 , n+ active 29 , and p+ active 28 are formed over n-well 24 and isolated p-well 22 . Composite-well ties 34 and 44 are formed at the same time, and with the same mask, as composite n-well ring 23 . The n-well plug 27 is formed at the same time as n-well ring 24 .
- the n-well plug 27 is doped with a concentration in a range of approximately 1 e17 atom/cm 3 to 1 e19 atom/cm 3
- the buried n-well 25 is doped with a concentration in a range of approximately 1 e17 atom/cm 3 to 5 e19 atom/cm 3
- p+ active 36 , inter-well STI 38 , n+ active 40 , and intra-well STI 42 are formed over n-well plug 27 .
- the p+ active 36 forms a guard ring around the n-well plugs to eliminate process sensitive leakage and to make the composite n-well ties more robust.
- each of the plurality of n-well plugs 34 have a length in a range of approximately 0.5 microns to 1.0 microns and a width in a range of approximately 0.5 microns to 1.0 microns.
- the composite n-well ties can be spaced further apart than 50 microns and may be spaced in an uneven manner to accommodate circuit layout or other concerns.
- the n-well plugs may have different lengths and widths.
- the n-well plug may be rectangular in shape forming a strip.
- Composite well ties 34 and 44 are used to make contact to the deep n-well 25 , and reduce the deep n-well resistance of buried n-well 25 by providing a plurality of parallel conductive paths though isolated p-well 22 . Also, composite well ties 34 and 44 can be implanted inside isolated p-well 22 using the same mask as n-well ring 24 . After p-well implantation, n+ active region 40 and p+ active region 36 are formed to make ohmic contact to the well. In the illustrated embodiment, both the composite well ring 23 and composite well ties 34 and 44 have a similar structure to achieve optimum signal isolation. As the frequency increases, a lumped well resistance Rw determines the amount of signal isolation.
- GHz gigahertz
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
- The present invention relates generally to semiconductor devices, and more particularly, to high frequency signal isolation in a semiconductor device.
- To reduce cost in integrated circuit design, it is desirable to include as much functionality as possible on a single integrated circuit. For example, in a low cost wireless communication system, it is desirable to include the RF (radio frequency) circuits on the same integrated circuit as the digital logic circuits. However, noise generated by the digital logic circuits can be injected into sensitive RF circuit blocks such as phase locked loops (PLL) and low noise amplifier circuits. Conceptually, an ideal Faraday cage prohibits external electromagnetic interference and provides perfect signal isolation. In an integrated circuit, implanted wells are used to reduce the effect of noise and to provide signal isolation. In a CMOS twin well process with a p-type substrate, the pn junction between n-well and p-type substrate provides some signal isolation for PMOS. The NMOS signal isolation is accomplished using a deep n+ implant (DNW) with an n-well to create an isolated p-well (IPW) pocket, and is sometimes referred to as a triple well process. Implanted wells as used to approximate a Faraday cage in integrated circuits, reduce the effect of noise. However, the use of implanted wells fails to provide adequate signal isolation at higher RF frequencies.
- FIG. 1 illustrates a top view of a prior
art semiconductor device 10. FIG. 2 illustrates a cross-sectional view of the priorart semiconductor device 10 of FIG. 1.Semiconductor device 10 hasa p substrate 18. A deep n-well implant 16 together with a n-well ring 15 creates an isolated p-well pocket 12. A plurality ofp+ well ties 14 is implanted in the surface of the isolated p-well 12. Electronic circuits are built into the surface of the isolated p-well (not shown). The isolated p-well 12 functions to isolate the circuits implemented in the well from circuits that are implemented outside of the well. However, the deep n-well implant 16 has a relatively high resistance that is undesirable for signal isolation in the RF frequency range. - FIG. 1 illustrates a top view of a prior art semiconductor device.
- FIG. 2 illustrates a cross-sectional view of the prior art semiconductor device of FIG. 1.
- FIG. 3 illustrates a top view of a semiconductor device in accordance with the present invention.
- FIG. 4 illustrates a cross-sectional view of the semiconductor device of FIG. 3.
- Generally, the present invention provides a
semiconductor device 20 having asubstrate 21, a buried n-well 25, and an n-well ring 24. The n-well ring 24 extends from a surface of thesemiconductor device 20 to the buried n-well 25. The n-wellring 24 and the buried n-well 25 form an isolated p-well 22. The isolated p-well 22 includes a plurality of n-well plugs 27 extending from the surface into the isolated p-well 22 and contacting the buried n-well 25. The plurality of n-well plugs 27 reduces an n-well resistance to provide better isolation for high frequency signals. - FIG. 3 illustrates a top view of a portion of a
semiconductor device 20 in accordance with the present invention. FIG. 4 illustrates a cross-sectional view ofsemiconductor device 20 of FIG. 3 along the line 4-4. Referring to both FIG. 3 and FIG. 4,semiconductor device 20 includes asubstrate 21, deep n-well 25,composite well ring 23, andcomposite well ties isolated p well 22 is formed by deep n-well 25 and n-wellring 24.Composite well ring 23 includes n-well ring 24, inter-well STI (shallow trench isolation) 26, intra-well STI 30, n+ active 29, and p+ active 28.Composite well tie 34 includes n-well plug 27, p+ active 36, inter-well STI 38, n+ active 40, and intra-well STI 42. A plurality of composite well ties, similar tocomposite well tie 34, are spaced throughout isolated p-well 22. However, for the purpose of illustration, only one other composite well tie,composite well tie 44, is illustrated in FIGS. 3 and 4. - Deep n-well25 is first implanted in
substrate 21. Then, n-well ring 24 is implanted over deep n-well 25 to construct isolated p-well 22. Inter-well STI 26, intra-well STI 30, n+ active 29, and p+ active 28 are formed over n-well 24 and isolated p-well 22. Composite-wellties ring 23. The n-well plug 27 is formed at the same time as n-wellring 24. The n-well plug 27 is doped with a concentration in a range of approximately 1 e17 atom/cm3 to 1 e19 atom/cm3, and the buried n-well 25 is doped with a concentration in a range of approximately 1 e17 atom/cm3 to 5 e19 atom/cm3 Then p+ active 36, inter-wellSTI 38, n+ active 40, andintra-well STI 42 are formed over n-well plug 27. The p+ active 36 forms a guard ring around the n-well plugs to eliminate process sensitive leakage and to make the composite n-well ties more robust. - Because of Ohm's parallel resistor law, more n-well ties in the isolated p-well results in lower resistance. However, the additional n-well ties reduce resistance at the cost of increased surface area of the integrated circuit. In the illustrated embodiment, the composite n-well ties are evenly spaced apart from each other at a distance of less than approximately 50 microns. Reducing n-well tie spacing, and thus increasing the number of n-well ties, results in better signal isolation quality. Each of the plurality of n-
well plugs 34 have a length in a range of approximately 0.5 microns to 1.0 microns and a width in a range of approximately 0.5 microns to 1.0 microns. In other embodiments, the composite n-well ties can be spaced further apart than 50 microns and may be spaced in an uneven manner to accommodate circuit layout or other concerns. Also, the n-well plugs may have different lengths and widths. For example, in one embodiment, the n-well plug may be rectangular in shape forming a strip. -
Composite well ties well 25, and reduce the deep n-well resistance of buried n-well 25 by providing a plurality of parallel conductive paths though isolated p-well 22. Also,composite well ties well 22 using the same mask as n-wellring 24. After p-well implantation, n+active region 40 and p+active region 36 are formed to make ohmic contact to the well. In the illustrated embodiment, both thecomposite well ring 23 andcomposite well ties - The lumped well resistance can be shown by the following equation: Rw =Rnw*Rpw/(Rnw+Rpw), where Rnw is the deep n-well resistance and Rpw is the isolated p-well resistance. At high frequencies, the lumped well resistance functions as a shunt resistor. Minimizing Rw improves noise isolation for frequencies up to about 10 gigahertz (GHz).
- Although the present invention has been described with reference to a specific embodiment, further modifications and improvements will occur to those skilled in the art. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.
Claims (21)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/003,535 US6563181B1 (en) | 2001-11-02 | 2001-11-02 | High frequency signal isolation in a semiconductor device |
KR1020047006727A KR100909346B1 (en) | 2001-11-02 | 2002-10-10 | High Frequency Signal Isolation in Semiconductor Devices |
EP02778496A EP1497858B1 (en) | 2001-11-02 | 2002-10-10 | High frequency signal isolation in a semiconductor device |
CNB028241436A CN1314098C (en) | 2001-11-02 | 2002-10-10 | High Frequency Signal Isolation in Semiconductor Devices |
JP2003543096A JP4579539B2 (en) | 2001-11-02 | 2002-10-10 | Semiconductor devices providing high frequency signal isolation |
PCT/US2002/032346 WO2003041161A2 (en) | 2001-11-02 | 2002-10-10 | High frequency signal isolation in a semiconductor device |
TW091125084A TW561550B (en) | 2001-11-02 | 2002-10-25 | High frequency signal isolation in a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/003,535 US6563181B1 (en) | 2001-11-02 | 2001-11-02 | High frequency signal isolation in a semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030085432A1 true US20030085432A1 (en) | 2003-05-08 |
US6563181B1 US6563181B1 (en) | 2003-05-13 |
Family
ID=21706319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/003,535 Expired - Lifetime US6563181B1 (en) | 2001-11-02 | 2001-11-02 | High frequency signal isolation in a semiconductor device |
Country Status (7)
Country | Link |
---|---|
US (1) | US6563181B1 (en) |
EP (1) | EP1497858B1 (en) |
JP (1) | JP4579539B2 (en) |
KR (1) | KR100909346B1 (en) |
CN (1) | CN1314098C (en) |
TW (1) | TW561550B (en) |
WO (1) | WO2003041161A2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050212071A1 (en) * | 2004-03-26 | 2005-09-29 | Honeywell International Inc. | Techniques to reduce substrate cross talk on mixed signal and RF circuit design |
US7138686B1 (en) | 2005-05-31 | 2006-11-21 | Freescale Semiconductor, Inc. | Integrated circuit with improved signal noise isolation and method for improving signal noise isolation |
US20080204135A1 (en) * | 2003-02-14 | 2008-08-28 | Hooman Darabi | Method and system for low noise amplifier (lna) gain adjustment through narrowband received signal strength indicator (nrssi) |
CN103199085A (en) * | 2012-01-10 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Dual DNW isolation structures for reducing RF noise on high voltage semiconductor devices |
Families Citing this family (21)
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US6710424B2 (en) | 2001-09-21 | 2004-03-23 | Airip | RF chipset architecture |
US20030234438A1 (en) * | 2002-06-24 | 2003-12-25 | Motorola, Inc. | Integrated circuit structure for mixed-signal RF applications and circuits |
US8089129B2 (en) * | 2002-08-14 | 2012-01-03 | Advanced Analogic Technologies, Inc. | Isolated CMOS transistors |
US7667268B2 (en) * | 2002-08-14 | 2010-02-23 | Advanced Analogic Technologies, Inc. | Isolated transistor |
US7825488B2 (en) | 2006-05-31 | 2010-11-02 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuits and modular methods of forming the same |
US7956391B2 (en) * | 2002-08-14 | 2011-06-07 | Advanced Analogic Technologies, Inc. | Isolated junction field-effect transistor |
US8513087B2 (en) * | 2002-08-14 | 2013-08-20 | Advanced Analogic Technologies, Incorporated | Processes for forming isolation structures for integrated circuit devices |
US7834421B2 (en) * | 2002-08-14 | 2010-11-16 | Advanced Analogic Technologies, Inc. | Isolated diode |
US6744112B2 (en) * | 2002-10-01 | 2004-06-01 | International Business Machines Corporation | Multiple chip guard rings for integrated circuit and chip guard ring interconnect |
US6891207B2 (en) * | 2003-01-09 | 2005-05-10 | International Business Machines Corporation | Electrostatic discharge protection networks for triple well semiconductor devices |
US7608913B2 (en) * | 2006-02-23 | 2009-10-27 | Freescale Semiconductor, Inc. | Noise isolation between circuit blocks in an integrated circuit chip |
US7881679B1 (en) | 2007-03-14 | 2011-02-01 | Rf Micro Devices, Inc. | Method and apparatus for integrating power amplifiers with phase locked loop in a single chip transceiver |
US7868414B2 (en) * | 2007-03-28 | 2011-01-11 | Advanced Analogic Technologies, Inc. | Isolated bipolar transistor |
US7651889B2 (en) | 2007-09-13 | 2010-01-26 | Freescale Semiconductor, Inc. | Electromagnetic shield formation for integrated circuit die package |
US8227902B2 (en) * | 2007-11-26 | 2012-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structures for preventing cross-talk between through-silicon vias and integrated circuits |
CN101635298B (en) * | 2009-06-10 | 2014-12-31 | 北京中星微电子有限公司 | Three-dimensional integrated circuit of planar technology |
US8546953B2 (en) * | 2011-12-13 | 2013-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit |
CN104332409B (en) * | 2014-11-05 | 2017-09-19 | 北京大学 | Isolate the preparation method of tunneling field-effect transistor based on deep N-well technique |
CN110880502B (en) * | 2018-09-05 | 2022-10-14 | 无锡华润上华科技有限公司 | Semiconductor structure and motor driving device |
JP7176676B2 (en) * | 2018-11-16 | 2022-11-22 | ミネベアミツミ株式会社 | detector |
KR20220167549A (en) | 2021-06-14 | 2022-12-21 | 삼성전자주식회사 | Semiconductor device including well region |
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JPS56120141A (en) * | 1980-02-27 | 1981-09-21 | Toshiba Corp | Semiconductor device |
JPS62177959A (en) * | 1986-01-31 | 1987-08-04 | Nec Corp | Semiconductor device |
JPH0353561A (en) * | 1989-07-21 | 1991-03-07 | Fujitsu Ltd | Semiconductor integrated circuit device |
US5027183A (en) * | 1990-04-20 | 1991-06-25 | International Business Machines | Isolated semiconductor macro circuit |
JPH04147668A (en) * | 1990-10-11 | 1992-05-21 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JP2976912B2 (en) * | 1997-01-13 | 1999-11-10 | 日本電気株式会社 | Semiconductor storage device |
JP2000021972A (en) * | 1998-07-03 | 2000-01-21 | Fujitsu Ltd | Semiconductor device |
US6349067B1 (en) * | 2001-01-30 | 2002-02-19 | International Business Machines Corporation | System and method for preventing noise cross contamination between embedded DRAM and system chip |
-
2001
- 2001-11-02 US US10/003,535 patent/US6563181B1/en not_active Expired - Lifetime
-
2002
- 2002-10-10 EP EP02778496A patent/EP1497858B1/en not_active Expired - Fee Related
- 2002-10-10 KR KR1020047006727A patent/KR100909346B1/en active IP Right Grant
- 2002-10-10 CN CNB028241436A patent/CN1314098C/en not_active Expired - Fee Related
- 2002-10-10 JP JP2003543096A patent/JP4579539B2/en not_active Expired - Fee Related
- 2002-10-10 WO PCT/US2002/032346 patent/WO2003041161A2/en active Application Filing
- 2002-10-25 TW TW091125084A patent/TW561550B/en not_active IP Right Cessation
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080204135A1 (en) * | 2003-02-14 | 2008-08-28 | Hooman Darabi | Method and system for low noise amplifier (lna) gain adjustment through narrowband received signal strength indicator (nrssi) |
US8301097B2 (en) * | 2003-02-14 | 2012-10-30 | Broadcom Corporation | Method and system for low noise amplifier (LNA) gain adjustment through narrowband received signal strength indicator (NRSSI) |
US20050212071A1 (en) * | 2004-03-26 | 2005-09-29 | Honeywell International Inc. | Techniques to reduce substrate cross talk on mixed signal and RF circuit design |
WO2005098937A1 (en) * | 2004-03-26 | 2005-10-20 | Honeywell International Inc. | Techniques to reduce substrate cross talk on mixed signal and rf circuit design |
US7851860B2 (en) | 2004-03-26 | 2010-12-14 | Honeywell International Inc. | Techniques to reduce substrate cross talk on mixed signal and RF circuit design |
US20110045652A1 (en) * | 2004-03-26 | 2011-02-24 | Honeywell International Inc. | Techniques to reduce substrate cross talk on mixed signal and rf circuit design |
US8058689B2 (en) | 2004-03-26 | 2011-11-15 | Yue Cheisan J | Techniques to reduce substrate cross talk on mixed signal and RF circuit design |
US7138686B1 (en) | 2005-05-31 | 2006-11-21 | Freescale Semiconductor, Inc. | Integrated circuit with improved signal noise isolation and method for improving signal noise isolation |
US20060267133A1 (en) * | 2005-05-31 | 2006-11-30 | Banerjee Suman K | Integrated circuit with improved signal noise isolation and method for improving signal noise isolation |
CN103199085A (en) * | 2012-01-10 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Dual DNW isolation structures for reducing RF noise on high voltage semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
KR20040053273A (en) | 2004-06-23 |
KR100909346B1 (en) | 2009-07-24 |
TW561550B (en) | 2003-11-11 |
JP2005536867A (en) | 2005-12-02 |
EP1497858A2 (en) | 2005-01-19 |
JP4579539B2 (en) | 2010-11-10 |
US6563181B1 (en) | 2003-05-13 |
CN1610966A (en) | 2005-04-27 |
WO2003041161A2 (en) | 2003-05-15 |
WO2003041161A3 (en) | 2003-11-13 |
EP1497858B1 (en) | 2011-09-28 |
CN1314098C (en) | 2007-05-02 |
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