US20030040146A1 - Mask for forming polysilicon and a method for fabricating thin film transistor using the same - Google Patents
Mask for forming polysilicon and a method for fabricating thin film transistor using the same Download PDFInfo
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- US20030040146A1 US20030040146A1 US10/135,066 US13506602A US2003040146A1 US 20030040146 A1 US20030040146 A1 US 20030040146A1 US 13506602 A US13506602 A US 13506602A US 2003040146 A1 US2003040146 A1 US 2003040146A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02678—Beam shaping, e.g. using a mask
- H01L21/0268—Shape of mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a method of fabricating liquid crystal display, and more particularly, to a mask for forming polysilicon and a method for fabricating thin film transistor using the same.
- a liquid crystal display has two substrates with electrodes, and a liquid crystal layer interposed between the two substrates.
- Each of the two substrates is sealed by a sealer while being spaced apart from each other by spacers.
- a voltage is applied to the electrodes so that the liquid crystal molecules in the liquid crystal layer are re-oriented to thereby control an amount of light transmission through the liquid crystal layer.
- Thin film transistors are provided at one of the substrates to control the signals transmitted to the electrodes.
- Amorphous silicon is typically used to form a semiconductor layer in the thin film transistors.
- current mobility of the amorphous silicon-based thin film transistor is low, at about 0.5-1 cm 2 /Vsec. This is inadequate for directly forming a driving circuit on a substrate.
- a polysilicon-based thin film transistor which has a relatively high current mobility of about 20-150 cm 2 /Vsec, has been developed to directly fabricate a driving circuit on the substrate.
- Various methods for forming a polysilicon thin film have been proposed, including: directly depositing polysilicon layer onto a substrate at a relatively high temperature; depositing amorphous silicon layer onto a substrate and crystallizing the amorphous silicon layer at a temperature of about 600° C.; and depositing amorphous silicon onto a substrate and heat-treating the amorphous silicon layer using laser.
- the polysilcon layer formed by using such high temperature has non-uniform crystalline particles, which deteriorate electrical characteristics of the thin film transistors, these methods are generally not applicable for substrates of liquid crystal display panels.
- a sequential lateral crystallization process where the distribution of crystalline particles can be controlled in an artificial manner has been developed.
- the sequential lateral crystallization process polysilicon grains are grown perpendicular to the interface between a laser-illuminated liquid phase region and a non-illuminated solid phase region.
- the laser beam passes through a mask having a slit-shaped transparent portion, then, a slit-shaped liquid phase region is formed at an amorphous silicon layer. Thereafter, the liquid phase amorphous silicon is crystallized while being cooled.
- the growth of crystalline begins from the boundary of the solid phase region, and stops at the center of the liquid phase region. Such a process is repeated with moving the mask in the growing direction of the polysilicon grains so that the sequential lateral crystallization is performed throughout the entire target area.
- the size of the polysilicon grains in the moving direction of about several micrometers can be obtained.
- a size of the polysilicon grains in the perpendicular direction of the moving direction is about several thousand angstroms.
- the sizes of the polysilicon grains in a peripheral region of the mask and an edge of the slit are non-uniform. Consequently, polysilicon thin film transistors exhibit anisotropic characteristics. For example, current mobility of the thin film transistors is largely differentiated in two directions.
- a mask for crystallization of amorphous silicon into polysilicon which includes a plurality of slit patterns for defining regions to be illuminated, wherein the plurality of slit patterns are formed along a longitudinal first direction and a mask moves along a longitudinal second direction and the first longitudinal direction being substantially perpendicular to the second longitudinal direction.
- each of the plurality of slit patterns is spaced apart by substantially a same distance from another.
- the mask includes a first region and a second region, the first region includes a first part of the plurality of slit patterns and the second region includes a second part of the plurality of slit patterns, the first part of the plurality of slit patterns is deviated from the second part of the plurality of slit patterns by one pitch, where the one pitch is a distance between the plurality of slit patterns.
- the mask includes a plurality of separate regions, each of the plurality of separate regions includes at least a portion of the plurality of slit patterns.
- a mask for crystallization of amorphous silicon into polysilicon which includes slit patterns for defining transmission regions of laser beams to be illuminated, wherein the slit patterns are arranged in first and second directions at two or more regions such that the polysilicon is grown in two or more directions.
- the first direction is substantially perpendicular to the second direction.
- the plurality of slit patterns are spaced apart with substantially the same distance.
- the mask includes a first region and a second region, the first region includes a first part of the plurality of slit patterns and the second region includes a second part of the plurality of slit patterns, the first part of the plurality of slit patterns is perpendicular to the second part of the plurality of slit patterns.
- Each of the first region and the second region has at least two portions.
- the two portions of the first region include the first part of the plurality of slit patterns deviated each other by one pitch, wherein the one pitch is a distance between the slit patterns.
- the two portions of the second region include the second part of the plurality of slit patterns deviated each other by one pitch, where the one pitch is a distance between the slit patterns.
- a method of a fabricating a thin film transistor is also provided.
- An amorphous silicon thin film is first formed on an insulating substrate.
- the amorphous silicon thin film is crystallized through a sequential lateral crystallization process to thereby form a semiconductor layer.
- the sequential lateral crystallization process is performed using a mask where slit patterns for defining transmission regions are arranged in first and second directions at two or more regions. The second direction is perpendicular to the first direction.
- a gate insulating layer is formed on the semiconductor layer such that the gate insulating layer covers the semiconductor layer.
- a gate electrode is formed on the gate insulating layer over the semiconductor layer. Impurities are implanted into the semiconductor layer to thereby form a source region and a drain region.
- An ohmic contract layer is formed such that the ohmic contact layer covers the gate electrode.
- the ohmic contact layer and the gate insulating layer are sequentially etched to thereby form contact holes exposing the source and the drain regions, respectively.
- Source and drain electrodes are formed such that the source and drain electrodes are connected to the source and the drain regions through the contact holes.
- the method further includes the step of forming a pixel electrode such that the pixel electrode is connected to the drain electrode.
- the gate insulating layer is preferably formed of silicon oxide or silicon nitride.
- the source and drain regions are preferably doped with n-type or p-type impurities.
- the pixel electrode is formed with transparent conductive material or reflective conductive material.
- the transparent conductive material includes ITO (indium tin oxide) or IZO (indium zinc oxide).
- FIG. 1 illustrates a sequential lateral crystallization process where amorphous silicon is crystallized into polysilicon through illuminating laser thereto;
- FIGS. 2A to 2 C are micro-structures of polysilicon grains during crystallizing amorphous silicon into polysilicon through the sequential lateral crystallization process;
- FIG. 3A is a plan view illustrating the structure of a mask for crystallizing amorphous silicon into polysilicon according to an embodiment of the present invention
- FIG. 3B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 3A;
- FIG. 4A is a plan view illustrating the structure of a mask for crystallizing amorphous silicon into polysilicon according to another embodiment of the present invention.
- FIG. 4B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 4A;
- FIG. 5 is a cross sectional view of a polysilicon thin film transistor fabricated by using the mask of FIG. 3A or 4 A;
- FIGS. 6A to 6 E are the steps of fabricating the polysilicon thin film transistor shown in FIG. 5.
- FIG. 1 is a sequential lateral crystallization process where amorphous silicon is crystallized into polysilicon
- FIGS. 2A to 2 C are micro-structures of polysilicon grains during crystallizing the amorphous silicon into the polysilicon through the sequential lateral crystallization process.
- an amorphous silicon layer 200 is formed on an insulating substrate, and laser beams are illuminated onto an amorphous silicon layer 200 using a mask 300 having a transparent region 310 .
- the amorphous silicon layer 200 corresponding to the transparent region 310 of the mask 300 is completely melted while forming a liquid phase region 210 at the amorphous silicon layer 200 .
- a non-transparent region of the amorphous silicon layer 200 exists as a solid phase region 220 .
- polysilicon grains are grown substantially perpendicular to an interface between the laser-illuminated liquid phase region 210 and the non-illuminated solid phase region 220 .
- the growth of polysilicon grain stops at substantially the center of the liquid phase region 210 .
- the laser beams are illuminated onto the amorphous silicon layer 200 while moving the mask 300 in the growing direction of the polysilicon grains, the lateral growth of polysilicon grains continuously proceeds so that the desired particle sizes can be obtained.
- FIG. 2A is a structure of polysilicon grains when the sequential lateral crystallization process is performed using a mask having a slit pattern proceeding in the horizontal direction. As shown in FIG. 2A, the polysilicon grains are grown perpendicular to the slit pattern while proceeding along the vertical direction.
- FIG. 2B is a structure of polysilicon grains when the sequential lateral crystallization process is performed using a mask having a slit pattern proceeding along the vertical direction. As shown in FIG. 2B, the polysilicon grains are grown perpendicular to the slit pattern while proceeding along the horizontal direction.
- a sequential lateral crystallization process is performed using a mask having slit patterns in the horizontal and vertical directions.
- polysilicon grains are grown to be isotropic with respect to the horizontal and vertical directions as shown in FIG. 2C.
- the polysilicon grains are one-directionally grown using the one-directional slit pattern, and then other-directionally grown using the other-directional slit pattern.
- the polysilicon grains one-directionally grown through first laser illumination become seeds, and the seeds are grown through second laser illumination perpendicular to the first growing direction. Accordingly, as shown in FIG. 2C, the resulting polysilicon grains are grown in the horizontal and vertical directions.
- the sequential lateral crystallization process is performed using a mask having slit patterns along the horizontal and vertical directions.
- the mask should be aligned to overlap edge portions to prevent misalignment while moving the mask.
- FIG. 3A is a plan view of a mask for crystallizing amorphous silicon into polysilicon according to an embodiment of the present invention.
- FIG. 3B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 3A.
- the mask includes a first vertical slit region 101 having a plurality of first slit patterns 11 in a vertical direction and a second vertical slit region 102 having a plurality of second slit patterns 12 in a vertical direction.
- Each of the plurality of first and second slit patterns 11 and 12 is spaced apart from each other with substantially the same distance (called “pitch”) at each of the first vertical slit region 101 and the second vertical slit region 102 .
- Each of the plurality of first slit patterns 11 is deviated from each of the plurality of second slit patterns 12 by one pitch.
- the sequential lateral crystallization process is performed through illuminating laser beams onto a target area while moving the mask for growing polysilicon grains.
- the mask moves horizontally but in a perpendicular direction from the plurality of first and second slit patterns 11 and 12 . Consequently, the polysilicon grains are grown from the interface between the laser illuminated region which is a liquid region and the laser non-illuminated region which is a solid region.
- the growing direction of the polysilicon grains is perpendicular to the interface between the laser illuminated region and the laser non-illuminated region and is perpendicular to the direction of the plurality of slit patterns 11 and 12 as shown in FIG. 3B.
- boundaries G of the polysilicon grains are in a vertical direction. That is, if the plurality of first and second slit patterns 11 and 12 are formed in a direction perpendicular to the mask moving direction, the boundaries G of the polysilicon grains are also formed in a perpendicular direction from the mask moving direction. Therefore, when the mask moves for in subsequent steps, the boundaries G of the polysilicon grains formed at the different steps are deviated from each other, but uniformly spaced apart from each other and with the same distance. Accordingly, even though channel regions C of thin film transistors are formed at any location, the channel regions C have substantially the same number of the polysilicon grains' boundaries, thereby fabricating thin film transistors having uniform characteristics.
- the mask of the present invention includes the first vertical slit region 101 and the second vertical slit region 102 , but are not limited to these regions and may include a further plurality of slit regions.
- FIG. 4A is a plan view of a mask for crystallizing amorphous silicon into polysilicon according to another embodiment of the present invention.
- FIG. 4B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 4A.
- the mask includes first and second vertical slit regions 101 and 102 where a plurality of first slit patterns 11 and a plurality of second slit patterns 12 are respectively arranged in a horizontal direction, and first and second horizontal slit regions 103 and 104 where a plurality of third slit patterns 13 and a plurality of fourth slit patterns 14 are respectively arranged in a vertical direction.
- the plurality of first slit patterns 11 of the first vertical slit region 101 and the plurality of second slit patterns 12 of the second vertical slit region 102 are deviated from each other by one pitch therebetween.
- the plurality of third slit patterns 13 and the plurality of fourth slit patterns 14 are also deviated from each other by one pitch therebetween.
- the sequential lateral crystallization process is performed through illuminating laser beams onto a target area while moving the mask by the distance of d/4 when the width of the mask is d.
- the polysilicon grains are grown twice in the horizontal direction due to the deviation between the plurality of first slit patterns 11 and the plurality of second slit patterns 12 .
- the polysilicon grains are grown twice in the vertical direction due to the deviation between the plurality of third slit patterns 13 and the plurality of fourth slit patterns 14 . In this way, the polysilicon grains are grown to be isotropic with respect to the horizontal and vertical directions as shown in FIG. 4B.
- the thin film transistor using the resulting polysilicon can have isotropic current mobility in vertical and horizontal directions.
- characteristics of the thin film transistors such as current mobility can be uniformly obtained even if they are arranged in various directions.
- the respective slit patterns are deviated from each other while dividing the horizontal and vertical slit regions into n-numbered multi-regions.
- FIG. 5 is a cross sectional view of a polysilicon thin film transistor according to a preferred embodiment of the present invention.
- a semiconductor layer 20 is formed on an insulating substrate 10 .
- the semiconductor layer 20 is formed of polysilicon.
- the semiconductor layer 20 includes source and drain regions 22 and 23 while interposing a channel region 21 .
- the source and the drain regions 22 and 23 are doped with n-type or p-type impurities.
- the source and the drain regions 22 and 23 can include a silicide layer.
- a gate insulating layer 30 is formed on the substrate 10 having the semiconductor layer 20 .
- the gate insulating layer 30 is formed of silicon oxide SiO 2 , silicon nitride SiN x , or the like.
- a gate electrode 40 is formed on the gate insulating layer 30 over the channel region 21 .
- An inter-layered insulating layer 50 is formed on the gate insulating layer 30 while covering the gate electrode 40 .
- the gate insulating layer 30 and the inter-layered insulating layer 50 have contact holes 52 and 53 exposing the source and the drain regions 22 and 23 of the semiconductor layer 20 .
- a source electrode 62 is formed on the inter-layered insulating layer 50 such that it is connected to the source region 22 through the contact hole 52 .
- a drain electrode 63 is also formed on the inter-layered insulating layer 50 such that it is connected to the drain region 23 through the contact hole 53 while facing the source electrode 62 around the gate electrode 40 .
- a passivation layer 70 covers the inter-layered insulating layer 50 with a contact hole 73 exposing the drain electrode 63 .
- a pixel electrode 80 is formed on the passivation layer 70 .
- the pixel electrode 80 is formed of transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), or reflective conductive material. The pixel electrode 80 is connected to the drain electrode 63 through the contact hole 73 .
- FIGS. 6A to 6 E illustrate sequential steps of fabricating the polysilicon thin film transistor shown in FIG. 5. This method is also applicable for fabricating a semiconductor device.
- an amorphous silicon thin film 25 is formed on an insulating substrate 10 through depositing amorphous silicon onto the substrate 10 using techniques such as low pressure chemical vapor deposition, plasma chemical vapor deposition, or sputtering, and then patterning.
- FIG. 6B laser beams are illuminated onto the amorphous silicon thin film 25 (in FIG. 6A) using a mask described in FIGS. 3A or 4 A, to thereby form a polysilicon semiconductor layer 20 .
- a sequential lateral crystallization process is performed as described above.
- FIG. 6C a gate insulating layer 30 is formed on the semiconductor layer 20 through depositing silicon oxide or silicon nitride onto the substrate 10 .
- conductive material is deposited onto the gate insulating layer 30 , and patterned to thereby form a gate electrode 40 .
- n-type or p-type impurities are ion-implanted into the semiconductor layer 20 using the gate electrode 40 as a mask, and thereby to form source and drain regions 22 and 23 .
- a channel region 21 is also formed between the source and the drain regions 22 and 23 .
- an inter-layered insulating layer 50 is formed on the gate insulating layer 30 such that it covers the gate electrode 40 , and patterned together with the gate insulating layer 30 to thereby form contact holes 52 and 53 , exposing the source and the drain regions 22 and 23 of the semiconductor layer 20 .
- a data line assembly metallic layer is deposited onto the insulating substrate 10 having the contact holes 52 and 53 , and patterned to thereby form source and drain electrodes 62 and 63 .
- the source and the drain electrodes 62 and 63 are connected to the source and the drain regions 22 and 23 through the contact holes 52 and 53 , respectively.
- a passivation layer 70 is deposited onto the substrate 10 having the source and the drain electrodes 62 and 63 , and patterned to thereby form a contact hole exposing the drain electrode 63 .
- a pixel electrode 80 is then formed on the passivation layer 70 through depositing transparent conductive material such as ITO and IZO or reflective conductive material onto the passivation layer 70 , and then patterning.
- amorphous silicon is crystallized into polysilicon using a mask having a slit pattern in the horizontal and vertical directions. Consequently, the polysilicon grains are grown to be isotropic with respect to the horizontal and vertical directions. As the resulting polysilicon thin film transistor has isotropic current mobility with respect to the horizontal and vertical directions, the characteristics of the thin film transistor can be uniformly obtained even if they are arranged in various directions.
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Abstract
A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.
Description
- (a) Field of the Invention
- The present invention relates to a method of fabricating liquid crystal display, and more particularly, to a mask for forming polysilicon and a method for fabricating thin film transistor using the same.
- (b) Description of the Related Art
- Generally, a liquid crystal display has two substrates with electrodes, and a liquid crystal layer interposed between the two substrates. Each of the two substrates is sealed by a sealer while being spaced apart from each other by spacers. A voltage is applied to the electrodes so that the liquid crystal molecules in the liquid crystal layer are re-oriented to thereby control an amount of light transmission through the liquid crystal layer. Thin film transistors are provided at one of the substrates to control the signals transmitted to the electrodes.
- Amorphous silicon is typically used to form a semiconductor layer in the thin film transistors. Generally, current mobility of the amorphous silicon-based thin film transistor is low, at about 0.5-1 cm2/Vsec. This is inadequate for directly forming a driving circuit on a substrate. Thus, a polysilicon-based thin film transistor, which has a relatively high current mobility of about 20-150 cm2/Vsec, has been developed to directly fabricate a driving circuit on the substrate.
- Various methods for forming a polysilicon thin film have been proposed, including: directly depositing polysilicon layer onto a substrate at a relatively high temperature; depositing amorphous silicon layer onto a substrate and crystallizing the amorphous silicon layer at a temperature of about 600° C.; and depositing amorphous silicon onto a substrate and heat-treating the amorphous silicon layer using laser. However, as the polysilcon layer formed by using such high temperature has non-uniform crystalline particles, which deteriorate electrical characteristics of the thin film transistors, these methods are generally not applicable for substrates of liquid crystal display panels.
- A sequential lateral crystallization process where the distribution of crystalline particles can be controlled in an artificial manner has been developed. In the sequential lateral crystallization process, polysilicon grains are grown perpendicular to the interface between a laser-illuminated liquid phase region and a non-illuminated solid phase region. The laser beam passes through a mask having a slit-shaped transparent portion, then, a slit-shaped liquid phase region is formed at an amorphous silicon layer. Thereafter, the liquid phase amorphous silicon is crystallized while being cooled. The growth of crystalline begins from the boundary of the solid phase region, and stops at the center of the liquid phase region. Such a process is repeated with moving the mask in the growing direction of the polysilicon grains so that the sequential lateral crystallization is performed throughout the entire target area.
- In the case wherein the sequential lateral crystallization is performed while moving the mask only in the growing direction of the polysilicon grains, the size of the polysilicon grains in the moving direction of about several micrometers can be obtained. However, a size of the polysilicon grains in the perpendicular direction of the moving direction is about several thousand angstroms. Furthermore, the sizes of the polysilicon grains in a peripheral region of the mask and an edge of the slit are non-uniform. Consequently, polysilicon thin film transistors exhibit anisotropic characteristics. For example, current mobility of the thin film transistors is largely differentiated in two directions.
- Thus, it is desirable to provide a method of fabricating a polysilicon layer and thin film transistors having isotropic current mobility.
- A mask for crystallization of amorphous silicon into polysilicon is provided, which includes a plurality of slit patterns for defining regions to be illuminated, wherein the plurality of slit patterns are formed along a longitudinal first direction and a mask moves along a longitudinal second direction and the first longitudinal direction being substantially perpendicular to the second longitudinal direction.
- According to an embodiment of the present invention, each of the plurality of slit patterns is spaced apart by substantially a same distance from another. The mask includes a first region and a second region, the first region includes a first part of the plurality of slit patterns and the second region includes a second part of the plurality of slit patterns, the first part of the plurality of slit patterns is deviated from the second part of the plurality of slit patterns by one pitch, where the one pitch is a distance between the plurality of slit patterns.
- According to an embodiment of the present invention, the mask includes a plurality of separate regions, each of the plurality of separate regions includes at least a portion of the plurality of slit patterns.
- A mask for crystallization of amorphous silicon into polysilicon is also provided, which includes slit patterns for defining transmission regions of laser beams to be illuminated, wherein the slit patterns are arranged in first and second directions at two or more regions such that the polysilicon is grown in two or more directions. The first direction is substantially perpendicular to the second direction.
- According to an embodiment of the present invention, the plurality of slit patterns are spaced apart with substantially the same distance. The mask includes a first region and a second region, the first region includes a first part of the plurality of slit patterns and the second region includes a second part of the plurality of slit patterns, the first part of the plurality of slit patterns is perpendicular to the second part of the plurality of slit patterns. Each of the first region and the second region has at least two portions. The two portions of the first region include the first part of the plurality of slit patterns deviated each other by one pitch, wherein the one pitch is a distance between the slit patterns. The two portions of the second region include the second part of the plurality of slit patterns deviated each other by one pitch, where the one pitch is a distance between the slit patterns.
- A method of a fabricating a thin film transistor is also provided. An amorphous silicon thin film is first formed on an insulating substrate. The amorphous silicon thin film is crystallized through a sequential lateral crystallization process to thereby form a semiconductor layer. The sequential lateral crystallization process is performed using a mask where slit patterns for defining transmission regions are arranged in first and second directions at two or more regions. The second direction is perpendicular to the first direction. A gate insulating layer is formed on the semiconductor layer such that the gate insulating layer covers the semiconductor layer. A gate electrode is formed on the gate insulating layer over the semiconductor layer. Impurities are implanted into the semiconductor layer to thereby form a source region and a drain region. An ohmic contract layer is formed such that the ohmic contact layer covers the gate electrode. The ohmic contact layer and the gate insulating layer are sequentially etched to thereby form contact holes exposing the source and the drain regions, respectively. Source and drain electrodes are formed such that the source and drain electrodes are connected to the source and the drain regions through the contact holes.
- According to an embodiment of the present invention, the method further includes the step of forming a pixel electrode such that the pixel electrode is connected to the drain electrode. The gate insulating layer is preferably formed of silicon oxide or silicon nitride. The source and drain regions are preferably doped with n-type or p-type impurities. The pixel electrode is formed with transparent conductive material or reflective conductive material. The transparent conductive material includes ITO (indium tin oxide) or IZO (indium zinc oxide).
- A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or the similar components, wherein:
- FIG. 1 illustrates a sequential lateral crystallization process where amorphous silicon is crystallized into polysilicon through illuminating laser thereto;
- FIGS. 2A to2C are micro-structures of polysilicon grains during crystallizing amorphous silicon into polysilicon through the sequential lateral crystallization process;
- FIG. 3A is a plan view illustrating the structure of a mask for crystallizing amorphous silicon into polysilicon according to an embodiment of the present invention;
- FIG. 3B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 3A;
- FIG. 4A is a plan view illustrating the structure of a mask for crystallizing amorphous silicon into polysilicon according to another embodiment of the present invention;
- FIG. 4B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 4A;
- FIG. 5 is a cross sectional view of a polysilicon thin film transistor fabricated by using the mask of FIG. 3A or4A; and
- FIGS. 6A to6E are the steps of fabricating the polysilicon thin film transistor shown in FIG. 5.
- Preferred embodiments of this invention will be explained with reference to the accompanying drawings.
- FIG. 1 is a sequential lateral crystallization process where amorphous silicon is crystallized into polysilicon, and FIGS. 2A to2C are micro-structures of polysilicon grains during crystallizing the amorphous silicon into the polysilicon through the sequential lateral crystallization process.
- Referring to FIG. 1, an
amorphous silicon layer 200 is formed on an insulating substrate, and laser beams are illuminated onto anamorphous silicon layer 200 using amask 300 having atransparent region 310. Theamorphous silicon layer 200 corresponding to thetransparent region 310 of themask 300 is completely melted while forming aliquid phase region 210 at theamorphous silicon layer 200. A non-transparent region of theamorphous silicon layer 200 exists as asolid phase region 220. At this time, polysilicon grains are grown substantially perpendicular to an interface between the laser-illuminatedliquid phase region 210 and the non-illuminatedsolid phase region 220. The growth of polysilicon grain stops at substantially the center of theliquid phase region 210. When the laser beams are illuminated onto theamorphous silicon layer 200 while moving themask 300 in the growing direction of the polysilicon grains, the lateral growth of polysilicon grains continuously proceeds so that the desired particle sizes can be obtained. - FIG. 2A is a structure of polysilicon grains when the sequential lateral crystallization process is performed using a mask having a slit pattern proceeding in the horizontal direction. As shown in FIG. 2A, the polysilicon grains are grown perpendicular to the slit pattern while proceeding along the vertical direction.
- FIG. 2B is a structure of polysilicon grains when the sequential lateral crystallization process is performed using a mask having a slit pattern proceeding along the vertical direction. As shown in FIG. 2B, the polysilicon grains are grown perpendicular to the slit pattern while proceeding along the horizontal direction.
- According to an embodiment of the present invention, a sequential lateral crystallization process is performed using a mask having slit patterns in the horizontal and vertical directions. Then, polysilicon grains are grown to be isotropic with respect to the horizontal and vertical directions as shown in FIG. 2C. The polysilicon grains are one-directionally grown using the one-directional slit pattern, and then other-directionally grown using the other-directional slit pattern. In this case, the polysilicon grains one-directionally grown through first laser illumination become seeds, and the seeds are grown through second laser illumination perpendicular to the first growing direction. Accordingly, as shown in FIG. 2C, the resulting polysilicon grains are grown in the horizontal and vertical directions. That is, to isotropically grow the polysilicon grains in the horizontal and vertical directions, the sequential lateral crystallization process is performed using a mask having slit patterns along the horizontal and vertical directions. During the crystallization process, the mask should be aligned to overlap edge portions to prevent misalignment while moving the mask.
- FIG. 3A is a plan view of a mask for crystallizing amorphous silicon into polysilicon according to an embodiment of the present invention. FIG. 3B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 3A.
- Referring to FIG. 3A, the mask includes a first
vertical slit region 101 having a plurality offirst slit patterns 11 in a vertical direction and a secondvertical slit region 102 having a plurality ofsecond slit patterns 12 in a vertical direction. Each of the plurality of first andsecond slit patterns vertical slit region 101 and the secondvertical slit region 102. Each of the plurality offirst slit patterns 11 is deviated from each of the plurality ofsecond slit patterns 12 by one pitch. - The sequential lateral crystallization process is performed through illuminating laser beams onto a target area while moving the mask for growing polysilicon grains. According to an embodiment of the present invention, the mask moves horizontally but in a perpendicular direction from the plurality of first and
second slit patterns slit patterns second slit patterns second slit patterns second slit patterns vertical slit region 101 and the secondvertical slit region 102, but are not limited to these regions and may include a further plurality of slit regions. - FIG. 4A is a plan view of a mask for crystallizing amorphous silicon into polysilicon according to another embodiment of the present invention. FIG. 4B is a micro-structure of polysilicon grains crystallized by using the mask of FIG. 4A.
- Referring to FIG. 4A, the mask includes first and second
vertical slit regions first slit patterns 11 and a plurality ofsecond slit patterns 12 are respectively arranged in a horizontal direction, and first and secondhorizontal slit regions third slit patterns 13 and a plurality offourth slit patterns 14 are respectively arranged in a vertical direction. The plurality offirst slit patterns 11 of the firstvertical slit region 101 and the plurality ofsecond slit patterns 12 of the secondvertical slit region 102 are deviated from each other by one pitch therebetween. The plurality ofthird slit patterns 13 and the plurality offourth slit patterns 14 are also deviated from each other by one pitch therebetween. - The sequential lateral crystallization process is performed through illuminating laser beams onto a target area while moving the mask by the distance of d/4 when the width of the mask is d. According to an embodiment of the present invention, the polysilicon grains are grown twice in the horizontal direction due to the deviation between the plurality of
first slit patterns 11 and the plurality ofsecond slit patterns 12. Furthermore, the polysilicon grains are grown twice in the vertical direction due to the deviation between the plurality ofthird slit patterns 13 and the plurality offourth slit patterns 14. In this way, the polysilicon grains are grown to be isotropic with respect to the horizontal and vertical directions as shown in FIG. 4B. Accordingly, the thin film transistor using the resulting polysilicon can have isotropic current mobility in vertical and horizontal directions. As a result, when the thin film transistors are formed on a liquid crystal display panel, characteristics of the thin film transistors such as current mobility can be uniformly obtained even if they are arranged in various directions. - Alternatively, it is possible that the respective slit patterns are deviated from each other while dividing the horizontal and vertical slit regions into n-numbered multi-regions.
- FIG. 5 is a cross sectional view of a polysilicon thin film transistor according to a preferred embodiment of the present invention. Referring to FIG. 5, a
semiconductor layer 20 is formed on an insulatingsubstrate 10. Preferably, thesemiconductor layer 20 is formed of polysilicon. Thesemiconductor layer 20 includes source and drainregions channel region 21. The source and thedrain regions drain regions gate insulating layer 30 is formed on thesubstrate 10 having thesemiconductor layer 20. Preferably, thegate insulating layer 30 is formed of silicon oxide SiO2, silicon nitride SiNx, or the like. Agate electrode 40 is formed on thegate insulating layer 30 over thechannel region 21. An inter-layered insulatinglayer 50 is formed on thegate insulating layer 30 while covering thegate electrode 40. Thegate insulating layer 30 and the inter-layered insulatinglayer 50 havecontact holes drain regions semiconductor layer 20. Asource electrode 62 is formed on the inter-layered insulatinglayer 50 such that it is connected to thesource region 22 through thecontact hole 52. Adrain electrode 63 is also formed on the inter-layered insulatinglayer 50 such that it is connected to thedrain region 23 through thecontact hole 53 while facing thesource electrode 62 around thegate electrode 40. Apassivation layer 70 covers the inter-layered insulatinglayer 50 with acontact hole 73 exposing thedrain electrode 63. Apixel electrode 80 is formed on thepassivation layer 70. Preferably, thepixel electrode 80 is formed of transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), or reflective conductive material. Thepixel electrode 80 is connected to thedrain electrode 63 through thecontact hole 73. - FIGS. 6A to6E illustrate sequential steps of fabricating the polysilicon thin film transistor shown in FIG. 5. This method is also applicable for fabricating a semiconductor device.
- Referring to FIG. 6A, an amorphous silicon
thin film 25 is formed on an insulatingsubstrate 10 through depositing amorphous silicon onto thesubstrate 10 using techniques such as low pressure chemical vapor deposition, plasma chemical vapor deposition, or sputtering, and then patterning. - Referring to FIG. 6B, laser beams are illuminated onto the amorphous silicon thin film25 (in FIG. 6A) using a mask described in FIGS. 3A or 4A, to thereby form a
polysilicon semiconductor layer 20. In this step, a sequential lateral crystallization process is performed as described above.. Thereafter, as shown in FIG. 6C, agate insulating layer 30 is formed on thesemiconductor layer 20 through depositing silicon oxide or silicon nitride onto thesubstrate 10. Subsequently, conductive material is deposited onto thegate insulating layer 30, and patterned to thereby form agate electrode 40. - Then, n-type or p-type impurities are ion-implanted into the
semiconductor layer 20 using thegate electrode 40 as a mask, and thereby to form source and drainregions channel region 21 is also formed between the source and thedrain regions - Referring to FIG. 6D, an inter-layered insulating
layer 50 is formed on thegate insulating layer 30 such that it covers thegate electrode 40, and patterned together with thegate insulating layer 30 to thereby form contact holes 52 and 53, exposing the source and thedrain regions semiconductor layer 20. - Referring to FIG. 6E, a data line assembly metallic layer is deposited onto the insulating
substrate 10 having the contact holes 52 and 53, and patterned to thereby form source and drainelectrodes drain electrodes drain regions - Finally, as shown in FIG. 5, a
passivation layer 70 is deposited onto thesubstrate 10 having the source and thedrain electrodes drain electrode 63. Apixel electrode 80 is then formed on thepassivation layer 70 through depositing transparent conductive material such as ITO and IZO or reflective conductive material onto thepassivation layer 70, and then patterning. - As described above, amorphous silicon is crystallized into polysilicon using a mask having a slit pattern in the horizontal and vertical directions. Consequently, the polysilicon grains are grown to be isotropic with respect to the horizontal and vertical directions. As the resulting polysilicon thin film transistor has isotropic current mobility with respect to the horizontal and vertical directions, the characteristics of the thin film transistor can be uniformly obtained even if they are arranged in various directions.
- While the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications and substitutions can be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.
Claims (20)
1. A mask for crystallization of amorphous silicon into polysilicon, the mask comprising a plurality of slit patterns for defining regions to be illuminated, wherein the plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction, the first longitudinal direction being substantially perpendicular to the second longitudinal direction.
2. The mask of claim 1 , wherein each of the plurality of slit patterns is spaced apart by substantially a same distance from another.
3. The mask of claim 2 , wherein the mask comprises a first region and a second region, the first region comprises a first part of the plurality of slit patterns and the second region comprises a second part of the plurality of slit patterns, the first part of the plurality of slit patterns is deviated from the second part of the plurality of slit patterns by one pitch, where the one pitch is a distance between the plurality of slit patterns.
4. The mask of claim 1 , wherein the mask comprises a plurality of separate regions, each of the plurality of separate regions comprises at least a portion of the plurality of slit patterns.
5. A mask for crystallization of amorphous silicon into polysilicon, the mask comprising a plurality of slit patterns for defining transmission regions to be illuminated, wherein the plurality of slit patterns are arranged in first and second directions at two or more regions in the mask such that the polysilicon are grown in two or more directions.
6. The mask of claim 5 , wherein the first direction is substantially perpendicular to the second direction.
7. The mask of claim 5 , wherein the plurality of slit patterns are spaced apart with substantially the same distance.
8. The mask of claim 7 , wherein the mask comprises a first region and a second region, the first region comprises a first part of the plurality of slit patterns and the second region comprises a second part of the plurality of slit patterns, the first part of the plurality of slit patterns is perpendicular to the second part of the plurality of slit patterns.
9. The mask of claim 8 , wherein each of the first region and the second region has at least two portions.
10. The mask of claim 9 , wherein the two portions of the first region comprise the first part of the plurality of slit patterns deviated each other by one pitch, where the one pitch is a distance between the slit patterns.
11. The mask of claim 9 , wherein the two portions of the second region comprise the second part of the plurality of slit patterns deviated each other by one pitch, where the one pitch is a distance between the slit patterns.
12. A method of fabricating a thin film transistor, the method comprising the steps of:
forming an amorphous silicon on an insulating substrate; and
crystallizing the amorphous silicon through a sequential lateral crystallization process for forming a polysilicon layer.
13. The method of claim 12 , wherein the sequential lateral crystallization process is performed using a mask, the mask comprises a plurality of slit patterns for defining transmission regions to be illuminated, the plurality of slit patterns are substantially perpendicular to a mask moving direction.
14. The method of claim 12 , wherein the sequential lateral crystallization process is performed using a mask, the mask comprises a plurality of slit patterns for defining transmission regions to be illuminated, wherein the plurality of slit patterns are arranged in first and second directions in the mask such that the polysilicon are grown in two or more directions, and the first direction is substantially perpendicular to the second direction.
15. The method of claim 12 , further comprising the steps of:
forming a gate insulating layer on the polysilicon layer;
forming a gate electrode on the gate insulating layer over the polysilicon layer;
implanting impurities into the polysilicon layer for forming a source region and a drain region;
forming an inter-layered insulating layer such that the inter-layered insulating layer covers the gate electrode;
sequentially etching the inter-layered insulating layer and the gate insulating layer for forming contact holes exposing the source and the drain regions, respectively; and
forming source and drain electrodes connected to the source and the drain regions through the contact holes, respectively.
16. The method of claim 15 , wherein the gate insulating layer is formed of silicon oxide or silicon nitride.
17. The method of claim 15 , wherein the source and the drain regions are doped with n-type or p-type impurities.
18. The method of claim 15 , further comprising the step of forming a pixel electrode connected to the drain electrode.
19. The method of claim 18 , wherein the pixel electrode is formed with transparent conductive material or reflective conductive material.
20. The method of claim 19 , wherein the transparent conductive material comprises ITO (indium tin oxide) or IZO (indium zinc oxide).
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/854,664 US7335541B2 (en) | 2001-08-21 | 2004-05-26 | Method for fabricating thin film transistor using the mask for forming polysilicon including slit patterns deviated from each other |
US12/016,430 US7488633B2 (en) | 2001-08-21 | 2008-01-18 | Method for forming polysilicon by illuminating a laser beam at the amorphous silicon substrate through a mask |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2001-50421 | 2001-08-21 | ||
KR20010050421 | 2001-08-21 | ||
KR2002-7365 | 2002-02-08 | ||
KR1020020007365A KR100816344B1 (en) | 2001-08-21 | 2002-02-08 | A mask for forming polysilicon and method for manufacturing thin film transistor using the mask |
Related Child Applications (1)
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US10/854,664 Continuation US7335541B2 (en) | 2001-08-21 | 2004-05-26 | Method for fabricating thin film transistor using the mask for forming polysilicon including slit patterns deviated from each other |
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US20030040146A1 true US20030040146A1 (en) | 2003-02-27 |
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US10/135,066 Abandoned US20030040146A1 (en) | 2001-08-21 | 2002-04-29 | Mask for forming polysilicon and a method for fabricating thin film transistor using the same |
US10/854,664 Expired - Lifetime US7335541B2 (en) | 2001-08-21 | 2004-05-26 | Method for fabricating thin film transistor using the mask for forming polysilicon including slit patterns deviated from each other |
US12/016,430 Expired - Lifetime US7488633B2 (en) | 2001-08-21 | 2008-01-18 | Method for forming polysilicon by illuminating a laser beam at the amorphous silicon substrate through a mask |
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US10/854,664 Expired - Lifetime US7335541B2 (en) | 2001-08-21 | 2004-05-26 | Method for fabricating thin film transistor using the mask for forming polysilicon including slit patterns deviated from each other |
US12/016,430 Expired - Lifetime US7488633B2 (en) | 2001-08-21 | 2008-01-18 | Method for forming polysilicon by illuminating a laser beam at the amorphous silicon substrate through a mask |
Country Status (4)
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US (3) | US20030040146A1 (en) |
JP (1) | JP2003092262A (en) |
KR (1) | KR100816344B1 (en) |
TW (1) | TW527732B (en) |
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US20040180274A1 (en) * | 2001-06-01 | 2004-09-16 | Yun-Ho Jung | Silicon crystallization method |
US20040266146A1 (en) * | 2003-06-30 | 2004-12-30 | Jung Yun Ho | Laser crystallizing device and method for crystallizing silicon by using the same |
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US20060276013A1 (en) * | 2005-06-03 | 2006-12-07 | Au Optronics Corp. | Sequential lateral solidification mask |
US20070187846A1 (en) * | 2001-11-14 | 2007-08-16 | Myung-Koo Kang | Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask |
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Also Published As
Publication number | Publication date |
---|---|
KR20030017302A (en) | 2003-03-03 |
TW527732B (en) | 2003-04-11 |
US7335541B2 (en) | 2008-02-26 |
KR100816344B1 (en) | 2008-03-24 |
US7488633B2 (en) | 2009-02-10 |
US20040219768A1 (en) | 2004-11-04 |
US20080166892A1 (en) | 2008-07-10 |
JP2003092262A (en) | 2003-03-28 |
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