US20030036261A1 - Semiconductor device and fabricating method thereof - Google Patents

Semiconductor device and fabricating method thereof Download PDF

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US20030036261A1
US20030036261A1 US10/279,050 US27905002A US2003036261A1 US 20030036261 A1 US20030036261 A1 US 20030036261A1 US 27905002 A US27905002 A US 27905002A US 2003036261 A1 US2003036261 A1 US 2003036261A1
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film
diffusion
semiconductor device
preventing
wire
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Koji Hamada
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NEC Electronics Corp
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NEC Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor device and a fabricating method thereof, and more particularly, to a structure of an interlayer film in a high-density semiconductor device and a fabricating method thereof.
  • FIG. 9 A structure of the conventional semiconductor device using this Cu wire is shown in FIG. 9.
  • An interlayer film 400 comprising silicon oxide film 407 and BPSG film 409 is formed on a semiconductor substrate 401 in which an MOS transistor is formed.
  • the interlayer film 400 is provided with a contact hole 410 which reaches a diffusion layer 406 .
  • a W plug 412 is embedded in the contact hole 410 .
  • a Cu wire 414 is formed on the silicon oxide film 413 provided on the interlayer film 400 , and a Cu plug 419 and a Cu wire 420 are formed on a silicon oxide film 416 provided on the Cu wire 414 .
  • the Cu wire 415 is formed in such a manner that a wire groove 415 is formed in the silicon oxide film 413 , Cu film is formed in the wire groove 415 and on the silicon oxide film 413 , the Cu film on the silicon oxide film is removed by CMP (Chemical Mechanical Polishing), and the Cu film only in the groove 415 is left.
  • the Cu plug 419 and the Cu wire 420 are formed by a so-called dual damascene process in which a via hole 417 and a wire groove 418 are formed in the silicon oxide film 416 , Cu is embedded in the via hole 417 and the wire groove 418 , and unnecessary Cu is removed by the CMP.
  • a semiconductor having a diffusion-barrier film for example, is disclosed in Japanese Unexamined Patent Publication (KOKAI) No. 8-306694. However, this film does not solve the above mentioned problems.
  • the present invention provides a semiconductor device comprising an interlayer film formed on a semiconductor substrate, wherein the interlayer film includes a diffusion-preventing film for preventing metal impurities invading from an upper portion of the interlayer film from reaching the semiconductor substrate.
  • the invention also provides a fabricating method of a semiconductor device comprising the steps of: forming, on a semiconductor substrate, a diffusion-preventing film for preventing metal impurities invading from an upper portion of the semiconductor substrate from reaching the semiconductor substrate, forming an insulating film on the diffusion-preventing film, forming a wire groove in the insulating film, forming a metal film in the wire groove and on the insulating film, and removing the metal film deposited on said insulating film by a CMP such that the metal film is remained in the wire groove to form a metal wire.
  • the diffusion-preventing film may be a polysilicon film, an SIPOS film or such a film doped with boron (B) or phosphorus (P).
  • the interlayer film Since at least a portion of the interlayer film is provided with the diffusion-preventing film, even if the metal impurities such as copper (Cu) used as the metal wire or Fe included slurry during the CMP invades from the upper portion of the film, the metal impurities are gettered by the diffusion-preventing film, the metal impurities do not reach the semiconductor substrate. Therefore, it is possible to prevent the characteristics of the device formed on the semiconductor substrate from being deteriorated.
  • Cu copper
  • FIG. 1 is a sectional view of a structure of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a sectional view of a step of a fabricating method of the semiconductor device according to the first embodiment of the invention.
  • FIG. 3 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention.
  • FIG. 4 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention.
  • FIG. 5 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention.
  • FIG. 6 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention.
  • FIG. 7 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention.
  • FIG. 8 is a sectional view of a structure of a semiconductor device according to a second embodiment of the invention.
  • FIG. 9 is a sectional view of a structure of a conventional semiconductor device.
  • FIG. 1 is a sectional view of a semiconductor device of a first embodiment of the invention.
  • a device region is defined by a field oxide film 2 provided in a semiconductor substrate 1 .
  • An MOS transistor comprising a gate electrode 4 , a gate oxide film 3 and source/drain diffusion layers 6 is formed in the device region.
  • the gate electrode 4 is formed at its sidewalls with sidewall insulating films 5 .
  • An interlayer film 100 is provided for covering the MOS transistor. Contact holes 10 are provided on a diffusion layer 6 of the interlayer film 100 , and W plugs 12 are embedded in the contact holes 10 .
  • the interlayer film 100 is of a three-layer structure comprising a silicon oxide film 7 , a polysilicon film 8 and a BPSG film. Of these films, the polysilicon film 8 is a diffusion-preventing film of the present invention.
  • contact sidewall insulating films 11 are provided on inner walls of the contact holes 10 for preventing short-circuit.
  • Wire grooves 14 are provided in the contact holes 10 of an insulating film 13 formed on the interlayer film 100 , and Cu wires 15 are provided in the wire grooves 14 .
  • Via holes 17 and wire grooves 18 are provided on the Cu wires 15 formed in the insulating film 13 .
  • a Cu plug 19 and a Cu wire 20 are provided in the via hole 17 and the wire groove 18 , respectively.
  • FIGS. 2 to 7 A fabricating method of the semiconductor device according to the first embodiment of the invention will be explained using FIGS. 2 to 7 .
  • the interlayer film 100 comprising the silicon oxide film 7 , the polysilicon film 8 and the BPSG film 9 is deposited on the semiconductor substrate 1 , and an upper surface of the BPSG film 9 is flattened by reflowing or the CMP process. It is preferable that thickness of the silicon oxide film 7 is 50 to 500 nm, thickness of polysilicon film 8 is 20 to 100 nm, and thickness of the BPSG film 9 is 100 to 1000 nm.
  • the polysilicon film 8 is deposited by an LPCVD process using SiH 4 or Si 2 H 6 as raw gas. At that time, the polysilicon film 8 may be doped with impurities such as B and P.
  • the contact holes 10 are formed in the interlayer film 100 and the gate oxide film 3 so that upper surfaces of the diffusion layers 6 are exposed by the lithography technique and etching technique.
  • silicon oxide films 11 are formed on the inner walls of the contact holes 10 as the contact sidewall insulating films by the CVD process and then, the W films are embedded in the contact holes 10 , and the CMP is carried out to form the W plugs 12 .
  • the CMP is carried out to form the W plugs
  • heavy metals such as Fe included in the residual slurry on the interlayer film 100 is remained even after the cleaning step. Although the heavy metals are diffused toward the semiconductor substrate 1 in the subsequent thermal step, but since the interlayer film 100 includes the polysilicon film 8 according to the present invention, the Fe passing through the BPSG film 9 is gettered due to crystal defect of the polysilicon film 8 , and the Fe does not reach the semiconductor substrate 1 .
  • the silicon oxide film 13 thickness of which is 200 to 1500 nm, is deposited on the interlayer film 100 , and the wire grooves 14 are formed on the W plugs of the of the silicon oxide film 13 .
  • the Cu film 15 ′ is deposited so as to embed in the wire grooves 14 .
  • the Cu film 15 ′ is formed also on the silicon oxide film 13 .
  • a silicon oxide film 16 thickness of which is 200 to 1000 nm, is formed on the silicon oxide film 13 , the via holes 17 and the wire grooves 18 are formed in the silicon oxide film 16 by the lithography technique and etching technique, and a Cu film 20 ′ is formed such as to embed the via holes 17 and the wire grooves 18 .
  • unnecessary portion of the Cu film 20 ′ is removed by the CMP using slurry including ferric nitrate, thereby forming the Cu plugs 19 and the Cu wires 20 as shown in FIG. 1.
  • the interlayer film 100 is of the three-layer structure in which the polysilicon film 8 is sandwiched between the silicon oxide film 7 and the BPSG film 9 so as to obtain complete insulation. Further, the contact sidewall insulating film 11 is required for insulation also on the inner wall of the contact hole 10 . Therefore, the number of steps is increased as compared with the conventional technique shown in FIG. 9. A semiconductor device that does not increase the number of steps as compared with the conventional technique will be shown below as a second embodiment of the invention.
  • FIG. 8 is a sectional view of a structure of a semiconductor device according to the second embodiment of the invention.
  • an interlayer film 300 of a two-layer structure comprising a diffusion preventing film 308 and a BPSG film 9 is provided instead of the interlayer film 100 of the three-layer structure of the first embodiment.
  • An SIPOS (semi-insulating polycrystalline silicon) film is used as the diffusion preventing film 308 .
  • the SIPOS film is a polysilicon film including O or N, and this film is a high insulating film having high resistance equal to 1E11 ohm/cm 2 or higher.
  • the SIPOS film 308 can be formed directly on the semiconductor device, and it is unnecessary to provide the insulating film on the inner wall of the contact hole 10 . Therefore, the number of steps is not increased as compared with the conventional technique shown in FIG. 9. Since the SIPOS film 308 also includes a large number of crystal defects in the film like the polysilicon film, when the CMP is carried out for forming the W plug and when the CMP is carried out for forming the metal wires 15 and 20 by the damascene process, even if the metal impurities remained on the interlayer film diffuse toward the substrate, the SIPOS film getters the metal impurities and thus, it is possible to prevent the metal impurities from reaching the substrate.
  • the SIPOS film 308 in the second embodiment is formed by an LPCVD process using SiH 4 and N 2 O or Si 2 H 6 and N 2 O as raw gas.
  • Preferable thickness of the film 308 is 20 to 100 nm, and more preferably, 50 to 100 nm.
  • the SIPOS film having high insulating ability is used as the diffusion preventing film, so that it is unnecessary to form the insulating film on the inner wall of the contact hole. Therefore, this is effective for forming a fine contact hole.
  • the SIPOS film when used as the diffusion preventing film, the SIPOS film may be doped with impurities such as B or P as is the case when the polysilicon film is used. In this case also, the gettering ability is enhanced as compared with non-doped SIPOS film. In this case, however, since the insulating ability of the SIPOS film is lowered, it is preferable to employ the structure having the insulating film on the device and the inner wall of the contact hole as shown in FIG. 1.
  • the interlayer film having the diffusion preventing film is of the three or two-layer structure.
  • the interlayer film can be a single-layered diffusion preventing film.
  • the diffusion-preventing film is not limited to those, and another film can be used only if the film can getter the metal impurities invading from the above layers.
  • a film having high gettering ability and high insulating ability is preferable because it is unnecessary to provide the insulating film on the contact hole.
  • the interlayer film provided under the first layer of a metal wire 15 has the diffusion preventing film.
  • the insulating film 100 , 300 itself can be formed may by the diffusion-preventing film.
  • the Cu wire is not limited to the metal wire, and another metal film may be used.
  • the interlayer film formed under the metal wire has the diffusion-preventing film capable of gettering the metal impurities invading from upper layers, it is possible to prevent the metal impurities from diffusing toward the semiconductor substrate. Therefore, it is possible to prevent the characteristics of the device from being deteriorated and to enhance the characteristics and reliability of the device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An interlayer film covering a semiconductor device formed on the semiconductor substrate has a film having ability of gettering the metal impurities invading from an upper portion of the interlayer film, and with this ability, the metal impurities are prevented from reaching the semiconductor substrate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly, to a structure of an interlayer film in a high-density semiconductor device and a fabricating method thereof. [0002]
  • 2. Description of the Related Art [0003]
  • In recent years, as devices become smaller, there is apprehension that resistance is increased by reduced wiring sectional area and electromigration resistance is deteriorated due to increase in current density. For this reason, various new materials have been tried as wiring materials, and one example of the materials is Cu wire. However, since the Cu is difficult to be finely etched, a method for forming the wire using damascene process is used to form the Cu wire. A structure of the conventional semiconductor device using this Cu wire is shown in FIG. 9. An [0004] interlayer film 400 comprising silicon oxide film 407 and BPSG film 409 is formed on a semiconductor substrate 401 in which an MOS transistor is formed. The interlayer film 400 is provided with a contact hole 410 which reaches a diffusion layer 406. A W plug 412 is embedded in the contact hole 410. A Cu wire 414 is formed on the silicon oxide film 413 provided on the interlayer film 400, and a Cu plug 419 and a Cu wire 420 are formed on a silicon oxide film 416 provided on the Cu wire 414.
  • The [0005] Cu wire 415 is formed in such a manner that a wire groove 415 is formed in the silicon oxide film 413, Cu film is formed in the wire groove 415 and on the silicon oxide film 413, the Cu film on the silicon oxide film is removed by CMP (Chemical Mechanical Polishing), and the Cu film only in the groove 415 is left. The Cu plug 419 and the Cu wire 420 are formed by a so-called dual damascene process in which a via hole 417 and a wire groove 418 are formed in the silicon oxide film 416, Cu is embedded in the via hole 417 and the wire groove 418, and unnecessary Cu is removed by the CMP.
  • It is possible to form a Cu wire having low resistance and high electromigration resistance by using the damascene process. [0006]
  • According to the method for forming the wire using the damascene process, however, a step for removing the unnecessary portion of the wire material by the CMP to flatten is required, and with this step, it is found that the following problems are caused. [0007]
  • That is, in the CMP of a metal film such as Cu and W, a solution comprising slurry including ferric nitrate or the like for oxidizing metal is used in some cases. Heavy metals such as Fe, alkaline metals or Cu and the wire materials have large diffusion coefficient in silicon oxide films or semiconductor substrates. Therefore, during the CMP for forming the Cu wire, or during the subsequent cleaning step, Fe or Cu remained on the interlayer insulating film is diffused in the silicon oxide film or the BPSG film during the subsequent thermal process, and the Fe or Cu reaches the semiconductor substrate. As a result, there are problems that reduction of lifetime is caused, and reliability of the device is lowered. Further, since the CMP is used also when the [0008] W plug 412 is formed, the same problems are caused.
  • A semiconductor having a diffusion-barrier film, for example, is disclosed in Japanese Unexamined Patent Publication (KOKAI) No. 8-306694. However, this film does not solve the above mentioned problems. [0009]
    • SUMMARY OF THE INVENTION
  • Thereupon, it is an object of the present invention to solve the above problems and to provide a semiconductor device having high reliability. [0010]
  • To achieve the above object, the present invention provides a semiconductor device comprising an interlayer film formed on a semiconductor substrate, wherein the interlayer film includes a diffusion-preventing film for preventing metal impurities invading from an upper portion of the interlayer film from reaching the semiconductor substrate. [0011]
  • The invention also provides a fabricating method of a semiconductor device comprising the steps of: forming, on a semiconductor substrate, a diffusion-preventing film for preventing metal impurities invading from an upper portion of the semiconductor substrate from reaching the semiconductor substrate, forming an insulating film on the diffusion-preventing film, forming a wire groove in the insulating film, forming a metal film in the wire groove and on the insulating film, and removing the metal film deposited on said insulating film by a CMP such that the metal film is remained in the wire groove to form a metal wire. [0012]
  • The diffusion-preventing film may be a polysilicon film, an SIPOS film or such a film doped with boron (B) or phosphorus (P). [0013]
  • Since at least a portion of the interlayer film is provided with the diffusion-preventing film, even if the metal impurities such as copper (Cu) used as the metal wire or Fe included slurry during the CMP invades from the upper portion of the film, the metal impurities are gettered by the diffusion-preventing film, the metal impurities do not reach the semiconductor substrate. Therefore, it is possible to prevent the characteristics of the device formed on the semiconductor substrate from being deteriorated.[0014]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a sectional view of a structure of a semiconductor device according to a first embodiment of the present invention. [0015]
  • FIG. 2 is a sectional view of a step of a fabricating method of the semiconductor device according to the first embodiment of the invention. [0016]
  • FIG. 3 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention. [0017]
  • FIG. 4 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention. [0018]
  • FIG. 5 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention. [0019]
  • FIG. 6 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention. [0020]
  • FIG. 7 is a sectional view of the step of the fabricating method of the semiconductor device according to the first embodiment of the invention. [0021]
  • FIG. 8 is a sectional view of a structure of a semiconductor device according to a second embodiment of the invention. [0022]
  • FIG. 9 is a sectional view of a structure of a conventional semiconductor device.[0023]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Embodiments of the present invention will be described below in detail with reference to the accompanying drawings to clarify the above, the other objects, features and merit. [0024]
  • (First Embodiment) [0025]
  • FIG. 1 is a sectional view of a semiconductor device of a first embodiment of the invention. [0026]
  • A device region is defined by a [0027] field oxide film 2 provided in a semiconductor substrate 1. An MOS transistor comprising a gate electrode 4, a gate oxide film 3 and source/drain diffusion layers 6 is formed in the device region. The gate electrode 4 is formed at its sidewalls with sidewall insulating films 5. An interlayer film 100 is provided for covering the MOS transistor. Contact holes 10 are provided on a diffusion layer 6 of the interlayer film 100, and W plugs 12 are embedded in the contact holes 10. The interlayer film 100 is of a three-layer structure comprising a silicon oxide film 7, a polysilicon film 8 and a BPSG film. Of these films, the polysilicon film 8 is a diffusion-preventing film of the present invention. Since the diffusion-preventing film is polysilicon film, contact sidewall insulating films 11 are provided on inner walls of the contact holes 10 for preventing short-circuit. Wire grooves 14 are provided in the contact holes 10 of an insulating film 13 formed on the interlayer film 100, and Cu wires 15 are provided in the wire grooves 14. Via holes 17 and wire grooves 18 are provided on the Cu wires 15 formed in the insulating film 13. A Cu plug 19 and a Cu wire 20 are provided in the via hole 17 and the wire groove 18, respectively.
  • A fabricating method of the semiconductor device according to the first embodiment of the invention will be explained using FIGS. [0028] 2 to 7.
  • First, as shown in FIG. 2, after the MOS transistor having the [0029] field oxide film 2 and the diffusion layer 6 is formed on the semiconductor substrate 1, the interlayer film 100 comprising the silicon oxide film 7, the polysilicon film 8 and the BPSG film 9 is deposited on the semiconductor substrate 1, and an upper surface of the BPSG film 9 is flattened by reflowing or the CMP process. It is preferable that thickness of the silicon oxide film 7 is 50 to 500 nm, thickness of polysilicon film 8 is 20 to 100 nm, and thickness of the BPSG film 9 is 100 to 1000 nm. The polysilicon film 8 is deposited by an LPCVD process using SiH4 or Si2H6 as raw gas. At that time, the polysilicon film 8 may be doped with impurities such as B and P.
  • Subsequently, as shown in FIG. 3, the [0030] contact holes 10 are formed in the interlayer film 100 and the gate oxide film 3 so that upper surfaces of the diffusion layers 6 are exposed by the lithography technique and etching technique.
  • Next, as shown in FIG. 4, [0031] silicon oxide films 11 are formed on the inner walls of the contact holes 10 as the contact sidewall insulating films by the CVD process and then, the W films are embedded in the contact holes 10, and the CMP is carried out to form the W plugs 12. When the CMP is carried out to form the W plugs, heavy metals such as Fe included in the residual slurry on the interlayer film 100 is remained even after the cleaning step. Although the heavy metals are diffused toward the semiconductor substrate 1 in the subsequent thermal step, but since the interlayer film 100 includes the polysilicon film 8 according to the present invention, the Fe passing through the BPSG film 9 is gettered due to crystal defect of the polysilicon film 8, and the Fe does not reach the semiconductor substrate 1.
  • Thereafter, as shown in FIG. 5, the [0032] silicon oxide film 13, thickness of which is 200 to 1500 nm, is deposited on the interlayer film 100, and the wire grooves 14 are formed on the W plugs of the of the silicon oxide film 13. Then the Cu film 15′ is deposited so as to embed in the wire grooves 14. At that time, the Cu film 15′ is formed also on the silicon oxide film 13.
  • Subsequently, [0033] unnecessary Cu film 15′ deposited on the silicon oxide film 13 is removed by the CMP using slurry including ferric nitrate, and Cu film is left only in the wire grooves 14, thereby forming the Cu wires 15 as shown in FIG. 6. At that time, as is the case when the W plugs are formed, the Cu which is heavy metal, alkaline metal and wire material such as Fe included in the slurry remained on the silicon oxide film 13 diffuse toward the substrate 1 in the subsequent thermal step, but since the interlayer film 100 includes the polysilicon film 8, Fe and Cu which have passed through the BPSG film 9 are gettered due to crystal defect of the polysilicon film 8, and the Fe and Cu are prevented from reaching the substrate 1.
  • Next, as shown in FIG. 7, a [0034] silicon oxide film 16, thickness of which is 200 to 1000 nm, is formed on the silicon oxide film 13, the via holes 17 and the wire grooves 18 are formed in the silicon oxide film 16 by the lithography technique and etching technique, and a Cu film 20′ is formed such as to embed the via holes 17 and the wire grooves 18. Then, as is the case when the wires 15 are formed, unnecessary portion of the Cu film 20′ is removed by the CMP using slurry including ferric nitrate, thereby forming the Cu plugs 19 and the Cu wires 20 as shown in FIG. 1. In the CMP of this step also, Cu of the heavy metal, alkaline metal and wire material such as Fe included in the slurry remains on the silicon oxide film 16, and the Cu diffuse toward the substrate through the silicon oxide films 16, 13 and the BPSG film 9 in the subsequent thermal step, these metal impurities are gettered because the polysilicon film 8 exists and thus, the metal impurities are prevented from being diffused toward the substrate.
  • In this embodiment, when polysilicon film including B or P is used as the [0035] diffusion preventing film 8, since such polysilicon film has higher gettering ability with respect to heavy metal as compared with non-doped polysilicon film, gettering ability of Fe and Cu is enhanced, and the diffusion preventing effect can be enhanced.
  • (Second Embodiment) [0036]
  • In the first embodiment, the [0037] interlayer film 100 is of the three-layer structure in which the polysilicon film 8 is sandwiched between the silicon oxide film 7 and the BPSG film 9 so as to obtain complete insulation. Further, the contact sidewall insulating film 11 is required for insulation also on the inner wall of the contact hole 10. Therefore, the number of steps is increased as compared with the conventional technique shown in FIG. 9. A semiconductor device that does not increase the number of steps as compared with the conventional technique will be shown below as a second embodiment of the invention.
  • FIG. 8 is a sectional view of a structure of a semiconductor device according to the second embodiment of the invention. In FIG. 8, an [0038] interlayer film 300 of a two-layer structure comprising a diffusion preventing film 308 and a BPSG film 9 is provided instead of the interlayer film 100 of the three-layer structure of the first embodiment. An SIPOS (semi-insulating polycrystalline silicon) film is used as the diffusion preventing film 308. The SIPOS film is a polysilicon film including O or N, and this film is a high insulating film having high resistance equal to 1E11 ohm/cm2 or higher. Therefore, the SIPOS film 308 can be formed directly on the semiconductor device, and it is unnecessary to provide the insulating film on the inner wall of the contact hole 10. Therefore, the number of steps is not increased as compared with the conventional technique shown in FIG. 9. Since the SIPOS film 308 also includes a large number of crystal defects in the film like the polysilicon film, when the CMP is carried out for forming the W plug and when the CMP is carried out for forming the metal wires 15 and 20 by the damascene process, even if the metal impurities remained on the interlayer film diffuse toward the substrate, the SIPOS film getters the metal impurities and thus, it is possible to prevent the metal impurities from reaching the substrate.
  • The [0039] SIPOS film 308 in the second embodiment is formed by an LPCVD process using SiH4 and N2O or Si2H6 and N2O as raw gas. Preferable thickness of the film 308 is 20 to 100 nm, and more preferably, 50 to 100 nm.
  • In the second embodiment, the SIPOS film having high insulating ability is used as the diffusion preventing film, so that it is unnecessary to form the insulating film on the inner wall of the contact hole. Therefore, this is effective for forming a fine contact hole. [0040]
  • Also when the SIPOS film is used as the diffusion preventing film, the SIPOS film may be doped with impurities such as B or P as is the case when the polysilicon film is used. In this case also, the gettering ability is enhanced as compared with non-doped SIPOS film. In this case, however, since the insulating ability of the SIPOS film is lowered, it is preferable to employ the structure having the insulating film on the device and the inner wall of the contact hole as shown in FIG. 1. [0041]
  • In the first and second embodiments, the interlayer film having the diffusion preventing film is of the three or two-layer structure. When a film having high insulating ability such as the non-doped SIPOS film is used, the interlayer film can be a single-layered diffusion preventing film. [0042]
  • Although the non-doped polysilicon film, the polysilicon film doped with impurities, the non-doped SIPOS film and the SIPOS film doped with impurities are indicated as the diffusion-preventing film in the above embodiments, the diffusion-preventing film is not limited to those, and another film can be used only if the film can getter the metal impurities invading from the above layers. A film having high gettering ability and high insulating ability is preferable because it is unnecessary to provide the insulating film on the contact hole. [0043]
  • In the embodiments, the interlayer film provided under the first layer of a [0044] metal wire 15 has the diffusion preventing film. The insulating film 100, 300 itself can be formed may by the diffusion-preventing film.
  • The Cu wire is not limited to the metal wire, and another metal film may be used. [0045]
  • As explained above, according to the present invention, the interlayer film formed under the metal wire has the diffusion-preventing film capable of gettering the metal impurities invading from upper layers, it is possible to prevent the metal impurities from diffusing toward the semiconductor substrate. Therefore, it is possible to prevent the characteristics of the device from being deteriorated and to enhance the characteristics and reliability of the device. [0046]
  • It is apparent that the present invention should not be limited to the above embodiments, and the invention can appropriately be changed within a scope of technical principles of the invention. [0047]

Claims (6)

What is claimed:
1. A fabricating method of a semiconductor device comprising the steps of:
forming, on a semiconductor substrate, a diffusion-preventing film for preventing metal impurities invading from an upper portion of said semiconductor substrate from reaching said semiconductor substrate,
forming an insulating film on said diffusion-preventing film,
forming a wire groove in said insulating film,
forming a metal film in said wire groove and on said insulating film, and
removing said metal film deposited on said insulating film by a CMP such that said metal film is remained in said wire groove to form a metal wire.
2. A fabricating method of a semiconductor device according to claim 1, wherein said CMP is carried out using slurry including ferric nitrate.
3. A fabricating method of a semiconductor device according to claim 1, wherein said metal film is Cu.
4. A fabricating method of a semiconductor device according to claim 1, wherein said diffusion-preventing film is either one of a polysilicon film and a SIPOS film.
5. A fabricating method of a semiconductor device according to claim 4, wherein said diffusion-preventing film includes B or P.
6. A fabricating method of a semiconductor device according to claim 1, further comprising the steps of:
forming first and second insulating film under and on said diffusion-preventing film, respectively,
forming a contact hole in said second insulating film, said diffusion-preventing film and said first insulating film such that said contact hole reaches said semiconductor substrate, and
forming a third insulating film on an inner wall of said contact hole.
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