US20020094668A1 - Thin layer structure made up of conductive and insulative zones - Google Patents
Thin layer structure made up of conductive and insulative zones Download PDFInfo
- Publication number
- US20020094668A1 US20020094668A1 US10/071,999 US7199902A US2002094668A1 US 20020094668 A1 US20020094668 A1 US 20020094668A1 US 7199902 A US7199902 A US 7199902A US 2002094668 A1 US2002094668 A1 US 2002094668A1
- Authority
- US
- United States
- Prior art keywords
- thin layer
- substrate
- layer
- conductive
- support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to a structure comprising a thin layer of material made up of conductive zones and insulating zones. It also relates to the method of manufacturing such a structure.
- Certain components created on the surface of a substrate require, in order to be used, that an electric current is able to pass through the thickness of the substrate, that is to say, in the vertical direction with respect to the plane of the substrate.
- components with vertical operation electroluminescent diodes, laser diodes (in particular, laser diodes with a vertical cavity), photodetectors, hyperfrequency detectors (in particular, Schottky diodes), power components, solar cells.
- These components are represented diagrammatically in the form of doped substrates, on which, the active or non-active layers are produced by a specific doping operation.
- the electrical contacts are made on the front facing surface and at the back of the component or at depth.
- Power diodes have two contacts: the anode contact on the front face and the cathode contact on the back face.
- the electrical current passes between the front and rear faces of the device (see for example the synthesis article entitles “Trends in power semiconductor devices” by B. JAYANT BALIGA, that appeared in IEEE Transactions on Electron Devices, Vol. 43, No. 10, October 1996).
- One of the techniques used to provide active layers on the substrate is epitaxial growth. This technique consists of causing a material to grow in an ordered manner from a crystalline substrate whilst controlling its composition. Stacks of epitaxiated semiconductor layers with variable doping levels can be produced in this way. If the epitaxiated semiconductor layers are of the same kind as the crystalline substrate, one refers to deposition by homo-epitaxy. If they are of a different kind, then this is deposition by hetero-epitaxy. This technique permits the production of semiconductor layers of very small thickness (a few tens of Angstrom units), of high purity and with interfaces of excellent quality.
- this technique is very expensive and its low rate of deposition does not enable one to obtain semiconductor layers of thickness greater than a few tens of micrometers in an industrial manner.
- the epitaxy of the layers can only be created if the substrate has crystal parameters which are close to those of the material to be epitaxiated. In effect, if the crystal parameters are not sufficiently close, the limitation to the matching the lattice parameters greatly reduces the good optical and electronic properties of the structures obtained by hetero-epitaxy. Therefore, this severely limits the number and the diversity of the layers that one is able to grow.
- one may mention the difficulty in obtaining components from the III-V family of semiconductors on silicon substrates. For certain components, it is of interest to combine the advantages of different semiconductors.
- solar cells for use in space are of great interest.
- energy for satellites is generally supplied by means of panels of solar cells.
- solar cells made of GaAs The problem of gallium arsenide is its cost and above all its weight and its fragile nature.
- a great improvement would consist of providing thin films of GaAs or InP on a silicon substrate. This type of structure would allow one to combine the advantages of GaAs (surface properties to create the component constituting the solar cell) and the advantages of silicon as a support (weight three times less than that of GaAs and much less fragile).
- the ion implantation step is carried out with an ion dose which is between a minimum dose and a maximum dose.
- the minimum dose is that from which sufficient micro-cavities will be created to provide weakening of the substrate along the reference plane.
- the maximum dose, or critical dose is that above which, during the heat treatment step, there is separation of the substrate.
- the separation step comprises the application of mechanical forces between the two parts of the substrate.
- the thin film defined in the substrate is sufficiently rigid itself (because of its thickness or because of its mechanical properties), after the transfer annealing, one can obtain a self-supporting film. This is what is disclosed in document FR-A-2 738 671.
- Document FR-A-2 767 416 discloses that it is possible to lower the annealing temperature if the thermal budget supplied to the substrate during the various steps of the method is taken into account (ion implantation step, possibly a step of bonding the substrate to a stiffener, possible intermediate treatments, an annealing step to allow separation).
- thermal budget one understands that for a step where thermal energy is supplied (for example during an annealing step), one must not only consider the temperature but the time-temperature couple supplied to the substrate.
- the thin layer of GaAs is therefore electrically insulated from the silicon support.
- a subject of the invention is a method of manufacturing a thin layer, the thin layer having to provide at least one vertical electrical connection through its entire thickness, the thin layer being made of a conductive or semiconductive material capable of having its electrical properties disrupted when it is subjected to an ion implantation using specified species, the method comprising the following steps:
- masking one face of a substrate comprising said material by masking means that define at least one masked area, the size of which does not exceed a limiting dimension specified for said material, this limiting dimension having to permit splitting of the substrate at the time of the subsequent step of cleavage
- ion implantation of the substrate through its masked face by means of said species the implantation being capable of creating, within the non-masked volume of the substrate and at a depth close to the mean depth of penetration of the species, a layer of micro-cavities defining said thin layer
- the implanted face of the substrate can be made integral with a support before the cleavage step. It can also be made integral with a support after the cleavage step.
- the cleavage step corresponds to a separation of the thin layer and the substrate.
- the masking means can comprise deposits of a material capable of preventing penetration of the ions into the substrate during the ion implantation, these deposits being deposited on said face of the substrate. They can also comprise micro-elements deposited on said face of the substrate. These micro-elements can be chosen from among micro-beads and particles.
- the masking can be carried out in such a way that the thin layer, retains overall, the electrical properties of the substrate. It can also be created in such a way that the thin layer behaves overall like an insulating layer except for at least one part formed from one zone or several neighboring zones that retain the electrical properties of the substrate. In this case, the part formed by this zone or by these neighboring zones that retain the electrical properties of the substrate can constitute a conductive path or a conductive track.
- Integration of the substrate with a support can be achieved by a method chosen between bonding by molecular adhesion and bonding by means of a brazing material, for example a brazing material based on indium.
- the method can comprise a step of preparing a conductive interface between said face of the substrate and the support.
- This step of preparing a conductive interface can comprise the deposition of a metal layer on the face of the substrate and/or on the face of the support, for example, the deposition of a layer of palladium.
- Associated with this metal layer can be the deposition of conductive metal bonding materials, for example, successive depositions of titanium, nickel and gold.
- a heat treatment can be carried out in a way to cause the diffusion of the deposited metal layer.
- the metal material is preferably chosen to react with at least a part of the material of the substrate and/or the support.
- This method is advantageously applicable to the manufacture of a structure comprising a thin layer of SiC, GaAs or InP on a support, the ion implantation using hydrogen and/or helium ions.
- the support can notably be silicon.
- Another subject of the invention is a structure comprising a thin layer, the thin layer being a layer of conductive or semiconductive material made insulating by ion implantation except for at least one zone that permits a vertical electrical connection through the entire thickness of the thin layer.
- the thin layer comprises a multitude of zones, these zones being distributed over the whole surface of the thin layer.
- the thin layer comprises one zone or a plurality of zones, concentrated in order to constitute at least one conductive path or at least one conductive track.
- the thin layer can be integral with a support through the use of an intermediate conductive interface so as to allow electrical connection between these two elements.
- This conductive interface can be constituted by a metal layer, for example a layer of palladium.
- a metal layer for example a layer of palladium.
- Associated with this metal layer can be the deposition of conductive metal bonding materials, for example, successive depositions of titanium, nickel and gold.
- the thin layer can also be made integral with a support by using a brazing material, for example a brazing material based on indium.
- the semiconductor material of the thin layer is chosen from among SiC, GaAs and InP.
- the support can notably be silicon.
- FIGS. 1 to 3 illustrate different steps of the method of manufacture according to this invention
- FIG. 4 represents, in cross section, a structure according to this invention, in a particular application.
- FIG. 5 is an enlarged view of the detail marked V in FIG. 4.
- FIGS. 1 to 3 are cross section views.
- FIG. 1 shows a semiconductor substrate 1 , for example, a substrate made of GaAs.
- the substrate 1 is intended to provide the thin layer 2 of a structure by integration with a support 3 , for example made of silicon (see FIGS. 2 to 5 ).
- Deposits 4 are made onto the upper face 5 of the substrate 1 which are capable of stopping the ions which will subsequently be implanted into the volume of substrate through face 5 .
- the deposits 4 can be resin deposits or deposits of another material (oxide, metal, etc.).
- the thickness of the deposits is such that ions are prevented from penetrating into the substrate.
- the size of the deposits is, for example, of the order of from 1 to 2 ⁇ m.
- FIG. 2 illustrates the ion implantation step.
- Hydrogen ions are, for example, used to bombard the substrate 1 through the upper face 5 .
- the energy and the dose of the ions are chosen in such a way as to constitute a layer of micro-cavities 6 at a distance from the face 5 of the substrate corresponding to the desired thickness of the thin layer 2 .
- the hydrogen ions make the thin layer 2 insulating.
- the zones of the thin layer 2 masked by the deposits 4 are not affected by the hydrogen ions. These masked zones therefore retain their initial electrical properties of the substrate 1 .
- micro-cavity or gaseous micro-bubble By micro-cavity or gaseous micro-bubble, one understands any cavity generated by the implantation of ions of hydrogen gas and/or rare gas in the material.
- the cavities can be of a very flattened shape, that is to say of small height, for example, a few inter-atomic distances, or of spherical shape or any other shape different from these two preceding shapes.
- These cavities can contain a free gaseous phase and/or atoms of gas arising from the implanted ions fixed onto atoms of the material forming the walls of the cavities. These cavities are generally called platelets, micro-blisters or even bubbles.
- micro-cavities By a layer of micro-cavities, one understands a region containing micro-cavities which can be situated at various depths and which can be adjacent or non-adjacent to one another.
- gaseous species By gaseous species, one understands elements, for example hydrogen or rare gases in their atomic form (for example H) or in their molecular form (for example H 2 ) or in their ionic form (for example H + , H 2+ ) or in their isotopic form (for example deuterium) or isotopic and ionic.
- H atomic form
- H 2 molecular form
- ionic form for example H + , H 2+
- isotopic form for example deuterium
- the layer 6 of micro-cavities obtained in this way is discontinuous.
- the discontinuities are of a small size (of the order of 1 to 2 ⁇ m) and are not liable to modify the phenomenon of crack propagation during the subsequent cleavage step.
- the deposits 4 made on the face 5 of the substrate 1 are removed.
- the face 5 of the substrate 1 can be made integral with a receiving surface of a support 3 by molecular adhesion (see FIG. 3).
- the faces to be joined are prepared in order to constitute a bonding interface.
- an ohmic contact of very low resistivity (1 ⁇ .cm) can be obtained if the bonding is carried out using an intermediate layer of palladium deposited on one of the faces or on both the faces to be joined.
- a brazing material such as an indium based brazing material.
- the heat treatment leads to coalescence of the micro-cavities which leads to a weakening of the structure at the level of the layer of micro-cavities.
- This weakening permits separation of the material under the effect of internal stresses and/or pressure within the micro-cavities.
- the separation can be natural or assisted by the application of external stresses.
- the cleavage of the substrate 1 along the layer of micro-cavities 6 is obtained, for example, solely following a suitable heat treatment or by combining a heat treatment and mechanical forces, for example, tensile forces and/or shearing forces and/or bending forces or solely by the use of mechanical stresses.
- the mechanical forces can be applied perpendicular to the planes of the layers and/or parallel to them. They can be localized to one point or one area or can be applied to different places in a symmetrical or non-symmetrical fashion.
- the cleavage produces a structure comprising the thin layer 2 integral with the support 3 or a self-supporting thin layer where the thin layer has not been made integral with a support.
- the free face of the thin layer 2 can then be subjected to a mechanical-chemical polishing operation.
- layers 7 and 8 of the same semiconductor material as the thin layer 2 can then be successively deposited.
- a solar cell can be formed in this way by depositing an n doped layer 7 and a p doped layer 8 .
- FIG. 5 shows, the assembly formed by the layers 7 and 8 is electrically connected to the support 3 through zones 9 which have a side dimension for example of 1 ⁇ m. If the zones 9 are constituted by a material with a resistivity of 1 ⁇ .cm, the resistance of a zone 9 , for a thin layer 2 of thickness 100 nm, is 1000 ⁇ .
- the total density of these zones is of the order of 10 6 /cm 2 , which corresponds to a total apparent resistance of 0.001 ⁇ for a surface area of 1 cm 2 of thin layer.
- the surface area of a thin layer is for example 70 cm 2 , its resistance in the vertical direction is then of the order of 10 ⁇ 5 ⁇ .
- the recoverable power for an efficiency of 20% is 200 W/m 2 .
- a voltage of 1 Volt this is equivalent to 200 A/m 2 or a current of 1.4 A for a structure of 70 cm 2 .
- the resistance of this structure then leads to a voltage drop of 10 5 V, or an absolutely negligible loss.
- this masking can be carried out using very simple means, without lithography.
- These means are for example, masking by micro-beads deposited on the face 5 of the substrate 1 before the ion implantation step.
- These micro-beads or other particles can be made of glass, quartz or any other suitable material. Their size varies from a few tenths of a ⁇ m to a few ⁇ m.
- the thin layer 2 can be heterogeneous, that is to say made up of materials of a different kind stacked one upon the other and/or aligned one by the side of the other.
- the thin layer can be self-supporting when its thickness, taking account of the nature of the material used to produce it, gives it sufficient rigidity to induce the separation.
- This self-supporting thin layer permits applications for example of the anisotropic conductive film type.
- the implantation can be the result of different species, implanted simultaneously or successively (cf. FR-A-2 773 26).
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Photovoltaic Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A structure comprising a thin layer (2) that can be integral with a support (3), the thin layer being a layer of a semiconductor material made insulating by ion implantation except for at least one zone that permits a vertical electrical connection through the entire thickness of the thin layer (2). A method of manufacturing such a structure is also disclosed.
Description
- This invention relates to a structure comprising a thin layer of material made up of conductive zones and insulating zones. It also relates to the method of manufacturing such a structure.
- Certain components created on the surface of a substrate require, in order to be used, that an electric current is able to pass through the thickness of the substrate, that is to say, in the vertical direction with respect to the plane of the substrate. One may mention as an example components with vertical operation: electroluminescent diodes, laser diodes (in particular, laser diodes with a vertical cavity), photodetectors, hyperfrequency detectors (in particular, Schottky diodes), power components, solar cells. These components are represented diagrammatically in the form of doped substrates, on which, the active or non-active layers are produced by a specific doping operation. As a general rule, the electrical contacts are made on the front facing surface and at the back of the component or at depth.
- Power diodes have two contacts: the anode contact on the front face and the cathode contact on the back face. For more sophisticated power components such as the MOSFETs, the IGBTs and the thyristor structures, there is still one contact on the front face and one contact on the back face with one or more contact points at depth. However, for all these types of components, the electrical current passes between the front and rear faces of the device (see for example the synthesis article entitles “Trends in power semiconductor devices” by B. JAYANT BALIGA, that appeared in IEEE Transactions on Electron Devices, Vol. 43, No. 10, October 1996).
- One of the techniques used to provide active layers on the substrate is epitaxial growth. This technique consists of causing a material to grow in an ordered manner from a crystalline substrate whilst controlling its composition. Stacks of epitaxiated semiconductor layers with variable doping levels can be produced in this way. If the epitaxiated semiconductor layers are of the same kind as the crystalline substrate, one refers to deposition by homo-epitaxy. If they are of a different kind, then this is deposition by hetero-epitaxy. This technique permits the production of semiconductor layers of very small thickness (a few tens of Angstrom units), of high purity and with interfaces of excellent quality. However, this technique is very expensive and its low rate of deposition does not enable one to obtain semiconductor layers of thickness greater than a few tens of micrometers in an industrial manner. Furthermore, the epitaxy of the layers can only be created if the substrate has crystal parameters which are close to those of the material to be epitaxiated. In effect, if the crystal parameters are not sufficiently close, the limitation to the matching the lattice parameters greatly reduces the good optical and electronic properties of the structures obtained by hetero-epitaxy. Therefore, this severely limits the number and the diversity of the layers that one is able to grow. In particular, one may mention the difficulty in obtaining components from the III-V family of semiconductors on silicon substrates. For certain components, it is of interest to combine the advantages of different semiconductors. By way of example, one can consider the cases of an active layer of GaAs or an active layer of InP on silicon. This configuration allows one to associate the good electronic properties of the GaAs or InP materials at hyperfrequency with a silicon substrate which has the advantage of being more robust, having less weight and which has better thermal conductivity than GaAs. One may also mention the case of a layer of GaN on a SiC substrate, a structure which offers many advantages for electronic power components.
- In another field, solar cells for use in space are of great interest. In effect, energy for satellites is generally supplied by means of panels of solar cells. Among the various possibilities for producing solar cells for use in space, one can mention solar cells made of GaAs. The problem of gallium arsenide is its cost and above all its weight and its fragile nature. In order to resolve this problem, it has been proposed to produce solar cells from thin films of GaAs epitaxiated onto a germanium substrate. A great improvement would consist of providing thin films of GaAs or InP on a silicon substrate. This type of structure would allow one to combine the advantages of GaAs (surface properties to create the component constituting the solar cell) and the advantages of silicon as a support (weight three times less than that of GaAs and much less fragile).
- In order to produce these structures made up of a thin film, integral with a substrate of a different material, processes other than hetero-epitaxy can be used. In particular, one may mention the methods of bringing semiconductor substrates into contact by bonding them using molecular adhesion or techniques for transferring thin films. The method disclosed by the document FR-A-2 681 472 offers numerous advantages. It allows one to transfer a thin semiconductor film with a large surface area (of a few thousand Angstrom units with a few micrometers of thickness), from its original substrate to the desired support by a combination of ionic implantation (using light ions), bonding by molecular adhesion and an appropriate heat treatment.
- This transfer technique has been the subject of other developments. According to document FR-A-2 748 851, the ion implantation step is carried out with an ion dose which is between a minimum dose and a maximum dose. The minimum dose is that from which sufficient micro-cavities will be created to provide weakening of the substrate along the reference plane. The maximum dose, or critical dose is that above which, during the heat treatment step, there is separation of the substrate. The separation step comprises the application of mechanical forces between the two parts of the substrate.
- If the thin film defined in the substrate is sufficiently rigid itself (because of its thickness or because of its mechanical properties), after the transfer annealing, one can obtain a self-supporting film. This is what is disclosed in document FR-A-2 738 671.
- Document FR-A-2 767 416 discloses that it is possible to lower the annealing temperature if the thermal budget supplied to the substrate during the various steps of the method is taken into account (ion implantation step, possibly a step of bonding the substrate to a stiffener, possible intermediate treatments, an annealing step to allow separation). By the term thermal budget one understands that for a step where thermal energy is supplied (for example during an annealing step), one must not only consider the temperature but the time-temperature couple supplied to the substrate.
- This technique is used now for the industrial manufacture of SOI substrates (see the article by A. J. AUBERTON et al., entitled “SOI materials for ULSI applications” that appeared in Semiconductor International, 1995, Vol. 11, pages 97-104). The feasibility of this technique to III-V semiconductor materials such as GaAs has recently been demonstrated (see the article by E. JALAGUIER et al., entitled “Transfer of 3 in GaAs Film on Silicon Substrate by Proton Implantation Process” published in Electronics Letters, Feb. 19, 1998, Vol. 34, No. 4, pages 408-409). For such a structure, made up of a thin film of GaAs on a silicon support, bonding by using an intermediate layer of silicon oxide has been used. The thin layer of GaAs is therefore electrically insulated from the silicon support. In the case of a solar cell constituted in this way, it is necessary to make an electrical connection on the front face and an electrical connection on the back face, electrical connection with the photo-voltaic thin layer being made through the substrate.
- One solution to this problem can be found by choosing a conductive interface between the thin layer and its support, this interface then having also to provide the adhesion of the two parts. Several techniques have been suggested to achieve this. They are given below.
- It is possible to provide a direct bond between two semiconductor elements which provide a good electrical contact between these two elements. On this subject one can make reference to the following articles
- “Electrical characteristics of directly-bonded GaAs and InP” by H. WADA et al., that appeared in Appl. Phys. Lett., 62(7), Feb. 15, 1993 “Low-resistance ohmic conduction across compound semiconductor wafer-bonded interfaces” by F. A. KISH et al., that appeared in Appl. Phys. Lett., 67(14), Oct. 2, 1995.
- The techniques described in these articles are however rather restricting. They frequently demand very good preparation of the surfaces before bonding, often under ultra-vacuum conditions and/or also post-bonding heat treatments at a high temperature (from 600 to 1000° C.) under a reducing atmosphere of hydrogen. These conditions are difficult to implement, in particular when the two semiconductor materials have very different coefficients of thermal expansion (for example, GaAs in relation to Si or SiC). In this case, it is necessary to use low temperature bonding.
- Another possibility consists of bringing the two semiconductor elements into contact using previously deposited metal layers. This solution is described in the article “Low Temperature Bonding of Epitaxial Lift-Off Devices with AuSn” by G. RAINER DOHLE et al., that appeared in IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, Vol. 19, No. 13, August 1996.
- In addition, a development of the method described in the document FR-A-2 681 472, mentioned above, has been disclosed in document FR-A-2 758 907. This latter document discloses that, under certain conditions, a masking technique can be used to protect sensitive zones of the future thin layer (for example, constituent zones of MOS transistors) from the passage of ions intended to create the micro-cavities. This implies an absence of micro-cavities in the zones of the bombarded substrate corresponding to the masked areas. Despite all this, cleavage of the substrate can be obtained allowing detachment of a thin film if the width of each masked area does not exceed a limiting value that is specified for the material that constitutes the substrate.
- One might then think, given the state of the art described above, that the method of transferring a thin semiconductor layer disclosed by the document FRA-2 681 472 would allow one to obtain a thin layer of GaAs integral with a silicon support using a conductive interface and that an electrical connection would be possible between the thin layer of GaAs and the silicon support. However, the application of this method of transfer has revealed the following problem. The ion implantation step is generally carried out using light ions such as hydrogen ions. It is found that the passage of hydrogen ions in the GaAs has the effect of considerably modifying the resistivity of the region bombarded by these ions. Hence, a region of GaAs with an initial resistivity of the order of 1 mΩ.cm, sees its resistivity reach a value of the order of 105 Ω.cm, after bombardment with hydrogen ions. This phenomenon is due to the hydrogen which has created centers deep within the GaAs. The result is that a film of GaAs epitaxiated onto a thin layer of GaAs transferred onto a silicon support would be electrically insulated from the support.
- To remedy this problem, one can consider using species other than hydrogen to carry out the ion implantation. Hydrogen is however preferred for practical reasons. One may also attempt to restore a certain conductivity to the thin layer of GaAs by means of annealing treatments subsequent to the cleavage. However, these annealing treatments imply a break in the progress of the manufacturing process and are not always desirable.
- So as to remedy the disadvantages of the prior art, a structure is proposed that is obtained by the method described in document FR-A-2 681 472, this method being modified so that the conductive or semiconductive layer to be transferred, which is a layer capable of being corrupted by the ion bombardment, is locally protected. This protection allows a transferable layer to be provided that has zones with electrical properties that have not been corrupted.
- Hence a subject of the invention is a method of manufacturing a thin layer, the thin layer having to provide at least one vertical electrical connection through its entire thickness, the thin layer being made of a conductive or semiconductive material capable of having its electrical properties disrupted when it is subjected to an ion implantation using specified species, the method comprising the following steps:
- masking one face of a substrate comprising said material by masking means that define at least one masked area, the size of which does not exceed a limiting dimension specified for said material, this limiting dimension having to permit splitting of the substrate at the time of the subsequent step of cleavage
- ion implantation of the substrate through its masked face by means of said species, the implantation being capable of creating, within the non-masked volume of the substrate and at a depth close to the mean depth of penetration of the species, a layer of micro-cavities defining said thin layer
- possible removal of said masking means
- cleavage of the substrate at the level of the layer of micro-cavities in order to obtain said thin layer.
- The implanted face of the substrate can be made integral with a support before the cleavage step. It can also be made integral with a support after the cleavage step.
- The cleavage step corresponds to a separation of the thin layer and the substrate.
- The masking means can comprise deposits of a material capable of preventing penetration of the ions into the substrate during the ion implantation, these deposits being deposited on said face of the substrate. They can also comprise micro-elements deposited on said face of the substrate. These micro-elements can be chosen from among micro-beads and particles.
- The masking can be carried out in such a way that the thin layer, retains overall, the electrical properties of the substrate. It can also be created in such a way that the thin layer behaves overall like an insulating layer except for at least one part formed from one zone or several neighboring zones that retain the electrical properties of the substrate. In this case, the part formed by this zone or by these neighboring zones that retain the electrical properties of the substrate can constitute a conductive path or a conductive track.
- Integration of the substrate with a support can be achieved by a method chosen between bonding by molecular adhesion and bonding by means of a brazing material, for example a brazing material based on indium.
- Before the integration, the method can comprise a step of preparing a conductive interface between said face of the substrate and the support. This step of preparing a conductive interface can comprise the deposition of a metal layer on the face of the substrate and/or on the face of the support, for example, the deposition of a layer of palladium. Associated with this metal layer can be the deposition of conductive metal bonding materials, for example, successive depositions of titanium, nickel and gold. A heat treatment can be carried out in a way to cause the diffusion of the deposited metal layer. The metal material is preferably chosen to react with at least a part of the material of the substrate and/or the support.
- This method is advantageously applicable to the manufacture of a structure comprising a thin layer of SiC, GaAs or InP on a support, the ion implantation using hydrogen and/or helium ions. The support can notably be silicon.
- Another subject of the invention is a structure comprising a thin layer, the thin layer being a layer of conductive or semiconductive material made insulating by ion implantation except for at least one zone that permits a vertical electrical connection through the entire thickness of the thin layer.
- According to a first variant, the thin layer comprises a multitude of zones, these zones being distributed over the whole surface of the thin layer. According to a second variant, the thin layer comprises one zone or a plurality of zones, concentrated in order to constitute at least one conductive path or at least one conductive track.
- The thin layer can be integral with a support through the use of an intermediate conductive interface so as to allow electrical connection between these two elements. This conductive interface can be constituted by a metal layer, for example a layer of palladium. Associated with this metal layer can be the deposition of conductive metal bonding materials, for example, successive depositions of titanium, nickel and gold.
- The thin layer can also be made integral with a support by using a brazing material, for example a brazing material based on indium.
- Advantageously, the semiconductor material of the thin layer is chosen from among SiC, GaAs and InP. The support can notably be silicon.
- The invention will be better understood and other advantages and particular features will become apparent on reading the description which will follow, given by way of a non-limitative example, accompanied by the appended drawings among which:
- FIGS.1 to 3 illustrate different steps of the method of manufacture according to this invention
- FIG. 4 represents, in cross section, a structure according to this invention, in a particular application,
- FIG. 5 is an enlarged view of the detail marked V in FIG. 4.
- FIGS.1 to 3 are cross section views. FIG. 1 shows a
semiconductor substrate 1, for example, a substrate made of GaAs. Thesubstrate 1 is intended to provide thethin layer 2 of a structure by integration with asupport 3, for example made of silicon (see FIGS. 2 to 5). -
Deposits 4 are made onto theupper face 5 of thesubstrate 1 which are capable of stopping the ions which will subsequently be implanted into the volume of substrate throughface 5. Thedeposits 4 can be resin deposits or deposits of another material (oxide, metal, etc.). The thickness of the deposits is such that ions are prevented from penetrating into the substrate. The size of the deposits is, for example, of the order of from 1 to 2 μm. - FIG. 2 illustrates the ion implantation step. Hydrogen ions are, for example, used to bombard the
substrate 1 through theupper face 5. The energy and the dose of the ions are chosen in such a way as to constitute a layer ofmicro-cavities 6 at a distance from theface 5 of the substrate corresponding to the desired thickness of thethin layer 2. By their passage, the hydrogen ions make thethin layer 2 insulating. However, the zones of thethin layer 2 masked by thedeposits 4 are not affected by the hydrogen ions. These masked zones therefore retain their initial electrical properties of thesubstrate 1. - By micro-cavity or gaseous micro-bubble, one understands any cavity generated by the implantation of ions of hydrogen gas and/or rare gas in the material. The cavities can be of a very flattened shape, that is to say of small height, for example, a few inter-atomic distances, or of spherical shape or any other shape different from these two preceding shapes. These cavities can contain a free gaseous phase and/or atoms of gas arising from the implanted ions fixed onto atoms of the material forming the walls of the cavities. These cavities are generally called platelets, micro-blisters or even bubbles.
- By a layer of micro-cavities, one understands a region containing micro-cavities which can be situated at various depths and which can be adjacent or non-adjacent to one another.
- By gaseous species, one understands elements, for example hydrogen or rare gases in their atomic form (for example H) or in their molecular form (for example H2) or in their ionic form (for example H+, H2+) or in their isotopic form (for example deuterium) or isotopic and ionic.
- In addition, by ion implantation, one understands any type of injection of the species previously defined either alone or in combination, such as ionic bombardment, diffusion, etc.
- The
layer 6 of micro-cavities obtained in this way is discontinuous. However the discontinuities are of a small size (of the order of 1 to 2 μm) and are not liable to modify the phenomenon of crack propagation during the subsequent cleavage step. - After the ion implantation step, the
deposits 4 made on theface 5 of thesubstrate 1 are removed. Theface 5 of thesubstrate 1 can be made integral with a receiving surface of asupport 3 by molecular adhesion (see FIG. 3). Before this integration step, the faces to be joined are prepared in order to constitute a bonding interface. By way of example, an ohmic contact of very low resistivity (1 Ω.cm) can be obtained if the bonding is carried out using an intermediate layer of palladium deposited on one of the faces or on both the faces to be joined. A similar result can be obtained in the case of a brazing material, such as an indium based brazing material. - Whatever the type of solid material, the heat treatment leads to coalescence of the micro-cavities which leads to a weakening of the structure at the level of the layer of micro-cavities. This weakening permits separation of the material under the effect of internal stresses and/or pressure within the micro-cavities. The separation can be natural or assisted by the application of external stresses.
- Hence, the cleavage of the
substrate 1 along the layer ofmicro-cavities 6 is obtained, for example, solely following a suitable heat treatment or by combining a heat treatment and mechanical forces, for example, tensile forces and/or shearing forces and/or bending forces or solely by the use of mechanical stresses. The mechanical forces can be applied perpendicular to the planes of the layers and/or parallel to them. They can be localized to one point or one area or can be applied to different places in a symmetrical or non-symmetrical fashion. The cleavage produces a structure comprising thethin layer 2 integral with thesupport 3 or a self-supporting thin layer where the thin layer has not been made integral with a support. - The free face of the
thin layer 2 can then be subjected to a mechanical-chemical polishing operation. By epitaxy, layers 7 and 8 of the same semiconductor material as thethin layer 2, can then be successively deposited. A solar cell can be formed in this way by depositing an n dopedlayer 7 and a p dopedlayer 8. As FIG. 5 shows, the assembly formed by thelayers support 3 throughzones 9 which have a side dimension for example of 1 μm. If thezones 9 are constituted by a material with a resistivity of 1 μ.cm, the resistance of azone 9, for athin layer 2 of thickness 100 nm, is 1000 Ω. If thezones 9 are each spaced at 10 μm, the total density of these zones is of the order of 106/cm2, which corresponds to a total apparent resistance of 0.001 Ω for a surface area of 1 cm2 of thin layer. If the surface area of a thin layer is for example 70 cm2, its resistance in the vertical direction is then of the order of 10−5 Ω. If such a solar cell receives a power of 1 kW/m2, the recoverable power for an efficiency of 20% is 200 W/m2. For a voltage of 1 Volt, this is equivalent to 200 A/m2 or a current of 1.4 A for a structure of 70 cm2. The resistance of this structure then leads to a voltage drop of 105 V, or an absolutely negligible loss. - Given that the dimensions of the masked areas are small and that the exact positioning of the masking deposits is not important, this masking can be carried out using very simple means, without lithography. These means are for example, masking by micro-beads deposited on the
face 5 of thesubstrate 1 before the ion implantation step. These micro-beads or other particles, can be made of glass, quartz or any other suitable material. Their size varies from a few tenths of a μm to a few μm. - Depending on the application, the
thin layer 2 can be heterogeneous, that is to say made up of materials of a different kind stacked one upon the other and/or aligned one by the side of the other. - Furthermore, the thin layer can be self-supporting when its thickness, taking account of the nature of the material used to produce it, gives it sufficient rigidity to induce the separation. This self-supporting thin layer permits applications for example of the anisotropic conductive film type.
- In order to obtain a thickness of thin layer that provides sufficient rigidity, one can modify the implantation depth of the species and/or one can form an extra thickness of material, for example, by epitaxy or by hetero-epitaxy at the surface of the thin layer or by deposition.
- In addition, according to the invention, the implantation can be the result of different species, implanted simultaneously or successively (cf. FR-A-2 773 26).
Claims (31)
1. Method of manufacturing a thin layer (2), the thin layer (2) having to provide at least one vertical electrical connection through its entire thickness, the thin layer (2) being made of a conductive or semiconductive material capable of having its electrical properties disrupted when it is subjected to an ion implantation using specified species, the method comprising the following steps
masking one face (5) of a substrate (1) comprising said material by masking means (4) that define at least one masked area, the size of which does not exceed a limiting dimension specified for said material, this limiting dimension having to allow cleavage of the substrate (1) at the time of the subsequent cleavage step
ion implantation of the substrate (1) through its masked face by means of said species, the implantation being capable of creating, within the non-masked volume of the substrate (1) and at a depth close to the mean depth of penetration of the species, a layer of micro-cavities (6) demarcating said thin layer (2)
possible removal of the masking means (4)
cleavage of the substrate (1) at the level of the layer of micro-cavities (6) in order to obtain said thin layer.
2. Method according to claim 1 , characterized in that the implanted face (5) of the substrate (1) is made integral with a support (3) before the cleavage step.
3. Method according to claim 1 , characterized in that the thin layer is made integral with a support after the cleavage step.
4. Method according to any one of claims 1 to 3 , characterized in that the masking means (4) comprise deposits of a material capable of preventing penetration of the ions into the substrate during the ion implantation, these deposits (4) being deposited on said face (5) of the substrate (1).
5. Method according to claim 1 , characterized in that the masking means comprise micro-elements deposited on said face of the substrate.
6. Method according to claim 5 , characterized in that said micro-elements are chosen from among micro-beads and particles.
7. Method according to any one of claims 1 to 6 , characterized in that the masking is carried out in such a way that the thin layer (2) overall preserves the electrical properties of the substrate (1).
8. Method according to any one of claims 1 to 6 , characterized in that the masking is carried out in such a way that the thin layer (2) overall behaves like an insulating layer except for at least one part formed from one zone or from several neighboring zones preserving the electrical properties of the substrate (1).
9. Method according to claim 8 , characterized in that the part formed from this zone or from several neighboring zones preserving the electrical properties of the substrate (1) constitutes a conductive path or a conductive track.
10. Method according to claim 2 , characterized in that the step of integrating the substrate with the support is carried out by a method chosen between bonding by molecular adhesion and bonding by means of a brazing material.
11. Method according to claim 10 , characterized in that said brazing material is based on indium.
12. Method according to claim 2 , characterized in that it includes, before the integration step, a step of preparing a conductive interface between said face (5) of the substrate (1) and said support (3).
13. Method according to claim 12 , characterized in that the step of preparing a conductive interface comprises the deposition of a metal layer onto said face (5) of the substrate (1) and/or onto the support (3).
14. Method according to claim 13 , characterized in that the said metal layer is a layer of palladium.
15. Method according to one of claims 13 or 14, characterized in that said interface metal layer is associated with the deposition of conductive metal bonding materials.
16. Method according to claim 15 , characterized in that the conductive bonding materials are successive deposits of titanium, nickel and gold.
17. Method according to any one of claims 13 to 16 , characterized in that a heat treatment is carried out in a way that causes diffusion of the deposited metal layer.
18. Application of the method according to any one of claims 1 to 17 to the manufacture of a structure comprising a thin layer of SiC, GaAs or InP on a support, the ion implantation being carried out using hydrogen and/or helium ions.
19. Application according to claim 18 , characterized in that the support is made of silicon.
20. Structure comprising a thin layer (2), the thin layer (2) being a layer of conductive or semiconductive material made insulating by ion implantation except for at least one zone (9) that allows a vertical electrical connection through the entire thickness of the thin layer (2).
21. Structure according to claim 20 , characterized in that the thin layer comprises a multitude of zones, these zones being distributed over the entire surface of the thin layer.
22. Structure according to claim 20 , characterized in that the thin layer comprises one zone or a plurality of zones concentrated to constitute at least one conductive path or at least one conductive track.
23. Structure according to any one of claims 20 to 22 , characterized in that the thin layer (2) is made integral with a support (3) through an intermediate conductive interface.
24. Structure according to claim 23 , characterized in that the conductive interface is constituted by a metal layer.
25. Structure according to claim 24 , characterized in that the metal layer is a layer of palladium.
26. Structure according to any one of claims 23 to 25 , characterized in that deposition of conductive bonding materials is associated with said metal interface layer.
27. Structure according to claim 26 , characterized in that the conductive bonding materials are successive deposits of titanium, nickel and gold.
28. Structure according to any one of claims 20 to 22 , characterized in that the thin layer (2) is made integral with a support (3) through the use of a brazing material.
29. Structure according to claim 28 , characterized in that the brazing material is based on indium.
30. Structure according to any one of claims 20 to 29 , characterized in that the material of the thin layer (2) is chosen from among SiC, GaAs and InP.
31. Structure according to any one of claims 23 to 29 , characterized in that the support (3) is made of silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/071,999 US20020094668A1 (en) | 1998-10-16 | 2002-02-06 | Thin layer structure made up of conductive and insulative zones |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9813010 | 1998-10-16 | ||
FR9813010A FR2784795B1 (en) | 1998-10-16 | 1998-10-16 | STRUCTURE COMPRISING A THIN LAYER OF MATERIAL COMPOSED OF CONDUCTIVE ZONES AND INSULATING ZONES AND METHOD FOR MANUFACTURING SUCH A STRUCTURE |
US09/413,483 US6362077B1 (en) | 1998-10-16 | 1999-10-06 | Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure |
US10/071,999 US20020094668A1 (en) | 1998-10-16 | 2002-02-06 | Thin layer structure made up of conductive and insulative zones |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/413,483 Division US6362077B1 (en) | 1998-10-16 | 1999-10-06 | Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020094668A1 true US20020094668A1 (en) | 2002-07-18 |
Family
ID=9531668
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/413,483 Expired - Lifetime US6362077B1 (en) | 1998-10-16 | 1999-10-06 | Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure |
US10/071,999 Abandoned US20020094668A1 (en) | 1998-10-16 | 2002-02-06 | Thin layer structure made up of conductive and insulative zones |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/413,483 Expired - Lifetime US6362077B1 (en) | 1998-10-16 | 1999-10-06 | Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure |
Country Status (3)
Country | Link |
---|---|
US (2) | US6362077B1 (en) |
EP (1) | EP0994503B1 (en) |
FR (1) | FR2784795B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040014299A1 (en) * | 2000-11-06 | 2004-01-22 | Hubert Moriceau | Method for making a stacked structure comprising a thin film adhering to a target substrate |
US20050032330A1 (en) * | 2002-01-23 | 2005-02-10 | Bruno Ghyselen | Methods for transferring a useful layer of silicon carbide to a receiving substrate |
US20050176222A1 (en) * | 2002-05-08 | 2005-08-11 | Atsushi Ogura | Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US9528196B2 (en) | 2011-07-25 | 2016-12-27 | Soitec | Method and device for fabricating a layer in semiconductor material |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (en) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | METHOD FOR THE TRANSFER OF A THIN FILM COMPRISING A STEP OF CREATING INCLUSIONS |
FR2809867B1 (en) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | FRAGILE SUBSTRATE AND METHOD FOR MANUFACTURING SUCH SUBSTRATE |
FR2811807B1 (en) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | METHOD OF CUTTING A BLOCK OF MATERIAL AND FORMING A THIN FILM |
FR2823599B1 (en) | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | DEMOMTABLE SUBSTRATE WITH CONTROLLED MECHANICAL HOLDING AND METHOD OF MAKING |
FR2823596B1 (en) * | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | SUBSTRATE OR DISMOUNTABLE STRUCTURE AND METHOD OF MAKING SAME |
FR2830983B1 (en) * | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING THIN FILMS CONTAINING MICROCOMPONENTS |
FR2845518B1 (en) * | 2002-10-07 | 2005-10-14 | Commissariat Energie Atomique | IMPLEMENTING A DEMONDABLE SEMICONDUCTOR SUBSTRATE AND OBTAINING A SEMICONDUCTOR ELEMENT |
US7176108B2 (en) * | 2002-11-07 | 2007-02-13 | Soitec Silicon On Insulator | Method of detaching a thin film at moderate temperature after co-implantation |
FR2847075B1 (en) * | 2002-11-07 | 2005-02-18 | Commissariat Energie Atomique | PROCESS FOR FORMING A FRAGILE ZONE IN A SUBSTRATE BY CO-IMPLANTATION |
US20040139531A1 (en) * | 2002-12-06 | 2004-07-22 | Moore Dan T. | Custom fitted helmet and method of making the same |
FR2848336B1 (en) * | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | METHOD FOR PRODUCING A STRESS STRUCTURE FOR DISSOCIATING |
JP4532846B2 (en) * | 2003-05-07 | 2010-08-25 | キヤノン株式会社 | Manufacturing method of semiconductor substrate |
FR2856844B1 (en) * | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | HIGH PERFORMANCE CHIP INTEGRATED CIRCUIT |
FR2857953B1 (en) | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | STACKED STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME |
FR2861497B1 (en) * | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION |
US7772087B2 (en) * | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
FR2886051B1 (en) | 2005-05-20 | 2007-08-10 | Commissariat Energie Atomique | METHOD FOR DETACHING THIN FILM |
FR2889887B1 (en) * | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | METHOD FOR DEFERING A THIN LAYER ON A SUPPORT |
DE102005052357A1 (en) * | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Method for the lateral dicing of a semiconductor wafer and optoelectronic component |
DE102005052358A1 (en) * | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Method for the lateral dicing of a semiconductor wafer and optoelectronic component |
FR2891281B1 (en) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM ELEMENT |
FR2899378B1 (en) * | 2006-03-29 | 2008-06-27 | Commissariat Energie Atomique | METHOD FOR DETACHING A THIN FILM BY FUSION OF PRECIPITS |
FR2910179B1 (en) * | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING THIN LAYERS OF GaN BY IMPLANTATION AND RECYCLING OF A STARTING SUBSTRATE |
FR2922359B1 (en) * | 2007-10-12 | 2009-12-18 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A MICROELECTRONIC STRUCTURE INVOLVING MOLECULAR COLLAGE |
FR2925221B1 (en) * | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | METHOD FOR TRANSFERRING A THIN LAYER |
CN102099894B (en) | 2008-08-27 | 2014-04-16 | S.O.I.Tec绝缘体上硅技术公司 | Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters |
US7967936B2 (en) * | 2008-12-15 | 2011-06-28 | Twin Creeks Technologies, Inc. | Methods of transferring a lamina to a receiver element |
FR2947098A1 (en) * | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | METHOD OF TRANSFERRING A THIN LAYER TO A TARGET SUBSTRATE HAVING A THERMAL EXPANSION COEFFICIENT DIFFERENT FROM THAT OF THE THIN LAYER |
US8114754B2 (en) * | 2009-11-18 | 2012-02-14 | S.O.I.Tec Silicon On Insulator Technologies | Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods |
US8569086B2 (en) * | 2011-08-24 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of dicing semiconductor devices |
CN104507853B (en) | 2012-07-31 | 2016-11-23 | 索泰克公司 | The method forming semiconductor equipment |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5328854A (en) * | 1993-03-31 | 1994-07-12 | At&T Bell Laboratories | Fabrication of electronic devices with an internal window |
US5513204A (en) * | 1995-04-12 | 1996-04-30 | Optical Concepts, Inc. | Long wavelength, vertical cavity surface emitting laser with vertically integrated optical pump |
US5796714A (en) * | 1994-09-28 | 1998-08-18 | Matsushita Electric Industrial Co., Ltd. | Optical module having a vertical-cavity surface-emitting laser |
US5812571A (en) * | 1996-10-25 | 1998-09-22 | W. L. Gore & Associates, Inc. | High-power vertical cavity surface emitting laser cluster |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5256581A (en) * | 1991-08-28 | 1993-10-26 | Motorola, Inc. | Silicon film with improved thickness control |
FR2681472B1 (en) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL. |
FR2714524B1 (en) * | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | PROCESS FOR MAKING A RELIEF STRUCTURE ON A SUPPORT IN SEMICONDUCTOR MATERIAL |
FR2744285B1 (en) * | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | METHOD FOR TRANSFERRING A THIN FILM FROM AN INITIAL SUBSTRATE TO A FINAL SUBSTRATE |
FR2748851B1 (en) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | PROCESS FOR PRODUCING A THIN FILM OF SEMICONDUCTOR MATERIAL |
US5783477A (en) * | 1996-09-20 | 1998-07-21 | Hewlett-Packard Company | Method for bonding compounds semiconductor wafers to create an ohmic interface |
KR100232886B1 (en) * | 1996-11-23 | 1999-12-01 | 김영환 | Soi wafer fabricating method |
FR2758907B1 (en) * | 1997-01-27 | 1999-05-07 | Commissariat Energie Atomique | METHOD FOR OBTAINING A THIN FILM, PARTICULARLY A SEMICONDUCTOR, WITH A PROTECTED AREA OF IONS, AND INVOLVING AN ION IMPLANTATION STEP |
US6013563A (en) * | 1997-05-12 | 2000-01-11 | Silicon Genesis Corporation | Controlled cleaning process |
-
1998
- 1998-10-16 FR FR9813010A patent/FR2784795B1/en not_active Expired - Fee Related
-
1999
- 1999-10-06 US US09/413,483 patent/US6362077B1/en not_active Expired - Lifetime
- 1999-10-14 EP EP99402531.0A patent/EP0994503B1/en not_active Expired - Lifetime
-
2002
- 2002-02-06 US US10/071,999 patent/US20020094668A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5328854A (en) * | 1993-03-31 | 1994-07-12 | At&T Bell Laboratories | Fabrication of electronic devices with an internal window |
US5796714A (en) * | 1994-09-28 | 1998-08-18 | Matsushita Electric Industrial Co., Ltd. | Optical module having a vertical-cavity surface-emitting laser |
US5513204A (en) * | 1995-04-12 | 1996-04-30 | Optical Concepts, Inc. | Long wavelength, vertical cavity surface emitting laser with vertically integrated optical pump |
US5812571A (en) * | 1996-10-25 | 1998-09-22 | W. L. Gore & Associates, Inc. | High-power vertical cavity surface emitting laser cluster |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6974759B2 (en) * | 2000-11-06 | 2005-12-13 | Commissariat A L'energie Atomique | Method for making a stacked comprising a thin film adhering to a target substrate |
US8679946B2 (en) | 2000-11-06 | 2014-03-25 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate |
US8481409B2 (en) | 2000-11-06 | 2013-07-09 | Commissariat A L'energie Atomique | Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate |
US20040014299A1 (en) * | 2000-11-06 | 2004-01-22 | Hubert Moriceau | Method for making a stacked structure comprising a thin film adhering to a target substrate |
US7262113B2 (en) | 2002-01-23 | 2007-08-28 | S.O.I.Tec Silicon On Insulator Technologies | Methods for transferring a useful layer of silicon carbide to a receiving substrate |
US6974760B2 (en) * | 2002-01-23 | 2005-12-13 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Methods for transferring a useful layer of silicon carbide to a receiving substrate |
US20050266659A1 (en) * | 2002-01-23 | 2005-12-01 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Methods for transferring a useful layer of silicon carbide to a receiving substrate |
US20050032330A1 (en) * | 2002-01-23 | 2005-02-10 | Bruno Ghyselen | Methods for transferring a useful layer of silicon carbide to a receiving substrate |
US7605443B2 (en) * | 2002-05-08 | 2009-10-20 | Nec Corporation | Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods |
US20050176222A1 (en) * | 2002-05-08 | 2005-08-11 | Atsushi Ogura | Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US8389385B2 (en) | 2009-02-04 | 2013-03-05 | Micron Technology, Inc. | Semiconductor material manufacture |
US9528196B2 (en) | 2011-07-25 | 2016-12-27 | Soitec | Method and device for fabricating a layer in semiconductor material |
Also Published As
Publication number | Publication date |
---|---|
US6362077B1 (en) | 2002-03-26 |
EP0994503A1 (en) | 2000-04-19 |
FR2784795B1 (en) | 2000-12-01 |
EP0994503B1 (en) | 2016-08-24 |
FR2784795A1 (en) | 2000-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6362077B1 (en) | Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure | |
US7939428B2 (en) | Methods for making substrates and substrates formed therefrom | |
US7498245B2 (en) | Embrittled substrate and method for making same | |
US8975156B2 (en) | Method of sealing two plates with the formation of an ohmic contact therebetween | |
US7741678B2 (en) | Semiconductor substrates having useful and transfer layers | |
US4891329A (en) | Method of forming a nonsilicon semiconductor on insulator structure | |
US7535115B2 (en) | Wafer and method of producing a substrate by transfer of a layer that includes foreign species | |
US20060286771A1 (en) | Layer transfer technique | |
EP3352207B1 (en) | Method for separating semiconductor substrate body from functional layer thereon | |
CN102543678B (en) | Method for cleaving a substrate | |
US7208392B1 (en) | Creation of an electrically conducting bonding between two semi-conductor elements | |
CN101315967A (en) | III-V nitride semiconductor layer-bonded substrate and semiconductor device | |
CN1708843B (en) | Method of detaching a thin film at moderate temperature after co-implantation | |
KR20100075877A (en) | Process for obtaining a hybrid substrate comprising at least one layer of a nitrided material | |
JP2023519165A (en) | Method for manufacturing a composite structure comprising a thin layer made of monocrystalline SiC on a carrier substrate made of SiC | |
WO2011008427A1 (en) | Method of bonding using a bonding layer based on zinc, silicon and oxygen and corresponding structures | |
Di Cioccio et al. | III–V layer transfer onto silicon and applications | |
JP3406376B2 (en) | Method for manufacturing compound semiconductor device | |
US20220223467A1 (en) | Method for direct hydrophilic bonding of substrates | |
JPH01266716A (en) | Gaas/si multilayer and gaas growth method | |
JP3193269B2 (en) | Method of forming semiconductor quantum wire structure | |
Ahadian et al. | Monolithic OEICs using GaAs VLSI technology | |
Gerard et al. | Monolithic Integration of III-V Microcavity Leds on Silicon Drivers using Conformal Epitaxy | |
JPH0468523A (en) | Heat treatment method | |
JPS63146482A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |