US20020064951A1

US20020064951A1 - Treatment of low-k dielectric films to enable patterning of deep submicron features

Info

Publication number: US20020064951A1
Application number: US09/997,775
Authority: US
Inventors: Mona Eissa; Guoqiang Xing; Kenneth Brennan; Hyesook Hong
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2000-11-30
Filing date: 2001-11-30
Publication date: 2002-05-30
Also published as: US20020127876A1; US6605536B2

Abstract

Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H₂O₂) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130,132). The wet treatment is performed to either pre-treat a low-k dielectric (104) before forming the pattern (130,132) or during a rework of the pattern (130,132) to reduce resist poisoning.

Description

FIELD OF THE INVENTION

The invention is generally related to the field of forming interconnect layers in a semiconductor device and more specifically to patterning low-k dielectric films.

BACKGROUND OF THE INVENTION

As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects and from traditional silicon-dioxide-based dielectrics to low-k dielectrics, such as organo-silicate glass (OSG). Semiconductor fabrication processes for working with the copper interconnects and newer low-k dielectrics are still needed.

Suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed. In a damascene process, the IMD is formed first. The IMD is then patterned and etched to form a trench for the interconnect line. If connection vias have not already been formed, a dual damascene process may be used. In a dual damascene process, after the trench is formed in the IMD, a via is etched in the ILD for connection to lower interconnect levels. A barrier layer and a copper seed layer are then deposited over the structure. The barrier layer is typically tantalum nitride or some other binary transition metal nitride. The copper layer is electrochemically deposited (ECD) using the seed layer over the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper from over the IMD, leaving copper interconnect lines and vias. A metal etch is thereby avoided.

When low-k dielectrics such as OSG are used for the IMD and ILD, a problem known as resist poisoning occurs. Resist poisoning occurs during a patterning step such as via pattern or trench pattern. It is a result of the interaction between a DUV (deep ultra-violet) resist and low-k films. Resist poisoning causes poor resist sidewall profiles, resist scumming, large CD variations, and requires a large resist exposure dose. Furthermore, the required pattern energy to achieve the target CD becomes too high and varies with film aging. A process to reduce or eliminate resist poisoning in low-k dielectrics is therefore desired.

SUMMARY OF THE INVENTION

The invention is a treatment for low-k films that improves patterning. The surface of the low-k film is oxidized using a highly oxidizing wet solution. Example wet solutions include H ₂SO₄:H₂O₂, HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O. The wet solution affects the surface of the film rendering patterning possible without disturbing the bulk properties of the low-k film. Wet treatment can be performed at various places in the semiconductor fabrication process with or without the presence of resist.

An advantage of the invention is providing a treatment to reduce resist poisoning of low-k dielectric films.

This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings: [0008]
FIGS. [0009] 1A-1F are cross-sectional diagrams of a process for forming metal interconnects according to the embodiments of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The invention will now be described in conjunction with dual damascene copper interconnect process. It will be apparent to those of ordinary skill in the art that the benefits of the invention may be applied generally to patterning of low-k (K<3.5???) and ultra-low-k (K<2.5) films. [0010]
In order to form the copper interconnects using a dual damascene process, the interlevel dielectrics (IMD [0011] 104 and ILD 102 of FIG. 1A) are patterned and etched to form trenches in IMD 104 and vias in ILD 102. When low-k or ultra low-k materials are used for the interlevel dielectrics, an interaction between the resist pattern and the low-k material causes resist poisoning. The cause of resist poisoning is believed to be the interaction of between the DUV resist and nitrogen from the low-k films. Possible sources of nitrogen include: the low-k film, the silicon nitride cap (if used), N₂in the clean (ash) process, N₂in the etch chemistry, use of a silicon-nitride etchstop layer, and the resist itself.
In order to reduce or eliminate the resist poisoning, a highly oxidizing wet treatment is performed on the surface of the low-k films. Only the top monolayers of the low-k film are affects. HOW DOES OXIDIZING THE TOP MONOLAYERS PREVENT RESIST POISONING?[0012]
The bulk properties of the film are unchanged. There is no significant change in the thickness, the refractive index, or the FTIR spectra of the low-k films subjected to a highly oxidizing wet solution according to the invention. Example chemistries for the highly oxidizing wet solution include H[0013] ₂SO₄: H₂O₂, HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O. In the preferred embodiment, H₂SO₄:H₂O₂is used at a ratio on the order of 4:1 at a temperature on the order of 120° C. and a duration of around 30 minutes. WOULD THE WAFERS TYPICALLY BE SET IN A BATH OF THE WET SOLUTION?
The above treatment using a highly oxidizing wet solution is beneficial at a variety of places in a metal interconnect process. The embodiments described below provide examples of where the wet treatment may be performed to reduce or eliminate resist poisoning. These embodiments may be combined to further reduce or eliminate resist poisoning. [0014]
Embodiments of the invention will now be discussed with reference to FIGS. [0015] 1A-1F. A semiconductor body 100 is processed through formation of the ILD 102/IMD 104. Semiconductor body 100 typically comprises a silicon substrate having transistors and other elements formed therein. IMD 104 is the dielectric for a copper interconnect level 114. Copper interconnect level 114 may be the first or any subsequent metal interconnect level of the semiconductor device 120.
An ILD [0016] 102 is formed over semiconductor body 100. IMD 104 is formed over ILD 102. An etchstop layer (not shown) may optionally be placed between ILD 102 and IMD 104. ILD 102 and IMD 104 comprise low-k or ultra low-k dielectrics, such as organo-silicate glass (OSG). WHAT OTHER CLASSES OF DIELECTRIC MAY BE USED?
In the preferred embodiment, ILD [0017] 102 and IMD 104 comprise the same material. However, ILD 102 and IMD 104 may alternatively comprise different materials. A capping layer (not shown) may be formed over IMD 104 if desired. Typically, the capping layer comprises silicon nitride. Alternatively, a TEOS (tetraethyoxtsilane) capping layer or no capping layer may be used.
In a first embodiment of the invention the wet treatment (using a highly oxidizing [0018] wet solution 136 as described above) is performed prior to forming the via pattern 130. This oxidizes the top monolayers of the IMD 104. SHOULD I SHOWA SEPARATE SURFACE LAYER AT THE SURFACE OF IMD 104 AFTER THE WET TREATMENT? Then, the via pattern 130 is formed as shown in FIG. 1B. The wet pre-treatment reduces resist poisoning at the via pattern level.
It is sometimes necessary to rework a resist pattern. Rework is a process of removing the photoresist and/or BARC material for re-patterning. Pattern rework significantly worsens the resist poisoning problem. Accordingly, in a second embodiment of the invention, the wet treatment (using a highly oxidizing wet solution) may be used to rework via [0019] pattern 130. The wet treatment both strips the resist pattern and oxidizes the top monolayers of IMD 104.
After any desired pattern re-work, the via [0020] 106 is then etched through IMD 104 and ILD 102, as shown in FIG. 1C. A post etch clean is then used to remove via pattern 106. WOULD A N2/H2 ASH BE USED HERE? THE PATENT COMMITTEE COMMENTED THAT THE H2O2 SHOULD NOT BE USED WITH THE VIAS OPENED.
In order to protect the bottom of [0021] vias 106 during the subsequent trench etch, vias 106 may be partially or completely filled. For example, a BARC material may be deposited over the structure and etched back such that BARC material remains only in the vias 106.
In a third embodiment of the invention, the exposed surfaces of IMD [0022] 104 (and ILD 102 if appropriate) may be pre-treated with the highly oxidizing wet solution prior to forming the trench pattern. CAN THE WET TREATMENT BE USED AT THIS POINT? Pre-treatment prior to forming the trench pattern eliminates or reduces resist poisoning at the trench pattern level.
After a post etch clean and wet pre-treatment if desired, a [0023] trench pattern 132 may be formed over IMD 104, as shown in FIG. 1D. If rework of the trench pattern 132 is desired, the wet treatment may be used to rework the trench pattern 132, according to a fifth embodiment of the invention. The wet treatment functions to strip the trench pattern and reduce resist poisoning at the trench pattern level.
After any desired pattern rework, a trench [0024] 108 is etched in IMD 104, as shown in FIG. 1 E. Copper interconnect structures will subsequently be formed in trench 108. Trench pattern 132 is then removed. WOULD A N2/H2 ASH BE USED FOR THIS?
[0025] Barrier layer 110 is deposited over IMD 104 including in trench 108 and via 106. Barrier layer 110 functions to prevent copper diffusion into the ILD and IMD layers. Suitable barrier materials such as Ta/TaN are known in the art. A seed layer is deposited over barrier layer 110.
Electrochemical deposition (ECD) may then be used to deposit [0026] copper layer 124. Various copper ECD processes are known in the art. In one example, a 3-step process is used. After placing the wafer in the plating solution, a current of approximately 0.75 Amps is passed through the seed layer for a time on the order of 15 secs. The current is then increased to around 3 Amps for approximately 60 seconds. Final plating occurs at a current of about 7.5 Amps with the duration determined by the final desired thickness. A quick spin-rinse dry (SRD) is performed in the plating cell above the plating solution. The wafer is then transferred to the SRD cell and a post-ECD SRD is used to clean the plating residue.
After copper ECD, the [0027] copper 124 and barrier 110 are chemically mechanically polished (CMP) to remove the material from above IMD 104. The resulting structure is shown in FIG. 1 F. Processing may then continue to form additional metal interconnect levels and package the device.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments. [0028]

Claims

1. A method for fabricating an integrated circuit, comprising the steps of:

forming a low-k dielectric layer over a semiconductor body;

treating a surface of said low-k dielectric layer with a highly oxidizing wet solution;

forming a resist pattern over said low-k dielectric layer; and

etching said low-k dielectric layer using said resist pattern.

2. The method of claim 1, wherein said highly oxidizing wet solution comprises H₂O₂.

3. The method of claim 1, wherein said highly oxidizing wet solution is selected from the group consisting of H₂SO₄:H₂O₂, HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O.

4. The method of claim 1, wherein said low-k dielectric layer comprises organo-silicate glass.

5. The method of claim 1, wherein said low-k dielectric layer comprises an ultralow-k dielectric layer having a dielectric constant less than 2.5.

6. The method of claim 1, wherein said treating step occurs prior to forming said resist pattern.

7. The method of claim 1, wherein said treating step removes said resist pattern as part of a pattern re-work step.

8. A method of fabricating an integrated circuit having copper metal interconnects, comprising the steps of:

forming an interlevel dielectric (ILD) over a semiconductor body;

forming an intrametal dielectric (IMD) over the ILD;

oxidizing said IMD with a highly oxidizing wet solution;

forming a via resist pattern over said IMD;

etching a via in said IMD and ILD using said via resist pattern;

at least partially filling said via with a material;

forming a trench resist pattern over said IMD;

etching a trench in said IMD using said trench resist pattern;

removing said trench resist pattern and said material in said via; and

forming a copper interconnect in said via and said trench.

9. The method of claim 8, wherein said highly oxidizing wet solution comprises H₂O₂.

10. The method of claim 8, wherein said highly oxidizing wet solution is selected from the group consisting of H₂SO₄:H₂O₂, HNO₃:H₂O₂, H₂O₂:H₂O, and O₃:H₂O.

11. The method of claim 8, wherein said oxidizing step occurs prior to the step of forming the via resist pattern.

12. The method of claim 11, further comprising the step of additionally treating the IMD using a highly oxidizing wet solution after said step of at least partially filling the via and prior to the step of etching the trench.

13. The method of claim 8, wherein said oxidizing step occurs after the step of forming the via resist pattern as part of a pattern re-work step.

14. The method of claim 8, wherein said oxidizing step occurs after said step of at least partially filling the via and prior to the step of etching the trench.