US20020045301A1 - Semiconductor device and method for protecting such device from a reversed drain voltage - Google Patents
Semiconductor device and method for protecting such device from a reversed drain voltage Download PDFInfo
- Publication number
- US20020045301A1 US20020045301A1 US09/510,814 US51081400A US2002045301A1 US 20020045301 A1 US20020045301 A1 US 20020045301A1 US 51081400 A US51081400 A US 51081400A US 2002045301 A1 US2002045301 A1 US 2002045301A1
- Authority
- US
- United States
- Prior art keywords
- region
- type
- conductivity type
- channel
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000000034 method Methods 0.000 title claims description 14
- 210000000746 body region Anatomy 0.000 claims abstract description 26
- 230000005669 field effect Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 26
- 238000002955 isolation Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 claims description 2
- 108091006146 Channels Proteins 0.000 claims 7
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims 3
- 230000000903 blocking effect Effects 0.000 abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Definitions
- This invention relates generally to a field effect transistor and to a method for protecting such device, and more specifically to a lateral double diffused metal oxide semiconductor (LDMOS) field effect transistor and to a method for protecting that device from a reversed drain voltage.
- LDMOS lateral double diffused metal oxide semiconductor
- Semiconductor devices including discrete devices and integrated circuits, are designed to operate correctly upon the application of specified voltages to the terminals of the devices. Most semiconductor devices would not survive if the voltages applied to the devices were of the reverse polarity from the specified voltages. Some semiconductor devices are designed, for example, to operate with plus 12 volts applied to a given device terminal and most would not survive the application of minus 12 volts to that terminal. Most of such devices would be subjected to a very large and destructive current if the battery connection was accidentally reversed in this manner. Upon the application of the reversed voltage, diodes that are normally reverse biased and able to block an applied voltage of normal polarity would become forward biased and would draw a large forward bias current.
- the protective device is a MOSFET (metal oxide semiconductor field effect transistor) in series with the device to be protected
- MOSFET metal oxide semiconductor field effect transistor
- the intrinsic body diode of the MOSFET efficiently blocks any large current that might otherwise flow under reverse battery conditions.
- the on resistance (Rd on) of the protective MOSFET is in series with the resistance of the protected circuit.
- the protective MOSFET must be made large. A large additional device is costly and is an inefficient use of available semiconductor area, especially if the protective device is to be integrated with the protected circuit.
- FIG. 1 illustrates schematically, in cross-section, a portion of a prior art semiconductor device
- FIG. 2 illustrates schematically an integrated half bridge, including intrinsic diodes, utilizing the prior art structure of FIG. 1;
- FIG. 3 illustrates schematically, in cross section, a field effect transistor in accordance with an embodiment of the invention
- FIG. 4 illustrates schematically the device of FIG. 3 including intrinsic devices formed therewith
- FIG. 5 illustrates schematically an application of an embodiment of the invention in an integrated application including intrinsic devices formed therewith.
- FIG. 1 illustrates, in cross-section, a portion of a prior art semiconductor device 20 .
- Device 20 is a typical lateral double diffused metal oxide-semiconductor (LDMOS) field effect transistor that might be one of many such devices constituting an integrated circuit structure.
- LDMOS metal oxide-semiconductor
- the integrated circuit might also include other MOS transistors and/or other bipolar transistors.
- MOS specifically derives from “metaloxide-semiconductor,” it will be used herein in its more generic sense to refer to any insulated gate field effect transistor regardless of the material used for either the gate electrode or the gate insulator.
- Device 20 includes a P-type silicon substrate 22 on which a high conductivity N-type buried layer 24 is formed.
- An N-type epitaxial layer 26 is grown overlying buried layer 24 .
- a P-type body region 28 is formed in epitaxial layer 26 .
- High conductivity N-type source region 30 and drain region 32 are formed in the body region and epitaxial layer, respectively.
- the portion of body region 28 that lies between source region 30 and the epitaxial layer 26 forms a diffused channel 34 of the MOS transistor.
- a gate electrode 36 overlies channel 34 and is insulated from the channel by a gate dielectric (not shown).
- a heavily doped P-type region 38 is also formed in body region 28 .
- a conductive electrode 40 makes electrical contact to source region 30 and to P-type region 38 and electrically shorts the two regions together. The short between source region 30 and P-type region 38 effectively shorts the source region to body region 28 .
- a conductive electrode 42 makes electrical contact to drain region 32 . Terminals 44 , 46 , and 48 make electrical contact to the source, gate, and drain, respectively, of the LDMOS transistor.
- drain region 32 is biased positively with respect to source region 30 .
- a bias applied to gate electrode 36 modulates the conductivity of channel 34 and causes the controlled flow of current between source and drain.
- substrate 22 is normally maintained at the lowest potential available for operation of the circuit, often at the same potential as the source region.
- Diode 50 is a pn junction diode formed by body region 28 and epitaxial layer 26 .
- a second diode, pn junction diode 52 is formed by substrate 22 and buried layer 24 .
- both diodes are reversed biased, and the only current that flows through these diodes is the very low current associated with a reverse biased diode. This is in addition, of course, to the normal current that flows from source to drain through channel 34 if a voltage in excess of the threshold voltage is applied to gate 36 .
- both diodes would be forward biased and a large forward bias diode current would flow through the device.
- the forward bias diode current flowing through device 20 might have serious consequences, even to the extent of resulting in the destruction of device 20 .
- FIG. 2 illustrates schematically one application in which two devices 60 and 62 , each similar to device 20 , might be serially connected to form an integrated half bridge 58 .
- Such an integrated device finds application, for example, in the automotive industry.
- An automotive battery or other power supply (not illustrated) is coupled between a terminal 64 at the drain of device 60 and ground.
- the substrate of the integrated device is coupled to ground.
- LDMOS transistor 60 forms a high side switch controlled by a gate terminal 68 and LDMOS transistor 62 forms a low side switch controlled by a gate terminal 70 .
- the output of the integrated half bridge is taken at output terminal 66 .
- Four intrinsic diodes are formed as part of the integrated half bridge in a similar manner to the formation of diodes 50 and 52 illustrated in FIG. 1. The corresponding diodes have been labeled by these same numerals in FIG. 2.
- Integrated half bridge 58 functions normally if terminal 64 is coupled to the positive terminal of the applied power supply. If, however, the applied power supply terminals are reversed and terminal 64 is coupled to the negative terminal of the applied power supply, diodes 50 and 52 are forward biased and bridge 58 malfunctions or, in a worst case, is destroyed.
- One solution has been to connect an additional MOS transistor in series with the half bridge.
- the additional MOS transistor is coupled between substrate 22 and ground in a polarity reversed from that of device 62 . That is, the substrate and source of the additional transistor are coupled to the substrate and source of device 62 so that substrate 22 is raised above ground and the intrinsic diodes in the additional transistor are reversed with respect to diodes 50 and 52 .
- diodes 50 and 52 are inadvertently biased in the forward direction, the intrinsic diodes in the additional transistor are reverse biased. The reverse biased diodes prevent the unwanted flow of a large current during the reversed battery condition.
- the intrinsic diodes in the additional transistor are forward biased and are shunted by the channel of the additional MOS transistor.
- the on resistance of the additional transistor is in series with the half bridge. Because any additional resistance is undesirable, the additional transistor must be made large to reduce its on resistance. The solution, though effective, is undesirable.
- FIG. 3 illustrates schematically, in cross-section, a dual gate LDMOS transistor 80 in accordance with one embodiment of the invention that overcomes the aforementioned problems and provides protection against the inadvertent reversal of applied potential to the device.
- Dual gate LDMOS transistor 80 includes a semiconductor substrate 22 formed of P-type silicon. Overlying at least a portion of the semiconductor substrate 22 is a heavily doped, high conductivity N-type buried layer 24 . Those of skill in the art will recognize that buried layer 24 will be patterned so as to be present in those portions of the integrated circuit that require such a low conductivity region. Overlying buried layer 24 is an epitaxial layer 26 of N-type silicon.
- a low resistivity connection to buried layer 24 can be made, if necessary, through a deep, heavily doped N-type diffused region 27 . Additionally, a deep, P-type doped region 31 extending from the surface of epitaxial layer 26 to the underlying P-type substrate 24 can be formed to effectively isolate transistor 80 from other components of the integrated circuit.
- a P-type body region 28 formed in epitaxial layer 26 provides a channel 34 at a surface 35 of epitaxial layer 26 .
- a source region 30 of N-type conductivity is formed at surface 35 within body region 28 .
- a high conductivity P-type region 38 is also formed at the surface in body region 28 .
- a source electrode 40 forms an electrical short between source region 30 and high conductivity P-type region 38 . This short serves to electrically short the source to the body region.
- an additional, electrically floating, P-type blocking region 82 is formed at the surface of epitaxial layer 26 at a location spaced apart from body region 28 .
- the portion of epitaxial region 26 located between body region 28 and floating P-type blocking region 82 forms a drift region 92 .
- a pn junction is formed between the P-type blocking region and the N-type drift region.
- Drain region 32 is formed in P-type blocking region 82 at surface 35 of the epitaxial layer so that P-type blocking region 82 surrounds the drain region at surface 35 .
- a gate electrode 36 controls the conductivity of channel 34 formed at the surface of body region 28 .
- a gate electrode 84 (and hence the name “dual gate” LDMOS) controls the conductivity of a second channel 88 formed at surface 35 of P-type blocking region 82 .
- An electrode 42 makes contact to drain region 32 .
- Terminals 44 , 46 , and 48 provide electrical contact to the source, gate electrode 36 , and drain, respectively.
- An additional terminal 86 provides electrical contact to gate electrode 84 .
- Gate electrode 36 overlies channel 34 and gate electrode 84 overlies channel 88 of P-type blocking region 82 .
- each of the gate electrodes is spaced apart from the surface of the semiconductor material by a gate insulator such as silicon dioxide or the like.
- Terminal 90 is coupled to heavily doped N-type region 27 and terminal 23 is coupled to substrate 22 .
- contact to substrate 22 can be made through a terminal 91 coupled to P-type region 31 .
- drain terminal 48 is biased positively with respect to source terminal 44 .
- Substrate terminal 23 is held at the lowest potential available for the circuit.
- Terminal 46 coupled to gate electrode 36 , receives a control signal. When the control signal exceeds the threshold voltage of the device, current is conducted from source 30 through channel 34 to a drift region 92 at surface 35 of epitaxial layer 26 . The signal applied to gate electrode 36 thus controls the flow of current through channel 34 .
- Gate terminal 86 coupled to gate electrode 84 , is maintained at a sufficiently positive bias to invert the surface of electrically floating P-type blocking region 82 and to thereby form channel 88 .
- the voltage applied to gate electrode 84 thus modulates the conductivity of channel 88 and controls the flow of current through channel 88 .
- a current carrying path thus exists from source region 30 , through channel 34 and drift region 92 , to drain region 32 through the inverted surface of P-type region 82 .
- terminal 86 is coupled to terminal 48 so that both are coupled to receive the battery voltage. If the battery is properly connected so that terminal 48 is positive, gate electrode 84 is also positive and channel 88 is conducting. If the battery connection is reversed, terminal 48 is negative as is gate electrode 84 . With negative bias on gate electrode 84 , channel 88 is non conductive. Preferably terminal 90 is grounded.
- terminal 86 is coupled to a logic circuit (not illustrated) that controls the bias on gate electrode 84 .
- the logic circuit can apply any appropriate bias to the gate electrode.
- the logic circuit can apply the same bias as is applied to the drain or, in some applications can apply a bias such as the drain voltage plus an additional positive voltage. The additional voltage may be necessary when, for example, device 80 is used in an application for which the source of the device can swing to positive voltages.
- the logic circuit can control the bias applied to terminal 90 and hence to contact region 27 and buried layer 24 . By controlling the bias on buried layer 24 , the potential of epitaxial layer 26 and drift region 92 can be controlled.
- device 80 illustrated in FIG. 3 can be viewed as including three intrinsic bipolar transistors: a lateral pnp transistor, a vertical pnp transistor, and an npn transistor.
- FIG. 4 schematically illustrates the connection of the three intrinsic bipolar transistors as part of the dual gated LDMOS transistor.
- Lateral pnp transistor 100 includes a P-type emitter region formed by body 28 , an N-type base region formed by epitaxial layer 26 , and a P-type collector region formed by P-type blocking region 82 .
- Vertical pup transistor 102 includes a P-type emitter formed by P-type substrate 22 , an N-type base formed by epitaxial layer 26 , and a P-type collector formed by P-type blocking region 82 .
- An npn transistor 104 includes an N-type emitter formed by drain region 32 , a P-type base region formed by P-type blocking region 82 , and an N-type collector formed by epitaxial layer 26 .
- the three transistors form two thyristors.
- a lateral thyristor is formed by lateral pup transistor 100 in combination with npn transistor 104 .
- a vertical thyristor is formed by vertical pup transistor 102 in combination with npn transistor 104 .
- the intrinsic transistors and hence the intrinsic thyristors are preferably designed and implemented to avoid latching of either of the thyristors.
- a thyristor will not latch if the product of the current gains of the two respective transistors ( ⁇ n for the npn transistor and ⁇ p for the pup transistor) is less than one.
- ⁇ n will in most cases be less than about 100 if the same dopant distribution is used for P-type blocking region 82 as is used for body region 28 .
- the current gain for the vertical pnp transistor, ⁇ p is very low, usually less than about 0 . 005 , because of the presence of the heavily doped buried layer 24 . This follows from the fact that the current 5 gain of a transistor is inversely proportional to the integrated base doping under the emitter, and in the case of pnp transistor 102 , the base doping includes the doping in buried layer 24 .
- the product ⁇ n ⁇ p for the two transistors that form the vertical thyristor therefore is less than one.
- FIG. 5 illustrates schematically an integrated half bridge 150 , in which a device 80 , in accordance with the invention, is used as a high side switch.
- Source region 30 of LDMOS transistor 80 is coupled to drain 132 of MOS transistor 162 .
- Source 130 of transistor 162 is coupled to ground.
- the output of the half bridge is taken at terminal 66 coupled to source 30 of transistor 80 and to drain 132 of transistor 162 .
- the intrinsic transistors 100 , 102 , and 104 as well as intrinsic diode 50 associated with transistor 62 are also illustrated.
- terminal 48 is inadvertently coupled to a negative voltage.
- the lateral thyristor that includes npn transistor 104 and lateral pnp transistor 100 can turn on only if lateral pnp transistor 100 itself turns on. In order for the lateral pnp transistor to turn on, however, the emitter-base junction of the pnp transistor must be forward biased.
- a voltage of V be (the voltage drop across a forward biased pn junction diode) must be applied across the emitter-base junction.
- Such a voltage drop cannot occur across the emitter-base junction of lateral pnp transistor 100 because the emitter of transistor 100 is at one V be above ground because of 30 the forward bias across body diode 50 .
- the base of pnp transistor 100 is also one V be above ground because the emitter of lateral pnp transistor 102 is coupled to ground.
- the base of transistor 102 (which is also the base of transistor 100 ) cannot be more than one V be more positive than its emitter. Therefore, when transistor structure 80 is used as the high side switch in an integrated half bridge, the lateral thyristor cannot turn on.
- grounding terminal 90 grounds the base of lateral pnp transistor 100 and prevents the base-emitter junction of that device from being forward biased.
- the amount of reversed voltage that can be successfully sustained by device structure 80 is determined, at least in part, by the spacing between body region 28 and blocking region 82 . If a negative voltage is applied to terminal 48 , the pn junction formed between blocking region 82 and epitaxial layer 26 (or drift region 92 ) is reversed biased. As the depletion spread from the reverse biased junction spreads across the drift region at the surface of epitaxial layer 26 , the spread eventually, upon the application of sufficient reverse bias voltage, reaches body region 28 and punch through breakdown occurs. The spacing between regions 28 and 82 must, therefore, be adjusted to accommodate the maximum expected reversed voltage that may be applied across the pn junction formed by P-type blocking region 82 and epitaxial layer 26 .
- a semiconductor device in accordance with an embodiment of the invention, such as device 80 illustrated in FIG. 3 can be fabricated using conventional integrated circuit fabrication techniques.
- Device 80 can be fabricated, for example, as part of an integrated circuit structure on a P-type semiconductor substrate having a resistivity of about 6 Ohm centimeter.
- a buried layer can be formed by selectively diffusing arsenic into portions of the upper surface of the silicon substrate.
- the buried layer may be used in other portions of the circuit, for example, to reduce the collector resistance of an npn transistor if the integrated circuit being fabricated utilizes both bipolar and field effect transistors.
- the buried layer can have, for example, a sheet resistivity of about 18 Ohms per square.
- an N-type epitaxial layer having a resistivity of about 1 Ohm centimeter can be deposited to a thickness of about 10 micrometers.
- Insulating layers for device isolation and for gate electrodes can be formed on the surface of the epitaxial layer.
- the gate insulator can be formed, for example, by thermal oxidation to form a silicon dioxide layer having a thickness of 35 nanometers.
- Gate electrodes can be formed overlying the gate insulator by the deposition and patterning of a layer of polycrystalline silicon.
- the polycrystalline silicon can be deposited to a thickness of about 400 nanometers.
- the patterned polycrystalline silicon is then preferably used as an ion implantation mask for the P-type ion implantion doping of the body region and the floating blocking region.
- the body region and blocking region are preferable doped with boron to a dose that yields, after a subsequent thermal redistribution step, regions having a junction depth of about 2 micrometers and a sheet resistivity of about 600 Ohms per square.
- a punch through voltage of about 13.5 volts can be assured. This is sufficient to provide protection against the application of a reversed voltage of about 12 volts.
- the patterned polycrystalline silicon is then used as an ion implantation mask for the N-type ion implantion doping of the source and drain regions.
- the source and drain regions are preferably doped with arsenic and have a depth of about 0.4 micrometers and a sheet resistivity of about 50 Ohms per square.
- Using the same patterned polycrystalline silicon to mask both ion implantations provides self alignment between the source and body and between the drain and floating blocking region.
- Using the polycrystalline gate regions as an ion implantation mask also provides self alignment between the gate electrode and the underlying channel. Contact to and interconnection of the various device regions can then be accomplished in conventional manner.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- BACKGROUND OF THE INVENTION
- This invention relates generally to a field effect transistor and to a method for protecting such device, and more specifically to a lateral double diffused metal oxide semiconductor (LDMOS) field effect transistor and to a method for protecting that device from a reversed drain voltage.
- Semiconductor devices, including discrete devices and integrated circuits, are designed to operate correctly upon the application of specified voltages to the terminals of the devices. Most semiconductor devices would not survive if the voltages applied to the devices were of the reverse polarity from the specified voltages. Some semiconductor devices are designed, for example, to operate with plus 12 volts applied to a given device terminal and most would not survive the application of minus 12 volts to that terminal. Most of such devices would be subjected to a very large and destructive current if the battery connection was accidentally reversed in this manner. Upon the application of the reversed voltage, diodes that are normally reverse biased and able to block an applied voltage of normal polarity would become forward biased and would draw a large forward bias current.
- There are a number of applications, however, that require semiconductor devices to survive the accidental application of reversed polarities. For example, in some automotive circuit applications the circuit specification requires the semiconductor devices to survive a “reverse battery condition.” This would be the condition that would occur if the automobile battery was accidentally connected in reverse.
- Solutions that ensure reliability in the event of a reversed voltage application have relied upon adding an additional component in series with the device that is to be protected. For example, in applications requiring such reliability, the typical integrated circuit has been protected by providing an additional protective device or circuit in series with the circuit to be protected. Essentially that amounts to providing a blocking diode in series with the protected circuit. The blocking diode is forward biased during normal operation of the integrated circuit, but is blocking or reverse biased in the event the polarity of the applied voltage is reversed. Such a solution requires one or more additional devices and each of these devices adds an additional unwanted resistance or voltage offset during normal operation of the integrated circuit. For example, if the protective device is a MOSFET (metal oxide semiconductor field effect transistor) in series with the device to be protected, the intrinsic body diode of the MOSFET efficiently blocks any large current that might otherwise flow under reverse battery conditions. Under normal operation of the protected circuit, the on resistance (Rd on) of the protective MOSFET is in series with the resistance of the protected circuit. To make this additional resistance as small as possible (and thus insignificant to the operation of the circuit) the protective MOSFET must be made large. A large additional device is costly and is an inefficient use of available semiconductor area, especially if the protective device is to be integrated with the protected circuit.
- In view of the foregoing problem and the lack of a suitable solution, a need exists for an integrated solution that provides the necessary voltage protection in the case of a reversed bias application, that does not add additional voltage offset, and that does not require the use of additional devices.
- FIG. 1 illustrates schematically, in cross-section, a portion of a prior art semiconductor device;
- FIG. 2 illustrates schematically an integrated half bridge, including intrinsic diodes, utilizing the prior art structure of FIG. 1;
- FIG. 3 illustrates schematically, in cross section, a field effect transistor in accordance with an embodiment of the invention;
- FIG. 4 illustrates schematically the device of FIG. 3 including intrinsic devices formed therewith; and
- FIG. 5 illustrates schematically an application of an embodiment of the invention in an integrated application including intrinsic devices formed therewith.
- FIG. 1 illustrates, in cross-section, a portion of a prior art semiconductor device20. Device 20 is a typical lateral double diffused metal oxide-semiconductor (LDMOS) field effect transistor that might be one of many such devices constituting an integrated circuit structure. The integrated circuit might also include other MOS transistors and/or other bipolar transistors. Although the term “MOS” specifically derives from “metaloxide-semiconductor,” it will be used herein in its more generic sense to refer to any insulated gate field effect transistor regardless of the material used for either the gate electrode or the gate insulator. The remainder of the term derives from the fact that the current through the device flows laterally, i.e., along the surface of the device, through a channel region that (in addition to the source and drain regions) is formed by impurity diffusion. For purposes of illustration only, all devices to be described herein will be N-channel silicon gate devices. Those of skill in the art will understand that such descriptions are equally applicable to P-channel devices. For such P-channel devices the conductivity of all regions would be reversed from the illustrated description and all voltage polarities would be reversed. That is, N-regions would be substituted for P-regions, and vice versa. Additionally, all devices described herein will be illustrated as silicon devices, but the description is equally applicable to devices fabricated in other semiconductor materials such as gallium arsenide or other III-V materials, II-VI materials, mixtures of silicon and germanium, and the like.
- Device20 includes a P-
type silicon substrate 22 on which a high conductivity N-type buriedlayer 24 is formed. An N-typeepitaxial layer 26 is grown overlying buriedlayer 24. A P-type body region 28 is formed inepitaxial layer 26. High conductivity N-type source region 30 anddrain region 32 are formed in the body region and epitaxial layer, respectively. The portion ofbody region 28 that lies betweensource region 30 and theepitaxial layer 26 forms adiffused channel 34 of the MOS transistor. Agate electrode 36 overlieschannel 34 and is insulated from the channel by a gate dielectric (not shown). A heavily doped P-type region 38 is also formed inbody region 28. Aconductive electrode 40 makes electrical contact tosource region 30 and to P-type region 38 and electrically shorts the two regions together. The short betweensource region 30 and P-type region 38 effectively shorts the source region tobody region 28. Aconductive electrode 42 makes electrical contact todrain region 32.Terminals - In its intended operation,
drain region 32 is biased positively with respect tosource region 30. A bias applied togate electrode 36 modulates the conductivity ofchannel 34 and causes the controlled flow of current between source and drain. During such operation,substrate 22 is normally maintained at the lowest potential available for operation of the circuit, often at the same potential as the source region. - As is illustrated, two PN junction diodes are intrinsically formed as part of device structure20.
Diode 50 is a pn junction diode formed bybody region 28 andepitaxial layer 26. A second diode,pn junction diode 52, is formed bysubstrate 22 and buriedlayer 24. During the normal operation of device 20, in whichdrain region 32 is more positive than eithersource region 30 orsubstrate 22, both diodes are reversed biased, and the only current that flows through these diodes is the very low current associated with a reverse biased diode. This is in addition, of course, to the normal current that flows from source to drain throughchannel 34 if a voltage in excess of the threshold voltage is applied togate 36. If, however, the polarity applied to device 20 is inadvertently reversed so thatdrain region 32 is biased more negatively thansource region 30 andsubstrate 22, as would be the case if battery connections attached to the device were reversed, both diodes would be forward biased and a large forward bias diode current would flow through the device. Unless somehow limited, for example, by an additional blocking diode or a current limiting resistor, the forward bias diode current flowing through device 20 might have serious consequences, even to the extent of resulting in the destruction of device 20. - FIG. 2 illustrates schematically one application in which two
devices 60 and 62, each similar to device 20, might be serially connected to form an integratedhalf bridge 58. Such an integrated device finds application, for example, in the automotive industry. An automotive battery or other power supply (not illustrated) is coupled between aterminal 64 at the drain ofdevice 60 and ground. The substrate of the integrated device is coupled to ground.LDMOS transistor 60 forms a high side switch controlled by a gate terminal 68 and LDMOS transistor 62 forms a low side switch controlled by a gate terminal 70. The output of the integrated half bridge is taken atoutput terminal 66. Four intrinsic diodes are formed as part of the integrated half bridge in a similar manner to the formation ofdiodes -
Integrated half bridge 58 functions normally ifterminal 64 is coupled to the positive terminal of the applied power supply. If, however, the applied power supply terminals are reversed and terminal 64 is coupled to the negative terminal of the applied power supply,diodes bridge 58 malfunctions or, in a worst case, is destroyed. - One solution (not illustrated) has been to connect an additional MOS transistor in series with the half bridge. The additional MOS transistor is coupled between
substrate 22 and ground in a polarity reversed from that of device 62. That is, the substrate and source of the additional transistor are coupled to the substrate and source of device 62 so thatsubstrate 22 is raised above ground and the intrinsic diodes in the additional transistor are reversed with respect todiodes diodes - FIG. 3 illustrates schematically, in cross-section, a dual
gate LDMOS transistor 80 in accordance with one embodiment of the invention that overcomes the aforementioned problems and provides protection against the inadvertent reversal of applied potential to the device. Like regions have been identified by like numerals. Dualgate LDMOS transistor 80 includes asemiconductor substrate 22 formed of P-type silicon. Overlying at least a portion of thesemiconductor substrate 22 is a heavily doped, high conductivity N-type buriedlayer 24. Those of skill in the art will recognize that buriedlayer 24 will be patterned so as to be present in those portions of the integrated circuit that require such a low conductivity region. Overlying buriedlayer 24 is anepitaxial layer 26 of N-type silicon. A low resistivity connection to buriedlayer 24 can be made, if necessary, through a deep, heavily doped N-type diffusedregion 27. Additionally, a deep, P-type dopedregion 31 extending from the surface ofepitaxial layer 26 to the underlying P-type substrate 24 can be formed to effectively isolatetransistor 80 from other components of the integrated circuit. - A P-
type body region 28 formed inepitaxial layer 26 provides achannel 34 at asurface 35 ofepitaxial layer 26. Asource region 30 of N-type conductivity is formed atsurface 35 withinbody region 28. A high conductivity P-type region 38 is also formed at the surface inbody region 28. Asource electrode 40 forms an electrical short betweensource region 30 and high conductivity P-type region 38. This short serves to electrically short the source to the body region. - In accordance with this embodiment of the invention, an additional, electrically floating, P-
type blocking region 82 is formed at the surface ofepitaxial layer 26 at a location spaced apart frombody region 28. The portion ofepitaxial region 26 located betweenbody region 28 and floating P-type blocking region 82 forms adrift region 92. A pn junction is formed between the P-type blocking region and the N-type drift region.Drain region 32 is formed in P-type blocking region 82 atsurface 35 of the epitaxial layer so that P-type blocking region 82 surrounds the drain region atsurface 35. Agate electrode 36 controls the conductivity ofchannel 34 formed at the surface ofbody region 28. A gate electrode 84 (and hence the name “dual gate” LDMOS) controls the conductivity of asecond channel 88 formed atsurface 35 of P-type blocking region 82. Anelectrode 42 makes contact to drainregion 32. -
Terminals gate electrode 36, and drain, respectively. Anadditional terminal 86 provides electrical contact togate electrode 84.Gate electrode 36 overlieschannel 34 andgate electrode 84 overlieschannel 88 of P-type blocking region 82. Although not illustrated in the figure, each of the gate electrodes is spaced apart from the surface of the semiconductor material by a gate insulator such as silicon dioxide or the like.Terminal 90 is coupled to heavily doped N-type region 27 andterminal 23 is coupled tosubstrate 22. Alternatively, contact tosubstrate 22 can be made through a terminal 91 coupled to P-type region 31. - In the normal operation of
device 80,drain terminal 48 is biased positively with respect to source terminal 44.Substrate terminal 23 is held at the lowest potential available for the circuit.Terminal 46, coupled togate electrode 36, receives a control signal. When the control signal exceeds the threshold voltage of the device, current is conducted fromsource 30 throughchannel 34 to adrift region 92 atsurface 35 ofepitaxial layer 26. The signal applied togate electrode 36 thus controls the flow of current throughchannel 34.Gate terminal 86, coupled togate electrode 84, is maintained at a sufficiently positive bias to invert the surface of electrically floating P-type blocking region 82 and to thereby formchannel 88. The voltage applied togate electrode 84 thus modulates the conductivity ofchannel 88 and controls the flow of current throughchannel 88. A current carrying path thus exists fromsource region 30, throughchannel 34 and driftregion 92, to drainregion 32 through the inverted surface of P-type region 82. - Because of the presence of the additional P-type blocking region,
device 80 is protected from the inadvertent application toterminal 48 of a bias that is more negative than the bias applied to terminal 44 or toterminal 23. The intrinsic diodes illustrated in FIG. 1, that is,diodes region 32. Instead, there is now a floating P-type blocking region 82 interposed between the diode and the drain region. In accordance with one embodiment, terminal 86 is coupled to terminal 48 so that both are coupled to receive the battery voltage. If the battery is properly connected so that terminal 48 is positive,gate electrode 84 is also positive andchannel 88 is conducting. If the battery connection is reversed, terminal 48 is negative as isgate electrode 84. With negative bias ongate electrode 84,channel 88 is non conductive. Preferably terminal 90 is grounded. - In accordance with a further embodiment of the invention, terminal86 is coupled to a logic circuit (not illustrated) that controls the bias on
gate electrode 84. The logic circuit can apply any appropriate bias to the gate electrode. For example, the logic circuit can apply the same bias as is applied to the drain or, in some applications can apply a bias such as the drain voltage plus an additional positive voltage. The additional voltage may be necessary when, for example,device 80 is used in an application for which the source of the device can swing to positive voltages. Further, the logic circuit can control the bias applied toterminal 90 and hence to contactregion 27 and buriedlayer 24. By controlling the bias on buriedlayer 24, the potential ofepitaxial layer 26 and driftregion 92 can be controlled. - With additional P-
type region 82,device 80 illustrated in FIG. 3 can be viewed as including three intrinsic bipolar transistors: a lateral pnp transistor, a vertical pnp transistor, and an npn transistor. FIG. 4 schematically illustrates the connection of the three intrinsic bipolar transistors as part of the dual gated LDMOS transistor.Lateral pnp transistor 100 includes a P-type emitter region formed bybody 28, an N-type base region formed byepitaxial layer 26, and a P-type collector region formed by P-type blocking region 82.Vertical pup transistor 102 includes a P-type emitter formed by P-type substrate 22, an N-type base formed byepitaxial layer 26, and a P-type collector formed by P-type blocking region 82. Annpn transistor 104 includes an N-type emitter formed bydrain region 32, a P-type base region formed by P-type blocking region 82, and an N-type collector formed byepitaxial layer 26. - The three transistors form two thyristors. A lateral thyristor is formed by
lateral pup transistor 100 in combination withnpn transistor 104. A vertical thyristor is formed byvertical pup transistor 102 in combination withnpn transistor 104. For optimum performance ofdevice 80, the intrinsic transistors and hence the intrinsic thyristors are preferably designed and implemented to avoid latching of either of the thyristors. A thyristor will not latch if the product of the current gains of the two respective transistors (βn for the npn transistor and βp for the pup transistor) is less than one. For the vertical thyristor, βn will in most cases be less than about 100 if the same dopant distribution is used for P-type blocking region 82 as is used forbody region 28. The current gain for the vertical pnp transistor, βp, is very low, usually less than about 0.005, because of the presence of the heavily doped buriedlayer 24. This follows from the fact that the current 5 gain of a transistor is inversely proportional to the integrated base doping under the emitter, and in the case ofpnp transistor 102, the base doping includes the doping in buriedlayer 24. The product βnβp for the two transistors that form the vertical thyristor therefore is less than one. If a reverse battery voltage is applied todevice 80 so that terminal 48 is attached to the negative battery terminal, the vertical thyristor would be biased to turn on. The low value of the product βnβp, however, prevents the vertical thyristor from latching. - Because of the processing used to fabricate
device 80, it is likely that the product of the current gains oflateral pnp transistor 100 andnpn transistor 104 will exceed one, the condition necessary for the lateral thyristor to latch. The lateral thyristor cannot latch, however, when used in a half bridge configuration, for reasons illustrated in FIG. 5. FIG. 5 illustrates schematically anintegrated half bridge 150, in which adevice 80, in accordance with the invention, is used as a high side switch.Source region 30 ofLDMOS transistor 80 is coupled to drain 132 ofMOS transistor 162.Source 130 oftransistor 162 is coupled to ground. The output of the half bridge is taken atterminal 66 coupled tosource 30 oftransistor 80 and to drain 132 oftransistor 162. Theintrinsic transistors intrinsic diode 50 associated with transistor 62 are also illustrated. Consider the situation in whichterminal 48 is inadvertently coupled to a negative voltage. The lateral thyristor that includesnpn transistor 104 andlateral pnp transistor 100 can turn on only iflateral pnp transistor 100 itself turns on. In order for the lateral pnp transistor to turn on, however, the emitter-base junction of the pnp transistor must be forward biased. That is, a voltage of Vbe (the voltage drop across a forward biased pn junction diode) must be applied across the emitter-base junction. Such a voltage drop cannot occur across the emitter-base junction oflateral pnp transistor 100 because the emitter oftransistor 100 is at one Vbe above ground because of 30 the forward bias acrossbody diode 50. At the same time, the base ofpnp transistor 100 is also one Vbe above ground because the emitter oflateral pnp transistor 102 is coupled to ground. The base of transistor 102 (which is also the base of transistor 100) cannot be more than one Vbe more positive than its emitter. Therefore, whentransistor structure 80 is used as the high side switch in an integrated half bridge, the lateral thyristor cannot turn on. - If
device 80, in accordance with an embodiment of the invention, is used in a stand-alone application and not in, for example, a half bridge application, the lateral thyristor can be controlled and kept from latching by groundingterminal 90. Grounding terminal 90 grounds the base oflateral pnp transistor 100 and prevents the base-emitter junction of that device from being forward biased. - Again, referring to FIG. 3, the amount of reversed voltage that can be successfully sustained by
device structure 80 is determined, at least in part, by the spacing betweenbody region 28 and blockingregion 82. If a negative voltage is applied toterminal 48, the pn junction formed between blockingregion 82 and epitaxial layer 26 (or drift region 92) is reversed biased. As the depletion spread from the reverse biased junction spreads across the drift region at the surface ofepitaxial layer 26, the spread eventually, upon the application of sufficient reverse bias voltage, reachesbody region 28 and punch through breakdown occurs. The spacing betweenregions type blocking region 82 andepitaxial layer 26. - A semiconductor device, in accordance with an embodiment of the invention, such as
device 80 illustrated in FIG. 3 can be fabricated using conventional integrated circuit fabrication techniques.Device 80 can be fabricated, for example, as part of an integrated circuit structure on a P-type semiconductor substrate having a resistivity of about 6 Ohm centimeter. A buried layer can be formed by selectively diffusing arsenic into portions of the upper surface of the silicon substrate. In addition to being used to controllably lower the current gain of the intrinsic vertical pnp transistor, the buried layer may be used in other portions of the circuit, for example, to reduce the collector resistance of an npn transistor if the integrated circuit being fabricated utilizes both bipolar and field effect transistors. The buried layer can have, for example, a sheet resistivity of about 18 Ohms per square. Following the formation of the buried layer, an N-type epitaxial layer having a resistivity of about 1 Ohm centimeter can be deposited to a thickness of about 10 micrometers. Insulating layers for device isolation and for gate electrodes can be formed on the surface of the epitaxial layer. The gate insulator can be formed, for example, by thermal oxidation to form a silicon dioxide layer having a thickness of 35 nanometers. Gate electrodes can be formed overlying the gate insulator by the deposition and patterning of a layer of polycrystalline silicon. The polycrystalline silicon can be deposited to a thickness of about 400 nanometers. The patterned polycrystalline silicon is then preferably used as an ion implantation mask for the P-type ion implantion doping of the body region and the floating blocking region. The body region and blocking region are preferable doped with boron to a dose that yields, after a subsequent thermal redistribution step, regions having a junction depth of about 2 micrometers and a sheet resistivity of about 600 Ohms per square. By providing a spacing between the two P-type regions of about 1.8 micrometers, a punch through voltage of about 13.5 volts can be assured. This is sufficient to provide protection against the application of a reversed voltage of about 12 volts. The patterned polycrystalline silicon is then used as an ion implantation mask for the N-type ion implantion doping of the source and drain regions. The source and drain regions are preferably doped with arsenic and have a depth of about 0.4 micrometers and a sheet resistivity of about 50 Ohms per square. Using the same patterned polycrystalline silicon to mask both ion implantations provides self alignment between the source and body and between the drain and floating blocking region. Using the polycrystalline gate regions as an ion implantation mask also provides self alignment between the gate electrode and the underlying channel. Contact to and interconnection of the various device regions can then be accomplished in conventional manner. - Thus it is apparent that there has been provided, in accordance with the invention, a semiconductor device and method for protecting such device from a reversed drain voltage. Although the invention has been described and illustrated with reference to preferred embodiments, it is not intended that the invention be limited to these illustrative embodiments. For example, the invention can be applied to other integrated circuit applications. Likewise, other processing techniques, device sizes, doping types, junction depths and resistivities, dielectric types and isolation techniques can be used to fabricate the inventive devices. Accordingly, it is intended to include within the invention all such modifications and variations as fall within the scope of the appended claims.
Claims (16)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/510,814 US6413806B1 (en) | 2000-02-23 | 2000-02-23 | Semiconductor device and method for protecting such device from a reversed drain voltage |
US10/126,562 US6667500B2 (en) | 2000-02-23 | 2002-04-19 | Semiconductor device and method for protecting such device from a reversed drain voltage |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/510,814 US6413806B1 (en) | 2000-02-23 | 2000-02-23 | Semiconductor device and method for protecting such device from a reversed drain voltage |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/126,562 Division US6667500B2 (en) | 2000-02-23 | 2002-04-19 | Semiconductor device and method for protecting such device from a reversed drain voltage |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020045301A1 true US20020045301A1 (en) | 2002-04-18 |
US6413806B1 US6413806B1 (en) | 2002-07-02 |
Family
ID=24032311
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/510,814 Expired - Lifetime US6413806B1 (en) | 2000-02-23 | 2000-02-23 | Semiconductor device and method for protecting such device from a reversed drain voltage |
US10/126,562 Expired - Lifetime US6667500B2 (en) | 2000-02-23 | 2002-04-19 | Semiconductor device and method for protecting such device from a reversed drain voltage |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/126,562 Expired - Lifetime US6667500B2 (en) | 2000-02-23 | 2002-04-19 | Semiconductor device and method for protecting such device from a reversed drain voltage |
Country Status (1)
Country | Link |
---|---|
US (2) | US6413806B1 (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6486034B1 (en) * | 2001-07-20 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method of forming LDMOS device with double N-layering |
US20060194392A1 (en) * | 2003-03-10 | 2006-08-31 | Fuji Electric Device Technology Co., Ltd. | Mis-type semiconductor device |
US20070246738A1 (en) * | 2006-04-24 | 2007-10-25 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20100207197A1 (en) * | 2009-02-18 | 2010-08-19 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
WO2011123332A2 (en) * | 2010-03-31 | 2011-10-06 | Volterra Semiconductor Corporation | Dual gate ldmos device with reduced capacitance |
US20110241083A1 (en) * | 2010-03-30 | 2011-10-06 | Freescale Semiconductor, Inc. | Semiconductor device and method |
US20110241112A1 (en) * | 2010-03-31 | 2011-10-06 | Zuniga Marco A | LDMOS Device with P-Body for Reduced Capacitance |
US20150371705A1 (en) * | 2013-01-30 | 2015-12-24 | Commissariat a l'énergie atomique et aux énergies alternatives | Method for programming a bipolar resistive switching memory device |
WO2016049590A1 (en) * | 2014-09-25 | 2016-03-31 | Kilopass Technology, Inc. | Cross-coupled thyristor sram semiconductor structures and methods of fabrication |
US9564199B2 (en) | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Methods of reading and writing data in a thyristor random access memory |
US9564441B2 (en) | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Two-transistor SRAM semiconductor structure and methods of fabrication |
US9613968B2 (en) | 2014-09-25 | 2017-04-04 | Kilopass Technology, Inc. | Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication |
US9741413B2 (en) | 2014-09-25 | 2017-08-22 | Kilopass Technology, Inc. | Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells |
EP3101686A4 (en) * | 2014-01-31 | 2017-11-29 | Alps Electric Co., Ltd. | Semiconductor integrated circuit device |
US9837418B2 (en) | 2014-09-25 | 2017-12-05 | Kilopass Technology, Inc. | Thyristor volatile random access memory and methods of manufacture |
CN108364945A (en) * | 2018-01-19 | 2018-08-03 | 湖南师范大学 | A kind of double grid grid-control Electro-static Driven Comb device and preparation method thereof improving maintenance voltage |
US10090037B2 (en) | 2014-09-25 | 2018-10-02 | Tc Lab, Inc. | Methods of retaining and refreshing data in a thyristor random access memory |
US10283185B2 (en) | 2014-09-25 | 2019-05-07 | Tc Lab, Inc. | Write assist thyristor-based SRAM circuits and methods of operation |
US20200006490A1 (en) * | 2018-06-28 | 2020-01-02 | Richtek Technology Corporation | High voltage device and manufacturing method thereof |
CN112271217A (en) * | 2020-11-02 | 2021-01-26 | 中国工程物理研究院电子工程研究所 | Impact-resistant field effect transistor and impact-resistant low-noise amplifier |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6413806B1 (en) * | 2000-02-23 | 2002-07-02 | Motorola, Inc. | Semiconductor device and method for protecting such device from a reversed drain voltage |
TW490907B (en) * | 2000-11-14 | 2002-06-11 | Silicon Touch Tech Inc | Circuit with protection for inverted connection of power source polarity |
US6573562B2 (en) * | 2001-10-31 | 2003-06-03 | Motorola, Inc. | Semiconductor component and method of operation |
US8212317B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8212315B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253196B2 (en) | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253195B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253197B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US7230302B2 (en) * | 2004-01-29 | 2007-06-12 | Enpirion, Inc. | Laterally diffused metal oxide semiconductor device and method of forming the same |
US8212316B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US7232733B2 (en) * | 2004-08-23 | 2007-06-19 | Enpirion, Inc. | Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein |
US7335948B2 (en) * | 2004-08-23 | 2008-02-26 | Enpirion, Inc. | Integrated circuit incorporating higher voltage devices and low voltage devices therein |
US7195981B2 (en) * | 2004-08-23 | 2007-03-27 | Enpirion, Inc. | Method of forming an integrated circuit employable with a power converter |
US7186606B2 (en) * | 2004-08-23 | 2007-03-06 | Enpirion, Inc. | Method of forming an integrated circuit employable with a power converter |
US7229886B2 (en) * | 2004-08-23 | 2007-06-12 | Enpirion, Inc. | Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein |
US7214985B2 (en) * | 2004-08-23 | 2007-05-08 | Enpirion, Inc. | Integrated circuit incorporating higher voltage devices and low voltage devices therein |
US7190026B2 (en) * | 2004-08-23 | 2007-03-13 | Enpirion, Inc. | Integrated circuit employable with a power converter |
US7405443B1 (en) * | 2005-01-07 | 2008-07-29 | Volterra Semiconductor Corporation | Dual gate lateral double-diffused MOSFET (LDMOS) transistor |
US7217628B2 (en) * | 2005-01-17 | 2007-05-15 | International Business Machines Corporation | High performance integrated vertical transistors and method of making the same |
US8319283B2 (en) * | 2009-05-29 | 2012-11-27 | Freescale Semiconductor, Inc. | Laterally diffused metal oxide semiconductor (LDMOS) device with multiple gates and doped regions |
US20140159130A1 (en) | 2012-11-30 | 2014-06-12 | Enpirion, Inc. | Apparatus including a semiconductor device coupled to a decoupling device |
US9536938B1 (en) | 2013-11-27 | 2017-01-03 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US10020739B2 (en) | 2014-03-27 | 2018-07-10 | Altera Corporation | Integrated current replicator and method of operating the same |
US9673192B1 (en) | 2013-11-27 | 2017-06-06 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US10103627B2 (en) | 2015-02-26 | 2018-10-16 | Altera Corporation | Packaged integrated circuit including a switch-mode regulator and method of forming the same |
US9799763B2 (en) * | 2015-08-31 | 2017-10-24 | Intersil Americas LLC | Method and structure for reducing switching power losses |
CN109545782A (en) * | 2018-11-29 | 2019-03-29 | 上海华力集成电路制造有限公司 | A kind of electrostatic discharge protective circuit and semiconductor structure |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3609479A (en) * | 1968-02-29 | 1971-09-28 | Westinghouse Electric Corp | Semiconductor integrated circuit having mis and bipolar transistor elements |
GB2150753B (en) * | 1983-11-30 | 1987-04-01 | Toshiba Kk | Semiconductor device |
US5212396A (en) * | 1983-11-30 | 1993-05-18 | Kabushiki Kaisha Toshiba | Conductivity modulated field effect transistor with optimized anode emitter and anode base impurity concentrations |
US4963951A (en) * | 1985-11-29 | 1990-10-16 | General Electric Company | Lateral insulated gate bipolar transistors with improved latch-up immunity |
US4821095A (en) * | 1987-03-12 | 1989-04-11 | General Electric Company | Insulated gate semiconductor device with extra short grid and method of fabrication |
US5204541A (en) * | 1991-06-28 | 1993-04-20 | Texas Instruments Incorporated | Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices |
US5721445A (en) * | 1995-03-02 | 1998-02-24 | Lucent Technologies Inc. | Semiconductor device with increased parasitic emitter resistance and improved latch-up immunity |
US6413806B1 (en) * | 2000-02-23 | 2002-07-02 | Motorola, Inc. | Semiconductor device and method for protecting such device from a reversed drain voltage |
-
2000
- 2000-02-23 US US09/510,814 patent/US6413806B1/en not_active Expired - Lifetime
-
2002
- 2002-04-19 US US10/126,562 patent/US6667500B2/en not_active Expired - Lifetime
Cited By (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6486034B1 (en) * | 2001-07-20 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method of forming LDMOS device with double N-layering |
US6580131B2 (en) * | 2001-07-20 | 2003-06-17 | Taiwan Semiconductor Manufacturing Company | LDMOS device with double N-layering and process for its manufacture |
US20060194392A1 (en) * | 2003-03-10 | 2006-08-31 | Fuji Electric Device Technology Co., Ltd. | Mis-type semiconductor device |
US7692239B2 (en) * | 2003-03-10 | 2010-04-06 | Fuji Electric Device Technology Co., Ltd. | MIS-type semiconductor device |
US20070246738A1 (en) * | 2006-04-24 | 2007-10-25 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US7906811B2 (en) * | 2006-04-24 | 2011-03-15 | Sanyo Electric Co., Ltd. (Osaka) | Semiconductor device with protection element disposed around a formation region of a transistor |
US20100207197A1 (en) * | 2009-02-18 | 2010-08-19 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US8314458B2 (en) * | 2009-02-18 | 2012-11-20 | Sanyo Semiconductor Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20110241083A1 (en) * | 2010-03-30 | 2011-10-06 | Freescale Semiconductor, Inc. | Semiconductor device and method |
US8344472B2 (en) * | 2010-03-30 | 2013-01-01 | Freescale Semiconductor, Inc. | Semiconductor device and method |
US20110241112A1 (en) * | 2010-03-31 | 2011-10-06 | Zuniga Marco A | LDMOS Device with P-Body for Reduced Capacitance |
WO2011123332A3 (en) * | 2010-03-31 | 2012-02-02 | Volterra Semiconductor Corporation | Dual gate ldmos device with reduced capacitance |
WO2011123332A2 (en) * | 2010-03-31 | 2011-10-06 | Volterra Semiconductor Corporation | Dual gate ldmos device with reduced capacitance |
US20150371705A1 (en) * | 2013-01-30 | 2015-12-24 | Commissariat a l'énergie atomique et aux énergies alternatives | Method for programming a bipolar resistive switching memory device |
US10566055B2 (en) * | 2013-01-30 | 2020-02-18 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for programming a bipolar resistive switching memory device |
EP3101686A4 (en) * | 2014-01-31 | 2017-11-29 | Alps Electric Co., Ltd. | Semiconductor integrated circuit device |
US9748223B2 (en) | 2014-09-25 | 2017-08-29 | Kilopass Technology, Inc. | Six-transistor SRAM semiconductor structures and methods of fabrication |
US10090037B2 (en) | 2014-09-25 | 2018-10-02 | Tc Lab, Inc. | Methods of retaining and refreshing data in a thyristor random access memory |
US9613968B2 (en) | 2014-09-25 | 2017-04-04 | Kilopass Technology, Inc. | Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication |
US9741413B2 (en) | 2014-09-25 | 2017-08-22 | Kilopass Technology, Inc. | Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells |
US9564441B2 (en) | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Two-transistor SRAM semiconductor structure and methods of fabrication |
US9564199B2 (en) | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Methods of reading and writing data in a thyristor random access memory |
US9837418B2 (en) | 2014-09-25 | 2017-12-05 | Kilopass Technology, Inc. | Thyristor volatile random access memory and methods of manufacture |
US9899389B2 (en) | 2014-09-25 | 2018-02-20 | Kilopass Technology, Inc. | Two-transistor SRAM semiconductor structure and methods of fabrication |
US10020043B2 (en) | 2014-09-25 | 2018-07-10 | Tc Lab, Inc. | Methods of reading and writing data in a thyristor random access memory |
US11114438B2 (en) | 2014-09-25 | 2021-09-07 | Tc Lab, Inc. | Thyristor volatile random access memory and methods of manufacture |
US10056389B2 (en) | 2014-09-25 | 2018-08-21 | Kilopass Technology, Inc. | Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication |
US9564198B2 (en) | 2014-09-25 | 2017-02-07 | Kilopass Technology, Inc. | Six-transistor SRAM semiconductor structures and methods of fabrication |
US10283185B2 (en) | 2014-09-25 | 2019-05-07 | Tc Lab, Inc. | Write assist thyristor-based SRAM circuits and methods of operation |
US10332886B2 (en) | 2014-09-25 | 2019-06-25 | Tc Lab, Inc. | Thyristor volatile random access memory and methods of manufacture |
US10381063B2 (en) | 2014-09-25 | 2019-08-13 | Tc Lab, Inc. | Methods of reading and writing data in a thyristor random access memory |
US10438952B2 (en) | 2014-09-25 | 2019-10-08 | Tc Lab, Inc. | Method of writing into and refreshing a thyristor volatile random access memory |
US10460789B2 (en) | 2014-09-25 | 2019-10-29 | Tc Lab, Inc. | Methods of reading and writing data in a thyristor random access memory |
WO2016049590A1 (en) * | 2014-09-25 | 2016-03-31 | Kilopass Technology, Inc. | Cross-coupled thyristor sram semiconductor structures and methods of fabrication |
US10529718B2 (en) | 2014-09-25 | 2020-01-07 | Tc Lab, Inc. | Thyristor volatile random access memory and methods of manufacture |
US10553588B2 (en) | 2014-09-25 | 2020-02-04 | Tc Lab, Inc. | Thyristor volatile random access memory and methods of manufacture |
CN108364945A (en) * | 2018-01-19 | 2018-08-03 | 湖南师范大学 | A kind of double grid grid-control Electro-static Driven Comb device and preparation method thereof improving maintenance voltage |
US20200006490A1 (en) * | 2018-06-28 | 2020-01-02 | Richtek Technology Corporation | High voltage device and manufacturing method thereof |
US10943978B2 (en) * | 2018-06-28 | 2021-03-09 | Richtek Technology Corporation | High voltage device and manufacturing method thereof |
CN112271217A (en) * | 2020-11-02 | 2021-01-26 | 中国工程物理研究院电子工程研究所 | Impact-resistant field effect transistor and impact-resistant low-noise amplifier |
Also Published As
Publication number | Publication date |
---|---|
US20030008443A1 (en) | 2003-01-09 |
US6667500B2 (en) | 2003-12-23 |
US6413806B1 (en) | 2002-07-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6413806B1 (en) | Semiconductor device and method for protecting such device from a reversed drain voltage | |
US4987465A (en) | Electro-static discharge protection device for CMOS integrated circuit inputs | |
US6960807B2 (en) | Drain extend MOS transistor with improved breakdown robustness | |
KR930010827B1 (en) | Semiconductor device | |
EP0750793B1 (en) | Silicon controlled rectifier for esd protection | |
US8823051B2 (en) | High-voltage diodes formed in advanced power integrated circuit devices | |
JP4623775B2 (en) | VDMOS transistor | |
US20080023767A1 (en) | High voltage electrostatic discharge protection devices and electrostatic discharge protection circuits | |
KR20060006036A (en) | Low voltage silicon controlled rectifier (scr) for electrostatic discharge (esd) protection on silicon-on-insulator technologies | |
JPH05183114A (en) | Semiconductor device | |
US8107203B2 (en) | Electrostatic discharge protection device | |
US4562454A (en) | Electronic fuse for semiconductor devices | |
US20210167206A1 (en) | Electrostatic discharge guard ring with complementary drain extended devices | |
EP0103306B1 (en) | Semiconductor protective device | |
US6784029B1 (en) | Bi-directional ESD protection structure for BiCMOS technology | |
US6847059B2 (en) | Semiconductor input protection circuit | |
US5903034A (en) | Semiconductor circuit device having an insulated gate type transistor | |
KR20040023477A (en) | Electrostatic discharge protection silicon controlled rectifier(esd-scr) for silicon germanium technologies | |
US4622573A (en) | CMOS contacting structure having degeneratively doped regions for the prevention of latch-up | |
US6717219B1 (en) | High holding voltage ESD protection structure for BiCMOS technology | |
JP2680788B2 (en) | Integrated structure active clamp device | |
US5789785A (en) | Device for the protection of an integrated circuit against electrostatic discharges | |
US8188568B2 (en) | Semiconductor integrated circuit | |
US5587595A (en) | Lateral field-effect-controlled semiconductor device on insulating substrate | |
US5148250A (en) | Bipolar transistor as protective element for integrated circuits |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MOTOROLA, INC., ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SICARD, THIERRY;MACARY, VERONIQUE C.;REEL/FRAME:010644/0456 Effective date: 20000222 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424 Effective date: 20130521 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266 Effective date: 20131101 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:040652/0241 Effective date: 20161107 Owner name: NXP USA, INC., TEXAS Free format text: MERGER;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:040652/0241 Effective date: 20161107 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:041260/0850 Effective date: 20161107 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536 Effective date: 20151207 |
|
AS | Assignment |
Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001 Effective date: 20190217 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:053547/0421 Effective date: 20151207 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |