US20020030527A1 - Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic - Google Patents

Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic Download PDF

Info

Publication number
US20020030527A1
US20020030527A1 US09/739,704 US73970400A US2002030527A1 US 20020030527 A1 US20020030527 A1 US 20020030527A1 US 73970400 A US73970400 A US 73970400A US 2002030527 A1 US2002030527 A1 US 2002030527A1
Authority
US
United States
Prior art keywords
type mos
mos transistor
voltage
zero cut
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/739,704
Other versions
US6404268B1 (en
Inventor
Hsi-Hsien Hung
Hsin Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sunplus Technology Co Ltd
Original Assignee
Sunplus Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sunplus Technology Co Ltd filed Critical Sunplus Technology Co Ltd
Assigned to SUNPLUS TECHNOLOGY CO., LTD. reassignment SUNPLUS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUNG, HSI-HSIEN, LEE, HSIN CHOU
Publication of US20020030527A1 publication Critical patent/US20020030527A1/en
Application granted granted Critical
Publication of US6404268B1 publication Critical patent/US6404268B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a diode circuit and rectifier and, more particularly, to a MOS transistor circuit manufactured by the CMOS process for simulating zero cut-in voltage diode and a zero cut-in voltage rectifier including the diode.
  • the conventional AC to DC full wave rectifier is generally formed by diodes. Since the diode has a cut-in voltage of 0.6V, the rectifier will have a power loss in voltage conversion. Particularly, when the input voltage is small, the negative influence caused by such a power loss becomes obvious and unacceptable.
  • the power of IC is supplied from a small AC power generated by the induction of a coil, and thus, the efficiency of rectifying will directly affect the use range of this IC. As a result, the operating efficiency of such an IC is determined by the performance of the rectifier.
  • FIG. 6 a popular circuit, known as a full wave bridge rectifier, is illustrated in FIG. 6, which has four diodes 902 to 905 connected in a bridge structure.
  • the diodes 902 and 905 are turned on if the applied waveform ACIN 1 >ACIN 2 .
  • the AC signal charges the capacitor 906 through the diodes 902 and 905 .
  • the diodes 903 and 904 are turned on, and the AC signal charges the capacitor 906 through the diodes 903 and 904 .
  • the AC power can be rectified to produce a DC power.
  • FIG. 7 is the rectifying waveform of a bridge rectifier, which shows that, due to the influence of the cut-in voltage of the diode, the rectified DC voltage VDD only has a maximum value of Vac ⁇ 2*Vd, where Vac is the voltage peak value of the AC power source 901 and Vd is the cut-in voltage of the diode. Therefore, the rectifying performance of the rectifier is greatly degraded.
  • FIG. 8 shows another conventional rectifier circuit, which uses metal oxide semiconductor (MOS) transistors 914 and 915 with N-type substrate to control the diodes for performing the rectifying operation of AC to DC conversion.
  • MOS metal oxide semiconductor
  • FIG. 9 is a rectifying waveform of the rectifier circuit shown in FIG. 8.
  • this improved rectifier circuit is able to reduce a voltage drop equal to one cut-in voltage of a diode. That is, the maximum value of the DC voltage VDD is only improved to be Vac ⁇ Vd. Under a condition of no current load, there is still a voltage loss of 0.6V. Thus, the influence of the cut-in voltage can not be completely removed.
  • U.S. Pat. No. 5,825,214 granted to Klosa discloses an “Integrated circuit arrangement with diode characteristic” for replacing the conventional diodes to realize a rectifier with zero cut-in voltage.
  • the schematic view of the circuit is illustrated in FIG. 10, which comprises three inverters 921 , 922 , and 923 and a P-type MOS transistor 924 for being used as a switch.
  • the input end and output end of the inverter 921 are connected together, and thus the output voltage level is automatically set at the trigger point of the inverter. This voltage will change positively with the level of the supplying power.
  • the voltage level set by the inverter 921 is directly applied to the input end of the inverter 922 which receives power from an AC input ACIN.
  • the two inverters 921 and 922 have the same size and characteristic. Therefore, when the ACIN is smaller than the VDD, the input of the inverter 922 is considered to be a high voltage level. Through the inverter 923 , the P-type MOS transistor 924 is turned off so as to avoid a leakage current. On the other hand, when the ACIN is larger than the VDD, the input of the inverter 922 is considered to be a low voltage level, the P-type MOS transistor 924 is turned on through the inverter 923 , so as to charge VDD.
  • the P-type MOS transistor 924 can be turned on completely to provide the advantage of zero cut-in voltage.
  • the inverters 921 and 922 are operating at a high speed, it is inevitable that a high current loss problem will be encountered. Therefore, the overall efficiency of the rectifier is unsatisfactory due to such a current loss. Consequently, it is desirable to provide an improved circuit to mitigate and/or obviate the aforementioned problems.
  • the object of the present invention is to provide a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic, so as to improve the efficiency of rectifying, reduce the current loss, and avoid the output voltage drop caused by the cut-in voltage of diode.
  • a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output comprising: a constant bias circuit having a resistor and a N-type MOS transistor, the N-type MOS transistor having a drain connected to the resistor and a gate connected to the drain; a first N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first P-type MOS transistor and a second P-type MOS transistor connected in a cross couple structure which are coupled to the first and second N-type MOS transistors, whereby a high voltage level of the AC voltage input is applied to a high voltage level of the DC voltage output, and a low voltage level of
  • a circuit for simulating zero cut-in voltage diode comprising: a first N-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first N-type MOS transistor for forming a bias circuit; and a second N-type MOS transistor with the same characteristic as the first N-type MOS transistor, having a gate connected to the gate of the first N-type MOS transistor; wherein the first N-type MOS transistor is controlled by the resistor to be biased almost to a threshold voltage.
  • a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output comprising: a constant bias circuit having a resistor and a P-type MOS transistor, the P-type MOS transistor having a drain connected to the resistor, and a gate connected to the drain; a first P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first N-type MOS transistor and a second N-type MOS transistor connected in a cross couple structure which are coupled to the first and second P-type MOS transistors, whereby a low voltage level of the AC voltage input is applied to a low voltage level of the DC voltage output, and a high voltage level
  • a circuit for simulating zero cut-in voltage diode comprising: a first P-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first P-type MOS transistor, so as to form a bias circuit; and a second P-type MOS transistor with the same characteristic as the first P-type MOS transistor, having a gate connected to the gate of the first P-type MOS transistor; wherein the first P-type MOS transistor is controlled by the resistor to be based to VDD ⁇ Vtp, where VDD represents a high voltage level of a DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.
  • FIG. 1 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the first embodiment of the present invention
  • FIG. 3 shows the characteristic curve of the circuit for simulating zero cut-in voltage diode in accordance with the present invention
  • FIG. 4 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a second embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the second embodiment of the present invention.
  • FIG. 6 is the schematic diagram of a conventional full wave rectifier
  • FIG. 7 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 6;
  • FIG. 8 is a schematic diagram of another conventional full wave rectifier
  • FIG. 9 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 8.
  • FIG. 10 is a schematic diagram of a conventional zero cut-in voltage diode.
  • FIG. 1 there is shown a rectifier formed by the circuit for simulating zero cut-in voltage diode in accordance with a preferred embodiment of the present invention.
  • ACIN 1 and ACIN 2 represent the inputs of an AC voltage source
  • VDD and VSS represent the high voltage level and low voltage level of a DC voltage output.
  • the transistors 101 and 102 are P-type MOS transistors connected in a cross couple structure. That is, the gate and drain of transistor 101 are connected to the drain and gate of the transistor 102 , respectively, such that one of the AC voltage source inputs ACIN 1 and ACIN 2 with a higher voltage level is applied to VDD.
  • the N-type MOS transistor 106 is connected to a resistor 105 for forming a constant bias circuit.
  • the N-type MOS transistor 103 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with a low current loss.
  • the N-type MOS transistor 104 is connected to the bias circuit so as to form another circuit for simulating zero cut-in voltage diode with a lower current loss.
  • FIG. 2 For the purpose of convenient description, a single circuit for simulating zero cut-in voltage diode is illustrated in FIG. 2.
  • the gate and drain of the N-type MOS transistor 106 are connected together.
  • One end of the resistor 105 is connected to the VDD, and the other end thereof is connected the drain of the N-type MOS transistor 106 so as to form a bias circuit.
  • the gate of the N-type MOS transistor 106 is connected to the gate of the N-type MOS transistor 103 or 104 .
  • the sources of the transistor 106 and the transistor 103 or 104 are all connected to VSS.
  • the transistor 103 or 104 and the transistor 106 have the same characteristic.
  • the current flowing through the transistor 106 can be controlled.
  • the transistor 106 is biased almost to its threshold voltage. Since the gates of the transistor 103 or 104 and the transistor 106 are connected together, and the transistor 103 or 104 and the transistor 106 have the same characteristic, the transistor 103 or 104 is also biased to the threshold voltage.
  • the AC power can be converted into DC power.
  • the rectifier is formed by diode circuit with zero cut-in voltage, thereby having the zero cut-in voltage characteristic.
  • the circuit is primarily formed by MOS transistors, the current loss is small (only several microamperes) no matter the rectifier is operating at high speed or low speed. Accordingly, it is able to implement a high efficient rectifier having a low current loss.
  • FIG. 4 shows a rectifier having zero cut-in voltage characteristic in accordance with another preferred embodiment of the present invention.
  • the transistors 303 and 304 are N-type MOS transistors which are connected in a cross couple structure. That is, the gate and drain of the transistor 303 are connected to the drain and gate of the transistor 304 , respectively, such that one of the AC voltage source inputs ACIN 1 and ACIN 2 with a lower voltage level is applied to VSS.
  • the P-type MOS transistor 305 is connected to a resistor 306 for forming a constant bias circuit.
  • the P-type MOS transistor 301 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss.
  • the P-type MOS transistor 302 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss.
  • the circuit for simulating zero cut-in voltage diode as described above is individually illustrated in FIG. 5. As shown, the gate and drain of the P-type MOS transistor 305 are connected together. One end of the resistor 306 is connected to VSS, and the other end thereof is connected to the drain of the P-type MOS transistor 305 so as to form a bias circuit. The gate of the P-type MOS transistor 305 is connected to the gate of the P-type MOS transistor 301 or 302 . The sources of the transistor 305 and the transistor 301 or 302 are all connected to VDD. The transistor 301 or 302 and the transistor 305 have the same characteristic.
  • the transistor 305 can be biased to VDD ⁇ Vtp (Vtp is the threshold voltage of the P-type MOS transistor). Accordingly, when ACIN>VDD, the circuit is deemed as a “diode” operating in a forward bias region. When ACIN ⁇ VDD, the leakage current is only several microamperes and the circuit is deemed as a “diode” operating in a reverse bias region. The operation of this embodiment is similar to the previous one, and thus a detailed description is deemed unnecessary.
  • the cross-coupled N-type MOS transistors 303 and 304 are coupled to the P-type MOS transistors 301 and 302 of the circuit for simulating zero cut-in voltage diode.
  • the operation of the rectifier is as follows:
  • the AC power can be converted into DC power, and the rectifier can be provided with zero cut-in voltage characteristic, so as to implement a high efficient rectifier having a low current loss.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

There is disclosed a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic. The MOS transistors manufactured by the CMOS process are used as circuit components and are properly biased so as to provide the rectifying capability, and thus are used as a rectifying diode. Furthermore, with a proper bias, the rectifying diode has zero cut-in voltage and a low current loss, and thus a high efficient rectifier can be implement.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a diode circuit and rectifier and, more particularly, to a MOS transistor circuit manufactured by the CMOS process for simulating zero cut-in voltage diode and a zero cut-in voltage rectifier including the diode. [0002]
  • 2. Description of Related Art [0003]
  • The conventional AC to DC full wave rectifier is generally formed by diodes. Since the diode has a cut-in voltage of 0.6V, the rectifier will have a power loss in voltage conversion. Particularly, when the input voltage is small, the negative influence caused by such a power loss becomes obvious and unacceptable. [0004]
  • In the field of contactless IC and the like, the power of IC is supplied from a small AC power generated by the induction of a coil, and thus, the efficiency of rectifying will directly affect the use range of this IC. As a result, the operating efficiency of such an IC is determined by the performance of the rectifier. [0005]
  • In the aforementioned AC to DC full wave rectifier, a popular circuit, known as a full wave bridge rectifier, is illustrated in FIG. 6, which has four [0006] diodes 902 to 905 connected in a bridge structure. With such a circuit, when the AC power source 901 applies AC signal to the full wave rectifier, the diodes 902 and 905 are turned on if the applied waveform ACIN1>ACIN2. The AC signal charges the capacitor 906 through the diodes 902 and 905. On the contrary, if ACIN2>ACIN1, the diodes 903 and 904 are turned on, and the AC signal charges the capacitor 906 through the diodes 903 and 904. As such, the AC power can be rectified to produce a DC power.
  • FIG. 7 is the rectifying waveform of a bridge rectifier, which shows that, due to the influence of the cut-in voltage of the diode, the rectified DC voltage VDD only has a maximum value of Vac−2*Vd, where Vac is the voltage peak value of the [0007] AC power source 901 and Vd is the cut-in voltage of the diode. Therefore, the rectifying performance of the rectifier is greatly degraded.
  • In order to solve such a problem, FIG. 8 shows another conventional rectifier circuit, which uses metal oxide semiconductor (MOS) [0008] transistors 914 and 915 with N-type substrate to control the diodes for performing the rectifying operation of AC to DC conversion. When ACIN1−ACIN2>Vtn (Vtn is the threshold voltage of N-type MOS transistor), the N-type MOS transistor 915 is turned on, and the ACIN2 is applied to a lowest voltage VSS. When ACIN1−VDD>Vd, the diode 912 is turned on, and the AC power source starts to charge VDD. When ACIN2−ACIN1>Vtn, the N-type MOS transistor 914 is turned on, ACIN1 is applied to a lowest voltage VSS. When ACIN2−VDD>Vd, the diode 913 is turned on, and the AC voltage source starts to charge the VDD.
  • FIG. 9 is a rectifying waveform of the rectifier circuit shown in FIG. 8. In comparison with the waveform shown in FIG. 7, it is known that this improved rectifier circuit is able to reduce a voltage drop equal to one cut-in voltage of a diode. That is, the maximum value of the DC voltage VDD is only improved to be Vac−Vd. Under a condition of no current load, there is still a voltage loss of 0.6V. Thus, the influence of the cut-in voltage can not be completely removed. [0009]
  • In order to entirely remove the cut-in voltage of the diode so that the maximum value of the VDD is Vac, U.S. Pat. No. 5,825,214 granted to Klosa discloses an “Integrated circuit arrangement with diode characteristic” for replacing the conventional diodes to realize a rectifier with zero cut-in voltage. The schematic view of the circuit is illustrated in FIG. 10, which comprises three [0010] inverters 921, 922, and 923 and a P-type MOS transistor 924 for being used as a switch. The input end and output end of the inverter 921 are connected together, and thus the output voltage level is automatically set at the trigger point of the inverter. This voltage will change positively with the level of the supplying power. The voltage level set by the inverter 921 is directly applied to the input end of the inverter 922 which receives power from an AC input ACIN. The two inverters 921 and 922 have the same size and characteristic. Therefore, when the ACIN is smaller than the VDD, the input of the inverter 922 is considered to be a high voltage level. Through the inverter 923, the P-type MOS transistor 924 is turned off so as to avoid a leakage current. On the other hand, when the ACIN is larger than the VDD, the input of the inverter 922 is considered to be a low voltage level, the P-type MOS transistor 924 is turned on through the inverter 923, so as to charge VDD.
  • In the aforementioned circuit, the P-[0011] type MOS transistor 924 can be turned on completely to provide the advantage of zero cut-in voltage. However, if the inverters 921 and 922 are operating at a high speed, it is inevitable that a high current loss problem will be encountered. Therefore, the overall efficiency of the rectifier is unsatisfactory due to such a current loss. Consequently, it is desirable to provide an improved circuit to mitigate and/or obviate the aforementioned problems.
    • SUMMARY OF THE INVENTION
  • Accordingly, the object of the present invention is to provide a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic, so as to improve the efficiency of rectifying, reduce the current loss, and avoid the output voltage drop caused by the cut-in voltage of diode. [0012]
  • In accordance with a first aspect of the present invention, there is provided a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising: a constant bias circuit having a resistor and a N-type MOS transistor, the N-type MOS transistor having a drain connected to the resistor and a gate connected to the drain; a first N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first P-type MOS transistor and a second P-type MOS transistor connected in a cross couple structure which are coupled to the first and second N-type MOS transistors, whereby a high voltage level of the AC voltage input is applied to a high voltage level of the DC voltage output, and a low voltage level of the AC voltage input charges a low voltage level of the DC voltage output through one of the zero cut-in voltage diodes. [0013]
  • In accordance with a second aspect of the present invention, there is provided a circuit for simulating zero cut-in voltage diode comprising: a first N-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first N-type MOS transistor for forming a bias circuit; and a second N-type MOS transistor with the same characteristic as the first N-type MOS transistor, having a gate connected to the gate of the first N-type MOS transistor; wherein the first N-type MOS transistor is controlled by the resistor to be biased almost to a threshold voltage. [0014]
  • In accordance with a third aspect of the present invention, there is provided a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising: a constant bias circuit having a resistor and a P-type MOS transistor, the P-type MOS transistor having a drain connected to the resistor, and a gate connected to the drain; a first P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first N-type MOS transistor and a second N-type MOS transistor connected in a cross couple structure which are coupled to the first and second P-type MOS transistors, whereby a low voltage level of the AC voltage input is applied to a low voltage level of the DC voltage output, and a high voltage level of the AC voltage input charges a high voltage level of the DC voltage output through one of the zero cut-in voltage diodes. [0015]
  • In accordance with a fourth aspect of the present invention, there is provided a circuit for simulating zero cut-in voltage diode comprising: a first P-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first P-type MOS transistor, so as to form a bias circuit; and a second P-type MOS transistor with the same characteristic as the first P-type MOS transistor, having a gate connected to the gate of the first P-type MOS transistor; wherein the first P-type MOS transistor is controlled by the resistor to be based to VDD−Vtp, where VDD represents a high voltage level of a DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.[0016]
  • Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. [0017]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a first embodiment of the present invention; [0018]
  • FIG. 2 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the first embodiment of the present invention; [0019]
  • FIG. 3 shows the characteristic curve of the circuit for simulating zero cut-in voltage diode in accordance with the present invention; [0020]
  • FIG. 4 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a second embodiment of the present invention; [0021]
  • FIG. 5 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the second embodiment of the present invention; [0022]
  • FIG. 6 is the schematic diagram of a conventional full wave rectifier; [0023]
  • FIG. 7 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 6; [0024]
  • FIG. 8 is a schematic diagram of another conventional full wave rectifier; [0025]
  • FIG. 9 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 8; and [0026]
  • FIG. 10 is a schematic diagram of a conventional zero cut-in voltage diode.[0027]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Referring to the drawings and initially to FIG. 1, there is shown a rectifier formed by the circuit for simulating zero cut-in voltage diode in accordance with a preferred embodiment of the present invention. As shown, ACIN[0028] 1 and ACIN2 represent the inputs of an AC voltage source, and VDD and VSS represent the high voltage level and low voltage level of a DC voltage output. The transistors 101 and 102 are P-type MOS transistors connected in a cross couple structure. That is, the gate and drain of transistor 101 are connected to the drain and gate of the transistor 102, respectively, such that one of the AC voltage source inputs ACIN1 and ACIN2 with a higher voltage level is applied to VDD.
  • Furthermore, the N-[0029] type MOS transistor 106 is connected to a resistor 105 for forming a constant bias circuit. The N-type MOS transistor 103 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with a low current loss. Similarly, the N-type MOS transistor 104 is connected to the bias circuit so as to form another circuit for simulating zero cut-in voltage diode with a lower current loss.
  • For the purpose of convenient description, a single circuit for simulating zero cut-in voltage diode is illustrated in FIG. 2. The gate and drain of the N-[0030] type MOS transistor 106 are connected together. One end of the resistor 105 is connected to the VDD, and the other end thereof is connected the drain of the N-type MOS transistor 106 so as to form a bias circuit. Furthermore, the gate of the N-type MOS transistor 106 is connected to the gate of the N- type MOS transistor 103 or 104. The sources of the transistor 106 and the transistor 103 or 104 are all connected to VSS. Moreover, the transistor 103 or 104 and the transistor 106 have the same characteristic. Therefore, by setting the resistance value of the resistor 105, the current flowing through the transistor 106 can be controlled. When the current is of several microamperes (μA), the transistor 106 is biased almost to its threshold voltage. Since the gates of the transistor 103 or 104 and the transistor 106 are connected together, and the transistor 103 or 104 and the transistor 106 have the same characteristic, the transistor 103 or 104 is also biased to the threshold voltage.
  • After being biased, the operation of the circuit for simulating zero cut-in voltage diode is analyzed as follows: [0031]
  • 1. When ACIN[0032] 1>VSS, the transistor 103 or 104 is operating in a saturation region. The current flowing from ACIN to VSS is the aspect ratio of the transistor 103 or 104 to the transistor 106 multiplied by the bias current. This current is defined as the leakage current. The value of this current is designed to be several microamperes. As such, this operation region is deemed as a “diode” operating in a reverse bias region.
  • 2. When ACIN<VSS, the source of the [0033] transistor 103 or 104 is changed from VSS to ACIN. The relation between the current and ACIN is: ld=K*(VACIN)2, where K is a constant. This operation region is deemed as the “diode” operating in a forward bias region, and its characteristic curve is shown in FIG. 3.
  • Referring to FIG. 1 again, when the aforementioned circuit is applied to a practical rectifier circuit, the cross coupled P-[0034] type MOS transistors 101 and 102 are coupled to the N- type MOS transistors 103 and 104 of the circuit for simulating zero cut-in voltage diode. Consequently, the operation of the rectifier is as follows:
  • 1. When ACIN−ACIN[0035] 2>|Vtp| (Vp is the threshold voltage of the P-type MOS transistor), the P-type MOS transistor 101 is turned on, and ACIN1 is applied to VDD. At this moment, if ACIN2 is smaller than VSS, ACIN2 starts to charge VSS through the circuit for simulating zero cut-in voltage diode formed by the transistor 104 and the bias circuit.
  • 2. When ACIN[0036] 2−ACIN1>|Vtp|, the P-type MOS transistor 102 is turned on, and ACIN2 is applied to VDD. At this moment, if ACIN1 is smaller than VSS, ACIN1 starts to charge VSS through the circuit for simulating zero cut-in voltage diode formed by the transistor 103 and the bias circuit.
  • By alternately charging VSS, the AC power can be converted into DC power. Furthermore, the rectifier is formed by diode circuit with zero cut-in voltage, thereby having the zero cut-in voltage characteristic. In addition, because the circuit is primarily formed by MOS transistors, the current loss is small (only several microamperes) no matter the rectifier is operating at high speed or low speed. Accordingly, it is able to implement a high efficient rectifier having a low current loss. [0037]
  • FIG. 4 shows a rectifier having zero cut-in voltage characteristic in accordance with another preferred embodiment of the present invention. As shown, the [0038] transistors 303 and 304 are N-type MOS transistors which are connected in a cross couple structure. That is, the gate and drain of the transistor 303 are connected to the drain and gate of the transistor 304, respectively, such that one of the AC voltage source inputs ACIN1 and ACIN2 with a lower voltage level is applied to VSS.
  • Moreover, the P-[0039] type MOS transistor 305 is connected to a resistor 306 for forming a constant bias circuit. The P-type MOS transistor 301 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss. Similarly, the P-type MOS transistor 302 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss.
  • The circuit for simulating zero cut-in voltage diode as described above is individually illustrated in FIG. 5. As shown, the gate and drain of the P-[0040] type MOS transistor 305 are connected together. One end of the resistor 306 is connected to VSS, and the other end thereof is connected to the drain of the P-type MOS transistor 305 so as to form a bias circuit. The gate of the P-type MOS transistor 305 is connected to the gate of the P- type MOS transistor 301 or 302. The sources of the transistor 305 and the transistor 301 or 302 are all connected to VDD. The transistor 301 or 302 and the transistor 305 have the same characteristic. Therefore, by setting the resistance value of the resistor 306, the transistor 305 can be biased to VDD−Vtp (Vtp is the threshold voltage of the P-type MOS transistor). Accordingly, when ACIN>VDD, the circuit is deemed as a “diode” operating in a forward bias region. When ACIN<VDD, the leakage current is only several microamperes and the circuit is deemed as a “diode” operating in a reverse bias region. The operation of this embodiment is similar to the previous one, and thus a detailed description is deemed unnecessary.
  • Referring to FIG. 4 again, when the aforementioned circuit is applied to a practical rectifier circuit, the cross-coupled N-[0041] type MOS transistors 303 and 304 are coupled to the P- type MOS transistors 301 and 302 of the circuit for simulating zero cut-in voltage diode. The operation of the rectifier is as follows:
  • 1. When ACIN[0042] 1−ACIN2>Vtn, the N-type MOS transistor 304 is turned on, and ACIN2 is applied to VSS. When ACIN1 is larger than VDD, ACIN1 starts to charge VDD through the P-type MOS transistor 301.
  • 2. When ACIN[0043] 2−ACIN1>Vtn, the N-type MOS transistor 303 is turned on, and ACIN1 is applied to VSS. When ACIN2 is larger than VDD, ACIN2 starts to charge VDD through the P-type MOS transistor 302.
  • Similarly, by alternately charging VDD, the AC power can be converted into DC power, and the rectifier can be provided with zero cut-in voltage characteristic, so as to implement a high efficient rectifier having a low current loss. [0044]
  • Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. [0045]

Claims (8)

What is claimed is:
1. A rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising:
a constant bias circuit having a resistor and a N-type MOS transistor, the N-type MOS transistor having a drain connected to the resistor and a gate connected to the drain;
a first N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode;
a second N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and
a first P-type MOS transistor and a second P-type MOS transistor connected in a cross couple structure which are coupled to the first and second N-type MOS transistors, whereby a high voltage level of the AC voltage input is applied to a high voltage level of the DC voltage output, and a low voltage level of the AC voltage input charges a low voltage level of the DC voltage output through one of the zero cut-in voltage diodes.
2. The rectifier as claimed in claim 1, wherein the first and second N-type MOS transistors and the N-type MOS transistor of the constant bias circuit have the same characteristic.
3. The rectifier as claimed in claim 1, wherein the N-type MOS transistor of the constant bias circuit is controlled by the resistor to be biased almost to a threshold voltage.
4. A circuit for simulating zero cut-in voltage diode comprising:
a first N-type MOS transistor having a gate and a drain connected together;
a resistor connected to the drain of the first N-type MOS transistor for forming a bias circuit; and
a second N-type MOS transistor with the same characteristic as the first N-type MOS transistor, having a gate connected to the gate of the first N-type MOS transistor;
wherein the first N-type MOS transistor is controlled by the resistor to be biased almost to a threshold voltage.
5. A rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising:
a constant bias circuit having a resistor and a P-type MOS transistor, the P-type MOS transistor having a drain connected to the resistor, and a gate connected to the drain;
a first P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode;
a second P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and
a first N-type MOS transistor and a second N-type MOS transistor connected in a cross couple structure which are coupled to the first and second P-type MOS transistors, whereby a low voltage level of the AC voltage input is applied to a low voltage level of the DC voltage output, and a high voltage level of the AC voltage input charges a high voltage level of the DC voltage output through one of the zero cut-in voltage diodes.
6. The rectifier as claimed in claim 5, wherein the first and second P-type MOS transistors and the P-type MOS transistor of the constant bias circuit have the same characteristic.
7. The rectifier as claimed in claim 6, wherein the P-type MOS transistor of the constant bias circuit is controlled by the resistor to be based to VDD−Vtp, where VDD is the high voltage level of the DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.
8. A circuit for simulating zero cut-in voltage diode comprising:
a first P-type MOS transistor having a gate and a drain connected together;
a resistor connected to the drain of the first P-type MOS transistor, so as to form a bias circuit; and
a second P-type MOS transistor with the same characteristic as the first P-type MOS transistor, having a gate connected to the gate of the first P-type MOS transistor;
wherein the first P-type MOS transistor is controlled by the resistor to be based to VDD−Vtp, where VDD represents a high voltage level of a DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.
US09/739,704 2000-10-09 2000-12-20 Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic Expired - Fee Related US6404268B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW89217537 2000-09-10
TW089217537U TW479904U (en) 2000-10-09 2000-10-09 Diode circuit to simulate zero cutoff voltage and the rectifying circuit having zero cutoff voltage characteristics

Publications (2)

Publication Number Publication Date
US20020030527A1 true US20020030527A1 (en) 2002-03-14
US6404268B1 US6404268B1 (en) 2002-06-11

Family

ID=21673651

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/739,704 Expired - Fee Related US6404268B1 (en) 2000-10-09 2000-12-20 Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic

Country Status (2)

Country Link
US (1) US6404268B1 (en)
TW (1) TW479904U (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050272514A1 (en) * 2004-06-07 2005-12-08 Laurent Bissonnette Launch monitor
US7837572B2 (en) 2004-06-07 2010-11-23 Acushnet Company Launch monitor
US7959517B2 (en) 2004-08-31 2011-06-14 Acushnet Company Infrared sensing launch monitor
US8556267B2 (en) 2004-06-07 2013-10-15 Acushnet Company Launch monitor
KR20160091351A (en) * 2013-11-22 2016-08-02 캘리포니아 인스티튜트 오브 테크놀로지 Active cmos recovery units for wireless power transmission
US10090714B2 (en) 2013-11-12 2018-10-02 California Institute Of Technology Wireless power transfer
US10320242B2 (en) 2012-11-09 2019-06-11 California Institute Of Technology Generator unit for wireless power transfer
US10720797B2 (en) 2017-05-26 2020-07-21 California Institute Of Technology Method and apparatus for dynamic RF lens focusing and tracking of wireless power recovery unit
US11146113B2 (en) 2013-11-22 2021-10-12 California Institute Of Technology Generator unit for wireless power transfer
US11616520B2 (en) 2012-11-09 2023-03-28 California Institute Of Technology RF receiver
US11843260B2 (en) 2012-11-09 2023-12-12 California Institute Of Technology Generator unit for wireless power transfer

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7088145B2 (en) * 2002-12-23 2006-08-08 3M Innovative Properties Company AC powered logic circuitry
RU2008104539A (en) * 2005-07-08 2009-08-20 Мед-Эль Электромедицинише Герэте Гмбх (At) METHOD FOR SIGNAL RECTIFICATION, RECTIFIER, ELECTRICAL DEVICE (OPTIONS), POLARITY PROTECTION DEVICE AND IMPLANTED MEDICAL DEVICE CONTAINING THIS MEMORY
US8248141B2 (en) * 2005-07-08 2012-08-21 Med-El Elekromedizinische Geraete Gmbh Data and power system based on CMOS bridge
US7821323B2 (en) * 2008-11-06 2010-10-26 Osram Sylvania Inc. Bias circuit for a switching power supply
CN102821515B (en) * 2011-07-07 2015-05-13 广州市明光光电科技有限公司 LED controller

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA954644A (en) * 1972-11-28 1974-09-10 Arthur D. Moore Polarity guard
US4139880A (en) * 1977-10-03 1979-02-13 Motorola, Inc. CMOS polarity reversal circuit
US4485348A (en) * 1982-06-01 1984-11-27 Motorola, Inc. Full wave envelope detector using current mirrors
JPH0778481A (en) * 1993-04-30 1995-03-20 Sgs Thomson Microelectron Inc Direct-current sum band-gap voltage comparator
US5622886A (en) * 1994-03-31 1997-04-22 Atmel Corporation Method of making a high voltage rectifier for an integrated circuit chip
EP0791706B1 (en) * 1996-01-31 2004-07-14 Texas Instruments Deutschland Gmbh Improvements in or relating to full-wave rectifiers
FR2756679B1 (en) * 1996-11-29 1999-02-12 France Telecom VOLTAGE RECTIFIER WITH INTEGRATED COMPONENTS
US6052299A (en) * 1998-01-15 2000-04-18 Microship Technology Incorporated Robust LC full-wave bridge rectifier input structure

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050272514A1 (en) * 2004-06-07 2005-12-08 Laurent Bissonnette Launch monitor
US7837572B2 (en) 2004-06-07 2010-11-23 Acushnet Company Launch monitor
US8475289B2 (en) * 2004-06-07 2013-07-02 Acushnet Company Launch monitor
US8556267B2 (en) 2004-06-07 2013-10-15 Acushnet Company Launch monitor
US7959517B2 (en) 2004-08-31 2011-06-14 Acushnet Company Infrared sensing launch monitor
US11843260B2 (en) 2012-11-09 2023-12-12 California Institute Of Technology Generator unit for wireless power transfer
US11502552B2 (en) 2012-11-09 2022-11-15 California Institute Of Technology Smart RF lensing: efficient, dynamic and mobile wireless power transfer
US11616520B2 (en) 2012-11-09 2023-03-28 California Institute Of Technology RF receiver
US10320242B2 (en) 2012-11-09 2019-06-11 California Institute Of Technology Generator unit for wireless power transfer
US10367380B2 (en) 2012-11-09 2019-07-30 California Institute Of Technology Smart RF lensing: efficient, dynamic and mobile wireless power transfer
US11616402B2 (en) 2012-11-09 2023-03-28 California Institute Of Technology Smart RF lensing: efficient, dynamic and mobile wireless power transfer
US11616401B2 (en) 2012-11-09 2023-03-28 California Institute Of Technology Smart RF lensing: efficient, dynamic and mobile wireless power transfer
US10090714B2 (en) 2013-11-12 2018-10-02 California Institute Of Technology Wireless power transfer
KR20160091351A (en) * 2013-11-22 2016-08-02 캘리포니아 인스티튜트 오브 테크놀로지 Active cmos recovery units for wireless power transmission
US11146113B2 (en) 2013-11-22 2021-10-12 California Institute Of Technology Generator unit for wireless power transfer
KR102367364B1 (en) 2013-11-22 2022-02-23 캘리포니아 인스티튜트 오브 테크놀로지 Active cmos recovery units for wireless power transmission
US10673351B2 (en) 2013-11-22 2020-06-02 California Institute Of Technology Active CMOS recovery units for wireless power transmission
US10003278B2 (en) 2013-11-22 2018-06-19 California Institute Of Technology Active CMOS recovery units for wireless power transmission
EP3072213A4 (en) * 2013-11-22 2017-08-16 California Institute Of Technology Active cmos recovery units for wireless power transmission
US11095164B2 (en) 2014-08-19 2021-08-17 California Institute Of Technology Wireless power transfer
US10720797B2 (en) 2017-05-26 2020-07-21 California Institute Of Technology Method and apparatus for dynamic RF lens focusing and tracking of wireless power recovery unit

Also Published As

Publication number Publication date
TW479904U (en) 2002-03-11
US6404268B1 (en) 2002-06-11

Similar Documents

Publication Publication Date Title
US6404268B1 (en) Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic
JP4347423B2 (en) Power supply using synchronous rectification
TWI509971B (en) System and method and controller for output detection and synchronous rectification mechanism for adjusting power supply conversion system
JP5169170B2 (en) Step-down switching regulator
JP6169892B2 (en) Semiconductor integrated circuit and operation method thereof
US4519024A (en) Two-terminal transistor rectifier circuit arrangement
US10079542B2 (en) High voltage current source with short circuit protection
US20060145746A1 (en) On chip power supply
US20060109693A1 (en) Switching power supply device and switching method
US5173849A (en) Integratable synchronous rectifier
CN108923660B (en) Synchronous rectification converter
US20200099285A1 (en) Driver circuit
JP2010028962A (en) Switching power supply device, and its dead time adjusting method
US6490178B1 (en) Switching power circuit which switches voltage supplied to a primary winding of a transformer with a switching element to rectify alternating current generated in a secondary winding of the transformer
US7239114B2 (en) Converter for direct current-to-direct current downward conversion
Núñez et al. Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications
US4754168A (en) Charge pump circuit for substrate-bias generator
US6504733B1 (en) Switch mode power supply
JP2002315311A (en) Switching regulator
CN114362501B (en) Dynamic anti-backflow circuit for wireless charging synchronous rectifier bridge and working method thereof
Ming et al. A high-reliability half-bridge GaN FET gate driver with advanced floating bias control techniques
Cho et al. A high voltage half bridge gate driver with mismatch-insensitive dead-time generator
US6839248B2 (en) Flyback power supply device and control method thereof
Wu et al. Asymmetrical dead-time control driver for buck regulator
TWI844324B (en) Boost converter with high conversion efficiency

Legal Events

Date Code Title Description
AS Assignment

Owner name: SUNPLUS TECHNOLOGY CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUNG, HSI-HSIEN;LEE, HSIN CHOU;REEL/FRAME:011383/0726

Effective date: 20001207

FEPP Fee payment procedure

Free format text: PAT HOLDER NO LONGER CLAIMS SMALL ENTITY STATUS, ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: STOL); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REFU Refund

Free format text: REFUND - SURCHARGE, PETITION TO ACCEPT PYMT AFTER EXP, UNINTENTIONAL (ORIGINAL EVENT CODE: R2551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140611