US20020030527A1 - Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic - Google Patents
Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic Download PDFInfo
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- US20020030527A1 US20020030527A1 US09/739,704 US73970400A US2002030527A1 US 20020030527 A1 US20020030527 A1 US 20020030527A1 US 73970400 A US73970400 A US 73970400A US 2002030527 A1 US2002030527 A1 US 2002030527A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
- H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to a diode circuit and rectifier and, more particularly, to a MOS transistor circuit manufactured by the CMOS process for simulating zero cut-in voltage diode and a zero cut-in voltage rectifier including the diode.
- the conventional AC to DC full wave rectifier is generally formed by diodes. Since the diode has a cut-in voltage of 0.6V, the rectifier will have a power loss in voltage conversion. Particularly, when the input voltage is small, the negative influence caused by such a power loss becomes obvious and unacceptable.
- the power of IC is supplied from a small AC power generated by the induction of a coil, and thus, the efficiency of rectifying will directly affect the use range of this IC. As a result, the operating efficiency of such an IC is determined by the performance of the rectifier.
- FIG. 6 a popular circuit, known as a full wave bridge rectifier, is illustrated in FIG. 6, which has four diodes 902 to 905 connected in a bridge structure.
- the diodes 902 and 905 are turned on if the applied waveform ACIN 1 >ACIN 2 .
- the AC signal charges the capacitor 906 through the diodes 902 and 905 .
- the diodes 903 and 904 are turned on, and the AC signal charges the capacitor 906 through the diodes 903 and 904 .
- the AC power can be rectified to produce a DC power.
- FIG. 7 is the rectifying waveform of a bridge rectifier, which shows that, due to the influence of the cut-in voltage of the diode, the rectified DC voltage VDD only has a maximum value of Vac ⁇ 2*Vd, where Vac is the voltage peak value of the AC power source 901 and Vd is the cut-in voltage of the diode. Therefore, the rectifying performance of the rectifier is greatly degraded.
- FIG. 8 shows another conventional rectifier circuit, which uses metal oxide semiconductor (MOS) transistors 914 and 915 with N-type substrate to control the diodes for performing the rectifying operation of AC to DC conversion.
- MOS metal oxide semiconductor
- FIG. 9 is a rectifying waveform of the rectifier circuit shown in FIG. 8.
- this improved rectifier circuit is able to reduce a voltage drop equal to one cut-in voltage of a diode. That is, the maximum value of the DC voltage VDD is only improved to be Vac ⁇ Vd. Under a condition of no current load, there is still a voltage loss of 0.6V. Thus, the influence of the cut-in voltage can not be completely removed.
- U.S. Pat. No. 5,825,214 granted to Klosa discloses an “Integrated circuit arrangement with diode characteristic” for replacing the conventional diodes to realize a rectifier with zero cut-in voltage.
- the schematic view of the circuit is illustrated in FIG. 10, which comprises three inverters 921 , 922 , and 923 and a P-type MOS transistor 924 for being used as a switch.
- the input end and output end of the inverter 921 are connected together, and thus the output voltage level is automatically set at the trigger point of the inverter. This voltage will change positively with the level of the supplying power.
- the voltage level set by the inverter 921 is directly applied to the input end of the inverter 922 which receives power from an AC input ACIN.
- the two inverters 921 and 922 have the same size and characteristic. Therefore, when the ACIN is smaller than the VDD, the input of the inverter 922 is considered to be a high voltage level. Through the inverter 923 , the P-type MOS transistor 924 is turned off so as to avoid a leakage current. On the other hand, when the ACIN is larger than the VDD, the input of the inverter 922 is considered to be a low voltage level, the P-type MOS transistor 924 is turned on through the inverter 923 , so as to charge VDD.
- the P-type MOS transistor 924 can be turned on completely to provide the advantage of zero cut-in voltage.
- the inverters 921 and 922 are operating at a high speed, it is inevitable that a high current loss problem will be encountered. Therefore, the overall efficiency of the rectifier is unsatisfactory due to such a current loss. Consequently, it is desirable to provide an improved circuit to mitigate and/or obviate the aforementioned problems.
- the object of the present invention is to provide a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic, so as to improve the efficiency of rectifying, reduce the current loss, and avoid the output voltage drop caused by the cut-in voltage of diode.
- a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output comprising: a constant bias circuit having a resistor and a N-type MOS transistor, the N-type MOS transistor having a drain connected to the resistor and a gate connected to the drain; a first N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first P-type MOS transistor and a second P-type MOS transistor connected in a cross couple structure which are coupled to the first and second N-type MOS transistors, whereby a high voltage level of the AC voltage input is applied to a high voltage level of the DC voltage output, and a low voltage level of
- a circuit for simulating zero cut-in voltage diode comprising: a first N-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first N-type MOS transistor for forming a bias circuit; and a second N-type MOS transistor with the same characteristic as the first N-type MOS transistor, having a gate connected to the gate of the first N-type MOS transistor; wherein the first N-type MOS transistor is controlled by the resistor to be biased almost to a threshold voltage.
- a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output comprising: a constant bias circuit having a resistor and a P-type MOS transistor, the P-type MOS transistor having a drain connected to the resistor, and a gate connected to the drain; a first P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first N-type MOS transistor and a second N-type MOS transistor connected in a cross couple structure which are coupled to the first and second P-type MOS transistors, whereby a low voltage level of the AC voltage input is applied to a low voltage level of the DC voltage output, and a high voltage level
- a circuit for simulating zero cut-in voltage diode comprising: a first P-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first P-type MOS transistor, so as to form a bias circuit; and a second P-type MOS transistor with the same characteristic as the first P-type MOS transistor, having a gate connected to the gate of the first P-type MOS transistor; wherein the first P-type MOS transistor is controlled by the resistor to be based to VDD ⁇ Vtp, where VDD represents a high voltage level of a DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.
- FIG. 1 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a first embodiment of the present invention
- FIG. 2 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the first embodiment of the present invention
- FIG. 3 shows the characteristic curve of the circuit for simulating zero cut-in voltage diode in accordance with the present invention
- FIG. 4 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a second embodiment of the present invention.
- FIG. 5 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the second embodiment of the present invention.
- FIG. 6 is the schematic diagram of a conventional full wave rectifier
- FIG. 7 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 6;
- FIG. 8 is a schematic diagram of another conventional full wave rectifier
- FIG. 9 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 8.
- FIG. 10 is a schematic diagram of a conventional zero cut-in voltage diode.
- FIG. 1 there is shown a rectifier formed by the circuit for simulating zero cut-in voltage diode in accordance with a preferred embodiment of the present invention.
- ACIN 1 and ACIN 2 represent the inputs of an AC voltage source
- VDD and VSS represent the high voltage level and low voltage level of a DC voltage output.
- the transistors 101 and 102 are P-type MOS transistors connected in a cross couple structure. That is, the gate and drain of transistor 101 are connected to the drain and gate of the transistor 102 , respectively, such that one of the AC voltage source inputs ACIN 1 and ACIN 2 with a higher voltage level is applied to VDD.
- the N-type MOS transistor 106 is connected to a resistor 105 for forming a constant bias circuit.
- the N-type MOS transistor 103 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with a low current loss.
- the N-type MOS transistor 104 is connected to the bias circuit so as to form another circuit for simulating zero cut-in voltage diode with a lower current loss.
- FIG. 2 For the purpose of convenient description, a single circuit for simulating zero cut-in voltage diode is illustrated in FIG. 2.
- the gate and drain of the N-type MOS transistor 106 are connected together.
- One end of the resistor 105 is connected to the VDD, and the other end thereof is connected the drain of the N-type MOS transistor 106 so as to form a bias circuit.
- the gate of the N-type MOS transistor 106 is connected to the gate of the N-type MOS transistor 103 or 104 .
- the sources of the transistor 106 and the transistor 103 or 104 are all connected to VSS.
- the transistor 103 or 104 and the transistor 106 have the same characteristic.
- the current flowing through the transistor 106 can be controlled.
- the transistor 106 is biased almost to its threshold voltage. Since the gates of the transistor 103 or 104 and the transistor 106 are connected together, and the transistor 103 or 104 and the transistor 106 have the same characteristic, the transistor 103 or 104 is also biased to the threshold voltage.
- the AC power can be converted into DC power.
- the rectifier is formed by diode circuit with zero cut-in voltage, thereby having the zero cut-in voltage characteristic.
- the circuit is primarily formed by MOS transistors, the current loss is small (only several microamperes) no matter the rectifier is operating at high speed or low speed. Accordingly, it is able to implement a high efficient rectifier having a low current loss.
- FIG. 4 shows a rectifier having zero cut-in voltage characteristic in accordance with another preferred embodiment of the present invention.
- the transistors 303 and 304 are N-type MOS transistors which are connected in a cross couple structure. That is, the gate and drain of the transistor 303 are connected to the drain and gate of the transistor 304 , respectively, such that one of the AC voltage source inputs ACIN 1 and ACIN 2 with a lower voltage level is applied to VSS.
- the P-type MOS transistor 305 is connected to a resistor 306 for forming a constant bias circuit.
- the P-type MOS transistor 301 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss.
- the P-type MOS transistor 302 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss.
- the circuit for simulating zero cut-in voltage diode as described above is individually illustrated in FIG. 5. As shown, the gate and drain of the P-type MOS transistor 305 are connected together. One end of the resistor 306 is connected to VSS, and the other end thereof is connected to the drain of the P-type MOS transistor 305 so as to form a bias circuit. The gate of the P-type MOS transistor 305 is connected to the gate of the P-type MOS transistor 301 or 302 . The sources of the transistor 305 and the transistor 301 or 302 are all connected to VDD. The transistor 301 or 302 and the transistor 305 have the same characteristic.
- the transistor 305 can be biased to VDD ⁇ Vtp (Vtp is the threshold voltage of the P-type MOS transistor). Accordingly, when ACIN>VDD, the circuit is deemed as a “diode” operating in a forward bias region. When ACIN ⁇ VDD, the leakage current is only several microamperes and the circuit is deemed as a “diode” operating in a reverse bias region. The operation of this embodiment is similar to the previous one, and thus a detailed description is deemed unnecessary.
- the cross-coupled N-type MOS transistors 303 and 304 are coupled to the P-type MOS transistors 301 and 302 of the circuit for simulating zero cut-in voltage diode.
- the operation of the rectifier is as follows:
- the AC power can be converted into DC power, and the rectifier can be provided with zero cut-in voltage characteristic, so as to implement a high efficient rectifier having a low current loss.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a diode circuit and rectifier and, more particularly, to a MOS transistor circuit manufactured by the CMOS process for simulating zero cut-in voltage diode and a zero cut-in voltage rectifier including the diode.
- 2. Description of Related Art
- The conventional AC to DC full wave rectifier is generally formed by diodes. Since the diode has a cut-in voltage of 0.6V, the rectifier will have a power loss in voltage conversion. Particularly, when the input voltage is small, the negative influence caused by such a power loss becomes obvious and unacceptable.
- In the field of contactless IC and the like, the power of IC is supplied from a small AC power generated by the induction of a coil, and thus, the efficiency of rectifying will directly affect the use range of this IC. As a result, the operating efficiency of such an IC is determined by the performance of the rectifier.
- In the aforementioned AC to DC full wave rectifier, a popular circuit, known as a full wave bridge rectifier, is illustrated in FIG. 6, which has four
diodes 902 to 905 connected in a bridge structure. With such a circuit, when theAC power source 901 applies AC signal to the full wave rectifier, thediodes capacitor 906 through thediodes diodes capacitor 906 through thediodes - FIG. 7 is the rectifying waveform of a bridge rectifier, which shows that, due to the influence of the cut-in voltage of the diode, the rectified DC voltage VDD only has a maximum value of Vac−2*Vd, where Vac is the voltage peak value of the
AC power source 901 and Vd is the cut-in voltage of the diode. Therefore, the rectifying performance of the rectifier is greatly degraded. - In order to solve such a problem, FIG. 8 shows another conventional rectifier circuit, which uses metal oxide semiconductor (MOS)
transistors type MOS transistor 915 is turned on, and the ACIN2 is applied to a lowest voltage VSS. When ACIN1−VDD>Vd, thediode 912 is turned on, and the AC power source starts to charge VDD. When ACIN2−ACIN1>Vtn, the N-type MOS transistor 914 is turned on, ACIN1 is applied to a lowest voltage VSS. When ACIN2−VDD>Vd, thediode 913 is turned on, and the AC voltage source starts to charge the VDD. - FIG. 9 is a rectifying waveform of the rectifier circuit shown in FIG. 8. In comparison with the waveform shown in FIG. 7, it is known that this improved rectifier circuit is able to reduce a voltage drop equal to one cut-in voltage of a diode. That is, the maximum value of the DC voltage VDD is only improved to be Vac−Vd. Under a condition of no current load, there is still a voltage loss of 0.6V. Thus, the influence of the cut-in voltage can not be completely removed.
- In order to entirely remove the cut-in voltage of the diode so that the maximum value of the VDD is Vac, U.S. Pat. No. 5,825,214 granted to Klosa discloses an “Integrated circuit arrangement with diode characteristic” for replacing the conventional diodes to realize a rectifier with zero cut-in voltage. The schematic view of the circuit is illustrated in FIG. 10, which comprises three
inverters type MOS transistor 924 for being used as a switch. The input end and output end of theinverter 921 are connected together, and thus the output voltage level is automatically set at the trigger point of the inverter. This voltage will change positively with the level of the supplying power. The voltage level set by theinverter 921 is directly applied to the input end of theinverter 922 which receives power from an AC input ACIN. The twoinverters inverter 922 is considered to be a high voltage level. Through theinverter 923, the P-type MOS transistor 924 is turned off so as to avoid a leakage current. On the other hand, when the ACIN is larger than the VDD, the input of theinverter 922 is considered to be a low voltage level, the P-type MOS transistor 924 is turned on through theinverter 923, so as to charge VDD. - In the aforementioned circuit, the P-
type MOS transistor 924 can be turned on completely to provide the advantage of zero cut-in voltage. However, if theinverters - Accordingly, the object of the present invention is to provide a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic, so as to improve the efficiency of rectifying, reduce the current loss, and avoid the output voltage drop caused by the cut-in voltage of diode.
- In accordance with a first aspect of the present invention, there is provided a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising: a constant bias circuit having a resistor and a N-type MOS transistor, the N-type MOS transistor having a drain connected to the resistor and a gate connected to the drain; a first N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first P-type MOS transistor and a second P-type MOS transistor connected in a cross couple structure which are coupled to the first and second N-type MOS transistors, whereby a high voltage level of the AC voltage input is applied to a high voltage level of the DC voltage output, and a low voltage level of the AC voltage input charges a low voltage level of the DC voltage output through one of the zero cut-in voltage diodes.
- In accordance with a second aspect of the present invention, there is provided a circuit for simulating zero cut-in voltage diode comprising: a first N-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first N-type MOS transistor for forming a bias circuit; and a second N-type MOS transistor with the same characteristic as the first N-type MOS transistor, having a gate connected to the gate of the first N-type MOS transistor; wherein the first N-type MOS transistor is controlled by the resistor to be biased almost to a threshold voltage.
- In accordance with a third aspect of the present invention, there is provided a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising: a constant bias circuit having a resistor and a P-type MOS transistor, the P-type MOS transistor having a drain connected to the resistor, and a gate connected to the drain; a first P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first N-type MOS transistor and a second N-type MOS transistor connected in a cross couple structure which are coupled to the first and second P-type MOS transistors, whereby a low voltage level of the AC voltage input is applied to a low voltage level of the DC voltage output, and a high voltage level of the AC voltage input charges a high voltage level of the DC voltage output through one of the zero cut-in voltage diodes.
- In accordance with a fourth aspect of the present invention, there is provided a circuit for simulating zero cut-in voltage diode comprising: a first P-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first P-type MOS transistor, so as to form a bias circuit; and a second P-type MOS transistor with the same characteristic as the first P-type MOS transistor, having a gate connected to the gate of the first P-type MOS transistor; wherein the first P-type MOS transistor is controlled by the resistor to be based to VDD−Vtp, where VDD represents a high voltage level of a DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.
- Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
- FIG. 1 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a first embodiment of the present invention;
- FIG. 2 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the first embodiment of the present invention;
- FIG. 3 shows the characteristic curve of the circuit for simulating zero cut-in voltage diode in accordance with the present invention;
- FIG. 4 is a schematic diagram of a rectifier having zero cut-in voltage characteristic in accordance with a second embodiment of the present invention;
- FIG. 5 is a schematic diagram of a circuit for simulating zero cut-in voltage diode in accordance with the second embodiment of the present invention;
- FIG. 6 is the schematic diagram of a conventional full wave rectifier;
- FIG. 7 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 6;
- FIG. 8 is a schematic diagram of another conventional full wave rectifier;
- FIG. 9 shows the rectifying waveform of the full wave rectifier circuit shown in FIG. 8; and
- FIG. 10 is a schematic diagram of a conventional zero cut-in voltage diode.
- Referring to the drawings and initially to FIG. 1, there is shown a rectifier formed by the circuit for simulating zero cut-in voltage diode in accordance with a preferred embodiment of the present invention. As shown, ACIN1 and ACIN2 represent the inputs of an AC voltage source, and VDD and VSS represent the high voltage level and low voltage level of a DC voltage output. The
transistors transistor 101 are connected to the drain and gate of thetransistor 102, respectively, such that one of the AC voltage source inputs ACIN1 and ACIN2 with a higher voltage level is applied to VDD. - Furthermore, the N-
type MOS transistor 106 is connected to aresistor 105 for forming a constant bias circuit. The N-type MOS transistor 103 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with a low current loss. Similarly, the N-type MOS transistor 104 is connected to the bias circuit so as to form another circuit for simulating zero cut-in voltage diode with a lower current loss. - For the purpose of convenient description, a single circuit for simulating zero cut-in voltage diode is illustrated in FIG. 2. The gate and drain of the N-
type MOS transistor 106 are connected together. One end of theresistor 105 is connected to the VDD, and the other end thereof is connected the drain of the N-type MOS transistor 106 so as to form a bias circuit. Furthermore, the gate of the N-type MOS transistor 106 is connected to the gate of the N-type MOS transistor transistor 106 and thetransistor transistor transistor 106 have the same characteristic. Therefore, by setting the resistance value of theresistor 105, the current flowing through thetransistor 106 can be controlled. When the current is of several microamperes (μA), thetransistor 106 is biased almost to its threshold voltage. Since the gates of thetransistor transistor 106 are connected together, and thetransistor transistor 106 have the same characteristic, thetransistor - After being biased, the operation of the circuit for simulating zero cut-in voltage diode is analyzed as follows:
- 1. When ACIN1>VSS, the
transistor transistor transistor 106 multiplied by the bias current. This current is defined as the leakage current. The value of this current is designed to be several microamperes. As such, this operation region is deemed as a “diode” operating in a reverse bias region. - 2. When ACIN<VSS, the source of the
transistor - Referring to FIG. 1 again, when the aforementioned circuit is applied to a practical rectifier circuit, the cross coupled P-
type MOS transistors type MOS transistors - 1. When ACIN−ACIN2>|Vtp| (Vp is the threshold voltage of the P-type MOS transistor), the P-
type MOS transistor 101 is turned on, and ACIN1 is applied to VDD. At this moment, if ACIN2 is smaller than VSS, ACIN2 starts to charge VSS through the circuit for simulating zero cut-in voltage diode formed by thetransistor 104 and the bias circuit. - 2. When ACIN2−ACIN1>|Vtp|, the P-
type MOS transistor 102 is turned on, and ACIN2 is applied to VDD. At this moment, if ACIN1 is smaller than VSS, ACIN1 starts to charge VSS through the circuit for simulating zero cut-in voltage diode formed by thetransistor 103 and the bias circuit. - By alternately charging VSS, the AC power can be converted into DC power. Furthermore, the rectifier is formed by diode circuit with zero cut-in voltage, thereby having the zero cut-in voltage characteristic. In addition, because the circuit is primarily formed by MOS transistors, the current loss is small (only several microamperes) no matter the rectifier is operating at high speed or low speed. Accordingly, it is able to implement a high efficient rectifier having a low current loss.
- FIG. 4 shows a rectifier having zero cut-in voltage characteristic in accordance with another preferred embodiment of the present invention. As shown, the
transistors transistor 303 are connected to the drain and gate of thetransistor 304, respectively, such that one of the AC voltage source inputs ACIN1 and ACIN2 with a lower voltage level is applied to VSS. - Moreover, the P-
type MOS transistor 305 is connected to aresistor 306 for forming a constant bias circuit. The P-type MOS transistor 301 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss. Similarly, the P-type MOS transistor 302 is connected to the bias circuit so as to form a circuit for simulating zero cut-in voltage diode with low current loss. - The circuit for simulating zero cut-in voltage diode as described above is individually illustrated in FIG. 5. As shown, the gate and drain of the P-
type MOS transistor 305 are connected together. One end of theresistor 306 is connected to VSS, and the other end thereof is connected to the drain of the P-type MOS transistor 305 so as to form a bias circuit. The gate of the P-type MOS transistor 305 is connected to the gate of the P-type MOS transistor transistor 305 and thetransistor transistor transistor 305 have the same characteristic. Therefore, by setting the resistance value of theresistor 306, thetransistor 305 can be biased to VDD−Vtp (Vtp is the threshold voltage of the P-type MOS transistor). Accordingly, when ACIN>VDD, the circuit is deemed as a “diode” operating in a forward bias region. When ACIN<VDD, the leakage current is only several microamperes and the circuit is deemed as a “diode” operating in a reverse bias region. The operation of this embodiment is similar to the previous one, and thus a detailed description is deemed unnecessary. - Referring to FIG. 4 again, when the aforementioned circuit is applied to a practical rectifier circuit, the cross-coupled N-
type MOS transistors type MOS transistors - 1. When ACIN1−ACIN2>Vtn, the N-
type MOS transistor 304 is turned on, and ACIN2 is applied to VSS. When ACIN1 is larger than VDD, ACIN1 starts to charge VDD through the P-type MOS transistor 301. - 2. When ACIN2−ACIN1>Vtn, the N-
type MOS transistor 303 is turned on, and ACIN1 is applied to VSS. When ACIN2 is larger than VDD, ACIN2 starts to charge VDD through the P-type MOS transistor 302. - Similarly, by alternately charging VDD, the AC power can be converted into DC power, and the rectifier can be provided with zero cut-in voltage characteristic, so as to implement a high efficient rectifier having a low current loss.
- Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.
Claims (8)
Applications Claiming Priority (2)
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TW89217537 | 2000-09-10 | ||
TW089217537U TW479904U (en) | 2000-10-09 | 2000-10-09 | Diode circuit to simulate zero cutoff voltage and the rectifying circuit having zero cutoff voltage characteristics |
Publications (2)
Publication Number | Publication Date |
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US20020030527A1 true US20020030527A1 (en) | 2002-03-14 |
US6404268B1 US6404268B1 (en) | 2002-06-11 |
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US09/739,704 Expired - Fee Related US6404268B1 (en) | 2000-10-09 | 2000-12-20 | Circuit for simulating zero cut-in voltage diode and rectifier having zero cut-in voltage characteristic |
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US (1) | US6404268B1 (en) |
TW (1) | TW479904U (en) |
Cited By (11)
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US20050272514A1 (en) * | 2004-06-07 | 2005-12-08 | Laurent Bissonnette | Launch monitor |
US7837572B2 (en) | 2004-06-07 | 2010-11-23 | Acushnet Company | Launch monitor |
US7959517B2 (en) | 2004-08-31 | 2011-06-14 | Acushnet Company | Infrared sensing launch monitor |
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US10720797B2 (en) | 2017-05-26 | 2020-07-21 | California Institute Of Technology | Method and apparatus for dynamic RF lens focusing and tracking of wireless power recovery unit |
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US7088145B2 (en) * | 2002-12-23 | 2006-08-08 | 3M Innovative Properties Company | AC powered logic circuitry |
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US6404268B1 (en) | 2002-06-11 |
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