US20020028532A1 - Method of manufacturing a multi-chip semiconductor device effective to improve alignment - Google Patents
Method of manufacturing a multi-chip semiconductor device effective to improve alignment Download PDFInfo
- Publication number
- US20020028532A1 US20020028532A1 US09/560,143 US56014300A US2002028532A1 US 20020028532 A1 US20020028532 A1 US 20020028532A1 US 56014300 A US56014300 A US 56014300A US 2002028532 A1 US2002028532 A1 US 2002028532A1
- Authority
- US
- United States
- Prior art keywords
- chips
- holes
- chip
- light
- semiconductor substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
- H01L2224/95121—Active alignment, i.e. by apparatus steering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
Definitions
- the present invention relates to a multi-chip semiconductor device and a chip to be applied to this device and, more particularly, to a multi-chip semiconductor device effective to improve alignment and a chip to be applied to this device.
- One characteristic feature of this chip is that a through hole is formed in a semiconductor device on which elements are integrally formed and a connecting plug made of a conductive material is formed in this through hole. Chips are electrically connected via these connecting plugs to accomplish a multi-chip semiconductor device including a plurality of stacked chips.
- pads made of a conductive material are used to connect connecting plugs of different chips or to electrically connect connecting plugs of different chips and a multilevel interconnecting layer.
- This pad has a solder bump.
- a chip applied to a multi-chip semiconductor device comprising: a semiconductor substrate on which at least one element is formed; a connecting portion formed in the semiconductor substrate and electrically connected to another chip; and two or more light-transmitting portions formed in the semiconductor substrate.
- a method of manufacturing a chip applied to a multi-chip semiconductor device comprising the steps of: forming a plurality of holes having a desired depth in a surface of a semiconductor substrate; forming an insulating film on side walls and bottoms of the holes; burying a conductive material in the holes except for at least two holes; and exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed.
- a method of aligning a plurality of stacked chips each having a light-transmitting portion comprising the steps of: irradiating light onto one of uppermost and lowermost chips of the stacked chips; detecting light output from the stacked chips through the light-transmitting portions of the chips; and aligning the chips in accordance with the detected light.
- a multi-chip semiconductor device comprising: a plurality of stacked chips; and a plurality of conducting portions each formed between the chips, wherein each of the chips comprises: a semiconductor substrate on which at least one element is formed; a connecting portion formed to extend through the semiconductor substrate and electrically connected to an adjacent chip via the conducting portions arranged on both surfaces of the semiconductor substrate; and two or more light-transmitting portions formed in the semiconductor substrate.
- a method of manufacturing a multi-chip semiconductor device comprising the steps of: manufacturing a plurality of semiconductor substrates; stacking the semiconductor substrates; arranging a plurality of conducting portions between the semiconductor substrates; aligning the semiconductor substrates; and electrically connecting the semiconductor substrates, wherein the step of manufacturing the semiconductor substrates comprises the substeps of: forming a plurality of holes having a desired depth in a surface of a semiconductor substrate; forming an insulating film on side walls and bottoms of the holes; burying a conductive material in the holes except for two holes; and exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed, and the step of performing alignment comprises the substeps of: irradiating light onto one of uppermost and lowermost semiconductor substrates of the stacked semiconductor substrates; detecting light output from the stacked semiconductor substrates through holes except for the holes formed in the semiconductor substrates and filled with the conductive material; and
- an apparatus for manufacturing a multi-chip semiconductor device comprising: a holding mechanism for stacking and holding a plurality of semiconductor substrates each having a light-transmitting portion in a predetermined position; a coarse adjustment unit for coarsely moving each of the semiconductor substrates; a fine adjustment unit for finely moving each of the semiconductor substrates; a light source for irradiating light onto one of uppermost and lowermost semiconductor substrates of the semiconductor substrates; a light-receiving unit for detecting light output from the stacked semiconductor substrates through the light-transmitting portions formed in the semiconductor substrates; and a controller for controlling the coarse adjustment unit and the fine adjustment unit in accordance with an amount of the light detected by the light-receiving unit, thereby aligning the semiconductor substrates.
- high-accuracy alignment can be performed by using multi-chip semiconductor device chips having light-transmitting portions (hollow portions) for alignment.
- FIG. 1 is a sectional view showing a multi-chip semiconductor device according to the first embodiment of the present invention
- FIG. 2 is a view for explaining a method of aligning chips in the first embodiment
- FIGS. 3A and 3B are views showing planar patterns of alignment holes applicable to the multi-chip semiconductor device shown in FIG. 1;
- FIGS. 4A to 4 K are sectional views for explaining a method of manufacturing a multi-chip-semiconductor device according to the second embodiment of the present invention.
- FIGS. 5A to 5 G are sectional views for explaining a method of manufacturing a multi-chip semiconductor device according to the third embodiment of the present invention.
- FIG. 6 is a view for explaining an apparatus for manufacturing a multi-chip semiconductor device according to the fourth embodiment of the present invention.
- FIG. 7 is a flow chart for explaining a method of manufacturing a multi-chip semiconductor device by using the manufacturing apparatus shown in FIG. 6;
- FIGS. 8A and 8B are views for explaining an effect when a stage is moved at an elevation angle in the manufacturing apparatus shown in FIG. 6.
- FIG. 1 is a sectional view showing a multi-chip semiconductor device according to this first embodiment.
- FIG. 2 is a view for explaining a method of aligning chips in this multi-chip semiconductor device.
- FIGS. 3A and 3B show examples of planar patterns of alignment holes.
- Each of the chips 1 A, 1 B, and 1 C roughly comprises a silicon substrate 2 on which elements are integrally formed, a multilevel interconnecting layer 3 for connecting these elements in a desired manner, a plurality of conductive through plugs 4 (conductive plugs) extending through the silicon substrate 2 to electrically connect the chips, and an alignment hole 5 (light-transmitting portion) for transmitting light used in aligning the chips in the step of connecting the chips.
- These chips 1 A, 1 B, and 1 C have the same size (the area and the shape) and need to be stacked without any deviation. Although only one alignment hole 5 is shown in FIG. 1 for simplicity, at least two alignment holes 5 must be formed in each chip. These alignment holes 5 are formed in the same position of the chips 1 A, 1 B, and 1 C. Note that the chips 1 A, 1 B, and 1 C are not always required to have the same shape and the same area. If this is the case, however, the alignment holes 5 must be so formed in these chips that these alignment holes are vertically aligned with no difference when the chips are stacked in a desired manner.
- An insulating interlayer constituting the multilevel interconnecting layer 3 is made of a material (e.g., SiO 2 ) which transmits light.
- An insulating film 6 is formed between the through plug 4 and the silicon substrate 2 , and this insulating film 6 and the through plug 4 constitute a connecting plug.
- Pads 7 are formed in the multilevel interconnecting layer 3 of each of the chips 1 A, 1 B, and 1 C. Also, a silicon region of the silicon substrate 2 away from the pad 7 , i.e., a silicon region except for the through plugs 4 and the alignment hole 5 in each of the chips 1 A, 1 B, and 1 C is covered with an insulating film 8 .
- the through plugs 4 of the chip 1 A are electrically connected via solder bumps 9 to the pads 7 formed in the multilevel interconnecting layer 3 of the chip 1 B. Consequently, the chips 1 A and 1 B are electrically connected. Note that bumps other than the solder bumps 9 can also be used.
- the through plugs 4 of the chip 1 B are electrically connected via solder bumps 9 to the pads 7 formed in the multilevel interconnecting layer 3 of the chip 1 C. Consequently, the chips 1 B and 1 C are electrically connected. In this way the chips 1 A, 1 B, and 1 C are electrically connected.
- a material which transmits a laser beam e.g., a silicon oxide film (SiO 2 film) 10 is buried in the alignment hole 5 of each of the chips 1 A, 1 B, and 1 C.
- the alignment holes 5 in the same position of these chips are at least partially aligned in the stacking direction of the chips.
- the alignment hole 5 is filled with the silicon oxide film 10 .
- the alignment hole 5 can also be filled with another film which transmits a laser beam, and can also be kept unfilled. That is, the alignment hole 5 need only have a function of transmitting light used in alignment.
- a laser light source 11 is arranged below the lowermost chip 1 C.
- a laser beam 12 emitted from this laser light source 11 enters from the alignment hole 5 in the lowermost chip 1 C and is sequentially transmitted through the alignment holes 5 in the chips 1 B and 1 A.
- the transmitted laser beam 12 is sent into a photodetector 13 arranged above the alignment hole 5 in the uppermost chip 1 A and constituted by, e.g., a photomultiplier. Note that the photodetector 13 and the laser light source 11 can also be arranged below the lowermost chip 1 C and above the uppermost chip 1 A, respectively.
- the amount of the laser beam 12 fed into the photodetector 13 is a maximum when the projection area in which the photodetector 13 can be seen from the laser light source 11 through the alignment holes 5 is a maximum.
- this projection area is a common area of the alignment holes 5 , i.e., a common area 5 A of alignment holes 5 indicated by the solid line, the alternate long and short dashed line, and the broken line.
- the chips 1 A, 1 B, and 1 C can be aligned by adjusting the positional relationship between these chips so that the light amount is a maximum.
- the larger the light amount the closer the connecting portion such as the pad 7 of each chip to a desired position (where the chips are not misaligned). Therefore, as described previously, the alignment holes 5 and the pads 7 of the chips are so formed as to be vertically aligned when the chips are stacked in desired positions.
- FIGS. 3A and 3B show practical examples of planar patterns of the alignment holes 5 .
- FIG. 3A shows an example in which two alignment holes 5 are formed in positions close to the corners on a diagonal line of each chip.
- FIG. 3B shows an example in which two alignment holes 5 are formed in positions close to the corners on a diagonal line of each chip, and one alignment hole 5 in a position close to another corner of the chip. Basically, the larger the number of the alignment holes 5 the higher the alignment accuracy.
- the chips 1 A, 1 B, and 1 C are stacked. This eliminates the problem of an increase in the planar area of the device unlike in conventional multi-chip semiconductor devices in which a plurality of chips are arranged two-dimensionally.
- the chips are connected by the through plugs 4 extending through the silicon substrates 2 . Therefore, the number of chips to be stacked is not limited to two unlike in conventional multi-chip semiconductor devices in which chips are connected face to face.
- the through plug 4 has an effect of promoting heat dissipation. In this first embodiment, therefore, it is possible to realize a multi-chip semiconductor device having a small planar area, a simple structure, a small thickness, and good heat dissipation properties.
- the number of chips is three. However, four or more chips can be similarly connected when the chip structure of this embodiment is used. Also, not all of chips having the through plugs 4 need to be connected via these through plugs 4 . That is, the through plugs 4 can also be formed only for the purpose of improving the heat dissipation properties in some chips.
- the through plugs 4 are formed in all chips. However, this is not always necessary. For example, the chips 1 A and 1 C need only be connected to the chip 1 B, so it is not always necessary to form the through plugs 4 .
- the through plug 4 has the effect of encouraging heat dissipation.
- the alignment hole 5 also has this effect of promoting heat dissipation. Accordingly, in addition to the arrangements of the alignment holes explained with reference to FIGS. 3A and 3B, it is possible to promote heat dissipation in an intermediate chip by forming an alignment hole near a portion where heat is generated in the chip.
- a method of manufacturing a multi-chip semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 4A to 4 K.
- FIGS. 4A to 4 K are sectional views of a chip or a multi-chip semiconductor device in individual manufacturing steps.
- a through hole extending through a semiconductor substrate is not directly formed because a semiconductor substrate is generally thick, so it is difficult to directly form a through hole.
- a 1- ⁇ m thick SiO 2 mask pattern 22 is formed on a silicon substrate 21 .
- this mask pattern 22 is used as a mask to selectively etch the silicon substrate 21 by RIE (Reactive Ion Etching), thereby forming a plurality of 100- ⁇ m deep holes 23 in the surface of the silicon substrate 21 .
- RIE Reactive Ion Etching
- An example of the etching source is F (fluorine)-based gas.
- a 100-nm thick SiO 2 film and a 100-nm thick Si 3 N 4 film are sequentially deposited on the entire surface by CVD (Chemical Vapor Deposition), forming an SiO 2 /Si 3 N 4 stacked insulating film 24 .
- CVD Chemical Vapor Deposition
- a single-layered insulating film can also be used instead of the stacked insulating film 24 .
- a silicon oxide film 25 (optical transparent film) is formed on the entire surface by using CVD such that the film 25 overflows from the holes 23 . Consequently, the holes 23 are filled with the silicon oxide film 25 . This silicon film 25 finally remains only in alignment holes.
- CMP Chemical Mechanical Polishing
- a 1- ⁇ m thick resist mask pattern 26 is formed on the stacked insulating film 24 and used as a mask to selectively remove the silicon oxide film 25 buried in the hole 23 for a connecting plug. Consequently, the silicon oxide film 25 is selectively left behind only in the hole 23 for an alignment hole on the right side of FIG. 4E.
- an amorphous silicon film 27 which is used as the material of a through plug and into which an impurity such as B (boron) is doped is formed on the entire surface such that the film 27 overflows from the holes 23 . Consequently, the hole 23 for a connecting plug on the left side of FIG. 4F is filled with the amorphous silicon film 27 .
- the impurity-doped polysilicon film 27 is used as a conductive film serving as a through plug.
- an impurity-doped amorphous silicon film can also be used instead of the film 27 .
- CMP is used to polish the surface of the amorphous silicon film 27 until the surface of the silicon substrate 21 is exposed.
- the result is a structure in which the amorphous silicon film (through plug) 27 is buried in the hole 23 for a connecting plug.
- a multilevel interconnecting layer including a multilevel metal interconnection 28 and a light-transmitting insulating interlayer 29 is formed on the surface of the substrate in which the holes 23 are formed.
- An example of the insulating interlayer 29 is an SiO 2 film.
- a trench is formed in the surface of the insulating interlayer 29 on the multilevel metal interconnection 28 , and a metal pad 30 is formed in this trench.
- the semiconductor substrate 21 is cut out into a chip or chips from the wafer.
- the surface (lower surface) of the silicon substrate 21 away from the surface in which the holes 23 are formed is polished by using CMP until the stacked insulating film 24 on the bottoms of the holes 23 is exposed.
- the silicon substrate 21 is preferably polished after the silicon substrate 21 is cut out from the wafer. This is so because a wafer is generally large and has small mechanical strength and hence is difficult to evenly polish.
- the lower surface of the silicon substrate 21 is selectively etched. This etching amount is larger than the film thickness of the stacked insulating film 24 on the bottoms of the holes 23 . Thereafter, as shown in FIG. 41, a silicon oxide film (SiO 2 film) 31 is formed on the entire lower surface.
- CMP is used to polish the silicon oxide film 31 and the stacked insulating film 24 until the silicon oxide film 25 and the amorphous silicon film (through plug) 27 are exposed.
- the result is a structure in which a connecting plug is formed by filling the through hole with the through plug 27 via the stacked insulating film 24 , an alignment hole is formed by filling the through hole with the silicon oxide film 25 via the stacked insulating film 24 , and the silicon region on the lower surface of the silicon substrate 21 is covered with the silicon oxide film 31 . Note that it is not always necessary to cover the silicon region on the lower surface with the silicon oxide film 31 .
- a laser light source 11 below the chip 21 C irradiates a laser beam 12 onto the lower surface of the alignment hole 25 in the chip 21 C.
- This laser beam 12 sequentially passes through the alignment holes in the chips 21 C, 21 B, and 21 A and is output from the surface of the chip 21 A.
- This output laser beam is detected by a laser detector 13 mounted above the chip 21 A.
- the chips 21 A, 21 B, and 21 C are so aligned that the amount of the laser beam 12 to be detected by the detector 13 is a maximum. Consequently, the connecting portions (the through plugs 27 , the pads 30 , and the solder bumps 32 ) of these chips are aligned. In this manner the chips 21 A to 21 C are easily aligned with high accuracy.
- the chip is heated by a heater (not shown) to a temperature at which the solder bumps 32 melt, and the chips are crimped by a crimping apparatus (not shown). Consequently, the chips are electrically connected to complete the multi-chip semiconductor device.
- multi-chip semiconductor device chips having light-transmitting portions for alignment are manufactured, and a multi-chip semiconductor device is manufactured by high-accuracy alignment using these light-transmitting portions.
- a method of manufacturing a multi-chip semiconductor device according to the third embodiment of the present invention will be described below with reference to FIGS. 5A to 5 G.
- FIGS. 5A to 5 G are sectional views showing a chip or a multi-chip semiconductor device in individual manufacturing steps. Note that the same reference numerals as in the second embodiment (FIGS. 4A to 4 K) denote the same parts in FIGS. 5A to 5 G, and a detailed description thereof will be omitted.
- CMP is used to polish the surface of the amorphous silicon film 27 until the surface of a silicon substrate 21 is exposed.
- the result is a structure in which the amorphous silicon film (through plug) 27 is buried in the hole 23 for a connecting plug on the left side of FIG. 5B.
- the amorphous silicon film 27 is also buried in the hole 23 for an alignment hole on the right side of FIG. 5B, this film 27 is finally removed.
- a multilevel interconnecting layer including a multilevel metal interconnection 28 and a light-transmitting insulating interlayer 29 is formed on the surface of the substrate in which the holes 23 are formed.
- An example of the insulating interlayer 29 is an SiO 2 film.
- the insulating interlayer 29 between layers of the multilevel metal interconnection 28 is omitted in FIG. 5C. Note also that element isolation and element formation must be performed before the multilevel interconnecting layer is formed.
- the multilevel metal interconnection 28 is formed so as not to prevent the detection of light transmitted through an alignment hole. However, this is unnecessary if a transparent metal material such as ITO is used as the material of the multilevel metal interconnection 28 .
- a trench is formed in the surface of the insulating interlayer 29 on the multilevel metal interconnection 28 , and a metal pad 30 is formed in this trench.
- a resist mask pattern 33 is formed on the insulating interlayer 29 and used as a mask to sequentially selectively etch away the insulating interlayer 29 on and near the hole 23 as an alignment hole and the amorphous silicon film 27 in the hole 23 as an alignment hole.
- anisotropic etching dry etching
- wet etching wet etching
- the mask pattern 33 is peeled.
- the semiconductor substrate 21 is cut out into a chip or chips from the wafer.
- the surface (lower surface) of the silicon substrate 21 away from the surface in which the holes 23 are formed is polished by using CMP until a stacked insulating film 24 on the bottoms of the holes 23 is exposed.
- the lower surface of the silicon substrate 21 is selectively etched. This etching amount is larger than the film thickness of the stacked insulating film 24 on the bottoms of the holes 23 . Thereafter, as shown in FIG. 5E, a silicon oxide film (SiO 2 film) 31 is formed on the entire lower surface.
- CMP is used to polish the silicon oxide film 31 and the stacked insulating film 24 until the amorphous silicon film (through plug) 27 is exposed.
- the result is a structure in which a connecting plug is formed by filling the through hole with the through plug 27 via the stacked insulating film 24 , an alignment hole is formed by making the through hole hollow, and the silicon region on the lower surface of the silicon substrate 21 is covered with the silicon oxide film 31 . Note that it is not always necessary to cover the silicon region on the lower surface with the silicon oxide film 31 .
- a laser light source 11 underneath the chip 34 C irradiates a laser beam 12 into the alignment hole in the chip 34 C.
- This laser beam 12 sequentially passes through the alignment holes in the chips 34 C, 34 B, and 34 A and is output from the surface of the chip 34 A.
- This output laser beam is detected by a laser detector 13 mounted above the chip 34 A.
- the chips 34 A, 34 B, and 34 C are so aligned that the amount of the laser beam 12 to be detected by the detector 13 is a maximum, thereby aligning the connecting portions of these chips. In this manner the chips 34 A to 34 C can be easily aligned with high accuracy.
- the chip is heated by a heater (not shown) to a temperature at which the solder bumps 32 are melted, and the chips are crimped by a crimping apparatus (not shown). Consequently, the chips are electrically connected to complete the multi-chip semiconductor device.
- multi-chip semiconductor device chips having hollow portions for alignment are manufactured, and a multi-chip semiconductor device is manufactured by performing high-accuracy alignment by using these hollow portions.
- the hollow portions for alignment are formed in this third embodiment, and these hollow portions have an effect of encouraging heat dissipation. Accordingly, as in the first embodiment described earlier, in addition to the arrangements of the alignment holes explained with reference to FIGS. 3A and 3B, it is possible to promote heat dissipation in an intermediate chip by forming an alignment hole near a portion where heat is generated in the chip.
- FIG. 6 is a view showing the apparatus for manufacturing the multi-chip semiconductor device according to this fourth embodiment.
- FIG. 7 is a flow chart showing a process of manufacturing the multi-chip semiconductor device by using this manufacturing apparatus.
- FIGS. 8A and 8B are views for explaining an effect when a stage of the manufacturing apparatus is moved at an elevation angle.
- the manufacturing apparatus aligns and electrically connects chips manufactured by the manufacturing steps explained in the second or third embodiment.
- reference numerals 40 A, 40 B, and 40 C denote stages on which chips 41 A, 41 B, and 41 C, respectively, are placed, and these stages are stacked.
- the stages 40 A, 40 B, and 40 C have chip clamping mechanisms 42 A, 42 B, and 42 C, respectively.
- the chip clamping mechanisms 42 A, 42 B, and 42 C clamp the chips 41 A, 41 B, and 41 C, respectively, by two upper and lower clamping members. Consequently, each chip is placed on the lower clamping member and held between the upper and lower clamping members.
- the chip clamping mechanisms 42 A to 42 C are placed in positions at which they do not collide with each other even during the chip connecting operation in which the chips are moved closest to each other. That is, the chip clamping mechanisms 42 A to 42 C are arranged in different positions in a direction perpendicular to the page so that they do not overlap each other when viewed from above.
- the chip clamping mechanisms 42 A to 42 C are arranged so as not to cover alignment holes 43 and 44 and connecting plugs (not shown) of the chips 40 A to 40 C. That is, the chip clamping mechanisms 42 A to 42 C have through holes in regions corresponding to the alignment holes 43 and 44 and the connecting plugs. Consequently, it is possible to transmit a laser beam through all of the alignment holes 43 and 44 and connect the chips.
- the through holes in regions corresponding to the alignment holes 43 and 44 can also be filled with a film which transmits light. That is, the chip clamping mechanisms 42 A to 42 C can overlap the alignment holes provided that the overlapping portions are made of a material which transmits light.
- the stages 40 A to 40 C can be linearly moved in two directions (X- and Y-axis directions) parallel to planes in which the chips 41 A to 41 C are set and perpendicular to each other, linearly moved in a direction (Z-axis direction) perpendicular to the setting planes, and rotated about an axis parallel to the Z-axis direction by a stage position coarse adjustment unit (not shown).
- a stage position coarse adjustment unit (not shown).
- An example of a driving mechanism in the stage position coarse adjustment unit is a stage driving mechanism in a step apparatus.
- stages 40 A to 40 C can be linearly moved and rotated with respect to the three axes described above by a stage position fine adjustment unit (not shown). In this way the positional relationship between the stages 40 A to 40 C can be finely adjusted.
- a stage driving mechanism in a step apparatus is an example of a driving mechanism in the stage position fine adjustment unit.
- a laser light source 45 is arranged below the stage 40 A, and a photodetector 46 above the stage 40 C.
- the laser light source 45 and the photodetector 46 are aligned along the optical axis of a laser beam and can be linearly moved in the X- and Y-axis directions perpendicular to each other in the plane perpendicular to the optical axis.
- the laser beam from the laser light source 45 be not absorbed by a material burying the alignment holes 43 and 44 .
- a material that does not absorb the laser beam is used as the material for burying the alignment holes 43 and 44 .
- the alignment holes 43 and 44 are filled with SiO 2 having several absorption bands in the infrared region with a wavelength of 9 ⁇ m or more, it is preferable to use an He:Ne laser (wavelength 1.15 ⁇ m) or an Ar laser (wavelength 0.51 ⁇ m) having another wavelength.
- the alignment holes 43 and 44 are left unfilled, it is only necessary to use a wavelength which is not largely absorbed by the atmosphere (e.g., the air) in the apparatus.
- the photodetector 46 is constituted by, e.g., a photomultiplier.
- the detection result from the photodetector 46 is supplied to a controller (not shown). On the basis of the detection result from the photodetector 46 , the controller controls the stage position coarse adjustment unit and the stage position fine adjustment unit described above.
- Heaters 47 capable of heating up to a temperature at which solder bumps of chips melt are arranged above the stage 40 A and below the stage 40 C. Note that lamp heaters are shown as the heaters 47 in FIG. 6, but the heaters 47 are not limited to lamp heaters.
- a heat-insulating material e.g., porous alumina
- an optical mechanism which condenses radiated light from a lamp heater onto a chip, so that only chips can be heated.
- both of the two means are used.
- an RF heating apparatus which selectively heats solder bumps can be used. In short, it is only necessary to heat to a temperature at which solder bumps melt without any misalignment.
- the manufacturing apparatus of this fourth embodiment uses one alignment mechanism (a pair of laser light source 45 and photodetector 46 ). However, a plurality of alignment mechanisms can also be used. If this is the case, the alignment operation time is shortened although the construction is more or less complicated.
- a method of manufacturing a multi-chip semiconductor device by aligning and electrically connecting the chips 41 A to 41 C by using the manufacturing apparatus with the above arrangement will be described below with reference to FIG. 7.
- step S 1 the chips 41 A, 41 B, and 41 C are set and held by the stages 40 A, 40 B, and 40 C, respectively. Solder bumps necessary for connection are previously formed on pads of the chips 41 B and 41 C. Subsequently, the chips 41 A to 41 C are aligned following the procedure explained below (step S 2 ).
- the stage position coarse adjustment unit coarsely moves the stage 40 C linearly in the X- and Y-axis directions. That is, the stage 40 C is set in a position where the amount of the laser beam detected by the photodetector 46 is a maximum.
- the stage position fine adjustment unit finely moves the stage 40 C linearly in the X- and Y-axis directions.
- the stage 40 C is set in a position where the amount of the laser beam detected by the photodetector 46 is a maximum.
- the stage position coarse adjustment unit coarsely moves the stages 40 A and 40 B linearly in the X- and Y-axis directions. That is, the stages 40 A and 40 B are set in positions where the amount of the laser beam detected by the photodetector 46 is a maximum.
- the stage position fine adjustment unit finely moves the stages 40 A and 40 B linearly in the X- and Y-axis directions.
- the stages 40 A and 40 B are set in positions where the amount of the laser beam detected by the photodetector 46 is a maximum.
- the stage position coarse adjustment unit coarsely rotates the stages 40 A and 40 B about an axis parallel to the Z-axis direction. That is, the stages 40 A and 40 B are set in positions where the amount of the laser beam detected by the photodetector 46 is a maximum.
- stage position fine adjustment unit finely rotates the stages 40 A and 40 B about the axis parallel to the Z-axis direction.
- the stages 40 A and 40 B are set in positions where the amount of the laser beam detected by the photodetector 46 is a maximum. In this manner the alignment of the chips 41 A to 41 C is completed.
- the chips 41 A to 41 C are electrically connected by heating and crimping (steps S 3 and S 4 ). That is, the heaters 47 heat the chips 41 A to 41 C to melt the solder bumps.
- the stage position fine adjustment unit linearly moves the stages 40 A to 40 C in the Z-axis direction to crimp the chips. Consequently, the chips 41 A to 41 C are electrically connected. If necessary, the electrical connection can also be performed by the stage position coarse adjustment unit or by both the stage position fine adjustment unit and the stage position coarse adjustment unit.
- alignment is performed by linearly moving and rotating the stages.
- elevation-angle movement can also be performed in addition to the movements in these directions.
- the upper surface of the chip 41 C has a tilt as shown in FIG. 8A, it is effective to move the chip 41 C at an elevation angle so that the upper surface of the chip 41 C is parallel to the lower surface of the chip 41 B. Accordingly, when the chip 41 C is moved as shown in FIG. 8B, alignment and connection can be performed in the same manner as when the upper surface has no tilt.
- high-accuracy alignment can be performed by the use of multi-chip semiconductor device chips having light-transmitting portions (hollow portions) for alignment.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A plurality of chips each having two or more alignment holes for transmitting a laser beam are stacked. The laser beam is irradiated onto the uppermost or lowermost one of the stacked chips. A photodetector detects the laser beam output from the stacked chips through the alignment holes in these chips. The positions of the chips are so controlled that the amount of the light detected by this photodetector is a maximum.
Description
- The present invention relates to a multi-chip semiconductor device and a chip to be applied to this device and, more particularly, to a multi-chip semiconductor device effective to improve alignment and a chip to be applied to this device.
- This application is based on Japanese Patent Application No. 9-109130, filed on Apr. 25, 1997, the content of which is incorporated herein by reference.
- Recently, a very large scale integrated circuit (chip) manufactured by integrally forming a number of elements such as transistors and resistors on a semiconductor substrate is often used in an important portion of a computer or a communication apparatus. The performance of this chip is closely related to the performance of a whole apparatus.
- On the other hand, a so-called multi-chip semiconductor module has been proposed in which a plurality of chips are stacked to improve the performance of a whole apparatus. Recently, the assignee of the present application has proposed a multi-chip semiconductor device chip, three or more of which can be connected in a small space by a simple method, and a method of forming the chip (U.S. patent application Ser. No. 08/980,873 filed on Dec. 1, 1997).
- One characteristic feature of this chip is that a through hole is formed in a semiconductor device on which elements are integrally formed and a connecting plug made of a conductive material is formed in this through hole. Chips are electrically connected via these connecting plugs to accomplish a multi-chip semiconductor device including a plurality of stacked chips.
- In this multi-chip semiconductor device, pads made of a conductive material are used to connect connecting plugs of different chips or to electrically connect connecting plugs of different chips and a multilevel interconnecting layer. This pad has a solder bump.
- When misalignment between chips is taken into consideration, it is necessary to form a pad having a relatively large area. This is so because the solder bump described above and a connecting plug to be connected to this solder bump are not connected in some cases due to misalignment between the chips. However, forming such pads having a large area is contrary to demanding improved performance by forming pads as many as possible in a chip in order to reduce the parasitic resistance in the interconnecting layer.
- It is an object of the present invention to provide a multi-chip semiconductor device by which high-accuracy alignment is possible and a chip to be applied to this device.
- It is a second object of the present invention to provide a method and an apparatus for manufacturing the multi-chip semiconductor device.
- It is a third object of the present invention to provide a method of manufacturing a chip to be applied to the multi-chip semiconductor device, and a method of aligning the chips.
- According to an aspect of the present invention, there is provided a chip applied to a multi-chip semiconductor device, comprising: a semiconductor substrate on which at least one element is formed; a connecting portion formed in the semiconductor substrate and electrically connected to another chip; and two or more light-transmitting portions formed in the semiconductor substrate.
- According to the second aspect of the present invention, there is provided a method of manufacturing a chip applied to a multi-chip semiconductor device, comprising the steps of: forming a plurality of holes having a desired depth in a surface of a semiconductor substrate; forming an insulating film on side walls and bottoms of the holes; burying a conductive material in the holes except for at least two holes; and exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed.
- According to the third aspect of the present invention, there is provided a method of aligning a plurality of stacked chips each having a light-transmitting portion, comprising the steps of: irradiating light onto one of uppermost and lowermost chips of the stacked chips; detecting light output from the stacked chips through the light-transmitting portions of the chips; and aligning the chips in accordance with the detected light.
- According to the fourth aspect of the present invention, there is provided a multi-chip semiconductor device comprising: a plurality of stacked chips; and a plurality of conducting portions each formed between the chips, wherein each of the chips comprises: a semiconductor substrate on which at least one element is formed; a connecting portion formed to extend through the semiconductor substrate and electrically connected to an adjacent chip via the conducting portions arranged on both surfaces of the semiconductor substrate; and two or more light-transmitting portions formed in the semiconductor substrate.
- According to the fifth aspect of the present invention, there is provided a method of manufacturing a multi-chip semiconductor device, comprising the steps of: manufacturing a plurality of semiconductor substrates; stacking the semiconductor substrates; arranging a plurality of conducting portions between the semiconductor substrates; aligning the semiconductor substrates; and electrically connecting the semiconductor substrates, wherein the step of manufacturing the semiconductor substrates comprises the substeps of: forming a plurality of holes having a desired depth in a surface of a semiconductor substrate; forming an insulating film on side walls and bottoms of the holes; burying a conductive material in the holes except for two holes; and exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed, and the step of performing alignment comprises the substeps of: irradiating light onto one of uppermost and lowermost semiconductor substrates of the stacked semiconductor substrates; detecting light output from the stacked semiconductor substrates through holes except for the holes formed in the semiconductor substrates and filled with the conductive material; and aligning the semiconductor substrates in accordance with the detected light.
- According to the sixth aspect of the present invention, there is provided an apparatus for manufacturing a multi-chip semiconductor device, comprising: a holding mechanism for stacking and holding a plurality of semiconductor substrates each having a light-transmitting portion in a predetermined position; a coarse adjustment unit for coarsely moving each of the semiconductor substrates; a fine adjustment unit for finely moving each of the semiconductor substrates; a light source for irradiating light onto one of uppermost and lowermost semiconductor substrates of the semiconductor substrates; a light-receiving unit for detecting light output from the stacked semiconductor substrates through the light-transmitting portions formed in the semiconductor substrates; and a controller for controlling the coarse adjustment unit and the fine adjustment unit in accordance with an amount of the light detected by the light-receiving unit, thereby aligning the semiconductor substrates.
- In the present invention as described above, high-accuracy alignment can be performed by using multi-chip semiconductor device chips having light-transmitting portions (hollow portions) for alignment.
- This obviates the need for forming pads having a relatively large area by taking account of misalignment, unlike in conventional structures. Consequently, it is possible to form a large number of pads in a chip and reduce the parasitic resistance in the interconnecting layer.
- Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinbefore.
- The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
- FIG. 1 is a sectional view showing a multi-chip semiconductor device according to the first embodiment of the present invention;
- FIG. 2 is a view for explaining a method of aligning chips in the first embodiment;
- FIGS. 3A and 3B are views showing planar patterns of alignment holes applicable to the multi-chip semiconductor device shown in FIG. 1;
- FIGS. 4A to4K are sectional views for explaining a method of manufacturing a multi-chip-semiconductor device according to the second embodiment of the present invention;
- FIGS. 5A to5G are sectional views for explaining a method of manufacturing a multi-chip semiconductor device according to the third embodiment of the present invention;
- FIG. 6 is a view for explaining an apparatus for manufacturing a multi-chip semiconductor device according to the fourth embodiment of the present invention;
- FIG. 7 is a flow chart for explaining a method of manufacturing a multi-chip semiconductor device by using the manufacturing apparatus shown in FIG. 6; and
- FIGS. 8A and 8B are views for explaining an effect when a stage is moved at an elevation angle in the manufacturing apparatus shown in FIG. 6.
- Embodiments of the present invention will be described below with reference to the accompanying drawings.
- The first embodiment of the present invention will be described with reference to FIGS.1 to 3B.
- FIG. 1 is a sectional view showing a multi-chip semiconductor device according to this first embodiment. FIG. 2 is a view for explaining a method of aligning chips in this multi-chip semiconductor device. FIGS. 3A and 3B show examples of planar patterns of alignment holes.
- In the multi-chip semiconductor device of this first embodiment, three
chips 1A, 1B, and 1C (chips for a multi-chip semiconductor device) are stacked. - Each of the
chips 1A, 1B, and 1C roughly comprises asilicon substrate 2 on which elements are integrally formed, amultilevel interconnecting layer 3 for connecting these elements in a desired manner, a plurality of conductive through plugs 4 (conductive plugs) extending through thesilicon substrate 2 to electrically connect the chips, and an alignment hole 5 (light-transmitting portion) for transmitting light used in aligning the chips in the step of connecting the chips. - These
chips 1A, 1B, and 1C have the same size (the area and the shape) and need to be stacked without any deviation. Although only onealignment hole 5 is shown in FIG. 1 for simplicity, at least twoalignment holes 5 must be formed in each chip. Thesealignment holes 5 are formed in the same position of thechips 1A, 1B, and 1C. Note that thechips 1A, 1B, and 1C are not always required to have the same shape and the same area. If this is the case, however, thealignment holes 5 must be so formed in these chips that these alignment holes are vertically aligned with no difference when the chips are stacked in a desired manner. - An insulating interlayer constituting the multilevel interconnecting
layer 3 is made of a material (e.g., SiO2) which transmits light. Aninsulating film 6 is formed between the throughplug 4 and thesilicon substrate 2, and thisinsulating film 6 and the throughplug 4 constitute a connecting plug. -
Pads 7 are formed in the multilevel interconnectinglayer 3 of each of thechips 1A, 1B, and 1C. Also, a silicon region of thesilicon substrate 2 away from thepad 7, i.e., a silicon region except for the throughplugs 4 and thealignment hole 5 in each of thechips 1A, 1B, and 1C is covered with aninsulating film 8. - The through
plugs 4 of the chip 1A are electrically connected viasolder bumps 9 to thepads 7 formed in the multilevel interconnectinglayer 3 of the chip 1B. Consequently, the chips 1A and 1B are electrically connected. Note that bumps other than thesolder bumps 9 can also be used. - Similarly, the through
plugs 4 of the chip 1B are electrically connected viasolder bumps 9 to thepads 7 formed in themultilevel interconnecting layer 3 of thechip 1C. Consequently, thechips 1B and 1C are electrically connected. In this way thechips 1A, 1B, and 1C are electrically connected. - A material which transmits a laser beam, e.g., a silicon oxide film (SiO2 film) 10 is buried in the
alignment hole 5 of each of thechips 1A, 1B, and 1C. The alignment holes 5 in the same position of these chips are at least partially aligned in the stacking direction of the chips. - In this embodiment, the
alignment hole 5 is filled with thesilicon oxide film 10. However, thealignment hole 5 can also be filled with another film which transmits a laser beam, and can also be kept unfilled. That is, thealignment hole 5 need only have a function of transmitting light used in alignment. - With these
alignment holes 5, alignment as will be described below can be executed. - A
laser light source 11 is arranged below thelowermost chip 1C. Alaser beam 12 emitted from thislaser light source 11 enters from thealignment hole 5 in thelowermost chip 1C and is sequentially transmitted through the alignment holes 5 in the chips 1B and 1A. The transmittedlaser beam 12 is sent into aphotodetector 13 arranged above thealignment hole 5 in the uppermost chip 1A and constituted by, e.g., a photomultiplier. Note that thephotodetector 13 and thelaser light source 11 can also be arranged below thelowermost chip 1C and above the uppermost chip 1A, respectively. - As shown in FIG. 2, the amount of the
laser beam 12 fed into thephotodetector 13 is a maximum when the projection area in which thephotodetector 13 can be seen from thelaser light source 11 through the alignment holes 5 is a maximum. Referring to FIG. 2, this projection area is a common area of the alignment holes 5, i.e., acommon area 5A ofalignment holes 5 indicated by the solid line, the alternate long and short dashed line, and the broken line. - Accordingly, the
chips 1A, 1B, and 1C can be aligned by adjusting the positional relationship between these chips so that the light amount is a maximum. In this adjustment, the larger the light amount the closer the connecting portion such as thepad 7 of each chip to a desired position (where the chips are not misaligned). Therefore, as described previously, the alignment holes 5 and thepads 7 of the chips are so formed as to be vertically aligned when the chips are stacked in desired positions. - Furthermore, a change in the projection area is sensitively reflected on the amount of the
laser beam 12 incident on thephotodetector 13. Consequently, the chips can be aligned with high accuracy. - This eliminates the need for forming pads having a relatively large area by taking misalignment into consideration, unlike in conventional structures. Therefore, it is possible to form a large number of pads in a chip and reduce the parasitic resistance in the interconnecting layer.
- FIGS. 3A and 3B show practical examples of planar patterns of the alignment holes5.
- FIG. 3A shows an example in which two
alignment holes 5 are formed in positions close to the corners on a diagonal line of each chip. With this arrangement of the alignment holes 5, when a step of electrically connecting the chips is performed, the chips can be aligned with high accuracy with minimum necessary numbers ofalignment holes 5 and an alignment mechanism (a pair of a laser light source and a photodetector). - FIG. 3B shows an example in which two
alignment holes 5 are formed in positions close to the corners on a diagonal line of each chip, and onealignment hole 5 in a position close to another corner of the chip. Basically, the larger the number of the alignment holes 5 the higher the alignment accuracy. - In the first embodiment described above, the
chips 1A, 1B, and 1C are stacked. This eliminates the problem of an increase in the planar area of the device unlike in conventional multi-chip semiconductor devices in which a plurality of chips are arranged two-dimensionally. - Also, in this first embodiment the chips are connected by the through
plugs 4 extending through thesilicon substrates 2. Therefore, the number of chips to be stacked is not limited to two unlike in conventional multi-chip semiconductor devices in which chips are connected face to face. - Furthermore, no stacked plate is used to connect chips. Therefore, unlike in conventional multi-chip semiconductor devices in which chips are connected by a stacked plate, the structure is not complicated, and the thickness of the whole device is not increased.
- Additionally, the through
plug 4 has an effect of promoting heat dissipation. In this first embodiment, therefore, it is possible to realize a multi-chip semiconductor device having a small planar area, a simple structure, a small thickness, and good heat dissipation properties. - In the above first embodiment, the number of chips is three. However, four or more chips can be similarly connected when the chip structure of this embodiment is used. Also, not all of chips having the through
plugs 4 need to be connected via these throughplugs 4. That is, the throughplugs 4 can also be formed only for the purpose of improving the heat dissipation properties in some chips. - In the first embodiment, the through
plugs 4 are formed in all chips. However, this is not always necessary. For example, thechips 1A and 1C need only be connected to the chip 1B, so it is not always necessary to form the through plugs 4. - As described above, the through
plug 4 has the effect of encouraging heat dissipation. Thealignment hole 5 also has this effect of promoting heat dissipation. Accordingly, in addition to the arrangements of the alignment holes explained with reference to FIGS. 3A and 3B, it is possible to promote heat dissipation in an intermediate chip by forming an alignment hole near a portion where heat is generated in the chip. - A method of manufacturing a multi-chip semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 4A to4K.
- FIGS. 4A to4K are sectional views of a chip or a multi-chip semiconductor device in individual manufacturing steps.
- In this second embodiment, a through hole extending through a semiconductor substrate is not directly formed because a semiconductor substrate is generally thick, so it is difficult to directly form a through hole.
- First, a 1-μm thick SiO2 mask pattern 22 is formed on a
silicon substrate 21. Next, as shown in FIG. 4A, thismask pattern 22 is used as a mask to selectively etch thesilicon substrate 21 by RIE (Reactive Ion Etching), thereby forming a plurality of 100-μmdeep holes 23 in the surface of thesilicon substrate 21. An example of the etching source is F (fluorine)-based gas. Some of theholes 23 are finally used as through holes for connecting plugs, and the rest are used as through holes for alignment holes. - As shown in FIG. 4B, after the
mask pattern 22 is removed, a 100-nm thick SiO2 film and a 100-nm thick Si3N4 film are sequentially deposited on the entire surface by CVD (Chemical Vapor Deposition), forming an SiO2/Si3N4 stacked insulatingfilm 24. Note that a single-layered insulating film can also be used instead of the stacked insulatingfilm 24. - Next, as shown in FIG. 4C, a silicon oxide film25 (optical transparent film) is formed on the entire surface by using CVD such that the
film 25 overflows from theholes 23. Consequently, theholes 23 are filled with thesilicon oxide film 25. Thissilicon film 25 finally remains only in alignment holes. - As shown in FIG. 4D, CMP (Chemical Mechanical Polishing) is used to polish the surface of the
silicon oxide film 25 until the surface of the stacked insulatingfilm 24 is exposed. The result is a structure in which thesilicon oxide film 25 is buried in theholes 23. - Next, as shown in FIG. 4E, a 1-μm thick resist
mask pattern 26 is formed on the stacked insulatingfilm 24 and used as a mask to selectively remove thesilicon oxide film 25 buried in thehole 23 for a connecting plug. Consequently, thesilicon oxide film 25 is selectively left behind only in thehole 23 for an alignment hole on the right side of FIG. 4E. - As shown in FIG. 4F, after the
mask pattern 26 is peeled, anamorphous silicon film 27 which is used as the material of a through plug and into which an impurity such as B (boron) is doped is formed on the entire surface such that thefilm 27 overflows from theholes 23. Consequently, thehole 23 for a connecting plug on the left side of FIG. 4F is filled with theamorphous silicon film 27. - In this embodiment, the impurity-doped
polysilicon film 27 is used as a conductive film serving as a through plug. However, an impurity-doped amorphous silicon film can also be used instead of thefilm 27. It is also possible to use a metal film made of, e.g., Al, Cu, W, Mo, Ni, or Ti, or a metal silicide film of any of these metals. - Next, as shown in FIG. 4G, CMP is used to polish the surface of the
amorphous silicon film 27 until the surface of thesilicon substrate 21 is exposed. The result is a structure in which the amorphous silicon film (through plug) 27 is buried in thehole 23 for a connecting plug. - As shown in FIG. 4H, a multilevel interconnecting layer including a
multilevel metal interconnection 28 and a light-transmitting insulatinginterlayer 29 is formed on the surface of the substrate in which theholes 23 are formed. An example of the insulatinginterlayer 29 is an SiO2 film. - Note that the insulating
interlayer 29 between layers of themultilevel metal interconnection 28 is omitted in FIG. 4H. Note also that element isolation and element formation must be performed before the multilevel interconnecting layer is formed. - It is also necessary that only the insulating
interlayer 29 between the layers of the interconnection as the component of the multilevel interconnecting layer be formed and themultilevel metal interconnection 28 be not present in a region (alignment region) immediately above thesilicon oxide film 25. This is to prevent themultilevel metal interconnection 28 from disturbing the detection of light transmitted through an alignment hole. However, this is unnecessary if a transparent metal material such as ITO is used as the material of themultilevel metal interconnection 28. - Next, as shown in FIG. 4H, a trench is formed in the surface of the insulating
interlayer 29 on themultilevel metal interconnection 28, and ametal pad 30 is formed in this trench. At this point, thesemiconductor substrate 21 is cut out into a chip or chips from the wafer. - As shown in FIG. 4I, the surface (lower surface) of the
silicon substrate 21 away from the surface in which theholes 23 are formed is polished by using CMP until the stacked insulatingfilm 24 on the bottoms of theholes 23 is exposed. - As in this second embodiment, the
silicon substrate 21 is preferably polished after thesilicon substrate 21 is cut out from the wafer. This is so because a wafer is generally large and has small mechanical strength and hence is difficult to evenly polish. - Next, as is still shown in FIG. 4I, the lower surface of the
silicon substrate 21 is selectively etched. This etching amount is larger than the film thickness of the stacked insulatingfilm 24 on the bottoms of theholes 23. Thereafter, as shown in FIG. 41, a silicon oxide film (SiO2 film) 31 is formed on the entire lower surface. - As shown in FIG. 4J, CMP is used to polish the
silicon oxide film 31 and the stacked insulatingfilm 24 until thesilicon oxide film 25 and the amorphous silicon film (through plug) 27 are exposed. - The result is a structure in which a connecting plug is formed by filling the through hole with the through
plug 27 via the stacked insulatingfilm 24, an alignment hole is formed by filling the through hole with thesilicon oxide film 25 via the stacked insulatingfilm 24, and the silicon region on the lower surface of thesilicon substrate 21 is covered with thesilicon oxide film 31. Note that it is not always necessary to cover the silicon region on the lower surface with thesilicon oxide film 31. - In this second embodiment as described above, even if the
silicon substrate 21 is thick (the substrate is usually thick), no deep through holes need to be formed. Consequently, it is readily possible to form a chip (for a multi-chip semiconductor device) having a connecting plug formed by filling a through hole with the throughplug 27 and an alignment hole formed by filling a through hole with the silicon oxide film 25 (transparent film). - Thereafter, as shown in FIG. 4K, three
chips 21A to 21C formed by the same steps as above are vertically arranged. Before this step, solder bumps 32 are formed on thepads 30 of thechips 21B and 21C. The alignment holes in these chips are at least partially aligned in the stacking direction of the chips. - Next, as is still shown in FIG. 4K, a
laser light source 11 below thechip 21C irradiates alaser beam 12 onto the lower surface of thealignment hole 25 in thechip 21C. Thislaser beam 12 sequentially passes through the alignment holes in thechips chip 21A. This output laser beam is detected by alaser detector 13 mounted above thechip 21A. - The
chips laser beam 12 to be detected by thedetector 13 is a maximum. Consequently, the connecting portions (the through plugs 27, thepads 30, and the solder bumps 32) of these chips are aligned. In this manner thechips 21A to 21C are easily aligned with high accuracy. - When the alignment is complete, the chip is heated by a heater (not shown) to a temperature at which the solder bumps32 melt, and the chips are crimped by a crimping apparatus (not shown). Consequently, the chips are electrically connected to complete the multi-chip semiconductor device.
- In the second embodiment as described above, multi-chip semiconductor device chips having light-transmitting portions for alignment are manufactured, and a multi-chip semiconductor device is manufactured by high-accuracy alignment using these light-transmitting portions.
- This obviates the need for forming pads having a relatively large area by taking account of misalignment, unlike in conventional structures. Consequently, it is possible to form a large number of pads in a chip and reduce the parasitic resistance in the interconnecting layer.
- A method of manufacturing a multi-chip semiconductor device according to the third embodiment of the present invention will be described below with reference to FIGS. 5A to5G.
- FIGS. 5A to5G are sectional views showing a chip or a multi-chip semiconductor device in individual manufacturing steps. Note that the same reference numerals as in the second embodiment (FIGS. 4A to 4K) denote the same parts in FIGS. 5A to 5G, and a detailed description thereof will be omitted.
- In this third embodiment, a method of manufacturing a multi-chip semiconductor device characterized in that an alignment hole is hollow will be described. The heat dissipation efficiency is improved by making an alignment hole hollow. This improvement in the heat dissipation efficiency helps prevent misalignment caused by a thermal expansion coefficient difference when chips are connected by heating and crimping.
- First, steps similar to the steps shown in FIGS. 4A and 4B of the second embodiment described above are executed. Thereafter, as shown in FIG. 5A, an
amorphous silicon film 27 into which an impurity such as B (boron) is doped is formed on the entire surface so as to overflow from holes 23. Consequently, theholes 23 are filled with theamorphous silicon film 27. - Next, as shown in FIG. 5B, CMP is used to polish the surface of the
amorphous silicon film 27 until the surface of asilicon substrate 21 is exposed. The result is a structure in which the amorphous silicon film (through plug) 27 is buried in thehole 23 for a connecting plug on the left side of FIG. 5B. Although theamorphous silicon film 27 is also buried in thehole 23 for an alignment hole on the right side of FIG. 5B, thisfilm 27 is finally removed. - As shown in FIG. 5C, a multilevel interconnecting layer including a
multilevel metal interconnection 28 and a light-transmitting insulatinginterlayer 29 is formed on the surface of the substrate in which theholes 23 are formed. An example of the insulatinginterlayer 29 is an SiO2 film. - Note that the insulating
interlayer 29 between layers of themultilevel metal interconnection 28 is omitted in FIG. 5C. Note also that element isolation and element formation must be performed before the multilevel interconnecting layer is formed. - It is also necessary that only the insulating
interlayer 29 between the layers of the interconnection as the component of the multilevel interconnecting layer be formed and themultilevel metal interconnection 28 be not present in a region serving as an alignment hole. That is, themultilevel metal interconnection 28 is formed so as not to prevent the detection of light transmitted through an alignment hole. However, this is unnecessary if a transparent metal material such as ITO is used as the material of themultilevel metal interconnection 28. - Next, as shown in FIG. SC, a trench is formed in the surface of the insulating
interlayer 29 on themultilevel metal interconnection 28, and ametal pad 30 is formed in this trench. - As shown in FIG. 5D, a resist
mask pattern 33 is formed on the insulatinginterlayer 29 and used as a mask to sequentially selectively etch away the insulatinginterlayer 29 on and near thehole 23 as an alignment hole and theamorphous silicon film 27 in thehole 23 as an alignment hole. As this etching, anisotropic etching (dry etching) such as RIE is used, and wet etching can also be used. - Thereafter, the
mask pattern 33 is peeled. At this point, thesemiconductor substrate 21 is cut out into a chip or chips from the wafer. - As shown in FIG. 5E, the surface (lower surface) of the
silicon substrate 21 away from the surface in which theholes 23 are formed is polished by using CMP until a stacked insulatingfilm 24 on the bottoms of theholes 23 is exposed. - Next, as is still shown in FIG. 5E, the lower surface of the
silicon substrate 21 is selectively etched. This etching amount is larger than the film thickness of the stacked insulatingfilm 24 on the bottoms of theholes 23. Thereafter, as shown in FIG. 5E, a silicon oxide film (SiO2 film) 31 is formed on the entire lower surface. - As shown in FIG. 5F, CMP is used to polish the
silicon oxide film 31 and the stacked insulatingfilm 24 until the amorphous silicon film (through plug) 27 is exposed. - The result is a structure in which a connecting plug is formed by filling the through hole with the through
plug 27 via the stacked insulatingfilm 24, an alignment hole is formed by making the through hole hollow, and the silicon region on the lower surface of thesilicon substrate 21 is covered with thesilicon oxide film 31. Note that it is not always necessary to cover the silicon region on the lower surface with thesilicon oxide film 31. - Thereafter, three
chips 34A to 34C formed by the same steps as explained with reference to FIGS. 5A to 5F are vertically arranged (FIG. 5G). Before this step, solder bumps 32 are formed on thepads 30 of thechips 34B and 34C. The alignment holes in these chips are at least partially aligned in the stacking direction of the chips. - Next, as is still shown in FIG. 5G, a
laser light source 11 underneath the chip 34C irradiates alaser beam 12 into the alignment hole in the chip 34C. Thislaser beam 12 sequentially passes through the alignment holes in thechips chip 34A. This output laser beam is detected by alaser detector 13 mounted above thechip 34A. - The
chips laser beam 12 to be detected by thedetector 13 is a maximum, thereby aligning the connecting portions of these chips. In this manner thechips 34A to 34C can be easily aligned with high accuracy. - When the alignment is complete, the chip is heated by a heater (not shown) to a temperature at which the solder bumps32 are melted, and the chips are crimped by a crimping apparatus (not shown). Consequently, the chips are electrically connected to complete the multi-chip semiconductor device.
- In the third embodiment as described above, multi-chip semiconductor device chips having hollow portions for alignment are manufactured, and a multi-chip semiconductor device is manufactured by performing high-accuracy alignment by using these hollow portions.
- This obviates the need for forming pads having a relatively large area by taking account of misalignment, unlike in conventional structures. Consequently, it is possible to form a large number of pads in a chip and reduce the parasitic resistance in the interconnecting layer.
- Also, the hollow portions for alignment are formed in this third embodiment, and these hollow portions have an effect of encouraging heat dissipation. Accordingly, as in the first embodiment described earlier, in addition to the arrangements of the alignment holes explained with reference to FIGS. 3A and 3B, it is possible to promote heat dissipation in an intermediate chip by forming an alignment hole near a portion where heat is generated in the chip.
- An apparatus for manufacturing a multi-chip semiconductor device according to the fourth embodiment of the present invention will be described below with reference to FIGS.6 to 8B.
- FIG. 6 is a view showing the apparatus for manufacturing the multi-chip semiconductor device according to this fourth embodiment. FIG. 7 is a flow chart showing a process of manufacturing the multi-chip semiconductor device by using this manufacturing apparatus. FIGS. 8A and 8B are views for explaining an effect when a stage of the manufacturing apparatus is moved at an elevation angle.
- The manufacturing apparatus aligns and electrically connects chips manufactured by the manufacturing steps explained in the second or third embodiment.
- In FIG. 6,
reference numerals 40A, 40B, and 40C denote stages on which chips 41A, 41B, and 41C, respectively, are placed, and these stages are stacked. Thestages 40A, 40B, and 40C havechip clamping mechanisms - The
chip clamping mechanisms chips - The
chip clamping mechanisms 42A to 42C are placed in positions at which they do not collide with each other even during the chip connecting operation in which the chips are moved closest to each other. That is, thechip clamping mechanisms 42A to 42C are arranged in different positions in a direction perpendicular to the page so that they do not overlap each other when viewed from above. - Furthermore, the
chip clamping mechanisms 42A to 42C are arranged so as not to cover alignment holes 43 and 44 and connecting plugs (not shown) of thechips 40A to 40C. That is, thechip clamping mechanisms 42A to 42C have through holes in regions corresponding to the alignment holes 43 and 44 and the connecting plugs. Consequently, it is possible to transmit a laser beam through all of the alignment holes 43 and 44 and connect the chips. - Note that the through holes in regions corresponding to the alignment holes43 and 44 can also be filled with a film which transmits light. That is, the
chip clamping mechanisms 42A to 42C can overlap the alignment holes provided that the overlapping portions are made of a material which transmits light. - Also, the
stages 40A to 40C can be linearly moved in two directions (X- and Y-axis directions) parallel to planes in which thechips 41A to 41C are set and perpendicular to each other, linearly moved in a direction (Z-axis direction) perpendicular to the setting planes, and rotated about an axis parallel to the Z-axis direction by a stage position coarse adjustment unit (not shown). In this manner the positional relationship between thestages 40A to 40C can be coarsely adjusted. An example of a driving mechanism in the stage position coarse adjustment unit is a stage driving mechanism in a step apparatus. - Additionally, the
stages 40A to 40C can be linearly moved and rotated with respect to the three axes described above by a stage position fine adjustment unit (not shown). In this way the positional relationship between thestages 40A to 40C can be finely adjusted. A stage driving mechanism in a step apparatus is an example of a driving mechanism in the stage position fine adjustment unit. - A
laser light source 45 is arranged below thestage 40A, and aphotodetector 46 above the stage 40C. Thelaser light source 45 and thephotodetector 46 are aligned along the optical axis of a laser beam and can be linearly moved in the X- and Y-axis directions perpendicular to each other in the plane perpendicular to the optical axis. - It is necessary that the laser beam from the
laser light source 45 be not absorbed by a material burying the alignment holes 43 and 44. In other words, a material that does not absorb the laser beam is used as the material for burying the alignment holes 43 and 44. - For example, when the alignment holes43 and 44 are filled with SiO2 having several absorption bands in the infrared region with a wavelength of 9 μm or more, it is preferable to use an He:Ne laser (wavelength 1.15 μm) or an Ar laser (wavelength 0.51 μm) having another wavelength. On the other hand, if the alignment holes 43 and 44 are left unfilled, it is only necessary to use a wavelength which is not largely absorbed by the atmosphere (e.g., the air) in the apparatus. The
photodetector 46 is constituted by, e.g., a photomultiplier. - The detection result from the
photodetector 46 is supplied to a controller (not shown). On the basis of the detection result from thephotodetector 46, the controller controls the stage position coarse adjustment unit and the stage position fine adjustment unit described above. -
Heaters 47 capable of heating up to a temperature at which solder bumps of chips melt are arranged above thestage 40A and below the stage 40C. Note that lamp heaters are shown as theheaters 47 in FIG. 6, but theheaters 47 are not limited to lamp heaters. - What is important is to prevent misalignment, when chip alignment is performed, caused by thermal expansion of the stages or the like resulting from the difference between the chip temperature and the chip adhesion temperature.
- To this end, for example, it is only necessary to use a heat-insulating material (e.g., porous alumina) in that portion of the stage which is brought into contact with a chip or install an optical mechanism which condenses radiated light from a lamp heater onto a chip, so that only chips can be heated. Preferably, both of the two means are used. Alternatively, an RF heating apparatus which selectively heats solder bumps can be used. In short, it is only necessary to heat to a temperature at which solder bumps melt without any misalignment.
- Note that the manufacturing apparatus of this fourth embodiment uses one alignment mechanism (a pair of
laser light source 45 and photodetector 46). However, a plurality of alignment mechanisms can also be used. If this is the case, the alignment operation time is shortened although the construction is more or less complicated. - A method of manufacturing a multi-chip semiconductor device by aligning and electrically connecting the
chips 41A to 41C by using the manufacturing apparatus with the above arrangement will be described below with reference to FIG. 7. - First, the
chips stages 40A, 40B, and 40C, respectively (step S1). Solder bumps necessary for connection are previously formed on pads of thechips chips 41A to 41C are aligned following the procedure explained below (step S2). - First, the stage position coarse adjustment unit coarsely moves the stage40C linearly in the X- and Y-axis directions. That is, the stage 40C is set in a position where the amount of the laser beam detected by the
photodetector 46 is a maximum. - Thereafter, the stage position fine adjustment unit finely moves the stage40C linearly in the X- and Y-axis directions. As in the coarse adjustment, the stage 40C is set in a position where the amount of the laser beam detected by the
photodetector 46 is a maximum. - Next, the stage position coarse adjustment unit coarsely moves the
stages 40A and 40B linearly in the X- and Y-axis directions. That is, thestages 40A and 40B are set in positions where the amount of the laser beam detected by thephotodetector 46 is a maximum. - Thereafter, the stage position fine adjustment unit finely moves the
stages 40A and 40B linearly in the X- and Y-axis directions. As in the coarse adjustment, thestages 40A and 40B are set in positions where the amount of the laser beam detected by thephotodetector 46 is a maximum. - Subsequently, the stage position coarse adjustment unit coarsely rotates the
stages 40A and 40B about an axis parallel to the Z-axis direction. That is, thestages 40A and 40B are set in positions where the amount of the laser beam detected by thephotodetector 46 is a maximum. - Finally, the stage position fine adjustment unit finely rotates the
stages 40A and 40B about the axis parallel to the Z-axis direction. As in the coarse adjustment, thestages 40A and 40B are set in positions where the amount of the laser beam detected by thephotodetector 46 is a maximum. In this manner the alignment of thechips 41A to 41C is completed. - Next, the
chips 41A to 41C are electrically connected by heating and crimping (steps S3 and S4). That is, theheaters 47 heat thechips 41A to 41C to melt the solder bumps. At the same time, the stage position fine adjustment unit linearly moves thestages 40A to 40C in the Z-axis direction to crimp the chips. Consequently, thechips 41A to 41C are electrically connected. If necessary, the electrical connection can also be performed by the stage position coarse adjustment unit or by both the stage position fine adjustment unit and the stage position coarse adjustment unit. - In this fourth embodiment, alignment is performed by linearly moving and rotating the stages. However, elevation-angle movement can also be performed in addition to the movements in these directions.
- For example, if the upper surface of the
chip 41C has a tilt as shown in FIG. 8A, it is effective to move thechip 41C at an elevation angle so that the upper surface of thechip 41C is parallel to the lower surface of thechip 41B. Accordingly, when thechip 41C is moved as shown in FIG. 8B, alignment and connection can be performed in the same manner as when the upper surface has no tilt. - In the present invention as has been described in detail above, high-accuracy alignment can be performed by the use of multi-chip semiconductor device chips having light-transmitting portions (hollow portions) for alignment.
- This obviates the need for forming pads having a relatively large area by taking account of misalignment, unlike in conventional structures. Consequently, it is possible to form a large number of pads in a chip and reduce the parasitic resistance in an interconnecting layer.
- Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalent.
Claims (19)
1. A chip applied to a multi-chip semiconductor device, comprising:
a semiconductor substrate on which at least one element is formed;
a connecting portion formed in the semiconductor substrate and electrically connected to another chip; and
two or more light-transmitting portions formed in the semiconductor substrate.
2. A chip according to claim 1 , wherein the connecting portion is so formed as to extend through the semiconductor substrate.
3. A chip according to claim 1 , wherein the light-transmitting portions are through holes extending through the semiconductor substrate.
4. A chip according to claim 3 , wherein an optical trans parent material is buried in the through holes.
5. A method of manufacturing a chip applied to a multi-chip semiconductor device, comprising the steps of:
forming a plurality of holes having a desired depth in a surface of a semiconductor substrate;
forming an insulating film on side walls and bottoms of the holes;
burying a conductive material in the holes except for at least two holes; and
exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed.
6. A method according to claim 5 , further comprising the step of:
burying an optical transparent material in holes except for the holes filled with the conductive material.
7. A method of aligning a plurality of stacked chips each having a light-transmitting portion, comprising the steps of:
irradiating light onto one of uppermost and lowermost chips of the stacked chips;
detecting light output from the stacked chips through the light-transmitting portions of the chips; and
aligning the chips in accordance with the detected light.
8. A method according to claim 7 , wherein the step of performing alignment comprises the substep of aligning the chips to maximize an amount of the light detected in the detection step.
9. A method according to claim 7 , wherein the irradiation step comprises the substep of irradiating a laser beam onto one of the uppermost and lowermost chips.
10. A multi-chip semiconductor device comprising:
a plurality of stacked chips; and
a plurality of conducting portions each formed between the chips,
wherein each of the chips comprises:
a semiconductor substrate on which at least one element is formed;
a connecting portion formed to extend through the semiconductor substrate and electrically connected to an adjacent chip via the conducting portions arranged on both surfaces of the semiconductor substrate; and
two or more light-transmitting portions formed in the semiconductor substrate.
11. A device according to claim 10 , wherein the light-transmitting portions are through holes extending through the semiconductor substrate.
12. A device according to claim 11 , wherein an optical transparent material is buried in the through holes.
13. A method of manufacturing a multi-chip semiconductor device, comprising the steps of:
manufacturing a plurality of semiconductor substrates;
stacking the semiconductor substrates;
arranging a plurality of conducting portions between the semiconductor substrates;
aligning the semiconductor substrates; and
electrically connecting the semiconductor substrates,
wherein the step of manufacturing the semiconductor substrates comprises the substeps of:
forming a plurality of holes having a desired depth in a surface of a semiconductor substrate;
forming an insulating film on side walls and bottoms of the holes;
burying a conductive material in the holes except for two holes; and
exposing the conductive material by polishing a surface of the semiconductor substrate away from the surface in which the holes are formed, and
the step of performing alignment comprises the substeps of:
irradiating light onto one of uppermost and lowermost semiconductor substrates of the stacked semiconductor substrates;
detecting light output from the stacked semiconductor substrates through holes except for the holes formed in the semiconductor substrates and filled with the conductive material; and
aligning the semiconductor substrates in accordance with the detected light.
14. A method according to claim 13 , wherein the step of manufacturing the semiconductor substrates comprises the substep of burying an optical transparent material in holes except for the holes filled with the conductive material.
15. A method according to claim 13 , wherein the step of performing alignment comprises the substep of aligning the semiconductor substrates to maximize an amount of the light detected in the detection step.
16. An apparatus for manufacturing a multi-chip semiconductor device, comprising:
a holding mechanism for stacking and holding a plurality of semiconductor substrates each having a light-transmitting portion in a predetermined position;
a coarse adjustment unit for coarsely moving each of the semiconductor substrates;
a fine adjustment unit for finely moving each of the semiconductor substrates;
a light source for irradiating light onto one of uppermost and lowermost semiconductor substrates of the semiconductor substrates;
a light-receiving unit for detecting light output from the stacked semiconductor substrates through the light-transmitting portions formed in the semiconductor substrates; and
a controller for controlling the coarse adjustment unit and the fine adjustment unit in accordance with an amount of the light detected by the light-receiving unit, thereby aligning the semiconductor substrates.
17. An apparatus according to claim 16 , wherein the coarse adjustment unit and the fine adjustment unit move the semiconductor substrates in at least one of a direction parallel to a surface of the semiconductor substrate, a direction perpendicular to the surface, a direction of rotation about an axis perpendicular to the surface, and an elevation-angle direction of the surface.
18. An apparatus according to claim 16 , wherein the controller controls the coarse adjustment unit and the fine adjustment unit so as to crimp the semiconductor substrates.
19. An apparatus according to claim 16 , further comprising a heater for heating the semiconductor substrates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/560,143 US6383837B1 (en) | 1997-04-25 | 2000-04-28 | Method of manufacturing a multi-chip semiconductor device effective to improve alignment |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10913097A JP3920399B2 (en) | 1997-04-25 | 1997-04-25 | Multi-chip semiconductor device chip alignment method, and multi-chip semiconductor device manufacturing method and manufacturing apparatus |
JP9-109130 | 1997-04-25 | ||
US98087397A | 1997-12-01 | 1997-12-01 | |
US09/064,984 US6087719A (en) | 1997-04-25 | 1998-04-23 | Chip for multi-chip semiconductor device and method of manufacturing the same |
US09/377,486 US6809421B1 (en) | 1996-12-02 | 1999-08-20 | Multichip semiconductor device, chip therefor and method of formation thereof |
US09/560,143 US6383837B1 (en) | 1997-04-25 | 2000-04-28 | Method of manufacturing a multi-chip semiconductor device effective to improve alignment |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/064,984 Division US6087719A (en) | 1997-04-25 | 1998-04-23 | Chip for multi-chip semiconductor device and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020028532A1 true US20020028532A1 (en) | 2002-03-07 |
US6383837B1 US6383837B1 (en) | 2002-05-07 |
Family
ID=14502344
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/064,984 Expired - Lifetime US6087719A (en) | 1997-04-25 | 1998-04-23 | Chip for multi-chip semiconductor device and method of manufacturing the same |
US09/560,143 Expired - Fee Related US6383837B1 (en) | 1997-04-25 | 2000-04-28 | Method of manufacturing a multi-chip semiconductor device effective to improve alignment |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/064,984 Expired - Lifetime US6087719A (en) | 1997-04-25 | 1998-04-23 | Chip for multi-chip semiconductor device and method of manufacturing the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US6087719A (en) |
JP (1) | JP3920399B2 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040080013A1 (en) * | 2002-10-28 | 2004-04-29 | Sharp Kabushiki Kaisha | Chip-stack semiconductor device and manufacturing method of the same |
US20050224921A1 (en) * | 2001-05-01 | 2005-10-13 | Subhash Gupta | Method for bonding wafers to produce stacked integrated circuits |
US20060267190A1 (en) * | 2005-05-24 | 2006-11-30 | Sharp Kabushiki Kaisha | Semiconductor device, laminated semiconductor device, and method for producing semiconductor device |
WO2007024009A1 (en) * | 2005-08-26 | 2007-03-01 | Honda Motor Co., Ltd. | Semiconductor integrated circuit device and method for manufacturing same |
US20080265430A1 (en) * | 2003-10-30 | 2008-10-30 | Masamichi Ishihara | Semiconductor Device an Process for Fabricating the Same |
US20090153469A1 (en) * | 2007-12-14 | 2009-06-18 | Htc Corporation | Input Device and Handheld Electronic Device |
US20120133030A1 (en) * | 2010-11-26 | 2012-05-31 | Industrial Technology Research Institute | Tsv substrate structure and the stacked assembly thereof |
US20130011965A1 (en) * | 2009-04-29 | 2013-01-10 | Thomas Henry White | Distributing power with through-silicon-vias |
JP2013197412A (en) * | 2012-03-21 | 2013-09-30 | Toshiba Corp | Inspection device of semiconductor device and inspection method of semiconductor device |
CN103456707A (en) * | 2013-05-09 | 2013-12-18 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
US20140057434A1 (en) * | 2012-08-24 | 2014-02-27 | Jia-Jia Chen | Through silicon via process |
US9368481B2 (en) * | 2014-10-06 | 2016-06-14 | SK Hynix Inc. | Semiconductor devices and packages having through electrodes |
CN110017772A (en) * | 2019-04-30 | 2019-07-16 | 深圳格兰达智能装备股份有限公司 | A kind of system and method for detection chip positional shift |
US11024606B2 (en) * | 2015-01-16 | 2021-06-01 | Makoto Shizukuishi | Semiconductor device and manufacturing method thereof |
Families Citing this family (134)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3563604B2 (en) * | 1998-07-29 | 2004-09-08 | 株式会社東芝 | Multi-chip semiconductor device and memory card |
AU1687300A (en) * | 1998-12-16 | 2000-07-03 | Seiko Epson Corporation | Semiconductor chip, semiconductor device, circuit board and electronic equipmentand production methods for them |
US6404061B1 (en) * | 1999-02-26 | 2002-06-11 | Rohm Co., Ltd. | Semiconductor device and semiconductor chip |
US6281096B1 (en) | 1999-04-22 | 2001-08-28 | International Rectifier Corp. | Chip scale packaging process |
US6984571B1 (en) | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
JP3973340B2 (en) * | 1999-10-05 | 2007-09-12 | Necエレクトロニクス株式会社 | Semiconductor device, wiring board, and manufacturing method thereof |
JP4245754B2 (en) * | 1999-11-02 | 2009-04-02 | パナソニック株式会社 | Semiconductor device |
US6322903B1 (en) * | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
FR2805709B1 (en) * | 2000-02-28 | 2002-05-17 | Commissariat Energie Atomique | ELECTRICAL CONNECTION BETWEEN TWO FACES OF A SUBSTRATE AND METHOD OF MAKING |
US6586836B1 (en) * | 2000-03-01 | 2003-07-01 | Intel Corporation | Process for forming microelectronic packages and intermediate structures formed therewith |
US7125786B2 (en) * | 2000-04-11 | 2006-10-24 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
US6475889B1 (en) * | 2000-04-11 | 2002-11-05 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
US7892974B2 (en) | 2000-04-11 | 2011-02-22 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
JP3779524B2 (en) * | 2000-04-20 | 2006-05-31 | 株式会社東芝 | Multi-chip semiconductor device and memory card |
EP1151962B1 (en) | 2000-04-28 | 2007-06-13 | STMicroelectronics S.r.l. | Structure for electrically connecting a first body of semiconductor material overlaid by a second body of semiconductor material, composite structure using the electric connection structure, and manufacturing process thereof |
JP2002094082A (en) * | 2000-07-11 | 2002-03-29 | Seiko Epson Corp | Optical element and its manufacturing method and electronic equipment |
US6475432B2 (en) * | 2000-08-15 | 2002-11-05 | Ion Beam Applications, Inc. | Carrier and support for work pieces |
KR100686238B1 (en) * | 2000-08-29 | 2007-02-22 | 삼성전자주식회사 | Alignment key in panel and method for aligning the panel using the key |
JP2002176137A (en) | 2000-09-28 | 2002-06-21 | Toshiba Corp | Laminated semiconductor device |
JP3535461B2 (en) | 2001-01-10 | 2004-06-07 | 新光電気工業株式会社 | Semiconductor device manufacturing method and semiconductor device |
ITTO20011038A1 (en) * | 2001-10-30 | 2003-04-30 | St Microelectronics Srl | PROCEDURE FOR THE MANUFACTURE OF AN INTEGRATED SEMICONDUCTIVE SLICE FOR ELECTRONIC DEVICES AND A STRUCTURE FOR THE DECOUPLING AND |
US6599778B2 (en) * | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
JP3895987B2 (en) * | 2001-12-27 | 2007-03-22 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP3908148B2 (en) * | 2002-10-28 | 2007-04-25 | シャープ株式会社 | Multilayer semiconductor device |
JP4035034B2 (en) * | 2002-11-29 | 2008-01-16 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US7056810B2 (en) * | 2002-12-18 | 2006-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance |
TW569416B (en) * | 2002-12-19 | 2004-01-01 | Via Tech Inc | High density multi-chip module structure and manufacturing method thereof |
TWI239629B (en) * | 2003-03-17 | 2005-09-11 | Seiko Epson Corp | Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus |
KR100497111B1 (en) * | 2003-03-25 | 2005-06-28 | 삼성전자주식회사 | WL CSP, stack package stacking the same and manufacturing method thereof |
JP4589921B2 (en) * | 2003-04-02 | 2010-12-01 | サン・マイクロシステムズ・インコーポレーテッド | Optical communication between facing semiconductor chips |
JP3800335B2 (en) * | 2003-04-16 | 2006-07-26 | セイコーエプソン株式会社 | Optical device, optical module, semiconductor device, and electronic apparatus |
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
TWI221327B (en) * | 2003-08-08 | 2004-09-21 | Via Tech Inc | Multi-chip package and process for forming the same |
KR100621992B1 (en) * | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | structure and method of wafer level stack for devices of different kind and system-in-package using the same |
TWI225670B (en) * | 2003-12-09 | 2004-12-21 | Advanced Semiconductor Eng | Packaging method of multi-chip module |
US20050170609A1 (en) * | 2003-12-15 | 2005-08-04 | Alie Susan A. | Conductive bond for through-wafer interconnect |
JP4467318B2 (en) * | 2004-01-28 | 2010-05-26 | Necエレクトロニクス株式会社 | Semiconductor device, chip alignment method for multi-chip semiconductor device, and method for manufacturing chip for multi-chip semiconductor device |
JP4074862B2 (en) * | 2004-03-24 | 2008-04-16 | ローム株式会社 | Semiconductor device manufacturing method, semiconductor device, and semiconductor chip |
JP4800585B2 (en) * | 2004-03-30 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | Manufacturing method of through electrode, manufacturing method of silicon spacer |
JP3945493B2 (en) * | 2004-04-16 | 2007-07-18 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
US7608534B2 (en) | 2004-06-02 | 2009-10-27 | Analog Devices, Inc. | Interconnection of through-wafer vias using bridge structures |
KR100618838B1 (en) * | 2004-06-24 | 2006-09-01 | 삼성전자주식회사 | Stack type multi-chip package improving a connection reliability of stacked chips |
JP4383274B2 (en) * | 2004-06-30 | 2009-12-16 | Necエレクトロニクス株式会社 | Semiconductor device and semiconductor wafer manufacturing method |
JP2006019455A (en) * | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
US7224075B2 (en) * | 2004-08-13 | 2007-05-29 | Intel Corporation | Methods and systems for attaching die in stacked-die packages |
JP2006080399A (en) * | 2004-09-10 | 2006-03-23 | Toshiba Corp | Semiconductor device and method for manufacturing it |
US7462925B2 (en) * | 2004-11-12 | 2008-12-09 | Macronix International Co., Ltd. | Method and apparatus for stacking electrical components using via to provide interconnection |
JP4570446B2 (en) * | 2004-11-16 | 2010-10-27 | パナソニック株式会社 | Semiconductor wafer and inspection method thereof |
KR100652554B1 (en) * | 2005-01-07 | 2006-12-01 | 재단법인서울대학교산학협력재단 | Flip-chip bonding structure using multi chip module-deposited substrate |
US7675153B2 (en) * | 2005-02-02 | 2010-03-09 | Kabushiki Kaisha Toshiba | Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof |
US20060223220A1 (en) * | 2005-02-18 | 2006-10-05 | Bower Robert W | Methods and structures to form precisely aligned stacks of 3-dimensional stacks with high resolution vertical interconnect |
DE102005010272A1 (en) * | 2005-03-03 | 2006-09-14 | Infineon Technologies Ag | Semiconductor component and method for producing a semiconductor device |
JP4688526B2 (en) * | 2005-03-03 | 2011-05-25 | Okiセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
JP4456027B2 (en) * | 2005-03-25 | 2010-04-28 | Okiセミコンダクタ株式会社 | Method for manufacturing through conductor |
TW200644165A (en) * | 2005-05-04 | 2006-12-16 | Icemos Technology Corp | Silicon wafer having through-wafer vias |
US20080099924A1 (en) * | 2005-05-04 | 2008-05-01 | Icemos Technology Corporation | Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape |
US7838997B2 (en) | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US7534722B2 (en) * | 2005-06-14 | 2009-05-19 | John Trezza | Back-to-front via process |
US8456015B2 (en) | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7786592B2 (en) | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
US7687400B2 (en) | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US7521806B2 (en) * | 2005-06-14 | 2009-04-21 | John Trezza | Chip spanning connection |
US7767493B2 (en) | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
US20060278966A1 (en) | 2005-06-14 | 2006-12-14 | John Trezza | Contact-based encapsulation |
US7781886B2 (en) | 2005-06-14 | 2010-08-24 | John Trezza | Electronic chip contact structure |
US7851348B2 (en) | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US7560813B2 (en) * | 2005-06-14 | 2009-07-14 | John Trezza | Chip-based thermo-stack |
JP4507101B2 (en) | 2005-06-30 | 2010-07-21 | エルピーダメモリ株式会社 | Semiconductor memory device and manufacturing method thereof |
US7371663B2 (en) * | 2005-07-06 | 2008-05-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional IC device and alignment methods of IC device substrates |
US7863187B2 (en) * | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US8154105B2 (en) * | 2005-09-22 | 2012-04-10 | International Rectifier Corporation | Flip chip semiconductor device and process of its manufacture |
US7768085B2 (en) * | 2005-10-11 | 2010-08-03 | Icemos Technology Ltd. | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
TWI264787B (en) * | 2005-10-13 | 2006-10-21 | Phoenix Prec Technology Corp | Wafer structure with electroless plating metal connecting layer and method for fabricating the same |
US7560791B2 (en) * | 2005-10-28 | 2009-07-14 | Icemos Technology Ltd. | Front lit PIN/NIP diode having a continuous anode/cathode |
US7576404B2 (en) * | 2005-12-16 | 2009-08-18 | Icemos Technology Ltd. | Backlit photodiode and method of manufacturing a backlit photodiode |
KR100694424B1 (en) * | 2006-02-17 | 2007-03-12 | 주식회사 하이닉스반도체 | Multi chip package device and method for manufacturing the same |
EP1999788A2 (en) * | 2006-03-02 | 2008-12-10 | Icemos Technology Corporation | Photodiode having increased proportion of light-sensitive area to ligth-insensitive area |
TW200737506A (en) * | 2006-03-07 | 2007-10-01 | Sanyo Electric Co | Semiconductor device and manufacturing method of the same |
US7835001B2 (en) * | 2006-05-24 | 2010-11-16 | Samsung Mobile Display Co., Ltd. | Method of aligning a substrate, mask to be aligned with the same, and flat panel display apparatus using the same |
US7687397B2 (en) | 2006-06-06 | 2010-03-30 | John Trezza | Front-end processed wafer having through-chip connections |
WO2008002670A2 (en) * | 2006-06-29 | 2008-01-03 | Icemos Technology Corporation | Varying pitch adapter and a method of forming a varying pitch adapter |
TWI307406B (en) * | 2006-07-06 | 2009-03-11 | Au Optronics Corp | Misalignment detection devices |
JP2010500766A (en) * | 2006-08-10 | 2010-01-07 | アイスモス・テクノロジー・リミテッド | Method for manufacturing photodiode array with through-wafer via |
US8102039B2 (en) * | 2006-08-11 | 2012-01-24 | Sanyo Semiconductor Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20080087979A1 (en) * | 2006-10-13 | 2008-04-17 | Analog Devices, Inc. | Integrated Circuit with Back Side Conductive Paths |
JP4312786B2 (en) * | 2006-11-02 | 2009-08-12 | Okiセミコンダクタ株式会社 | Manufacturing method of semiconductor chip |
JP5010247B2 (en) * | 2006-11-20 | 2012-08-29 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device and manufacturing method thereof |
JP4731456B2 (en) * | 2006-12-19 | 2011-07-27 | 富士通セミコンダクター株式会社 | Semiconductor device |
US7670874B2 (en) | 2007-02-16 | 2010-03-02 | John Trezza | Plated pillar package formation |
US8198716B2 (en) * | 2007-03-26 | 2012-06-12 | Intel Corporation | Die backside wire bond technology for single or stacked die package |
US7960290B2 (en) * | 2007-05-02 | 2011-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a semiconductor device |
US8110930B2 (en) * | 2007-06-19 | 2012-02-07 | Intel Corporation | Die backside metallization and surface activated bonding for stacked die packages |
JP5137059B2 (en) * | 2007-06-20 | 2013-02-06 | 新光電気工業株式会社 | Electronic component package, manufacturing method thereof, and electronic component device |
US8034702B2 (en) * | 2007-08-16 | 2011-10-11 | Micron Technology, Inc. | Methods of forming through substrate interconnects |
DE102007044685B3 (en) * | 2007-09-19 | 2009-04-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Electronic system and method for manufacturing a three-dimensional electronic system |
KR101176187B1 (en) * | 2007-11-21 | 2012-08-22 | 삼성전자주식회사 | Stacked semiconductor device and method for thereof serial path build up |
US9136259B2 (en) * | 2008-04-11 | 2015-09-15 | Micron Technology, Inc. | Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking |
US8035198B2 (en) * | 2008-08-08 | 2011-10-11 | International Business Machines Corporation | Through wafer via and method of making same |
JP2010087273A (en) * | 2008-09-30 | 2010-04-15 | Panasonic Corp | Electronic device and method for manufacturing the same |
WO2010035401A1 (en) * | 2008-09-26 | 2010-04-01 | パナソニック株式会社 | Electronic device and method for manufacturing same |
TWI380421B (en) * | 2009-03-13 | 2012-12-21 | Advanced Semiconductor Eng | Method for making silicon wafer having through via |
KR101366949B1 (en) * | 2009-11-25 | 2014-02-24 | 인텔 코포레이션 | Through silicon via guard ring |
US9269676B2 (en) | 2009-11-25 | 2016-02-23 | Intel Corporation | Through silicon via guard ring |
US8710629B2 (en) * | 2009-12-17 | 2014-04-29 | Qualcomm Incorporated | Apparatus and method for controlling semiconductor die warpage |
US8677613B2 (en) | 2010-05-20 | 2014-03-25 | International Business Machines Corporation | Enhanced modularity in heterogeneous 3D stacks |
KR101212061B1 (en) * | 2010-06-09 | 2012-12-13 | 에스케이하이닉스 주식회사 | Semiconductor chip and semicodnductor package including the same and stack package using the same |
US8518746B2 (en) * | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
US8928159B2 (en) | 2010-09-02 | 2015-01-06 | Taiwan Semiconductor Manufacturing & Company, Ltd. | Alignment marks in substrate having through-substrate via (TSV) |
TW201216439A (en) * | 2010-10-08 | 2012-04-16 | Universal Scient Ind Co Ltd | Chip stacked structure |
US8546961B2 (en) * | 2011-01-10 | 2013-10-01 | International Business Machines Corporation | Alignment marks to enable 3D integration |
US9165887B2 (en) * | 2012-09-10 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with discrete blocks |
JP2015005637A (en) | 2013-06-21 | 2015-01-08 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Semiconductor device |
US9171742B2 (en) | 2013-07-22 | 2015-10-27 | Globalfoundries U.S. 2 Llc | Alignment of integrated circuit chip stack |
JP6341653B2 (en) * | 2013-11-28 | 2018-06-13 | エスアイアイ・プリンテック株式会社 | Liquid ejecting head manufacturing method, liquid ejecting head, and liquid ejecting apparatus |
US9748167B1 (en) * | 2016-07-25 | 2017-08-29 | United Microelectronics Corp. | Silicon interposer, semiconductor package using the same, and fabrication method thereof |
CN112164688B (en) * | 2017-07-21 | 2023-06-13 | 联华电子股份有限公司 | Chip stacking structure and manufacturing method of chip stacking structure |
US11246218B2 (en) | 2018-03-02 | 2022-02-08 | Intel Corporation | Core layer with fully encapsulated co-axial magnetic material around PTH in IC package substrate |
US10319696B1 (en) * | 2018-05-10 | 2019-06-11 | Micron Technology, Inc. | Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages |
US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
US10867963B2 (en) * | 2019-03-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die stack structure and method of fabricating the same |
IT201900006740A1 (en) * | 2019-05-10 | 2020-11-10 | Applied Materials Inc | SUBSTRATE STRUCTURING PROCEDURES |
IT201900006736A1 (en) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | PACKAGE MANUFACTURING PROCEDURES |
US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
CN110634785A (en) * | 2019-09-24 | 2019-12-31 | 杭州臻镭微波技术有限公司 | Three-dimensional stacking alignment method based on optics |
US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US11257790B2 (en) | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
US11400545B2 (en) | 2020-05-11 | 2022-08-02 | Applied Materials, Inc. | Laser ablation for package fabrication |
US11232951B1 (en) | 2020-07-14 | 2022-01-25 | Applied Materials, Inc. | Method and apparatus for laser drilling blind vias |
US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
US11521937B2 (en) | 2020-11-16 | 2022-12-06 | Applied Materials, Inc. | Package structures with built-in EMI shielding |
US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3928094A (en) * | 1975-01-16 | 1975-12-23 | Fairchild Camera Instr Co | Method of aligning a wafer beneath a mask and system therefor and wafer having a unique alignment pattern |
US4256514A (en) * | 1978-11-03 | 1981-03-17 | International Business Machines Corporation | Method for forming a narrow dimensioned region on a body |
US4499655A (en) * | 1981-03-18 | 1985-02-19 | General Electric Company | Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire |
JPS60160645A (en) * | 1984-02-01 | 1985-08-22 | Hitachi Ltd | Laminated semiconductor integrated circuit device |
JPS61275609A (en) * | 1985-05-31 | 1986-12-05 | Fujitsu Ltd | Optical alignment method between substrates |
US4807021A (en) * | 1986-03-10 | 1989-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device having stacking structure |
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
US5399898A (en) * | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
US5270261A (en) * | 1991-09-13 | 1993-12-14 | International Business Machines Corporation | Three dimensional multichip package methods of fabrication |
US5237434A (en) * | 1991-11-05 | 1993-08-17 | Mcnc | Microelectronic module having optical and electrical interconnects |
US5821549A (en) * | 1997-03-03 | 1998-10-13 | Schlumberger Technologies, Inc. | Through-the-substrate investigation of flip-chip IC's |
US6156220A (en) * | 1997-03-10 | 2000-12-05 | Ohlig; Albert H. | System and method for optically aligning films and substrates used in printed circuit boards |
-
1997
- 1997-04-25 JP JP10913097A patent/JP3920399B2/en not_active Expired - Fee Related
-
1998
- 1998-04-23 US US09/064,984 patent/US6087719A/en not_active Expired - Lifetime
-
2000
- 2000-04-28 US US09/560,143 patent/US6383837B1/en not_active Expired - Fee Related
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050224921A1 (en) * | 2001-05-01 | 2005-10-13 | Subhash Gupta | Method for bonding wafers to produce stacked integrated circuits |
US20040080013A1 (en) * | 2002-10-28 | 2004-04-29 | Sharp Kabushiki Kaisha | Chip-stack semiconductor device and manufacturing method of the same |
US7944058B2 (en) | 2003-10-30 | 2011-05-17 | Oki Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US9559041B2 (en) | 2003-10-30 | 2017-01-31 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US20080265430A1 (en) * | 2003-10-30 | 2008-10-30 | Masamichi Ishihara | Semiconductor Device an Process for Fabricating the Same |
US10199310B2 (en) | 2003-10-30 | 2019-02-05 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US20110201178A1 (en) * | 2003-10-30 | 2011-08-18 | Oki Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US9093431B2 (en) | 2003-10-30 | 2015-07-28 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US10559521B2 (en) | 2003-10-30 | 2020-02-11 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US9887147B2 (en) | 2003-10-30 | 2018-02-06 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
TWI408795B (en) * | 2003-10-30 | 2013-09-11 | Oki Semiconductor Company Ltd | Semiconductor device and manufacturing method thereof |
US8664666B2 (en) | 2003-10-30 | 2014-03-04 | Oki Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US11127657B2 (en) | 2003-10-30 | 2021-09-21 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US20060267190A1 (en) * | 2005-05-24 | 2006-11-30 | Sharp Kabushiki Kaisha | Semiconductor device, laminated semiconductor device, and method for producing semiconductor device |
US8384207B2 (en) | 2005-08-26 | 2013-02-26 | Honda Motor Co., Ltd. | Semiconductor integrated circuit device having insulated through wires |
WO2007024009A1 (en) * | 2005-08-26 | 2007-03-01 | Honda Motor Co., Ltd. | Semiconductor integrated circuit device and method for manufacturing same |
US20090153469A1 (en) * | 2007-12-14 | 2009-06-18 | Htc Corporation | Input Device and Handheld Electronic Device |
US8835224B2 (en) * | 2009-04-29 | 2014-09-16 | Altera Corporation | Distributing power with through-silicon-vias |
US20130011965A1 (en) * | 2009-04-29 | 2013-01-10 | Thomas Henry White | Distributing power with through-silicon-vias |
US20120133030A1 (en) * | 2010-11-26 | 2012-05-31 | Industrial Technology Research Institute | Tsv substrate structure and the stacked assembly thereof |
US9257338B2 (en) | 2010-11-26 | 2016-02-09 | Industrial Technology Research Institute | TSV substrate structure and the stacked assembly thereof |
JP2013197412A (en) * | 2012-03-21 | 2013-09-30 | Toshiba Corp | Inspection device of semiconductor device and inspection method of semiconductor device |
US9052187B2 (en) | 2012-03-21 | 2015-06-09 | Kabushiki Kaisha Toshiba | Inspection apparatus and inspection method for semiconductor device |
US20140057434A1 (en) * | 2012-08-24 | 2014-02-27 | Jia-Jia Chen | Through silicon via process |
US9012324B2 (en) * | 2012-08-24 | 2015-04-21 | United Microelectronics Corp. | Through silicon via process |
US9589840B2 (en) | 2013-05-09 | 2017-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
US10056325B2 (en) | 2013-05-09 | 2018-08-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a trench penetrating a main body |
CN103456707A (en) * | 2013-05-09 | 2013-12-18 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
US9368481B2 (en) * | 2014-10-06 | 2016-06-14 | SK Hynix Inc. | Semiconductor devices and packages having through electrodes |
US11024606B2 (en) * | 2015-01-16 | 2021-06-01 | Makoto Shizukuishi | Semiconductor device and manufacturing method thereof |
CN110017772A (en) * | 2019-04-30 | 2019-07-16 | 深圳格兰达智能装备股份有限公司 | A kind of system and method for detection chip positional shift |
Also Published As
Publication number | Publication date |
---|---|
US6087719A (en) | 2000-07-11 |
JPH10303364A (en) | 1998-11-13 |
US6383837B1 (en) | 2002-05-07 |
JP3920399B2 (en) | 2007-05-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6383837B1 (en) | Method of manufacturing a multi-chip semiconductor device effective to improve alignment | |
US8222121B2 (en) | Fiducial scheme adapted for stacked integrated circuits | |
US5753536A (en) | Semiconductor device and associated fabrication method | |
US5712190A (en) | Process for controlling distance between integrated circuit chips in an electronic module | |
US8558351B2 (en) | Alignment for backside illumination sensor | |
CN100403082C (en) | Optoelectronic package and fabrication method | |
KR100403064B1 (en) | Three-dimensional chip stacking assembly | |
TWI472019B (en) | Solid-state imaging device and method for producing the same | |
US7883985B2 (en) | Chip and multi-chip semiconductor device using the chip, and method for manufacturing same | |
CN100521176C (en) | Semiconductor chip and semiconductor device | |
US10804252B2 (en) | Three dimensional integrated circuit | |
US6617702B2 (en) | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate | |
US11609389B2 (en) | Fiber coupler with an optical window | |
TW201027601A (en) | Laser bonding for stacking semiconductor substrates | |
JP2023010782A (en) | Semiconductor device and production method of the same | |
KR100757233B1 (en) | Optical waveguide platform and method of manufacturing the same | |
JPH06283663A (en) | Method for matching semiconductor chips with each other | |
CN102200612A (en) | Glass plate with embedded optical fiber and manufacturing method thereof | |
JPH04262566A (en) | Manufacture of hybrid module | |
CN217606139U (en) | Semiconductor packaging structure | |
JP2001244333A (en) | Method for manufacturing semiconductor integrated circuit device | |
TW202219570A (en) | Optical structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140507 |