US20010050431A1 - Semiconductor device and liquid crystal module adopting the same - Google Patents
Semiconductor device and liquid crystal module adopting the same Download PDFInfo
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- US20010050431A1 US20010050431A1 US09/822,219 US82221901A US2001050431A1 US 20010050431 A1 US20010050431 A1 US 20010050431A1 US 82221901 A US82221901 A US 82221901A US 2001050431 A1 US2001050431 A1 US 2001050431A1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
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Definitions
- the present invention relates to a package configuration of a semiconductor device which employs a tape in the mounting of a semiconductor chip, and to a liquid crystal module incorporating the semiconductor device.
- a liquid crystal display device used as a personal computer monitor, and portable devices such as a terminal device of a mobile phone and a game utilize a tape for mounting a semiconductor chip called TAB (Tape Automated Bonding).
- TAB Tape Automated Bonding
- a package configuration such as a TCP (Tape Carrier Package) and a COF (Chip on Film).
- TCP Transmission Carrier Package
- COF Chip on Film
- FIGS. 14 and 15 illustrate a conventional mounting method, of which FIG. 14 is a front view and FIG. 15 is a cross section of FIG. 14 taken along a cross sectional line A-A.
- FIGS. 14 and 15 show the TCP configuration.
- a tape 3 is formed by patterning a Cu wiring pattern 2 on a substrate 1 composed of an organic material such as polyimide.
- the Cu wiring pattern 2 has extending portions 2 a and 2 b which are extending from peripheral portions of the substrate 1 so as to be parallel to each other.
- the extending portions 2 a and 2 b are electrically connected to a pad of a liquid crystal panel and a pad of a power supply or a print board from which an image data signal is transmitted, respectively.
- the substrate 1 includes device holes 6 and 7 corresponding to semiconductor chips 4 and 5 to be mounted.
- the Cu wiring pattern 2 is lead into these device holes 6 and 7 so as to be inner leads 2 c. Portions of the Cu wiring pattern 2 such as the inner leads 2 c and the extending portions 2 a and 2 b are given Sn plating (not shown).
- Sn plating (not shown).
- the inner leads 2 c project to the interior of the device holes 6 and 7 through the four sides of each rectangular hole.
- the Au bumps 8 of the semiconductor chips 4 an 5 are subject to eutectic bonding with the Sn which was applied to the inner leads 2 c by electroless plating, that is called ILB (Inner Lead Bonding).
- Periphery w including the device surfaces of the semiconductor chips 4 and 5 , and the inner leads 2 c thus mounted are sealed with a resin 9 , thereby maintaining the mechanical strength while being protected from surrounding environment.
- the tape 3 is protected by a covering of a solder resist 10 , except for electrode portions thereof such as the inner leads 2 c. The foregoing processes are sequentially performed while remaining on the tape 3 , thereby efficiently performing mounting.
- the driver portion that is required to be resistant to pressure in order to control contrast in pixels of a liquid crystal panel is not suitable for manufacture by minuscule processing, yet adopting a minuscule process in the memory portion enables the memory portion to accommodate to integration which corresponds to the number of wires in the liquid crystal panel. Therefore, it is feasible that the driver portion and the memory portion are formed by an optimum process (design rule), while mounting two semiconductor chips, a driver chip and an SRAM chip, on a single tape.
- the Au bumps 8 of the semiconductor chips 4 and 5 are disposed on the periphery of the semiconductor chips 4 and 5 having the rectangular shape, for the ILB.
- the inner leads 2 c project to the interior of the device holes 6 and 7 through all the four sides of each rectangular hole, thereby accommodating to a high-density arrangement of the Cu wiring pattern 2 .
- the semiconductor device of the present invention is made up of a tape having an organic substrate and a wiring pattern formed on the organic substrate, and a plurality of semiconductor chips mounted on the tape, where the semiconductor chips individually have a lengthwise rectangular shape, and the semiconductor chips having the lengthwise rectangular shape is mounted so as to have a long side substantially perpendicular to an extending direction of the wiring pattern.
- the semiconductor device having a TCP or COF configuration including semiconductor chips mounted on a tape is mounted in such a manner that each semiconductor chip having the lengthwise rectangular shape has bumps along its long side which is substantially perpendicular to the extending direction of the wiring pattern.
- numerous wires of the wiring pattern can be provided so as to be substantially parallel to each other and substantially straight to a destination of in-/output.
- an interval between the chips can be reduced. Accordingly, in the mounting of a plurality of semiconductor chips, devices to be connected can be reduced in size by reducing a width of the tape.
- the semiconductor device of the present invention has an arrangement in which the semiconductor chips have a difference in thickness.
- bonding is performed on a thinner semiconductor chip first, thereby reducing a potential damage on a semiconductor chip due to a contact with a bonding tool (bonder equipment).
- the semiconductor chips can be mounted in the vicinity, while reducing restriction on a mounting position of a chip, and allows a spacious design, for example, in the routing of the wiring pattern.
- the semiconductor device of the present invention on the tape is formed a slit between the semiconductor chips, so as to ease bending of the tape.
- the semiconductor of the present invention has an arrangement in which a wiring pattern between the semiconductor chips is free from a solder resist for ease of bending.
- solder resist is not formed over the wiring pattern between the semiconductor chips, it is less feasible that bending the tape at a portion free from the solder resist may result in a break in the wiring pattern, thereby improving flexibility in composition such that the tape is bent with respect to the back side of the liquid crystal panel to be connected.
- the semiconductor device of the present invention has an arrangement in which the semiconductor chips are at least two chips selected from an SRAM, a liquid crystal driver IC and a controller-use IC.
- the semiconductor device is made up of two chips one of which is the liquid crystal driver IC and the other is the SRAM (static RAM) suitable as a memory capable of low power consumption and being provided adjacent to the liquid crystal driver IC.
- the semiconductor device may have three chips: the SRAM, the liquid crystal driver IC and the controller-use IC.
- the semiconductor device may have two of these chips arbitrary selected.
- the liquid crystal module of the present invention includes any one of the foregoing semiconductor devices that is connected to a liquid crystal panel.
- FIG. 1 is a front view of a semiconductor device according to a First Embodiment of the present invention.
- FIG. 2 is a cross sectional view of the semiconductor device of FIG. 1, taken along the line B-B.
- FIG. 3 is a front view of a plate used in ILB.
- FIG. 4 is a cross sectional view showing a mounting state of chips.
- FIG. 5 is a front view of a liquid crystal module which is one mounting example of the semiconductor device shown in FIGS. 1 to 4 .
- FIG. 6 is a cross sectional view of a semiconductor device according to a Second Embodiment of the present invention.
- FIG. 7 is a cross sectional view showing a mounting state of chips.
- FIG. 8 is a cross sectional view of a semiconductor device according to a Third Embodiment of the present invention.
- FIG. 9 is a cross sectional view of a semiconductor device according to a Fourth Embodiment of the present invention.
- FIG. 10 is a front view of a semiconductor device according to a Fifth Embodiment of the present invention.
- FIG. 11 is a cross sectional view of the semiconductor device of FIG. 10, taken along the line C-C.
- FIG. 12 is a cross sectional view of a liquid crystal module to which the semiconductor device shown in FIGS. 10 and 11 is to be mounted.
- FIG. 13 is a front view of a semiconductor device which is one modification example of the Fifth Embodiment of the present invention.
- FIG. 14 is a front view for explaining a conventional mounting method for a semiconductor device.
- FIG. 15 is a cross sectional view of the semiconductor device of FIG. 14, taken along the line A-A.
- FIG. 1 is a front view of a semiconductor device according to the First Embodiment of the present invention
- FIG. 2 is a cross sectional view of this semiconductor device, taken along a line B-B.
- a surface of a substrate (organic base material) 11 composed of an organic material such as polyimide is patterned to have a Cu wiring pattern (wiring pattern) 12 , thereby forming a tape 13 .
- the Cu wiring pattern 12 has extending portions 12 a and 12 b which are extended parallel to each other from a peripheral portion of the substrate 11 , so that the extending portions 12 a and 12 b are electrically and mechanically connected respectively to an electrode of a liquid crystal panel 30 (shown in FIG. 5) and an electrode of a power supply or a print board from which an image data signal is transmitted, via an anisotropic conductive film and the like in-between.
- the substrate 11 On the substrate 11 are formed device holes 16 and 17 in correspondence with semiconductor chips 14 and 15 to be mounted.
- the Cu wiring pattern 12 is lead into the device holes 16 and 17 , thereby becoming inner leads 12 c . Portions of the Cu wiring pattern 12 such as the inner lead 12 c and the extending portions 12 a and 12 b are given Sn plating (not shown).
- the semiconductor chips 14 and 15 individually have a lengthwise rectangular shape whose aspect ratio (a ratio of a long side to a short side) is not less than 10.
- the semiconductor chips 14 and 15 are mounted so as to be substantially perpendicular to an extending direction of the Cu wiring pattern 12 .
- the inner leads 12 c in correspondence with Au bumps 18 disposed along each long side of the semiconductor chips having the lengthwise rectangular shape, project to the interior of each of the device holes 16 and 17 .
- the Au bumps of the semiconductor chips 14 and 15 are subject to eutectic bonding with the Sn which was applied to the inner leads 12 c by electroless plating, thus connected by the ILB.
- the semiconductor chip 14 is an SRAM having, for example, a chip area of 16 mm ⁇ 1.6 mm and a thickness of 400 ⁇ m, which is manufactured according to a process (design rule) of not more than 0.35 ⁇ m.
- the semiconductor chip 15 is a driver IC having, for example, a chip area of 11 mm ⁇ 1 mm and a thickness of 625 ⁇ m, which is manufactured according to a process (design rule) of 0.65 ⁇ m.
- the SRAM requires more elements than a DRAM and others, but is capable of low power consumption and desirable as a memory to be disposed adjacent to a liquid crystal driver IC. In addition, by thus having the lengthwise rectangular shape, the SRAM can be disposed adjacent to the driver IC.
- either one of the semiconductor chips 14 and 15 may be a controller-use IC which may alternatively be provided in addition to the SRAM and the liquid crystal driver IC as being the semiconductor chips 14 and 15 , respectively.
- a controller-use IC in addition to the SRAM and the liquid crystal driver IC as the semiconductor chips 14 and 15 , respectively, for example, an arrangement as shown in FIG. 8 to be discussed later is available, where a semiconductor chip 44 serves as the controller-use IC.
- the controller-use IC herein has a function which will be explained below.
- the controller-use IC has the function to make this timing.
- the semiconductor chip 14 which is bonded first, which is followed by the bonding of the semiconductor chip 15 by the same bonding tool.
- a difference in thickness between these two semiconductor chips 14 and 15 is preferably not less than 200 ⁇ m, thereby reducing potential damages such as a damage on the semiconductor chip 14 that has been bonded first, given by a contact with the bonding tool when bonding the semiconductor chip 15 for the second time.
- This enables the semiconductor chips 14 and 15 to be mounted in the vicinity, greatly reduces restriction on a mounting position of a chip, and allows a spacious design, for example, in the routing of the Cu wiring pattern 12 .
- the tape 13 can also have a smaller width; however, taking into consideration an interaction with the bonding tool, the mounting interval needs to be in a range of 0.5 mm to 3 mm.
- Conditions for the ILB was such that a connection load per a bump is 30 gf, connection time is 3 seconds, and a bonding tool has a temperature of 400° C., thereby attaining electrical conduction between the Cu wiring pattern 12 including 100 wires or more and the semiconductor chips 14 and 15 .
- FIG. 3 is a front view of a plate 21 which is used in the ILB
- FIG. 4 is a cross sectional view showing a mounting state of chips.
- This plate 21 is made of, for example, an invar material (an alloy containing 36% of Ni and 64% of Fe) having a film thickness of 0.5 mm, and have blanks 21 a and 21 b respectively corresponding to the sizes of, and the interval between, the semiconductor chips 14 and 15 to be connected by the ILB.
- the plate 21 supports the tape 13 , thereby preventing distortion such as deformation due to bending in the tape 13 which may occur when pressed by a tool 22 in the bonding.
- Periphery W including device surfaces of the semiconductor chips 14 and 15 thus mounted, and the inner leads 12 c are sealed with a resin 19 , thereby maintaining the mechanical strength while being protected from surrounding environment.
- the sealing with resin is performed as follows: after the ILB, the required amount of liquid resin, 30 mg per 5 seconds for example, is dropped from the device surfaces of the semiconductor chips 14 and 15 , thereafter performing thermal processing at 120° C. for 20 minutes. Accordingly, the device surfaces of the semiconductor chips 14 and 15 are covered as indicated by a reference numeral 19 a, while forming a fillet 19 b on a side with resin seeped through the device surfaces. Allowing resin to be set on the device surfaces and the sides of the semiconductor chips 14 and 15 realizes firmer hold and seal.
- the tape 13 is protected by a covering of a solder resist 20 , except for electrode portions thereof such as the inner leads 12 c.
- the foregoing processes are sequentially performed while the semiconductor chips 14 and 15 remain on the tape 3 , thereby efficiently performing mounting.
- FIG. 5 is a front view of a liquid crystal module which is one mounting example of the semiconductor device having the foregoing arrangement.
- This liquid crystal module is used as a display of a terminal device of a cellular phone, which includes a liquid crystal panel 30 and the single tape 13 connected to each other.
- the semiconductor device of FIG. 5 may be adopted any of semiconductor devices according to Second to Fifth Embodiments to be discussed below.
- the semiconductor chips 14 and 15 having the lengthwise rectangular shape are mounted so as to be perpendicular to the extending direction of the Cu wiring pattern 12 , thereby making it possible to dispose a plurality of wires of the Cu wiring pattern 12 so as to be substantially parallel to each other and substantially straight-line along the extending portions 12 a and 12 b .
- the interval therebetween can be reduced.
- the semiconductor chips 14 and 15 are given long sides so as to enable numerous Au bumps 18 as being I/O terminals on the semiconductor chips 14 and 15 to be disposed on the same row so that numerous wires of the Cu wiring pattern 12 as being output signal wiring can be routed straight toward the extending portions 12 a and 12 b.
- short sides are provided so that, when thus providing the long sides, as many chips as possible can be obtained from a wafer from which the semiconductor chips 14 and 15 are obtained, and a minimum area required to form elements and circuits within the semiconductor chips 14 and 15 can be secured.
- the semiconductor chips 14 and 15 have an aspect ratio (a ratio of a long side to a short side) of not less than 10. More specifically, the semiconductor chips 14 and 15 having the aspect ratio of not less than 10 offer two advantages: (i) securing as many chips as obtainable from one wafer; and (ii) straight routing of the output signal wiring.
- the semiconductor chips 14 and 15 have each a long side of about 17 mm, and when adopting a fine pitch having a minimum pad pitch of 50 ⁇ m, it is possible to secure about 540 I/O terminals.
- the semiconductor chips 14 and 15 in order to secure the area corresponding to elements and circuits provided within the semiconductor chips 14 and 15 according to the process of the design rule of 0.65 ⁇ m, the semiconductor chips 14 and 15 each should have a short side of at least 1.6 mm.
- FIG. 6 is a cross sectional view of a semiconductor device according to the Second Embodiment of the present invention.
- the present semiconductor device adopts the COF configuration, but the corresponding members will be given the same reference numerals, and explanation thereof will be omitted here.
- a surface of a substrate 31 composed of the organic material is patterned to have a Cu wiring pattern 32 , thereby forming a tape 33 .
- the Cu wiring pattern 32 is given Ni plating (not shown) and, further, Au plating (not shown).
- the semiconductor chips 14 and 15 are mounted on the tape 33 by flip chip bonding.
- the mounting is performed as follows: after positioning and placing the tape 33 on a base 34 , the tool 22 is used to connect, for example, the Au bumps 18 and electrodes by Au-Au thermo-compression bonding.
- conditions for the connection are, for example, 450° C., 170 ⁇ 10 ⁇ 4 gf/m 2 , and 2 seconds.
- the sealing with resin is made in such a manner that liquid resin is continuously dropped from along long-side edges of the semiconductor chips 14 and 15 to a surface of the tape 33 , so as to fill the spacings between the tape 33 and each of the semiconductor chips 14 and 15 as indicated by a reference numeral 19 a according to capillary action, and further, a fillet 19 b is formed on a side of the semiconductor chip 14 or 15 .
- the setting conditions of the resin is the same as those in the ILB above.
- a fillet between the semiconductor chips 14 and 15 as indicated by a reference numeral 19 c has an improved strength due to a linking state of the resin.
- the present invention can thus be applied to the COF configuration.
- FIG. 8 is a cross sectional view of a semiconductor device according to the Third Embodiment of the present invention.
- This semiconductor device is similar to the semiconductor device shown in FIGS. 1 to 4 , 6 and 7 , and the corresponding members will be given the same reference numerals, and explanation thereof will be omitted here.
- a surface of a substrate 41 composed of the organic material is patterned to have a Cu wiring pattern 42 , thereby forming a tape 43 .
- the tape 43 includes the device holes 16 and 17 , thereby connecting the semiconductor chips 14 and 15 by the ILB.
- onto the tape 43 is connected a semiconductor chip 44 by the flip chip bonding.
- the present semiconductor device has the TCP and COF configurations in combination.
- the semiconductor chips 15 and 44 are mounted on the side of the Cu wiring pattern 42 , while the semiconductor chip 14 is mounted on the side of the substrate 41 (it may also be arranged such that the semiconductor chip 14 is mounted on the side of the Cu wiring pattern 42 and the semiconductor chip 15 is mounted on the side of the substrate 41 ).
- the semiconductor chips 14 and 15 are given the Au bumps 18 which are connected to the inner leads 12 c subject to the Sn plating, by eutectic bonding.
- the semiconductor chip 44 has the Au bumps 18 which are connected to electrodes by the Au-Au thermo-compression bonding.
- the semiconductor chips 14 and 15 thus mounted on the tape 43 are adjacent to each other, and the resin is applied therebetween in the linking state as indicated by a reference numeral 19 c, thereby improving the mechanical strength.
- FIG. 9 is a cross sectional view of a semiconductor device according to the Fourth Embodiment of the present invention.
- This semiconductor device is similar to the semiconductor device shown in FIG. 8, and the corresponding members will be given the same reference numerals, and explanation thereof will be omitted.
- on the tape 43 are mounted one or more electric members 45 and 46 such as a resistor and a capacitor, other than the semiconductor chips 14 and 15 .
- the electric members 45 and 46 are mounted in such a manner that soldering paste is initially printed with a metal mask, then, the electric members 45 and 46 are mounted next, which is followed by the application of solder in a thermal atmosphere at a peak temperature of 240° C.
- the two semiconductor chips 14 and 15 are mounted thereafter.
- the electric members 45 and 46 may be mounted between the two semiconductor chips 14 and 15 , and further, two or more pieces of the same member may be mounted.
- FIG. 10 is a front view of a semiconductor device according to the Fifth Embodiment of the present invention
- FIG. 11 is a cross sectional view of this semiconductor device of FIG. 10, taken along a line C-C.
- the present semiconductor device is similar to the semiconductor device shown in FIGS. 7 and 8, and the corresponding members will be given the same reference numerals, and explanation thereof will be omitted.
- the substrate 31 composed of the organic material includes a slit 52 between the semiconductor chips 14 and 15 , while providing part of the Cu wiring pattern 12 between the chips 14 and 15 with blank portions where the solder resist 20 is not formed.
- the slit 52 and the blank portions are provided so as to enable the tape 53 to be easily bent without impairing the strength, and these are formed along a long-side direction of the semiconductor chips 14 and 15 , and have a width of, for example, 100 ⁇ m. This enables the tape 53 to be flexibly bent, thereby reducing bending stress with respect to an area around the extending portions 12 a and 12 b.
- FIG. 12 is a cross sectional view of a liquid crystal module on which the semiconductor device shown in FIGS. 10 and 11 is to be mounted, where the tape 53 is bent, thereby greatly contributing to the miniaturization of the liquid crystal module.
- FIG. 13 is a front view of a semiconductor device which is a modification example of the Fifth Embodiment of the present invention, and members corresponding to those of the semiconductor device shown in FIG. 10 will be given the same reference numerals, and explanation thereof will be omitted.
- those indicated by a reference numeral 12 e are wired across the semiconductor chip 15 so as to be connected to the semiconductor chip 14
- those indicated by a reference numeral 12 d are wired across the semiconductor chips 14 and 15 .
- the number of semiconductor chips across which the Cu wiring pattern 12 is provided may be two or more, which should be selected depending on a circuit layout, as required. More specifically, it needs to be arranged such that the Cu wiring pattern 12 from a semiconductor chip can be connected partially to another semiconductor chip or the outside, through at least one different semiconductor chip. Further, a portion of the Cu wiring pattern 12 as indicated by a reference numeral 12 f is to connect the semiconductor chips 14 and 15 , which was shown in other drawings such as FIG. 10.
- Selection of the adhesive 54 is made in accordance with reference potentials of the semiconductor chips 14 and 15 .
- an insulating resin is adopted when the semiconductor chips 14 and 15 have different reference potentials, and an electrically conducting resin is adopted when the chips 14 and 15 have the same reference potential.
- the extending portion 12 a of the Cu wiring pattern 12 is electrically and mechanically connected to an electrode of the liquid crystal panel 30 , via the anisotropic conductive film and the like.
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Abstract
Description
- The present invention relates to a package configuration of a semiconductor device which employs a tape in the mounting of a semiconductor chip, and to a liquid crystal module incorporating the semiconductor device.
- A liquid crystal display device used as a personal computer monitor, and portable devices such as a terminal device of a mobile phone and a game utilize a tape for mounting a semiconductor chip called TAB (Tape Automated Bonding). In addition, in this mounting is adopted a package configuration such as a TCP (Tape Carrier Package) and a COF (Chip on Film). Note that, an example of the mounting of a semiconductor chip according to the TAB is disclosed in Japanese Unexamined Patent Publication No. 57233/1991 (Tokukaihei 3-57233 published on Mar. 12, 1991).
- FIGS. 14 and 15 illustrate a conventional mounting method, of which FIG. 14 is a front view and FIG. 15 is a cross section of FIG. 14 taken along a cross sectional line A-A. FIGS. 14 and 15 show the TCP configuration. A
tape 3 is formed by patterning aCu wiring pattern 2 on a substrate 1 composed of an organic material such as polyimide. TheCu wiring pattern 2 has extendingportions portions - The substrate1 includes
device holes 6 and 7 corresponding tosemiconductor chips 4 and 5 to be mounted. TheCu wiring pattern 2 is lead into thesedevice holes 6 and 7 so as to beinner leads 2 c. Portions of theCu wiring pattern 2 such as theinner leads 2 c and the extendingportions Au bumps 8 disposed on every side ofsemiconductor chips 4 and 5 each having a rectangular shape, the inner leads 2 c project to the interior of thedevice holes 6 and 7 through the four sides of each rectangular hole. TheAu bumps 8 of the semiconductor chips 4 an 5 are subject to eutectic bonding with the Sn which was applied to theinner leads 2 c by electroless plating, that is called ILB (Inner Lead Bonding). - Periphery w including the device surfaces of the
semiconductor chips 4 and 5, and theinner leads 2 c thus mounted are sealed with aresin 9, thereby maintaining the mechanical strength while being protected from surrounding environment. Note that, thetape 3 is protected by a covering of a solder resist 10, except for electrode portions thereof such as theinner leads 2 c. The foregoing processes are sequentially performed while remaining on thetape 3, thereby efficiently performing mounting. - Meanwhile, electric devices have been given enhanced functions in recent years, which calls for multi-chip mounting on a single tape as discussed. Referring to liquid crystal modules to be mounted on small devices such as the terminal device of the mobile phone and game for example, in order to realize efficient operations of a driver with respect to the increasing number of wires in a liquid crystal panel, a memory is provided first in an IC of the driver, thus resulting in an increase in a memory capacity due to a further increase in the number of pixels and adopting of colors. For example, when manufacturing a common and segment driver and an SRAM according to a process (design rule) necessary for the common and segment driver, an SRAM portion occupies 60% of the whole area of a semiconductor chip.
- On the other hand, though the driver portion that is required to be resistant to pressure in order to control contrast in pixels of a liquid crystal panel is not suitable for manufacture by minuscule processing, yet adopting a minuscule process in the memory portion enables the memory portion to accommodate to integration which corresponds to the number of wires in the liquid crystal panel. Therefore, it is feasible that the driver portion and the memory portion are formed by an optimum process (design rule), while mounting two semiconductor chips, a driver chip and an SRAM chip, on a single tape.
- However, in the foregoing mounting configuration, the
Au bumps 8 of thesemiconductor chips 4 and 5 are disposed on the periphery of thesemiconductor chips 4 and 5 having the rectangular shape, for the ILB. In correspondence with this, theinner leads 2 c project to the interior of thedevice holes 6 and 7 through all the four sides of each rectangular hole, thereby accommodating to a high-density arrangement of theCu wiring pattern 2. This raises a problem such that, of all the four sides of each of thedevice holes 6 and 7, through a side orthogonal to the extendingportions Cu wiring pattern 2; however, with regard to a side parallel to the extendingportions Cu wiring pattern 2 becomes complicated, thereby resulting in a process defect in thetape 3 and an increase in the size of thetape 3 due to the necessity for routing space. - This kind of problem emerges when mounting the
semiconductor chips 4 and 5 individually on thetape 3, and becomes more pronounced in the mounting of a plurality ofsemiconductor chips 4 and 5. Accordingly, multi-chip mounting cannot easily be realized due to the foregoing problems, though it has been called for. - It is an object of the present invention to provide a semiconductor device capable of compact mounting of a plurality of semiconductor chips on a single tape, and a liquid crystal module adopting the semiconductor device.
- The semiconductor device of the present invention is made up of a tape having an organic substrate and a wiring pattern formed on the organic substrate, and a plurality of semiconductor chips mounted on the tape, where the semiconductor chips individually have a lengthwise rectangular shape, and the semiconductor chips having the lengthwise rectangular shape is mounted so as to have a long side substantially perpendicular to an extending direction of the wiring pattern.
- With the foregoing arrangement, the semiconductor device having a TCP or COF configuration including semiconductor chips mounted on a tape is mounted in such a manner that each semiconductor chip having the lengthwise rectangular shape has bumps along its long side which is substantially perpendicular to the extending direction of the wiring pattern.
- Accordingly, numerous wires of the wiring pattern can be provided so as to be substantially parallel to each other and substantially straight to a destination of in-/output. Particularly, when the semiconductor chips have no complicated routing therebetween, and the chips are connected in a substantially straight-line wiring pattern, an interval between the chips can be reduced. Accordingly, in the mounting of a plurality of semiconductor chips, devices to be connected can be reduced in size by reducing a width of the tape.
- Further, the semiconductor device of the present invention has an arrangement in which the semiconductor chips have a difference in thickness.
- With the foregoing arrangement, bonding is performed on a thinner semiconductor chip first, thereby reducing a potential damage on a semiconductor chip due to a contact with a bonding tool (bonder equipment).
- Consequently, the semiconductor chips can be mounted in the vicinity, while reducing restriction on a mounting position of a chip, and allows a spacious design, for example, in the routing of the wiring pattern.
- Furthermore, in the semiconductor device of the present invention, on the tape is formed a slit between the semiconductor chips, so as to ease bending of the tape.
- With the foregoing arrangement, flexibility can be improved in composition such that the tape is bent with respect to a back side of a liquid crystal panel to be connected.
- Further, the semiconductor of the present invention has an arrangement in which a wiring pattern between the semiconductor chips is free from a solder resist for ease of bending.
- With the foregoing arrangement, since the solder resist is not formed over the wiring pattern between the semiconductor chips, it is less feasible that bending the tape at a portion free from the solder resist may result in a break in the wiring pattern, thereby improving flexibility in composition such that the tape is bent with respect to the back side of the liquid crystal panel to be connected.
- Furthermore, the semiconductor device of the present invention has an arrangement in which the semiconductor chips are at least two chips selected from an SRAM, a liquid crystal driver IC and a controller-use IC.
- With the foregoing arrangement, for example, more elements are required in comparison with a DRAM (dynamic RAM) and the like; however, the semiconductor device is made up of two chips one of which is the liquid crystal driver IC and the other is the SRAM (static RAM) suitable as a memory capable of low power consumption and being provided adjacent to the liquid crystal driver IC.
- Alternatively, the semiconductor device may have three chips: the SRAM, the liquid crystal driver IC and the controller-use IC. Alternatively, the semiconductor device may have two of these chips arbitrary selected.
- Further, the liquid crystal module of the present invention includes any one of the foregoing semiconductor devices that is connected to a liquid crystal panel.
- Additional objects, features, and strengths of the present invention will be made clear by the description below. Further, the advantages of the present invention will be evident from the following explanation in reference to the drawings.
- FIG. 1 is a front view of a semiconductor device according to a First Embodiment of the present invention.
- FIG. 2 is a cross sectional view of the semiconductor device of FIG. 1, taken along the line B-B.
- FIG. 3 is a front view of a plate used in ILB.
- FIG. 4 is a cross sectional view showing a mounting state of chips.
- FIG. 5 is a front view of a liquid crystal module which is one mounting example of the semiconductor device shown in FIGS.1 to 4.
- FIG. 6 is a cross sectional view of a semiconductor device according to a Second Embodiment of the present invention.
- FIG. 7 is a cross sectional view showing a mounting state of chips.
- FIG. 8 is a cross sectional view of a semiconductor device according to a Third Embodiment of the present invention.
- FIG. 9 is a cross sectional view of a semiconductor device according to a Fourth Embodiment of the present invention.
- FIG. 10 is a front view of a semiconductor device according to a Fifth Embodiment of the present invention.
- FIG. 11 is a cross sectional view of the semiconductor device of FIG. 10, taken along the line C-C.
- FIG. 12 is a cross sectional view of a liquid crystal module to which the semiconductor device shown in FIGS. 10 and 11 is to be mounted.
- FIG. 13 is a front view of a semiconductor device which is one modification example of the Fifth Embodiment of the present invention.
- FIG. 14 is a front view for explaining a conventional mounting method for a semiconductor device.
- FIG. 15 is a cross sectional view of the semiconductor device of FIG. 14, taken along the line A-A.
- The following will explain a First Embodiment of the present invention with reference to FIGS.1 to 5.
- FIG. 1 is a front view of a semiconductor device according to the First Embodiment of the present invention, and FIG. 2 is a cross sectional view of this semiconductor device, taken along a line B-B. A surface of a substrate (organic base material)11 composed of an organic material such as polyimide is patterned to have a Cu wiring pattern (wiring pattern) 12, thereby forming a
tape 13. TheCu wiring pattern 12 has extendingportions substrate 11, so that the extendingportions - On the
substrate 11 are formed device holes 16 and 17 in correspondence withsemiconductor chips Cu wiring pattern 12 is lead into the device holes 16 and 17, thereby becominginner leads 12 c. Portions of theCu wiring pattern 12 such as theinner lead 12 c and the extendingportions - In the present invention, the semiconductor chips14 and 15 individually have a lengthwise rectangular shape whose aspect ratio (a ratio of a long side to a short side) is not less than 10. The semiconductor chips 14 and 15 are mounted so as to be substantially perpendicular to an extending direction of the
Cu wiring pattern 12. The inner leads 12 c, in correspondence with Au bumps 18 disposed along each long side of the semiconductor chips having the lengthwise rectangular shape, project to the interior of each of the device holes 16 and 17. The Au bumps of the semiconductor chips 14 and 15 are subject to eutectic bonding with the Sn which was applied to the inner leads 12 c by electroless plating, thus connected by the ILB. - The
semiconductor chip 14 is an SRAM having, for example, a chip area of 16 mm×1.6 mm and a thickness of 400 μm, which is manufactured according to a process (design rule) of not more than 0.35 μm. Further, thesemiconductor chip 15 is a driver IC having, for example, a chip area of 11 mm×1 mm and a thickness of 625 μm, which is manufactured according to a process (design rule) of 0.65 μm. The SRAM requires more elements than a DRAM and others, but is capable of low power consumption and desirable as a memory to be disposed adjacent to a liquid crystal driver IC. In addition, by thus having the lengthwise rectangular shape, the SRAM can be disposed adjacent to the driver IC. Note that, either one of the semiconductor chips 14 and 15 may be a controller-use IC which may alternatively be provided in addition to the SRAM and the liquid crystal driver IC as being the semiconductor chips 14 and 15, respectively. When thus providing the controller-use IC in addition to the SRAM and the liquid crystal driver IC as the semiconductor chips 14 and 15, respectively, for example, an arrangement as shown in FIG. 8 to be discussed later is available, where asemiconductor chip 44 serves as the controller-use IC. Note that, the controller-use IC herein has a function which will be explained below. For example, in order to perform display on a screen in a TFT liquid crystal panel, it is necessary to distribute a voltage to be applied to each pixel with respect to every pixel for display of a certain image at a timing corresponding to the display of the image. The controller-use IC has the function to make this timing. - In the present invention, it is the
semiconductor chip 14 which is bonded first, which is followed by the bonding of thesemiconductor chip 15 by the same bonding tool. Thus, a difference in thickness between these twosemiconductor chips semiconductor chip 14 that has been bonded first, given by a contact with the bonding tool when bonding thesemiconductor chip 15 for the second time. This enables the semiconductor chips 14 and 15 to be mounted in the vicinity, greatly reduces restriction on a mounting position of a chip, and allows a spacious design, for example, in the routing of theCu wiring pattern 12. - Note that, the smaller a mounting interval between the semiconductor chips14 and 15 is, the
tape 13 can also have a smaller width; however, taking into consideration an interaction with the bonding tool, the mounting interval needs to be in a range of 0.5 mm to 3 mm. Conditions for the ILB was such that a connection load per a bump is 30 gf, connection time is 3 seconds, and a bonding tool has a temperature of 400° C., thereby attaining electrical conduction between theCu wiring pattern 12 including 100 wires or more and the semiconductor chips 14 and 15. - FIG. 3 is a front view of a
plate 21 which is used in the ILB, and FIG. 4 is a cross sectional view showing a mounting state of chips. Thisplate 21 is made of, for example, an invar material (an alloy containing 36% of Ni and 64% of Fe) having a film thickness of 0.5 mm, and haveblanks 21 a and 21 b respectively corresponding to the sizes of, and the interval between, the semiconductor chips 14 and 15 to be connected by the ILB. After mutually positioning the device holes 16 and 17, and theblanks 21 a and 21 b of theplate 21, connection is made by the ILB under the foregoing conditions. Theplate 21 supports thetape 13, thereby preventing distortion such as deformation due to bending in thetape 13 which may occur when pressed by atool 22 in the bonding. - Periphery W including device surfaces of the semiconductor chips14 and 15 thus mounted, and the inner leads 12 c are sealed with a
resin 19, thereby maintaining the mechanical strength while being protected from surrounding environment. The sealing with resin is performed as follows: after the ILB, the required amount of liquid resin, 30 mg per 5 seconds for example, is dropped from the device surfaces of the semiconductor chips 14 and 15, thereafter performing thermal processing at 120° C. for 20 minutes. Accordingly, the device surfaces of the semiconductor chips 14 and 15 are covered as indicated by areference numeral 19 a, while forming afillet 19 b on a side with resin seeped through the device surfaces. Allowing resin to be set on the device surfaces and the sides of the semiconductor chips 14 and 15 realizes firmer hold and seal. - Note that, the
tape 13 is protected by a covering of a solder resist 20, except for electrode portions thereof such as the inner leads 12 c. The foregoing processes are sequentially performed while the semiconductor chips 14 and 15 remain on thetape 3, thereby efficiently performing mounting. - FIG. 5 is a front view of a liquid crystal module which is one mounting example of the semiconductor device having the foregoing arrangement. This liquid crystal module is used as a display of a terminal device of a cellular phone, which includes a
liquid crystal panel 30 and thesingle tape 13 connected to each other. Note that, as the semiconductor device of FIG. 5 may be adopted any of semiconductor devices according to Second to Fifth Embodiments to be discussed below. - As discussed, in the present invention, the semiconductor chips14 and 15 having the lengthwise rectangular shape are mounted so as to be perpendicular to the extending direction of the
Cu wiring pattern 12, thereby making it possible to dispose a plurality of wires of theCu wiring pattern 12 so as to be substantially parallel to each other and substantially straight-line along the extendingportions chips tape 13 and the semiconductor chips 14 and 15 to have a similar shape, and, in the mounting of a plurality of the semiconductor chips 14 and 15 can be reduced the width of thetape 13, and therefore the size of a device to be connected (the liquid crystal panel 30). - In the present invention, the semiconductor chips14 and 15 are given long sides so as to enable numerous Au bumps 18 as being I/O terminals on the semiconductor chips 14 and 15 to be disposed on the same row so that numerous wires of the
Cu wiring pattern 12 as being output signal wiring can be routed straight toward the extendingportions - For example, when the semiconductor chips14 and 15 have each a long side of about 17 mm, and when adopting a fine pitch having a minimum pad pitch of 50 μm, it is possible to secure about 540 I/O terminals. In this case, in order to secure the area corresponding to elements and circuits provided within the semiconductor chips 14 and 15 according to the process of the design rule of 0.65 μm, the semiconductor chips 14 and 15 each should have a short side of at least 1.6 mm.
- The following will explain a Second Embodiment of the present invention with reference to FIGS. 6 and 7.
- FIG. 6 is a cross sectional view of a semiconductor device according to the Second Embodiment of the present invention. In contrast to the TCP configuration adopted by the semiconductor device shown in FIGS.1 to 4, the present semiconductor device adopts the COF configuration, but the corresponding members will be given the same reference numerals, and explanation thereof will be omitted here. A surface of a
substrate 31 composed of the organic material is patterned to have aCu wiring pattern 32, thereby forming atape 33. TheCu wiring pattern 32 is given Ni plating (not shown) and, further, Au plating (not shown). - On the
tape 33 is mounted the semiconductor chips 14 and 15 by flip chip bonding. The mounting, as shown in FIG. 7, is performed as follows: after positioning and placing thetape 33 on abase 34, thetool 22 is used to connect, for example, the Au bumps 18 and electrodes by Au-Au thermo-compression bonding. For example, conditions for the connection are, for example, 450° C., 170×10−4 gf/m2, and 2 seconds. - Thereafter, narrow spacings between the
tape 33 and each of the semiconductor chips 14 and 15, and the surroundings of the semiconductor chips 14 and 15 are sealed with theresin 19. The sealing with resin is made in such a manner that liquid resin is continuously dropped from along long-side edges of the semiconductor chips 14 and 15 to a surface of thetape 33, so as to fill the spacings between thetape 33 and each of the semiconductor chips 14 and 15 as indicated by areference numeral 19 a according to capillary action, and further, afillet 19 b is formed on a side of thesemiconductor chip reference numeral 19 c has an improved strength due to a linking state of the resin. - The present invention can thus be applied to the COF configuration.
- The following will explain a Third Embodiment of the present invention with reference to FIG. 8.
- FIG. 8 is a cross sectional view of a semiconductor device according to the Third Embodiment of the present invention. This semiconductor device is similar to the semiconductor device shown in FIGS.1 to 4, 6 and 7, and the corresponding members will be given the same reference numerals, and explanation thereof will be omitted here. In the present semiconductor device, a surface of a
substrate 41 composed of the organic material is patterned to have aCu wiring pattern 42, thereby forming atape 43. Thetape 43 includes the device holes 16 and 17, thereby connecting the semiconductor chips 14 and 15 by the ILB. In addition, onto thetape 43 is connected asemiconductor chip 44 by the flip chip bonding. Namely, the present semiconductor device has the TCP and COF configurations in combination. - The semiconductor chips15 and 44 are mounted on the side of the
Cu wiring pattern 42, while thesemiconductor chip 14 is mounted on the side of the substrate 41 (it may also be arranged such that thesemiconductor chip 14 is mounted on the side of theCu wiring pattern 42 and thesemiconductor chip 15 is mounted on the side of the substrate 41). The semiconductor chips 14 and 15 are given the Au bumps 18 which are connected to the inner leads 12 c subject to the Sn plating, by eutectic bonding. Thesemiconductor chip 44 has the Au bumps 18 which are connected to electrodes by the Au-Au thermo-compression bonding. The semiconductor chips 14 and 15 thus mounted on thetape 43 are adjacent to each other, and the resin is applied therebetween in the linking state as indicated by areference numeral 19 c, thereby improving the mechanical strength. - The following will explain a Fourth Embodiment of the present invention with reference to FIG. 9.
- FIG. 9 is a cross sectional view of a semiconductor device according to the Fourth Embodiment of the present invention. This semiconductor device is similar to the semiconductor device shown in FIG. 8, and the corresponding members will be given the same reference numerals, and explanation thereof will be omitted. In the present semiconductor device, on the
tape 43 are mounted one or moreelectric members 45 and 46 such as a resistor and a capacitor, other than the semiconductor chips 14 and 15. Theelectric members 45 and 46 are mounted in such a manner that soldering paste is initially printed with a metal mask, then, theelectric members 45 and 46 are mounted next, which is followed by the application of solder in a thermal atmosphere at a peak temperature of 240° C. The twosemiconductor chips - The
electric members 45 and 46 may be mounted between the twosemiconductor chips - The following will explain a Fifth Embodiment of the present invention with reference to FIGS.10 to 12.
- FIG. 10 is a front view of a semiconductor device according to the Fifth Embodiment of the present invention, and FIG. 11 is a cross sectional view of this semiconductor device of FIG. 10, taken along a line C-C. The present semiconductor device is similar to the semiconductor device shown in FIGS. 7 and 8, and the corresponding members will be given the same reference numerals, and explanation thereof will be omitted. What should be noted in the present semiconductor device is that the
substrate 31 composed of the organic material includes aslit 52 between the semiconductor chips 14 and 15, while providing part of theCu wiring pattern 12 between thechips - The
slit 52 and the blank portions are provided so as to enable thetape 53 to be easily bent without impairing the strength, and these are formed along a long-side direction of the semiconductor chips 14 and 15, and have a width of, for example, 100 μm. This enables thetape 53 to be flexibly bent, thereby reducing bending stress with respect to an area around the extendingportions - With this arrangement, as shown in FIG. 12, the
tape 53 can be bent, and bonding back surfaces of the semiconductor chips 14 and 15 with an adhesive 54 greatly reduces an area occupied by thetape 53. FIG. 12 is a cross sectional view of a liquid crystal module on which the semiconductor device shown in FIGS. 10 and 11 is to be mounted, where thetape 53 is bent, thereby greatly contributing to the miniaturization of the liquid crystal module. - Note that, as one modification example of the configuration shown in FIG. 10, a configuration as shown in FIG. 13 is also applicable. FIG. 13 is a front view of a semiconductor device which is a modification example of the Fifth Embodiment of the present invention, and members corresponding to those of the semiconductor device shown in FIG. 10 will be given the same reference numerals, and explanation thereof will be omitted. In the present configuration, among all the
Cu wiring pattern 12 on thetape 53, those indicated by areference numeral 12 e are wired across thesemiconductor chip 15 so as to be connected to thesemiconductor chip 14, and those indicated by areference numeral 12 d are wired across the semiconductor chips 14 and 15. By thus partially wiring theCu wiring pattern 12 across the semiconductor chips 14 and/or 15, various types of wire bound can be attained between in- and output, and between the semiconductor chips 14 and 15. Note that, the number of semiconductor chips across which theCu wiring pattern 12 is provided may be two or more, which should be selected depending on a circuit layout, as required. More specifically, it needs to be arranged such that theCu wiring pattern 12 from a semiconductor chip can be connected partially to another semiconductor chip or the outside, through at least one different semiconductor chip. Further, a portion of theCu wiring pattern 12 as indicated by a reference numeral 12 f is to connect the semiconductor chips 14 and 15, which was shown in other drawings such as FIG. 10. - Selection of the adhesive54 is made in accordance with reference potentials of the semiconductor chips 14 and 15. In order to prevent reduction in electrical performance, an insulating resin is adopted when the semiconductor chips 14 and 15 have different reference potentials, and an electrically conducting resin is adopted when the
chips portion 12 a of theCu wiring pattern 12 is electrically and mechanically connected to an electrode of theliquid crystal panel 30, via the anisotropic conductive film and the like. - Note that, a mounting method and the number of chips with regard to the semiconductor chips14 and 15; 44 are not limited to those explained above, and the same effect is attainable in any embodiments having a configuration according to the present invention.
- The embodiments and concrete examples of implementation discussed in the foregoing detailed explanation serve solely to illustrate the technical details of the present invention, which should not be narrowly interpreted within the limits of such embodiments and concrete examples, but rather may be applied in many variations within the spirit of the present invention, provided such variations do not exceed the scope of the patent claims set forth below.
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2000-106959 | 2000-04-07 | ||
JP2000106959A JP3798220B2 (en) | 2000-04-07 | 2000-04-07 | Semiconductor device and liquid crystal module using the same |
Publications (2)
Publication Number | Publication Date |
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US20010050431A1 true US20010050431A1 (en) | 2001-12-13 |
US6441474B2 US6441474B2 (en) | 2002-08-27 |
Family
ID=18620038
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/822,219 Expired - Lifetime US6441474B2 (en) | 2000-04-07 | 2001-04-02 | Semiconductor device and liquid crystal module adopting the same |
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Country | Link |
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US (1) | US6441474B2 (en) |
JP (1) | JP3798220B2 (en) |
KR (1) | KR100442728B1 (en) |
CN (1) | CN1184683C (en) |
TW (1) | TW515013B (en) |
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JPH0357233A (en) | 1989-07-26 | 1991-03-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPH04144142A (en) * | 1990-10-04 | 1992-05-18 | Toshiba Corp | Semiconductor device |
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2000
- 2000-04-07 JP JP2000106959A patent/JP3798220B2/en not_active Expired - Lifetime
-
2001
- 2001-04-02 US US09/822,219 patent/US6441474B2/en not_active Expired - Lifetime
- 2001-04-06 KR KR10-2001-0018353A patent/KR100442728B1/en active IP Right Grant
- 2001-04-06 TW TW090108320A patent/TW515013B/en not_active IP Right Cessation
- 2001-04-09 CN CNB011162740A patent/CN1184683C/en not_active Expired - Lifetime
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US20040199798A1 (en) * | 2003-04-03 | 2004-10-07 | Whelan Rochelle J. | Low power display refresh |
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US20080136033A1 (en) * | 2006-11-08 | 2008-06-12 | Sanyo Electric Co., Ltd. | Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus |
US7595553B2 (en) * | 2006-11-08 | 2009-09-29 | Sanyo Electric Co., Ltd. | Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus |
US20090304910A1 (en) * | 2006-11-08 | 2009-12-10 | Sanyo Electric Co., Ltd. | Packaging Board and Manufacturing Method Therefor, Semiconductor Module and Mobile Apparatus |
US8153186B2 (en) | 2006-11-08 | 2012-04-10 | Sanyo Eletric Co., Ltd. | Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus |
US20110169022A1 (en) * | 2008-09-29 | 2011-07-14 | Sharp Kabushiki Kaisha | Board module and method of manufacturing same |
US8450753B2 (en) | 2008-09-29 | 2013-05-28 | Sharp Kabushiki Kaisha | Board module and method of manufacturing same |
US20100194730A1 (en) * | 2009-01-30 | 2010-08-05 | Nec Electronics Corporation | Display driving semiconductor device |
US20160313838A1 (en) * | 2015-04-21 | 2016-10-27 | Lg Display Co., Ltd. | Touch Screen Integrated Display Device |
Also Published As
Publication number | Publication date |
---|---|
CN1317827A (en) | 2001-10-17 |
KR100442728B1 (en) | 2004-08-02 |
JP3798220B2 (en) | 2006-07-19 |
KR20010090758A (en) | 2001-10-19 |
JP2001291739A (en) | 2001-10-19 |
US6441474B2 (en) | 2002-08-27 |
TW515013B (en) | 2002-12-21 |
CN1184683C (en) | 2005-01-12 |
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