US20010048151A1 - Stackable ball grid array semiconductor package and fabrication method thereof - Google Patents
Stackable ball grid array semiconductor package and fabrication method thereof Download PDFInfo
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- US20010048151A1 US20010048151A1 US09/922,103 US92210301A US2001048151A1 US 20010048151 A1 US20010048151 A1 US 20010048151A1 US 92210301 A US92210301 A US 92210301A US 2001048151 A1 US2001048151 A1 US 2001048151A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73219—Layer and TAB connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a stackable ball grid array (BGA) semiconductor package and a fabrication method thereof.
- BGA ball grid array
- solder balls which are attached to a substrate are used as external terminals.
- a plurality of solder balls are attached to an upper or a lower surface of a substrate by the application of heat.
- the solder balls which act as external terminals, are not easily bent or deformed by inpacts with solid objects.
- FIG. 1 shows a structure of a background art BGA semiconductor package.
- an elastomer 2 is attached to a center portion of an upper surface of a semiconductor chip 1 , and a high strength adhesive resin 3 is formed on the elastomer 2 .
- a plurality of metal traces, which transmit electric signals, are formed on the adhesive resin 3 .
- First ends 4 a of the metal traces extend across a top surface of the adhesive resin 3
- second ends 4 b of each of the metal 5 traces are connected to chip pads 6 formed on a marginal portion of the upper surface of the semiconductor chip 1 .
- a solder resist 5 covers the metal traces 4 a and the adhesive resin 3 , except for exposed portions of the first ends 4 a of the metal traces, onto which solder balls will be attached.
- An encapsulant 7 such as a molding resin, covers the upper surface of the semiconductor chip 1 , and the portions of the metal 10 traces that are not covered with the solder resist 5 .
- Conductive balls 8 are then attached to the exposed portions of the metal traces to serve as output terminals.
- a stackable chip package embodying the invention includes a supporting member having a plurality of conductive patterns formed therein.
- a plurality of first conductive traces are formed on a surface of the supporting member, and respective ones of the first conductive traces are coupled to corresponding ones of the conductive patterns.
- a chip having chip pads is attached to a second surface of the supporting member, and a plurality of second conductive traces are arranged over the chip. Respective ones of the second conductive traces are electrically coupled to corresponding chip pads on the chip, and corresponding ones of the conductive patterns in the supporting member.
- An embodiment of the invention could also include a solder resist that covers selected portions of the first and second conductive traces. The solder resist would leave connecting portions of the first and second conductive traces exposed.
- Exterior leads in the form of conductive balls, could then be connected to the connecting portions of the first and second conductive traces.
- a device embodying the invention could also include a molding resin that encapsulates portions of the conductive traces and the chip.
- the supporting member could include a supporting plate and a supporting frame that surrounds the supporting plate.
- a supporting member having a plurality of conductive patterns is first formed.
- a plurality of first conductive traces are then formed on a first surface of the supporting member such that the conductive traces are electrically coupled to corresponding ones of the conductive patterns in the supporting member.
- a plurality of second traces are then attached to a surface of a chip, and the chip is attached to a second surface of the supporting member. Respective ones of the second conductive traces are attached to corresponding chip pads on the chip, and to corresponding ones of the conductive patterns in the supporting member.
- a method embodying the invention could also include the step of forming layers of solder resist over the first and second conductive traces, and removing portions of the solder resist to expose connecting portions of the first and second conductive traces.
- a method embodying the invention could also include attaching leads, in the form of conductive balls, to respective ones of the exposed connecting portions of the first and second conductive traces.
- FIG. 1 is a vertical cross-sectional diagram of a background art BGA semiconductor package
- FIG. 2 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a first embodiment of the present invention
- FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention.
- FIG. 4 is a vertical cross-sectional diagram of stacked BGA semiconductor packages according to the present invention.
- FIGS. 5A through 5H illustrate steps of a method of manufacturing a stackable BGA semiconductor package according to the present invention.
- FIG. 2 illustrates a stackable BGA semiconductor package according to a first embodiment of the present invention.
- a supporting member 21 includes a supporting plate 23 surrounded by a supporting frame 25 having a predetermined height.
- Metal traces 24 a are attached to a lower surface of the supporting plate 23 .
- a solder resist 27 covers portions of the metal traces 24 a and the supporting plate 23 to prevent short circuiting between solder balls and the metal traces, and to protect the metal traces 24 a from outside impacts.
- the solder resist 27 is partially removed to expose portions of the metal traces 24 a .
- the exposed portions of the metal traces 24 a act as connecting portions 24 b .
- the connecting portions 24 b are used to electrically connect the metal traces 24 a to conductive balls that act as external terminals.
- Metal patterns 26 are formed between upper and lower surfaces of the supporting frame 25 . One end of each of the metal patterns 26 is connected with an end of each of the metal traces 24 a . The other end of each of the metal patterns 26 is exposed at the upper surface of the supporting frame 25 .
- a semiconductor chip 1 is attached by an adhesive onto the supporting plate 23 of the supporting member 21 .
- An elastomer 2 is attached to a center portion of the upper surface of the semiconductor chip 1 , and a high strength adhesive resin 3 is formed on the elastomer 2 .
- Metal traces which transmit electric signals are attached onto the adhesive resin 3 .
- First ends 4 a of the metal traces extend over the top surface of the adhesive resin.
- Middle portions 4 b of the metal traces are connected with chip pads 6 formed on a marginal portion of the upper surface of the semiconductor chip 1 .
- Second ends 4 c of the metal traces are connected with upper surfaces of the metal patterns 26 formed in the supporting frame 25 .
- a solder resist 5 covers the upper surface of the adhesive resin 3 and portions of the first ends 4 a of the metal traces. Conductive balls 8 a are attached to the exposed portions of the first ends 4 a of the metal traces.
- An encapsulant 28 such as a molding resin, covers exposed portions of the upper surface of the semiconductor chip 1 , the metal traces, and the upper portion of the supporting frame 25 .
- Electrical signals which are output by the semiconductor chip 1 through the chip pads 6 can be externally transmitted over the conductive balls 8 a connected with the first ends 4 a of the metal traces.
- the electrical signals can also be externally transmitted through the connecting portions 24 b on the lower part of the supporting member 21 , which are connected to the second ends 4 c of the metal traces through the metal patterns 26 .
- FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention.
- the second embodiment is the same as the embodiment shown in FIG. 2, except that conductive balls 8 b are also attached to the exposed portions 24 b , of the metal traces 24 a formed on the lower part of the supporting member 21 .
- FIG. 4 illustrates stacked BGA semiconductor packages using the stackable BGA semiconductor package according to the first embodiment of the present invention shown in FIG. 2.
- a plurality of stackable BGA semiconductor packages 100 , 110 , 120 , 130 are stacked.
- Conductive balls 108 a which are formed on an upper surface of the first package 100 , connect the first ends 4 a of the metal traces on the first package 100 to the connecting portions 24 b formed on a lower surface of the second BGA semiconductor package 110 .
- Conductive balls 118 a formed on an upper surface of the second package 110 connect the first ends 4 a of the metal traces on the second package 110 to the connecting portions 24 b on a lower surface of the third BGA semiconductor package 120 .
- Conductive balls 128 a formed on an upper surface of the third package 120 connect the first ends 4 a of the metal traces on the third package 120 to the connecting portions 24 b on a lower surface of the fourth package 130 .
- FIG. 4 illustrates four stacked BGA packages, but the actual number of stacked BGA packages may be variously adjusted by a user according to his requirements.
- Conductive balls 138 a formed on the fourth package 130 can serve as external terminals which transmit signals from all the BGA packages to external circuits. For instance, the conductive balls 138 a could be connected to pads of a printed circuit board.
- FIGS. 5 A- 5 H A method of fabricating a stackable BGA semiconductor chip package according to the present invention will now be described with reference to FIGS. 5 A- 5 H.
- the supporting member 21 includes the supporting plate 23 and the supporting frame 25 .
- Metal traces 24 a are formed on a lower surface of the supporting plate 23 .
- the solder resist 27 covers portions of the metal traces 24 a , but leaves the connecting portions 24 b exposed.
- the metal patterns 26 formed in the supporting frame 25 are exposed at the upper surface of the supporting frame 25 , and are connected with the metal traces 24 a on the bottom of the supporting plate 23 .
- the semiconductor chip 1 which has chip pads 6 on a marginal portion of an upper surface thereof, is connected to a lower surface of an elastomer 2 .
- a high strength adhesive 3 is attached to an upper surface of the elastomer 2 .
- the metal traces are then attached to the upper surface of the adhesive 3 .
- First end portions of each of the metal traces are attached to the adhesive 3 , and the other end portions thereof extend from outer sides of the adhesive 3 .
- a layer of the solder resist 5 is formed on the metal traces and on the adhesive resin 3 .
- the chip pads 6 formed on the semiconductor chip 1 are connected to the middle portions 4 b of the metal traces by pressing down the middle portions 4 b.
- second ends 4 c of the metal traces are cut off by the bond tool 30 , and the second ends 4 c are connected with upper surfaces of the metal patterns 26 in the supporting frame 25 .
- a molding resin 28 is molded over the package so that it covers the exposed portions of the metal traces and the exposed portions of the chip 1 and chip pads 6 .
- portions of the solder resist 5 formed on the metal traces is removed to expose portions of the first ends 4 a of the metal traces that will be connected to conductive balls.
- the conductive balls 8 a are then placed on the exposed portions of the first ends 4 a of the metal traces, and a reflow process is performed to attach the conductive balls 8 a to the metal traces.
- One BGA package embodying the invention can be attached to a second BGA package embodying the invention by stacking the second package on the first package so that conductive balls on the first package align with corresponding connecting portions on a bottom surface of the second package, and then performing a reflow process to connect the two packages.
- metal traces and a conductive region in a semiconductor may not be structural equivalents in that metal traces use metal as an electrical conductor, whereas the conductive region in a semiconductor relies on charge carriers in the material to provide electrical conductivity, in the environment of conducting electricity, metal traces and a conductive region of a semiconductor may be equivalent structures.
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
- This application is a divisional of application Ser. No. 09/239,152, filed Jan. 28, 1999.
- 1. Field of the Invention
- The present invention relates to a stackable ball grid array (BGA) semiconductor package and a fabrication method thereof.
- 2. Background of the Related Art
- Currently, there is an effort to produce a highly integrated semiconductor package having a large number of exterior connections. One example is a BGA semiconductor package in which a plurality of solder balls which are attached to a substrate are used as external terminals. In these BGA packages, a plurality of solder balls are attached to an upper or a lower surface of a substrate by the application of heat. The solder balls, which act as external terminals, are not easily bent or deformed by inpacts with solid objects.
- FIG. 1 shows a structure of a background art BGA semiconductor package. As seen in FIG. 1, an
elastomer 2 is attached to a center portion of an upper surface of asemiconductor chip 1, and a high strengthadhesive resin 3 is formed on theelastomer 2. A plurality of metal traces, which transmit electric signals, are formed on theadhesive resin 3.First ends 4 a of the metal traces extend across a top surface of theadhesive resin 3, andsecond ends 4 b of each of themetal 5 traces are connected tochip pads 6 formed on a marginal portion of the upper surface of thesemiconductor chip 1. Asolder resist 5 covers themetal traces 4 a and theadhesive resin 3, except for exposed portions of thefirst ends 4 a of the metal traces, onto which solder balls will be attached. An encapsulant 7, such as a molding resin, covers the upper surface of thesemiconductor chip 1, and the portions of the metal 10 traces that are not covered with thesolder resist 5.Conductive balls 8 are then attached to the exposed portions of the metal traces to serve as output terminals. - Since the conductive balls are exposed on only one side of the package (in FIG. 1, the conductive balls are exposed at the upper surface thereof), it is impossible to fabricate a stackable package of high mount density.
- It is an object of the present invention to provide a stackable BGA semiconductor package, and a fabrication method thereof, that maintain advantages of the conventional BGA package.
- A stackable chip package embodying the invention includes a supporting member having a plurality of conductive patterns formed therein. A plurality of first conductive traces are formed on a surface of the supporting member, and respective ones of the first conductive traces are coupled to corresponding ones of the conductive patterns. A chip having chip pads is attached to a second surface of the supporting member, and a plurality of second conductive traces are arranged over the chip. Respective ones of the second conductive traces are electrically coupled to corresponding chip pads on the chip, and corresponding ones of the conductive patterns in the supporting member. An embodiment of the invention could also include a solder resist that covers selected portions of the first and second conductive traces. The solder resist would leave connecting portions of the first and second conductive traces exposed. Exterior leads, in the form of conductive balls, could then be connected to the connecting portions of the first and second conductive traces. A device embodying the invention could also include a molding resin that encapsulates portions of the conductive traces and the chip. The supporting member could include a supporting plate and a supporting frame that surrounds the supporting plate.
- In a method embodying the invention, a supporting member having a plurality of conductive patterns is first formed. A plurality of first conductive traces are then formed on a first surface of the supporting member such that the conductive traces are electrically coupled to corresponding ones of the conductive patterns in the supporting member. A plurality of second traces are then attached to a surface of a chip, and the chip is attached to a second surface of the supporting member. Respective ones of the second conductive traces are attached to corresponding chip pads on the chip, and to corresponding ones of the conductive patterns in the supporting member. A method embodying the invention could also include the step of forming layers of solder resist over the first and second conductive traces, and removing portions of the solder resist to expose connecting portions of the first and second conductive traces. A method embodying the invention could also include attaching leads, in the form of conductive balls, to respective ones of the exposed connecting portions of the first and second conductive traces.
- Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
- The accompanying drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawing figures, like elements are identified with like reference numerals, and:
- FIG. 1 is a vertical cross-sectional diagram of a background art BGA semiconductor package;
- FIG. 2 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a first embodiment of the present invention;
- FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention;
- FIG. 4 is a vertical cross-sectional diagram of stacked BGA semiconductor packages according to the present invention; and
- FIGS. 5A through 5H illustrate steps of a method of manufacturing a stackable BGA semiconductor package according to the present invention.
- FIG. 2 illustrates a stackable BGA semiconductor package according to a first embodiment of the present invention. As shown in FIG. 2, a supporting
member 21 includes a supportingplate 23 surrounded by a supportingframe 25 having a predetermined height.Metal traces 24 a are attached to a lower surface of the supportingplate 23. In addition, a solder resist 27 covers portions of themetal traces 24 a and the supportingplate 23 to prevent short circuiting between solder balls and the metal traces, and to protect themetal traces 24 a from outside impacts. Thesolder resist 27 is partially removed to expose portions of themetal traces 24 a. The exposed portions of the metal traces 24 a act as connectingportions 24 b. The connectingportions 24 b are used to electrically connect themetal traces 24 a to conductive balls that act as external terminals. -
Metal patterns 26 are formed between upper and lower surfaces of the supportingframe 25. One end of each of themetal patterns 26 is connected with an end of each of themetal traces 24 a. The other end of each of themetal patterns 26 is exposed at the upper surface of the supportingframe 25. - A
semiconductor chip 1 is attached by an adhesive onto the supportingplate 23 of the supportingmember 21. Anelastomer 2 is attached to a center portion of the upper surface of thesemiconductor chip 1, and a high strengthadhesive resin 3 is formed on theelastomer 2. Metal traces which transmit electric signals are attached onto theadhesive resin 3.First ends 4 a of the metal traces extend over the top surface of the adhesive resin.Middle portions 4 b of the metal traces are connected withchip pads 6 formed on a marginal portion of the upper surface of thesemiconductor chip 1. Second ends 4 c of the metal traces are connected with upper surfaces of themetal patterns 26 formed in the supportingframe 25. - A solder resist5 covers the upper surface of the
adhesive resin 3 and portions of the first ends 4 a of the metal traces.Conductive balls 8 a are attached to the exposed portions of the first ends 4 a of the metal traces. Anencapsulant 28, such as a molding resin, covers exposed portions of the upper surface of thesemiconductor chip 1, the metal traces, and the upper portion of the supportingframe 25. - Electrical signals which are output by the
semiconductor chip 1 through thechip pads 6 can be externally transmitted over theconductive balls 8 a connected with the first ends 4 a of the metal traces. The electrical signals can also be externally transmitted through the connectingportions 24 b on the lower part of the supportingmember 21, which are connected to the second ends 4 c of the metal traces through themetal patterns 26. - FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention. The second embodiment is the same as the embodiment shown in FIG. 2, except that
conductive balls 8 b are also attached to the exposedportions 24 b, of the metal traces 24 a formed on the lower part of the supportingmember 21. - With each of the embodiments shown in FIGS. 2 and 3, it becomes possible to stack a plurality of BGA semiconductor packages over a single mounting position on a printed circuit board. Thus, the density of the semiconductor devices on a circuit board can be increased by using BGA packages embodying the invention.
- FIG. 4 illustrates stacked BGA semiconductor packages using the stackable BGA semiconductor package according to the first embodiment of the present invention shown in FIG. 2. As shown therein, a plurality of stackable BGA semiconductor packages100, 110, 120, 130 are stacked.
Conductive balls 108 a, which are formed on an upper surface of thefirst package 100, connect the first ends 4 a of the metal traces on thefirst package 100 to the connectingportions 24 b formed on a lower surface of the secondBGA semiconductor package 110.Conductive balls 118 a formed on an upper surface of thesecond package 110 connect the first ends 4 a of the metal traces on thesecond package 110 to the connectingportions 24 b on a lower surface of the thirdBGA semiconductor package 120.Conductive balls 128 a formed on an upper surface of thethird package 120 connect the first ends 4 a of the metal traces on thethird package 120 to the connectingportions 24 b on a lower surface of thefourth package 130. - FIG. 4 illustrates four stacked BGA packages, but the actual number of stacked BGA packages may be variously adjusted by a user according to his requirements.
Conductive balls 138 a formed on thefourth package 130 can serve as external terminals which transmit signals from all the BGA packages to external circuits. For instance, theconductive balls 138 a could be connected to pads of a printed circuit board. - A method of fabricating a stackable BGA semiconductor chip package according to the present invention will now be described with reference to FIGS.5A-5H.
- In FIG. 5A, first the supporting
member 21 is provided. The supportingmember 21, includes the supportingplate 23 and the supportingframe 25. Metal traces 24 a are formed on a lower surface of the supportingplate 23. The solder resist 27 covers portions of the metal traces 24 a, but leaves the connectingportions 24 b exposed. Themetal patterns 26 formed in the supportingframe 25, are exposed at the upper surface of the supportingframe 25, and are connected with the metal traces 24 a on the bottom of the supportingplate 23. - As shown in FIG. 5B, the
semiconductor chip 1, which haschip pads 6 on a marginal portion of an upper surface thereof, is connected to a lower surface of anelastomer 2. Ahigh strength adhesive 3 is attached to an upper surface of theelastomer 2. The metal traces are then attached to the upper surface of the adhesive 3. First end portions of each of the metal traces are attached to the adhesive 3, and the other end portions thereof extend from outer sides of the adhesive 3. Next, a layer of the solder resist 5 is formed on the metal traces and on theadhesive resin 3. - Next, as shown in FIG. 5C, the semiconductor chip assembly shown in FIG. 5B is attached to the supporting
member 21 shown in FIG. 5A. - In FIG. 5D, using a
bond tool 30, thechip pads 6 formed on thesemiconductor chip 1 are connected to themiddle portions 4 b of the metal traces by pressing down themiddle portions 4 b. - As shown in FIG. 5E, second ends4 c of the metal traces are cut off by the
bond tool 30, and the second ends 4 c are connected with upper surfaces of themetal patterns 26 in the supportingframe 25. - As shown in FIG. 5F and 5G, a
molding resin 28 is molded over the package so that it covers the exposed portions of the metal traces and the exposed portions of thechip 1 andchip pads 6. Next, portions of the solder resist 5 formed on the metal traces is removed to expose portions of the first ends 4 a of the metal traces that will be connected to conductive balls. - As shown in FIG. 5G, the
conductive balls 8 a are then placed on the exposed portions of the first ends 4 a of the metal traces, and a reflow process is performed to attach theconductive balls 8 a to the metal traces. - One BGA package embodying the invention can be attached to a second BGA package embodying the invention by stacking the second package on the first package so that conductive balls on the first package align with corresponding connecting portions on a bottom surface of the second package, and then performing a reflow process to connect the two packages.
- The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. For example, although metal traces and a conductive region in a semiconductor may not be structural equivalents in that metal traces use metal as an electrical conductor, whereas the conductive region in a semiconductor relies on charge carriers in the material to provide electrical conductivity, in the environment of conducting electricity, metal traces and a conductive region of a semiconductor may be equivalent structures.
Claims (26)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/922,103 US6407448B2 (en) | 1998-05-30 | 2001-08-06 | Stackable ball grid array semiconductor package and fabrication method thereof |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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KR98-20098U | 1998-05-30 | ||
KR1019980020098A KR100266693B1 (en) | 1998-05-30 | 1998-05-30 | Stackable ball grid array semiconductor package and fabrication method thereof |
KR20098/1998 | 1998-05-30 | ||
US09/239,152 US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
US09/922,103 US6407448B2 (en) | 1998-05-30 | 2001-08-06 | Stackable ball grid array semiconductor package and fabrication method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/239,152 Division US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010048151A1 true US20010048151A1 (en) | 2001-12-06 |
US6407448B2 US6407448B2 (en) | 2002-06-18 |
Family
ID=19537977
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/239,152 Expired - Lifetime US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
US09/922,103 Expired - Lifetime US6407448B2 (en) | 1998-05-30 | 2001-08-06 | Stackable ball grid array semiconductor package and fabrication method thereof |
Family Applications Before (1)
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US09/239,152 Expired - Lifetime US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
Country Status (4)
Country | Link |
---|---|
US (2) | US6291259B1 (en) |
JP (1) | JP3063032B2 (en) |
KR (1) | KR100266693B1 (en) |
DE (1) | DE19845316C2 (en) |
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Also Published As
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JPH11354669A (en) | 1999-12-24 |
KR19990086916A (en) | 1999-12-15 |
US6407448B2 (en) | 2002-06-18 |
US6291259B1 (en) | 2001-09-18 |
DE19845316A1 (en) | 1999-12-02 |
JP3063032B2 (en) | 2000-07-12 |
DE19845316C2 (en) | 2002-01-24 |
KR100266693B1 (en) | 2000-09-15 |
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