US20010020287A1

US20010020287A1 - Error correcting apparatus

Info

Publication number: US20010020287A1
Application number: US09/753,884
Authority: US
Inventors: Tetsuya Yano; Kazuhisa Obuchi
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2000-02-17
Filing date: 2001-01-03
Publication date: 2001-09-06
Also published as: JP3857488B2; US6615386B2; JP2001230683A

Abstract

Disclosed herein is an error correcting apparatus for receiving a signal subjected to a repetition processing in which a part of bits of an error-correction code train are repeatedly transmitted, and decoding the received signal so as to be restored to the original data. A repetition rate calculator calculates the repetition rate of the received signal subjected to the repetition processing, a soft decision data cut-off position decision unit decides the position at which a part of the soft decision data is cut off from the soft decision data which is generated by the repetition regenerator, on the basis of the repetition rate Rr, and a bit selector cuts off the part of the soft decision data at the decided cut-off position and inputs the cut part into a soft decision error-correction decoder.

Description

BACKGROUND OF THE INVENTION

The present invention relates to an error correcting apparatus and, more particularly, to an error correcting apparatus which receives a signal subjected to a repetition processing for repeatedly transmitting a part of bits of an error-correction code train, and which restores the received signal to the original data train by subjecting the signal to a repetition regeneration processing and an error correcting decoding processing.

An error-correction coding technique is adopted so as to correct an error contained in received information or regenerated information and to restore it to the correct original information. Various codes such as a convolutional code and a turbo code are known as an error-correction code, and the error-correction coding technique is applied to various systems. In CDMA mobile communication, for example, an error-

correction encoder

1 subjects information to be transmitted to an error-correction encoding processing, and a CDMA transmitter 2 subjects the code obtained with an error-correction code to a spread modulation processing and transmits it from an antenna, as shown in FIG. 12A. On the other hand, on the reception side, a soft decision error-correction decoder 4 subjects a soft decision data train obtained by the despreading operation and the RAKE combining operation of a CDMA receiver 3 to an error-correction processing, decodes the data and outputs the original transmitted information before the error-correction encoding processing, as shown in FIG. 12B. A soft decision data a 1-bit data represented by a plurality of bits depending upon the level.

FIG. 13 shows the structure of a CDMA transmitter in a mobile station. The error-correction encoder 1 subjects a data to be transmitted to an error-correction encoding processing and inputs it into a mapping portion 21. A control data generator 22 generates a control data such as a pilot PILOT and inputs it into the mapping portion 21. The mapping portion 21 outputs an error-correction code as an in-phase component data, and the control data as quadrature component respectively for quadrature modulation at a constant symbol rate.

Spreaders

23 a, 23 b subject the in-phase (I) component and the quadrature (Q) component which are input from the mapping portion 21 to spreading modulation by using a predetermined spreading code, and input the spread data into

DA converters

25 a, 25 b, respectively, via

waveform shaping filters

24, 24 b. A QPSK quadrature modulator 26 subjects an I_chsignal, and a Q_chsignal output from each DA converter to QPSK quadrature modulation, and a radio transmitter 27 converts the frequency of a baseband signal output from the quadrature modulator 26 into a radio frequency (IF→RF), amplifies the frequency, and transmits the signal from an antenna.

FIG. 14 shows the structure of a

CDMA receiver

3 for 1 channel in a CDMA receiving apparatus at a base station. A radio receiver 31 converts the frequency of a high-frequency signal received from an antenna into a frequency of a baseband signal (RF→IF). A QPSK quadrature detector 32 subjects the baseband signal to quadrature detection and outputs an in-phase (I) component data and a quadrature (Q) component data. In the quadrature detector 32, the reference numeral 32 a denotes a receiving carrier generator, 32 b a phase shifter for shifting the phase of a receiving carrier by {fraction (π/2)}, and 32 c and 32 d multipliers for multiplying a baseband signal by a receiving carrier and outputting an I component signal and a Q component signal. Low-pass filters (LPF) 33 a, 33 b limit the band of an output signal, and

AD converters

35 a, 35 b convert an I component signal and a Q component signal, respectively, into digital signals, and input them into a searcher 36 and each of the finger portions 37 _a1to 37 _a4.

When a direct sequence signal (DS signal) influenced by a multi-path is input into the

searcher

36, the searcher 36 detects the multi-path by an autocorrelation operation using a matched filter (not shown), and inputs the data on the timing for starting the despreading operation and the data on the delay time adjustment in each path constituting the multi-path into the corresponding finger portions 37 _a1to 37 _a4. A despreading/adjustment time adjuster 41 of each of the finger portions 37 _a1to 37 _a4subjects a direct wave or a delayed wave which reaches via a predetermined path to a dispreading processing by using the same code as the spreading code for the purpose of dump integration, thereafter subjects it to a delay processing in accordance with the path and outputs a pilot signal (reference signal) and an information signal. A phase compensator (channel estimation unit) 42 averages the voltages of the I components and the Q components of the pilot signals for a predetermined number of slots, and outputs channel estimation signals I_t, Q_t. A synchronous detector 43 restores the phases of the despread information signals I′, Q′ to the original phases on the basis of the phase difference θ between the pilot signal contained in the received signal and a known pilot signal. That is, since the channel estimation signals I_t, Q_tare the cos component and the sin component of the phase difference θ, the synchronous detector 43 demodulates (executes synchronous detection of) the received information signals (I, Q) by applying a phase rotation processing to the received information signals (I′, Q′) by using the channel estimation signals I_t, Q_tin accordance with the following formula:

(\begin{matrix} I \\ Q \end{matrix}) = (\begin{matrix} I_{t} & Q_{t} \\ - Q_{t} & I_{t}, \end{matrix}) (\begin{matrix} I^{'} \\ Q^{'} \end{matrix})

A Rake combiner 37 b combines the signals output from the finger portions 37 _a1to 37 _a4, and outputs the combined signals to the soft decision error-correction decoder 4 (FIG. 12) as a soft decision data train.

FIG. 15 is an explanatory view of the frame format of an up signal transmitted from a mobile station to a base station. 1 frame is 10 msec and it is composed of 15 slots S₀˜S₁₄. The data portion is mapped in an orthogonal I channel for QPSK quadrature modulation, and the portions other than the data portion are mapped in an orthogonal Q channel for QPSK quadrature modulation. The channel transmitting the data portion is called a DPDCH (Dedicated Physical Data Channel), and the channel transmitting the portions other than data is called a DPCCH (Dedicated Physical Control Channel). Each slot of the DPDCH (I channel) transmitting the data portion is composed of n bits, and n changes in accordance with a symbol rate.

FIG. 16A shows the relationship among the symbol rate (ksps), the number n of bits per slot, and the data length Nm (=15×n) per frame in the data channel DPDCH. The data channel DPDCH multiplexes and transmits the data in more than 1 transport channels. For example, the data channel DPDCH divides sound data into a sound data portion with a high degree of importance and a sound data portion with a low degree of importance, allocates a predetermined number of bits per frame to the respective sound data, multiplexes and transmits the data in different transport channels.

Each slot of the DPCCH (Q channel) for transmitting a control data is composed of 10 bits (see FIG. 15), and transmits a pilot PILOT, a transmission power control data TPC, a transport format combination indicator TFCI, and feedback information FBI at a constant symbol rate of 15 ksps. It is possible to change the number of bits of PILOT, TPC, TFCI, and FBI as occasion demands, as shown in FIG. 16B. PILOT is utilized when the reception side performs synchronous detection or measures a signal interference ratio SIR, TPC is utilized for the control of a transmission power, TFCI indicates the symbol rate or the number of bits per frame of data, the number of bits of data which increases by repetition, etc., and FBI is used to control the diversity transmission in the base station.

FIGS. 17A and 17B are explanatory views of the frame format and the structure of the slots of a down signal transmitted from a base station to a mobile station. 1 frame is 10 msec, and it consists of 15 slots S ₀˜S₁₄. Each slot is constituted by k bits, wherein k varies in accordance with the symbol rate. Each slot transmits a first data portion DATA1, a second data portion DATA2, a pilot PILOT, a transmission power control data TPC, and a transport format combination indicator TFCI. The number of bits of PILOT, TPC, TFCI vary in accordance with the symbol rate, as shown in FIG. 17B, and even if the symbol rate is the same, the number of bits varies as occasion demands. The data in each slot is alternately distributed into the I channel and the Q channel for QPSK quadrature modulation, and after it is subjected to spread modulation and quadrature modulation, the data with the frequency converted is transmitted to the mobile station.

As shown in FIGS. 16A and 17B, the maximum number of bits (data length Nm) per frame of data which can be transmitted depends on the system of connection between stations such as a symbol rate. On the other hand, since the error-correction code length Nc which is obtained by applying an error-correction coding processing to information to be transmitted varies in accordance with the length N _Iof the information to be transmitted, the relationship Nc=Nm does not always hold. For this reason, if Nc<Nm, as shown in FIG. 18, the period S during which no data is transmitted generates. In addition, in the case of multiplexing information to be transmitted in a plurality of transport channels, the sum of the lengths of data in the plurality of transport channels does not usually coincide with the maximum data length Nm, and the period S during which no data are transmitted generates.

In order to effectively utilize the period S during which no data is transmitted, a repetition processing for repeatedly transmitting a part of bits of the error-correction code train is applied so as to make the total length of the information to be transmitted coincide with the maximum data length Nm. According to this repetition processing, the transmission energy per bit increases, which leads to an increase in the error-correction ability of the reception side.

FIGS. 19A and 19B show the structures of a transmission system and a reception system, respectively, provided with a repetition function. In the transmission system shown in FIG. 19A, a

repetition processor

5 is provided between the error-correction encoder 1 and the CDMA transmitter 2. In the reception system shown in FIG. 19B, a repetition regenerator 6 is provided between the CDMA receiver 3 and the soft decision error-correction decoder 4.

In the transmission system, the error-

correction encoder

1 subjects information to be transmitted to an error-correction coding processing and produces error-correction codes, and the repetition processor 5 subjects the error-correction codes to a repetition processing in accordance with a repetition algorithm. Due to the repetition processing, a part of the error-correction code train appears a plurality of times in the train subjected to the repetition processing, as shown in FIG. 20. In the example shown in FIG. 20, second, fifth, eighth, eleventh, fourteenth . . . bits are repeated. The CDMA transmitter 2 applies the spread modulation to the data which has been subjected to the repetition processing, and transmits the data.

In the reception system, the

CDMA receiver

3 demodulates a received signal, and inputs a soft decision data train A (see FIG. 21) having a predetermined bit width which is obtained by demodulation to the repetition regenerator 6. The repetition regenerator 6 executes a repetition algorithm so as to identify the bits (second, fifth, eighth, eleventh, fourteenth,. . . ) which are repeatedly transmitted due to the repetition processing, adds the soft decision data which corresponds to the bits, and converts the result into a soft decision data train B which corresponds to the original error-correction code train. The soft decision data is constituted by sign bits and soft decision bits. Thenceforth, the soft decision error-correction decoder 4 executes an error-correction decoding processing by using the soft decision data train B which is output from the repetition regenerator 6, and restores the data to the original data train before the error-correction coding processing.

Each of the

repetition processor

5 and the repetition regenerator 6 executes the following repetition algorithm. The parameters in the algorithm are as follows:

(1) N: number of bits of the data before the repetition processing

(2) ΔN: number of bits repeated due to the repetition

(3) (N+ΔN): number of bits of the data after the repetition processing

(4) e: parameter of the error which is updated in the algorithm (whether bits should be repeated or not is determined by judging the error e)

(5) e-ini: parameter used for determining the initial value of the error e

(6) e-plus: constant to be added to the error e when the error e is not more than 0 and predetermined bits are repeated (e-plus=a·N)

(7) e-minus: constant used for updating the error e (e-minus=a·AN)

(8) a: parameter used for determining e-plus or e-minus (e.g., a=2) In other words, execution of the repetition algorithm is enabled by giving the above 5 parameters N, ΔN, e-ini, e-plus, and e-minus, thereby enabling the decision of the repetition bits.

Repetition algorithm

e=e-ini

m=1 (m is an interested bit)

do while m≦N (execute the following as long as this relationship holds)

e=e−e-minus (e-minus=a·|ΔN|)

do while e≦0 (execute the following as long as this relationship holds)

repeat bit x _m(repeat m-th bit X_m)

e=e+e-plus (update e:e-plus=a·N)

end do

m=m+1 (increment the interested bit)

end do

As a concrete example of the repetition algorithm, an algorithm in which the number of multiplexed transport channels is 1, the data length N of the error-correction codes is 216 bits, and the data length (N+ΔN) after the repetition processing is 240 bits is shown in FIGS. 22 to 26. The parameters used in the repetition are N=216, ΔN=24, e-ini=1, e-plus=432 and-e minus=48. As is clear from FIGS. 22 to 26, when the sign of the error e is minus as a result of the subtraction of 48, the bit is repeated (RIS=“1”). In FIGS. 22 to 26, 1st, 10-th, 19-th, 28-th . . . 208-th bits are repeated.

As described above, the repetition regenerator 6 (FIG. 19) adds the bits which are repeatedly transmitted due to the repetition and generates the soft decision data train which corresponds to the original error-correction code train. As is clear from FIG. 21, the bit width of the soft decision data train increases by 1 bit due to the addition. In the example shown in FIG. 21, the number of soft decision bits is 5 including the sign bit before the repetition regeneration. However, after the repetition regeneration, the number of soft decision bits is 6 including the sign bit. In this manner, when the bit width of the soft decision data which is input into the error-correction decoder 4 increases, the circuit scale of the error-correction decoder 4 which uses a convolutional code or a turbo code inconveniently enlarges.

As a method for preventing the circuit scale of the error-

correction decoder

4 from being enlarged, there is known a method of inputting the soft decision data which is output from the repetition regenerator 6 into the error-correction decoder 4 after the bit width of the data is reduced. In this method, (the sign bit+upper m bits) or (the sign bit+lower m bits) are cut off from the soft decision data of (the sign bit+(m+1)) bits which is output from the repetition regenerator 6, and input into the error-correction decoder 4. In the example shown in FIG. 21, (1) (the sign bit+upper 4 bits) of the soft decision data train B are input into the error-correction decoder 4, or (2) (the sign bit+lower 4 bits) of the soft decision data train B are input into the error-correction decoder 4.

There is, however, a problem in reducing the bit width by cutting off a part of the data at the same bit position irrespective of the repetition rate Rr (=(N+ΔN)/N). That is, the amount of deterioration in the error-correction ratio in the error-

correction decoder

4 increases. FIG. 27 shows the relationship between the repetition rate and the amount of characteristic deterioration. In the case (1) of selecting the upper m bits, the smaller the repetition rate Rr is, the larger is the deterioration of the error-correction characteristic. In contrast, in the case (2) of selecting the lower m bits, the larger the repetition rate Rr is, the larger is the deterioration of the error-correction characteristic.

The reason is as follows. FIG. 28 shows the distribution of the signal having a predetermined size in correspondence with the repetition rate Rr. The larger the repetition rate Rr is, the larger is the range in which the most significant upper bit is valid (see the hatched area). In other words, as the repetition rate Rr becomes larger, it becomes more difficult to exactly represent the soft decision data output from the repetition regenerator by the lower m bits, while it is possible to represent them with accuracy by the upper m bits. As a result, when the repetition rate Rr becomes larger, the range where the most significant upper bit is valid enlarges, while when the repetition rate Rr becomes smaller, the range where the most significant upper bit is invalid enlarges, as shown in the tendency in FIG. 27.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to eliminate the above-described problems in the related art, and to reduce the bit width of a soft decision data after repetition regeneration without deteriorating the error-correction characteristic due to the reduction of the bit width.

To achieve this object, in a first aspect of the present invention, there is provided an error correcting apparatus comprising a repetition regenerator, a repetition rate calculator, a soft decision data cut-off position decision unit, and a soft decision data cutting means. The repetition regenerator obtains the positions of the bits which are repeatedly transmitted due to a repetition processing, adds the soft decision data corresponding to the positions of the bits and generates a soft decision data train which corresponds to the original error-correction code train. The repetition rate calculator calculates the repetition rate of a received signal which is subjected to the repetition processing. More specifically, the repetition rate calculator calculates the repetition rate Rr=(N+ΔN)/N on the basis of the number N of bits of the data which is notified of from the communication party before a repetition processing and the number ΔN of bits which are repeated due to the repetition. The soft decision data cut-off position decision unit decides the position at which a part of the soft decision data which is to be input into the soft decision error-correction decoder is cut off from the soft decision data which is produced by the repetition regenerator, on the basis of the repetition rate. The soft decision data cutting means cuts off the part of the soft decision data on the basis of the decided cut-off position and inputs it into the soft decision error-correction decoder.

The amount of characteristic deterioration increases or decreases depending upon the position at which the part of the soft decision data is cut off, but this tendency reverses at a predetermined repetition rate R TH. More specifically, if the actual repetition rate Rr is not more than RTH (Rr≦RTH), the amount of characteristic deterioration is smaller when the part of soft decision data is cut off at a first cut-off position which is the lower bit portion, but if Rr exceeds RTH (Rr>RTH), the amount of characteristic deterioration is smaller when the part of soft decision data is cut off at a second cut-off position which is the upper bit portion. According to an error correcting apparatus provided in a first aspect of the present invention, it is possible to suppress the deterioration of the characteristic by switching the position at which the part of the soft decision data is cut off on the basis of the repetition rate.

In a second aspect of the present invention, there is provided an error correcting apparatus comprising a repetition regenerator, an average value calculator, a soft decision data cut-off position decision unit, and a soft decision data cutting means. The repetition regenerator obtains the positions of the bits which are repeatedly transmitted due to a repetition processing, adds the soft decision data corresponding to the positions of the bits, and generates a soft decision data train which corresponds to the original error-correction code train. The average value calculator calculates the average value of the soft decision data which is output from the repetition regenerator. The soft decision data cut-off position decision unit decides the position at which the part of the soft decision data which is to be input into the soft decision error-correction decoder is cut off from the soft decision data which is output from the repetition regenerator, on the basis of the average value. The soft decision data cutting means cuts off the part of the soft decision data at the decided cut-off position and inputs it into the soft decision error-correction decoder.

The amount of characteristic deterioration increases or decreases depending upon the position at which the part of the soft decision data is cut off, but this tendency reverses at a predetermined average value VTH of the soft decision data. More specifically, if the actual average value Va of the soft decision data is not more than VTH (Va≦VTH), the amount of characteristic deterioration is smaller when the part of soft decision data is cut off at a first cut-off position which is the lower bit portion, but if Va exceeds VTH (Va>VTH), the amount of characteristic deterioration is smaller when the part of soft decision data is cut off at a second cut-off position which is the upper bit portion. According to an error correcting apparatus provided in a second aspect of the present invention, it is possible to suppress the deterioration of the characteristic by switching the position at which the part of the soft decision data is cut off on the basis of the average value of the soft decision data which is output from the repetition regenerator.

Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows the structure of a first embodiment of an error correcting apparatus according to the present invention; [0047]
FIG. 2 shows the relationship between a repetition rate and the characteristic deterioration; [0048]
FIG. 3 is an explanatory view of the repetition regeneration and the selection of a soft decision bit in the first embodiment; [0049]
FIG. 4 schematically shows the structure of a second embodiment of an error correcting apparatus according to the present invention; [0050]
FIG. 5 is an explanatory view of the repetition regeneration and the selection of a soft decision bit in the second embodiment; [0051]
FIG. 6 shows the structure of the first embodiment of an error correcting apparatus according to the present invention; [0052]
FIG. 7 is an explanatory view of the position at which a part of a soft decision data is cut off; [0053]
FIGS. 8A and 8B are explanatory views of a repetition regenerator; [0054]
FIG. 9 shows a modification of the first embodiment of an error-correction apparatus; [0055]
FIG. 10 shows the structure of a second embodiment of an error-correction apparatus according to the present invention; [0056]
FIG. 11 shows a modification of the second embodiment of an error-correction apparatus; [0057]
FIGS. 12A and 12B schematically show the structures of a conventional transmission system and a reception system, respectively; [0058]
FIG. 13 shows the structure of a CDMA transmitting apparatus; [0059]
FIG. 14 shows the structure of a CDMA receiver; [0060]
FIG. 15 is an explanatory view of the frame format of an up link; [0061]
FIGS. 16A and 16B are explanatory views of the structures of the data channel, and the control channel, respectively, of the up link; [0062]
FIGS. 17A and 17B are explanatory views of the structures of the data channel, and the control channel, respectively, of a down link; [0063]
FIG. 18 is an explanatory view of the necessity of a repetition processing; [0064]
FIGS. 19A and 19B show the structures of another conventional transmission system and another conventional reception system, respectively; [0065]
FIG. 20 is an explanatory view of a repetition processing; [0066]
FIG. 21 is an explanatory view of a repetition regeneration processing; [0067]
FIG. 22 is a first explanation table of bits to be repeated in accordance with a repetition algorithm; [0068]
FIG. 23 is a second explanation table of bits to be repeated in accordance with a repetition algorithm shows the structure of a conventional transmitting apparatus; [0069]
FIG. 24 is a third explanation table of bits to be repeated in accordance with a repetition algorithm; [0070]
FIG. 25 is a fourth explanation table of bits to be repeated in accordance with a repetition algorithm; [0071]
FIG. 26 is a fifth explanation table of bits to be repeated in accordance with a repetition algorithm; [0072]
FIG. 27 shows the relationship between the repetition rate and the characteristic deterioration; and [0073]
FIG. 28 is an explanatory view of the distribution of soft decision information before and after repetition regeneration. [0074]

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(A) Schematic Explanation of a First Embodiment [0075]
FIG. 1 schematically shows the structure of a first embodiment of the present invention. [0076]
A [0077] CDMA receiver 51 subjects a received signal to a processing such as demodulation, dispreading and Rake combination, and outputs a soft decision data of m (=5) bits (a sign bit+4 soft decision bits). A repetition regenerator 53 obtains the positions of the bits which are repeatedly transmitted in accordance with a repetition regeneration algorithm, adds a soft decision data which corresponds to the positions of the bits, and generates a soft decision data train of (m+1) (=6) bits which corresponds to the original error-correction code train. A threshold value decision unit 63 in a soft decision data take-out position controller 54 compares the repetition rate Rr of the received signal with a preset repetition rate RTH, and inputs the result of comparison into a soft decision data cut-off position decision unit 64.
If Rr>R[0078] TH, the soft decision data cut-off position decision unit 64 instructs a bit selector 65 to cut off the sign bit and the upper (m−1) bits. On the other hand, if Rr≦RTH, the soft decision data cut-off position decision unit 64 instructs the bit selector 65 to cut off the sign bit and the lower (m−1) bits. In accordance with the instruction, if Rr>RTH, the bit selector 65 cuts off the sign bit and the upper (m−1) bits from the soft decision data of (m+1) bits which is produced from the repetition regenerator 53, and inputs them into the soft decision error-correction decoder 55, while if Rr≦RTH, the bit selector 65 cuts off the sign bit and the lower (m−1) bits from the soft decision data of (m+1) bits which is produced from the repetition regenerator 53, and inputs them into the soft decision error-correction decoder 55. The soft decision error-correction decoder 55 subjects the input soft decision data to an error-correction decoding processing so as to restore it to the original data train before the error-correction coding processing.
When m=5, the relationship between the repetition rate and the amount of characteristic deterioration is as shown in FIG. 2. That is, in the case (1) of selecting the upper (m−1) (=4) bits from the [0079] repetition regenerator 53, as the repetition rate Rr becomes smaller, the deterioration of error correcting characteristic increases. In the case (2) of selecting the lower (m−1) bits, as the repetition rate Rr becomes larger, the deterioration of error correcting characteristic increases. Therefore, the repetition rate at which the characteristic curves in (1) and (2) cross each other is set as a threshold value RTH, and the cut-off position is switched on the basis of the result of comparison between the actual repetition rate Rr and the threshold value RTH. For example, as shown in FIG. 3, (1) when the actual repetition rate Rr is larger than RTH (Rr>RTH), the sign bit and the upper 4 bits are cut off and input into the soft decision error-correction decoder 55, while (2) when Rr≦RTH, the sign bit and the lower 4 bits are cut off and input into the soft decision error-correction decoder 55.
In this manner, it is possible to suppress the characteristic deterioration to a small extent by switching the position at which a part of the soft decision data is cut off on the basis of the repetition rate Rr. [0080]
(B) Schematic Explanation of a Second Embodiment [0081]
FIG. 4 schematically shows the structure of a second embodiment of the present invention. [0082]
The [0083] CDMA receiver 51 subjects a received signal to a processing such as demodulation, dispreading and Rake combination, and outputs a soft decision data of m (=5) bits (a sign bit+4 soft decision bits). The repetition regenerator 53 obtains the positions of the bits which are repeatedly transmitted in accordance with a repetition regeneration algorithm, adds a soft decision data which corresponds to the positions of the bits, and generates a soft decision data train of (m+1) (=6) bits which corresponds to the original error-correction code train. An average value calculator 62 in the soft decision data take-out position controller 54 calculates the average value Va of the soft decision data which is output from the repetition regenerator 53, and the threshold value decision unit 63 compares the average value Va with a preset average value VTH, and inputs the result into the soft decision data cut-off position decision unit 64.
If Va>VTH, the soft decision data cut-off [0084] position decision unit 64 instructs the bit selector 65 to cut off the sign bit and the lower (m−1) bits. On the other hand, if Va≦VTH, the soft decision data cut-off position decision unit 64 instructs the bit selector 65 to cut off the sign bit and the upper (m−1) bits. In accordance with the instruction, if Va>VTH, the bit selector 65 cuts off the sign bit and the upper (m−1) bits from the soft decision data of (m+1) bits which is produced from the repetition regenerator 53, and inputs them into the soft decision error-correction decoder 55, while if Va≦VTH, the bit selector 65 cuts off the sign bit and the lower (m−1) bits from the soft decision data of (m+1) bits which is produced from the repetition regenerator 53, and inputs them into the soft decision error-correction decoder 55. The soft decision error-correction decoder 55 subjects the input soft decision data to an error-correction decoding processing so as to restore it to the original data train before the error-correction coding processing.
As the repetition rate increases, the average value of the soft decision data increases, while as the repetition rate decreases, the average value of the soft decision data decreases. It is therefore possible to substitute the average value for the repetition rate in the first embodiment. In other words, the average value of the soft decision data which corresponds to the repetition rate R[0085] TH at which the characteristic curves cross each other in the first embodiment is set as a threshold value VTH, and the position at which the part of the soft decision data is cut off is switched on the basis of the result of comparison of the actual average value Va and the threshold value VTH. For example, as shown in FIG. 5, (1) when the actual average value Va is larger than VTH (Va>VTH), the sign bit and the upper 4 bits are cut off and input into the soft decision error-correction decoder 55, while (2) when Va≦VTH, the sign bit and the lower 4 bits are cut off and input into the soft decision error-correction decoder 55.
In this manner, it is possible to suppress the characteristic deterioration to a small extent as in the first embodiment, by switching the position at which a part of the soft decision data is cut off on the basis of the average value Va of the soft decision data output from the [0086] repetition regenerator 53.
(C) First Embodiment [0087]
(a) Structure [0088]
FIG. 6 shows the structure of the first embodiment of an error-correction apparatus according to the present invention. The same reference numerals are provided for the elements which are the same as those shown in FIG. 1. The [0089] CDMA receiver 51 has the structure similar to that explained with reference to FIG. 14. More specifically, the CDMA receiver 51 includes a radio circuit 51 a for amplifying a high-frequency signal received from an antenna 50, converting the frequency of the high-frequency signal into the frequency of a baseband signal and outputting the baseband signal, a quadrature detector (demodulator) 51 b for subjecting the baseband signal to quadrature detection, an AD converter 51 c for converting the output signals (an I component signal and a Q component signal) of the quadrature detector 51 b into digital signals, a despreading unit 51 d for subjecting the I component signal and the Q component signal which are output from the quadrature detector 51 b to a despreading processing, a synchronous detector 51 e for applying a synchronous detection processing to the despread data by using a pilot signal, and a Rake combiner 51 f for combining the outputs of the synchronous detector 51 e in accordance with the respective multi paths and outputting the result of combination as a soft decision data of 32 bits.
An ALC (Automatic Level Control) [0090] circuit 52 calculates the average values Vavr of the soft decision data which is input from the Rake combiner 51 f, cuts off the part of the soft decision data which corresponds to the average values Vavr and inputs it into the repetition regenerator 53. In the ALC circuit 52, a storage portion 52 a stores the soft decision data of 1 frame which is output from the Rake combiner 51 f, an average value calculator 52 b calculates the average values Vavr of the soft decision data for 1 frame, for example, and a soft decision data cut-off position decision unit 52 c decides the position at which a part of the soft decision data is cut off on the basis of the average value Vavr in such a manner that the original data can be faithfully represented even if the number of bits is reduced. A bit selector 52 d sequentially reads the soft decision data of 32 bits out of the storage portion 52 a, cuts off the data of 5 bits (the sign bit+4 soft decision bits) from the decided position and inputs it into the repetition regenerator 53. The bit cut-off position is decided, for example, in such a manner that the most significant upper bit position at which the binary average value Vavr is “1”, is situated at the third bit of 4 soft decision bits, as shown in FIG. 7.
The [0091] repetition regenerator 53 obtains the positions of the bits which are repeatedly transmitted due to a repetition processing, adds the soft decision data corresponding to the positions of the bits and generates a soft decision data train of 6 bits corresponding to the original error-correction data train. FIG. 8A shows the structure of the repetition regenerator 53, and FIG. 8B is an explanatory view of the condition for selecting an input signal. A repetition algorithm executor 53 a executes a repetition algorithm by using N (number of bits per frame before the repetition) and ΔN (number of bits increased due to the repetition) which will be described later, and outputs a repeat signal RIS=1 (see FIGS. 22 to 26) at the positions of the bits which are repeatedly transmitted. A register 53 b stores a soft decision data A output from the ALC circuit 52, and an adder 53 c adds the precedent and current soft decision data. A selector 53 d (1) outputs a soft decision data A of 6 bits, if RIS=“0” at both the precedent time and the current time (“0”→“0”), (2) outputs nothing, if RIS =“1” at the current time, and (3) selects and outputs the result B of the addition of 6 bits, if RIS=“1” at the precedent time and RIS=“0” at the current time precedent data (“1”→“0”). Alternatively, it is possible to constitute the repetition regenerator 53 in the form of a software including the addition processing and the selection processing.
Returning to FIG. 6, the soft decision data take-out [0092] position controller 54 cuts off the part of the soft decision data of 5 bits from the soft decision data of 6 bits which is generated by the repetition regenerator 53, on the basis of the repetition rate Rr. In the soft decision data take-out position controller 54, a conversion table 61 stores N (number of bits per frame before the repetition) and ΔN (number of bits increased due to the repetition) in correspondence with the result of a TFCI analysis, that is, the conversion table 61 is created on the basis of the information TFCI transmitted from the communication party in the negotiation before the start of communication.
A DSP (Digital Signal Processor) [0093] 62 (1) analyzes TFCI bits for 1 frame, and obtains N and ΔN used for the repetition processing of the transmission side by referring to the analyzed TFCI (number) and the conversion table 61, (2) inputs N and ΔN into the repetition regenerator 53, and (3) calculates the repetition rate Rr from the following formula:
Rr=(N+ΔN)/N
and outputs the result. N and ΔN during the negotiation are fixed in advance. However, N and ΔN can be changed during communication, and the transmission side transmits the number of TFCI bits corresponding to N and ΔN, while the DSP on the reception side identifies the number of the TFCI bits and executes the above-described processing. [0094]
The threshold [0095] value decision unit 63 compares the repetition rate Rr of the received signal with a preset repetition rate RTH, and inputs the result of comparison into the soft decision data cut-off position decision unit 64. If Rr>RTH, the soft decision data cut-off position decision unit 64 instructs the bit selector 65 to cut off the sign bit and the upper 4 bits. On the other hand, if Rr≦RTH, the soft decision data cut-off position decision unit 64 instructs the bit selector 65 to cut off the sign bit and the lower 4 bits.
In accordance with the instruction, if Rr>R[0096] TH, the bit selector 65 cuts off the sign bit and the upper 4 bits from the soft decision data of 6 bits which is generated by the repetition regenerator 53, and inputs them into the soft decision error-correction decoder 55,
while if Rr≦R[0097] TH, the bit selector 65 cuts off the sign bit and the lower 4 bits from the soft decision data of 6 bits which is generated by the repetition regenerator 53, and inputs them into the soft decision error-correction decoder 55.
The soft decision error-[0098] correction decoder 55 subjects the input soft decision data to an error-correction decoding processing so as to restore it to the original data train. A connection setting unit 56 creates the conversion table 61 on the basis of the information (decoded data) transmitted from the transmission side in the negotiation before the start of communication. A TFCI detector 57 detects TFCI bits and transmits them to the DSP 62.
(b) Operation [0099]
At the time of negotiation before the start of communication, the [0100] DSP 62 inputs N_oand ΔN_o, which are set in advance as N and ΔN, into the repetition regenerator 53, and also inputs a repetition rate Rr_ocalculated by using N_o, ΔN_ointo the threshold value decision unit 63. The CDMA receiver 51 outputs the received signal in the form of a soft decision data train of 32 bits, and the ALC circuit 52 cuts off the part of the soft decision data of 5 bits at the cut-off position corresponding to the average value Vavr of the soft decision data, and inputs it into the repetition regenerator 53. The repetition regenerator 53 obtains the positions of the bits which are repeatedly transmitted by executing the repetition regeneration algorithm on the basis of N_o, ΔN_o, and generates a soft decision data train of 6 bits which corresponds to the original error-correction code train by adding the soft decision data corresponding to the positions of the bits. The soft decision data take-out position controller 54 cuts off the sign bit and the upper 4 bits or the sign bit and the lower 4 bits on the basis of the result of comparison between the repetition rate Rr_oand the preset repetition rate RTH, and inputs the cut bits into the soft decision error-correction decoder 55. The soft decision error-correction decoder 55 subjects the input soft decision data to an error-correction decoding processing and outputs the decoded data. The connection setting unit 56 creates the conversion table 61 from the decoded data and sets it in the soft decision data take-out position controller 54.
After the end of negotiation, the [0101] DSP 62 obtains N and ΔN corresponding to the number which is transmitted in the form of the TFCI bits, and inputs the N and ΔN obtained in the repetition regenerator 53. The DSP 62 also calculates the repetition rate Rr from the N and ΔN obtained and inputs it into the threshold value decision unit 63. The CDMA receiver 51 outputs the received signal in the form of a soft decision data train of 32 bits, and the ALC circuit 52 cuts off the part of the soft decision data of 5 bits at the cut-off position corresponding to the average value Vavr, and inputs it into the repetition regenerator 53. The repetition regenerator 53 obtains the positions of the bits which are repeatedly transmitted by executing the repetition algorithm on the basis of the input N, ΔN, and generates a soft decision data train of 6 bits which corresponds to the original error-correction code train by adding the soft decision data corresponding to the positions of the bits. The soft decision data take-out position controller 54 cuts off the sign bit and the upper 4 bits or the sign bit and the lower 4 bits on the basis of the result of comparison between the calculated repetition rate Rr and the preset repetition rate RTH, and inputs the cut bits into the soft decision error-correction decoder 55. The soft decision error-correction decoder 55 subjects the input soft decision data to an error-correction decoding processing and outputs the decoded data.
In parallel with the above-described operation, the [0102] TFCI detector 57 detects TFCI bits and inputs them into the DSP 62. The DSP 62 analyzes the TFCI bits for 1 frame, and obtains N and ΔN by referring to the analyzed TFCI (number) and the conversion table 61. If the N and ΔN newly obtained are different from the current N and ΔN, the DSP 62 inputs the new N and ΔN into the repetition regenerator 53, calculates a new repetition rate Rr and inputs the result into the threshold value decision unit 63. Thenceforth, the CDMA receiver 51, the ALC circuit 52, the repetition regenerator 53, the soft decision data take-out position controller 54 and the soft decision error-correction decoder 55 repeat the above-described operation.
According to the first embodiment, it is possible to suppress the characteristic deterioration to a small extent by switching the position at which a part of the soft decision data is cut off on the basis of the repetition rate Rr. [0103]
(C) Modification [0104]
FIG. 9 shows a modification of the first embodiment. The same reference numerals are provided for the elements which are the same as those in the first embodiment shown in FIG. 6. This modification is different from the first embodiment in the following points: [0105]
(1) that the [0106] ALC circuit 52 does not cut off a bit from the 32 bits of the soft decision data which is output from the Rake combiner 5 If;
(2) that the repetition regenerator [0107] 53 sequentially reads the soft decision data of 32 bits out of the storage portion 52 a after the end of calculation of the average value Vavr of the soft decision data of 32 bits, executes a repetition regeneration processing and outputs the data in the form of a soft decision data of 33 bits;
(3) that the soft decision data cut-off [0108] position decision unit 64 decides the position at which a part of the soft decision data (4 soft decision bits) is cut off on the basis of the result of comparison between the repetition rate Rr and the preset repetition rate RTHand the average value Vavr of the soft decision data which is output from the average value calculator 52 b; and
(4) that the [0109] bit selector 65 cuts off the soft decision data of 5 bits (the sign bit+4 soft decision bits) out of the soft decision data of 33 bits which is output from the repetition regenerator 53 at the decided cut-off position.
The soft decision data cut-off [0110] position decision unit 64 decides the position at which a part of the soft decision data is cut off in such a manner (1) that the most significant upper bit at which the binary average value Vavr is “1”, is situated at the third bit of 4 soft decision bits, if Rr≦RTH, and (2) that the most significant upper bit at which the binary average value Vavr is “1” is situated at the second bit of 4 soft decision bits, if Rr>RTH .
According to this modification, it is possible to suppress the characteristic deterioration to a small extent and, in addition, to simplify the circuit structure by switching the position at which a part of the soft decision data is cut off on the basis of the repetition rate Rr. [0111]
(D) Second Embodiment [0112]
FIG. 10 shows the structure of the second embodiment of an error correcting apparatus according to the present invention. The same reference numerals are provided for the elements which are the same as those in the first embodiment shown in FIG. 6. The second embodiment is different from the first embodiment in the following points: [0113]
(1) that the [0114] DSP 62 calculates the average value Va of the soft decision data of 6 bits which is out put from the repetition regenerator 53;
(2) that a [0115] storage portion 66 for storing the soft decision data for 1 frame is provided in the soft decision data take-out position controller 54;
(3) that the threshold [0116] value decision unit 63 compares the average value Va and a preset threshold value VTH; and
(4) that the soft decision data cut-off [0117] position decision unit 64 decides the position at which the soft decision data of 5 bits (the sign bit+4 soft decision bits) is cut off on the basis of the result of comparison between the average value Va and the preset threshold value VTH.
The [0118] CDMA receiver 51 outputs a received signal in the form of a soft decision data train of 32 bits, and the ALC circuit 52 cuts off the part of soft decision data of 5 bits at the cut-off position which corresponds to the average value Vavr of the soft decision data, and inputs the cut data into the repetition regenerator 53. The repetition regenerator 53 executes a repetition algorithm so as to obtain the positions of the bits which are repeatedly transmitted, adds the soft decision data which corresponds to the positions of the bits, and outputs a soft decision data train of 6 bits which corresponds to the original error-correction code train.
The [0119] storage portion 66 of the soft decision data take-out position controller 54 sequentially stores the soft decision data output from the repetition regenerator 53, and the DSP 62 calculates the average value Va of the soft decision data for 1 frame.
When the calculation of the average value Va of the soft decision data for 1 frame is finished, the threshold [0120] value decision unit 63 compares the average value Va with the threshold value VTH, and inputs the result into the soft decision data cut-off position decision unit 64. The soft decision data cut-off position decision unit 64 instructs the bit selector 65 to cut off the sign bit and the upper 4 bits, if Va>VTH, while if Va≦VTH, the soft decision data cut-off position decision unit 64 instructs the bit selector 65 to cut off the sign bit and the lower 4 bits.
In accordance with the instruction, if Va>VTH, the [0121] bit selector 65 sequentially reads out the soft decision data of 6 bits, cuts off the sign bit and the upper 4 bits, and inputs them into the soft decision error-correction decoder 55, while if Va≦VTH, the bit selector 65 cuts off the sign bit and the lower 4 bits, and inputs them into the soft decision error-correction decoder 55.
The soft decision error-[0122] correction decoder 55 subjects the input soft decision data to an error-correction decoding processing so as to restore it to the original data train before the error-correction coding processing.
As described above, it is possible to suppress the characteristic deterioration to a small extent by switching the position at which a part of the soft decision data is cut off on the basis of the average value Va of the soft decision data which is output from the [0123] repetition regenerator 53.
FIG. 11 shows a modification of the second embodiment. The same reference numerals are provided for the elements which are the same as those in the second embodiment shown in FIG. 10. This modification is different from the second embodiment in the following points: [0124]
(1) that the [0125] ALC circuit 52 is eliminated;
(2) that the [0126] repetition regenerator 53 directly subjects the soft decision data of 32 bits which is output from the CDMA receiver 51 to a repetition regeneration processing, and output the data in the form of a soft decision data of 33 bits;
(3) that the [0127] DSP 62 outputs the average value Va of the soft decision data of 33 bits which is output from the repetition regenerator 53;
(4) that the soft decision data cut-off [0128] position decision unit 64 decides the position at which a part of soft decision data (4 soft decision bits) is cut off on the basis of the average value Va and the result of comparison between the average value Va and the preset threshold value VTH; and
(5) that the [0129] bit selector 65 cuts off the soft decision data of 5 bits (the sign bit+4 soft decision bits) from the soft decision data of 33 bits which is output from the repetition regenerator 53 at the decided cut-off position and outputs them.
The soft decision data cut-off [0130] position decision unit 64 decides the position at which a part of the soft decision data is cut off in such a manner (1) that the most significant upper bit at which the binary average value Va is “1” is situated at the third bit of 4 soft decision bits, if Va≦VTH, and (2) that the most significant upper first bit at which the binary average value Vavr is “1” is situated at the second bit of 4 soft decision bits, if Va>VTH.
According to this modification, it is possible to suppress the characteristic deterioration to a small extent and, in addition, to simplify the circuit structure by varying the position at which a part of the soft decision data is cut off on the basis of the average value of the soft decision data. [0131]
As described above, according to the present invention, since the position at which a part of the soft decision data (e.g., 4 soft decision bits) is cut off is switched on the basis of the repetition rate, it is possible to suppress the characteristic deterioration originated in the repetition rate. [0132]
According to the present invention, since the number of bits of the soft decision data which is output from the repetition regenerator is reduced to such an extent as to be within the processing limit of the soft decision error-correction decoder, on the basis of the repetition rate, it is possible to prevent an increase in the circuit scale of the soft decision error-correction decoder. [0133]
In addition, according to the present invention, since the position at which a part of soft decision data (4 soft decision bits) is cut off is determined on the basis of the average value of the soft decision data which is output from the CDMA receiver and the result of comparison between the repetition rate and the threshold value, and the part of the soft decision data is cut off at the decided position so as to reduce the number of bits, it is possible to reduce the total circuit scale. [0134]
According to the present invention, since the position at which a part of soft decision data (e.g., 4 soft decision bits) is cut off is determined on the basis of the average value of the soft decision data, it is possible to suppress the characteristic deterioration originated in the repetition rate. [0135]
Furthermore, according to the present invention, since the number of bits of the soft decision data which is output from the repetition regenerator is reduced to such an extent as to be within the processing limit of the soft decision error-correction decoder, on the basis of the average value of the soft decision data, it is possible to prevent an increase in the circuit scale of the soft decision error-correction decoder. [0136]
Moreover, according to the present invention, since the position at which a part of soft decision data (4 soft decision bits) is cut off is determined on the basis of the average value of the soft decision data output from the CDMA receiver and the result of comparison between the average value and the threshold value, and the part of the soft decision data is cut off at the decided position so as to reduce the number of bits, it is possible to reduce the total circuit scale. [0137]
As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the depended claims. [0138]

Claims

What is claimed is:

1. An error correcting apparatus for receiving a signal subjected to a repetition processing in which a part of bits of an error-correction code train are repeatedly transmitted, and decoding said received signal so as to be restored to the original data train, said error-correction apparatus comprising:

a receiver/demodulator unit for receiving and demodulating a signal subjected to the repetition processing in which a part of bits of the error-correction code train are repeatedly transmitted, and outputting a soft decision data train;

a soft decision data train generator for adding a soft decision data which corresponds to the repeatedly transmitted bits, so as to generate a soft decision data train which corresponds to the original error-correction code train; and

a soft decision error-correction decoder for restoring said soft decision data train to said original data train;

wherein said soft decision data train generator includes:

a repetition regenerator for obtaining the positions of said bits which are repeatedly transmitted due to said repetition processing, and adding a soft decision data which corresponds to said positions so as to generate said soft decision data train which corresponds to said original error-correction code train;

a repetition rate calculator for calculating the repetition rate of said received signal subjected to said repetition processing;

a first soft decision data cut-off position decision unit for deciding a position at which a part of said soft decision data which is to be input into said soft decision error-correction decoder is cut off from said soft decision data which is generated by said repetition regenerator, on the basis of said repetition rate; and

a first soft decision data cutting means for cutting off said part of said soft decision data at the decided cut-off position and inputting the cut part into said soft decision error-correction decoder.

2. An error-correcting apparatus according to

claim 1

, wherein said repetition rate calculator calculates said repetition rate on the basis of the number N of bits of the data before said repetition processing and the number ΔN of bits which are repeated due to said repetition processing, the numbers N and ΔN being notified of from a communication party.

3. An error correcting apparatus according to

claim 1

, wherein said repetition regenerator obtains said positions of said bits which are repeatedly transmitted by executing a repetition algorithm on the basis of the number N of bits of the data before said repetition processing and the number ΔN of bits which are repeated due to said repetition processing, the numbers N and ΔN being notified of from a communication party.

4. An error correcting apparatus according to

claim 1

, further comprising:

an average value calculator for calculating the average value of said soft decision data which is demodulated by said demodulator unit;

a second soft decision data cut-off position decision unit for deciding a position at which a part of said soft decision data which is to be input into said repetition regenerator is cut off from the demodulated soft decision data, on the basis of said average value;

a second soft decision data cutting means for cutting off a part of said soft decision data of a predetermined number of bits from said demodulated soft decision data on the basis of the decided cut-off position and inputting the cut part into said repetition regenerator; and

a comparator for comparing said repetition rate with a preset value;

wherein said first soft decision data cutting means cuts off a plural upper bits from said soft decision data which is generated by said repetition regenerator and inputs said bits into said soft decision error-correction decoder when said repetition rate is larger than said preset value, while cutting off plural lower bits and inputting said bits into said soft decision error-correction decoder when said repetition rate is smaller than said preset value.

5. An error correcting apparatus according to

claim 1

, further comprising:

an average value calculator for calculating the average value of said soft decision data which is demodulated by said demodulator unit; and

a comparator for comparing said repetition rate with a preset value;

wherein said first soft decision data cut-off position decision unit decides a position at which a part of the soft decision data which is to be input into said soft decision error-correction decoder is cut off from said soft decision data which is generated by said repetition regenerator, on the basis of said average value and the result of comparison between said repetition rate and said preset value.

6. An error correcting apparatus for receiving a signal subjected to a repetition processing in which a part of bits of an error-correction code train are repeatedly transmitted, and decoding said received signal so as to be restored to the original data train before error-correction coding, said error-correction apparatus comprising:

a receiver/demodulator unit for receiving and demodulating a signal subjected to the repetition processing in which a part of bits of said error-correction code train are repeatedly transmitted, and outputting a soft decision data train;

wherein said soft decision data train generator includes:

a repetition regenerator for obtaining the positions of said bits which are repeatedly transmitted due to said repetition processing, and adding said soft decision data which corresponds to said positions so as to generate said soft decision data train which corresponds to said original error-correction code train;

an average value calculator for calculating the average value (first average value) of said soft decision data which is output from said repetition regenerator;

a first soft decision data cut-off position decision unit for deciding a position at which a part of said soft decision data which is to be input into said soft decision error-correction decoder is cut off from said soft decision data which is generated by said repetition regenerator, on the basis of said first average value; and

7. An error correcting apparatus according to

claim 6

, further comprising:

an average value calculator for calculating the average value (second average value) of said soft decision data which is demodulated by said demodulator unit;

a second soft decision data cut-off position decision unit for deciding a position at which a part of said soft decision data which is to be input into said repetition regenerator is cut off from the demodulated soft decision data, on the basis of said second average value;

a comparator for comparing said first average value of said soft decision data which is output from said repetition regenerator with a preset value;

wherein said first soft decision data cutting means cuts off plural upper bits from said soft decision data which is generated by said repetition regenerator and inputs said bits into said soft decision error-correction decoder when said first average value is larger than said preset value, while cutting off plural lower bits and inputting said bits into said soft decision error-correction decoder when said first average value is smaller than said preset value.

8. An error correcting apparatus according to

claim 6

, further comprising:

an average value calculator for calculating the average value (second average value) of said soft decision data which is demodulated by said demodulator unit; and

wherein said first soft decision data cut-off position decision unit decides a position at which a part of the soft decision data which is to be input into said soft decision error-correction decoder is cut off from said soft decision data which is generated by said repetition regenerator, on the basis of the result of comparison between said first average value and said preset value, and said second average value.