US20010019866A1 - Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole - Google Patents

Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole Download PDF

Info

Publication number
US20010019866A1
US20010019866A1 US09/783,044 US78304401A US2001019866A1 US 20010019866 A1 US20010019866 A1 US 20010019866A1 US 78304401 A US78304401 A US 78304401A US 2001019866 A1 US2001019866 A1 US 2001019866A1
Authority
US
United States
Prior art keywords
insulating layer
contact hole
forming
gate
gate stacks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/783,044
Other versions
US6383862B2 (en
Inventor
Soon-Kyou Jang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/783,044 priority Critical patent/US6383862B2/en
Publication of US20010019866A1 publication Critical patent/US20010019866A1/en
Application granted granted Critical
Publication of US6383862B2 publication Critical patent/US6383862B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Definitions

  • the present invention relates to a contact hole fabrication, and more particularly to a method of forming a contact hole using oxide spacers on sidewalls of a contact hole to protect gate protecting spacers.
  • One important technique for fabricating a semiconductor device involves forming a connection between an upper level wiring layer and either a conductive region of an impurity-diffused layer in a semiconductor substrate or a lower level wiring layer. Such a connection is preferably formed through a contact hole formed in an interlayer insulating film.
  • the design rule i.e., the minimum feature size
  • the distance between gate stacks in a semiconductor device is being shortened to coordinate this reduced design rule.
  • a contact hole opened in the interlayer insulating layer between the gate stacks has a high aspect ratio and an over-etch is implemented during a step of etching the interlayer insulating layer.
  • an over-etch may also etch a silicon nitride gate spacer that operates to protect the gate stacks.
  • FIGS. 1A to 1 D are cross-sectional views at selected stages of a conventional fabrication process for forming a contact hole between gate stacks.
  • FIG. 1A schematically shows a semiconductor substrate 10 having a cell array region and a core region, each area having a plurality of gate stacks 18 .
  • Each gate stack 18 includes a gate oxide layer 11 , a gate electrode 15 , and a silicon nitride capping layer 16 .
  • the gate electrode 15 is generally made of a multilayer structure of a polysilicon layer 12 and a tungsten silicide layer 14 .
  • a first silicon nitride layer 20 is generally deposited over the entire surface of the semiconductor substrate 10 and the plurality of gate stacks 18 by a conventional method such as chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the first silicon nitride layer 20 is then etched back to form spacers 21 on both sidewalls of the gate stacks 18 as shown in FIG. 1 B.
  • a second silicon nitride layer 22 is then deposited over the resulting structure, including the substrate 10 and the gate stacks 18 , to serve as an etching stopper.
  • An interlayer insulating layer 24 is then deposited over the gate stacks 18 and in the spaces between the gate stacks 18 .
  • selected portions of the interlayer insulating layer 24 are etched to form a plurality of contact holes 26 between the gate stacks 18 using the second silicon nitride layer 22 as an etching stopper.
  • the second silicon nitride layer 22 between the gate stacks is removed as shown in FIG. 1D.
  • the above-mentioned method uses silicon nitride for the capping layer 16 , the gate spacer 21 , and the etching stopper 22 .
  • the gate spacer 21 and the capping layer 16 are also etched during the step of etching the second silicon nitride layer 22 , as shown in inside the dotted circle of FIG. 1D. Accordingly, the gate electrode 15 may electrically contact the subsequently-formed conductive bit line and storage node pads (or landing pads).
  • the present invention was made in view of the above problem, and it is therefore an object of the invention to provide a method of forming a contact hole between the gate stacks without etching the gate spacer and gate capping layer.
  • a key feature of this invention is to form a protective spacer layer having an etching selectivity with respect to the silicon nitride layer after forming the contact hole.
  • the protective layer is preferably formed on the sidewalls of the contact hole with a silicon oxide layer.
  • the protective silicon oxide layer acts to protect an underlying silicon nitride layer.
  • the silicon oxide layer forms a gate stack spacer together with the underlying silicon nitride layer on sidewalls of the gate stacks.
  • the present invention provides double gate spacers comprised of two different layers having an etching selectivity with respect to each other.
  • a method of forming a contact hole in a semiconductor device including forming at least two gate stacks over a semiconductor substrate, forming a first insulating layer over the semiconductor substrate and at least two gate stacks, forming an interlayer insulating layer over the first insulating layer, etching a selected portion of the interlayer insulating layer to form a contact hole between the gate stacks, forming a second insulating layer over the interlayer insulating layer, the contact hole and the semiconductor substrate, etching back the second insulating layer to form spacers on sidewalls of the contact hole, and using the interlayer insulating layer and the spacers as a mask to etch the first insulating layer to expose a top surface of the semiconductor substrate.
  • the first insulating layer preferably comprises silicon nitride and has a thickness of about 50 ⁇ to 100 ⁇ .
  • the first insulating layer preferably serves as an etching stopper during the etching of the interlayer insulating layer.
  • the second insulating layer comprises silicon oxide and has a thickness of about 300 ⁇ to 500 ⁇ .
  • Each of the gate stacks preferably comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer.
  • the gate capping insulating layer preferably comprises silicon nitride.
  • a method of forming a contact hole in a semiconductor substrate in which the semiconductor substrate has a cell array region and a core region, the cell array region having at least two first gate stacks and the core region having at least two second gate stacks.
  • This method includes forming first and second insulating layers over the semiconductor substrate, the first gate stacks, and the second gate stacks, forming a first photoresist layer over the second insulating layer to cover the cell array region and to expose the core region, using the first photoresist layer as a mask to etch the first and second insulating layers to form first spacers on sidewalls of the second gate stacks, removing the first photoresist layer, forming a second photoresist layer to cover the core region and to expose the cell array region, using the second photoresist layer as a mask to etch the second insulating layer to expose the first insulating layer, removing the second photoresist layer, forming an interlayer insulating layer over the semiconductor substrate, the first gate stacks
  • the first insulating layer preferably comprises silicon nitride and has a thickness of about 50 ⁇ to 100 ⁇ .
  • the first insulating layer preferably serves as an etching stopper during the etching of the interlayer insulating layer.
  • the second insulating layer preferably comprises silicon oxide and has a thickness of about 500 ⁇ .
  • the third insulating layer preferably comprises silicon oxide and has a thickness of about 300 ⁇ to 500 ⁇ .
  • Each of the gate stacks preferably comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer.
  • the gate capping insulating layer preferably comprises silicon nitride
  • FIGS. 1A to 1 D are cross-sectional views at selected stages of a conventional fabrication process for forming a contact hole between gate stacks
  • FIG. 2 is a layout diagram of a DRAM in accordance with a preferred embodiment of the present invention.
  • FIGS. 3A to 3 I are cross-sectional views at selected stages of a fabrication process for forming a contact hole between gate stacks, taken along line 3 a - 3 a ′ of FIG. 2.
  • FIG. 2 schematically shows a layout diagram of a DRAM device in accordance with a preferred embodiment of the present invention.
  • a plurality of gate electrodes 142 are running straight and spaced apart from each other by a predetermined distance over a semiconductor substrate 100 .
  • a plurality of bit line contact pads 162 b and storage node contact pads 162 a are disposed over selected portion of the spaces between the gate electrodes 142 .
  • a plurality of storage nodes 164 are aligned over corresponding storage node contact pads 162 a and are electrically connected to the storage node contact pads 162 a through storage contacts (not shown) formed in an interlayer insulating layer (not shown).
  • a plurality of bit lines 110 intersect the gate electrodes 142 and are connected to the bit line contact pads 162 b through bit line contacts 112 in the interlayer insulating layer (not shown).
  • the present invention relates to a method of forming a contact hole between transistors, and more particularly to a contact hole formation process that can prevent transistor components (e.g., a silicon nitride capping layer and a silicon nitride spacer) from being etched during the step of etching the etching stopper silicon nitride layer.
  • transistor components e.g., a silicon nitride capping layer and a silicon nitride spacer
  • FIGS. 3A to 3 I are cross-sectional views at selected stages of the preferred embodiment of the fabrication process for forming a contact hole between gate stacks, taken along line 3 a - 3 a ′ of FIG. 2.
  • a semiconductor substrate 100 is initially provided in which a cell array region and a core region are defined.
  • a device isolation layer is formed in and over the semiconductor substrate 100 to isolate active areas.
  • a plurality of gate electrode patterns 142 i.e., gate stacks
  • Each gate stack 142 preferably includes a gate oxide layer 132 , a gate electrode 140 , and a silicon nitride capping layer 138 .
  • the gate electrode 140 comprises a multilayer structure including a polysilicon layer 134 that is about 700 ⁇ thick and a tungsten silicide layer 136 that is about 1,000 ⁇ thick.
  • a first insulating layer 144 and a second insulating layer 146 are then sequentially formed over the entire surface of the semiconductor substrate 100 and the gate stacks 142 .
  • the first insulating layer 144 is preferably made of silicon nitride and preferably has a thickness in the range of about 50 ⁇ to 100 ⁇ .
  • the second insulating layer 146 is preferably made of silicon oxide and preferably has a thickness of about 500 ⁇ .
  • a first photoresist layer is deposited over the second insulating layer 146 and is patterned into a desired configuration as a first patterned photoresist layer 148 that exposes only the core region.
  • the second insulating layer 146 and first insulating layer 144 exposed by the first patterned photoresist layer 148 are etched back to form spacers 150 on both sidewalls of the gate stacks 142 in the core region.
  • a second patterned photoresist layer 152 is formed to expose only the cell array region, as shown in FIG. 3C.
  • the silicon oxide layer 146 in the cell array region is etched to expose the silicon nitride layer 144 .
  • the etching of the oxide layer 146 is preferably carried out by conventional wet etching process.
  • the second patterned photoresist layer 152 is then preferably removed by plasma ashing.
  • a planar interlayer insulating layer 154 is then formed over the resulting structure, preferably by the process of depositing and planarizing.
  • the planarizing process step itself preferably includes a chemical mechanical polishing (CMP) step.
  • CMP chemical mechanical polishing
  • a third photoresist layer (not shown) is then deposited over the interlayer insulating layer 154 and is patterned into a desired configuration that exposes a desired portion of the cell array region.
  • the interlayer insulating layer 154 is etched down to the silicon nitride layer 144 in certain areas, to form a plurality of contact holes 156 between the gate stacks as shown in FIG. 3E.
  • the silicon nitride layer 144 preferably serves as etching stopper.
  • a third insulating layer 158 is deposited over the resulting structure shown in FIG. 3E.
  • the third insulating layer 158 is preferably made of silicon oxide and preferably has a thickness in the range of about 300 ⁇ to 500 ⁇ . This silicon oxide layer 158 protects the silicon nitride capping layer 138 and a first insulating layer, i.e., silicon nitride layer 144 .
  • the third silicon oxide layer 158 is then etched to form oxide spacers 160 on the first silicon nitride layer 144 that is formed on sidewalls of the contact holes 156 as shown in FIG. 3G.
  • the oxide spacers 160 As a mask, the first silicon nitride layer 144 between the gate stacks is then removed as shown in FIG. 3H.
  • contact pads 162 for a bit line (corresponding to bit line contact pads 162 b from FIG. 2) and contact pads 162 for a storage node (corresponding to storage node contact pads 162 a from FIG. 2) are conventionally formed, as shown in FIG. 3I.
  • a fourth insulating layer 163 is deposited over the resulting structure.
  • Storage nodes 164 are then formed to electrically be connected to the contact pads 162 for the storage node.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a contact hole in a semiconductor device is provided wherein an oxide spacer is formed over a contact hole. The oxide contact hole spacer prevents an already-formed gate protecting spacer comprised of silicon nitride from being etched during a subsequent step of removing the already-formed silicon nitride etching stopper. After forming a gate stack having the protecting spacer, the silicon nitride etching stopper is formed. An interlayer insulating layer is formed thereon and a selected portion of the interlayer insulating layer is etched to form a contact hole. The oxide spacer is formed on both sidewalls of the contact hole and then the etching stopper silicon nitride layer is removed.

Description

  • This application is a continuation application of “METHOD OF FORMING A CONTACT HOLE IN A SEMICONDUCTOR SUBSTRATE USING OXIDE SPACERS ON THE SIDEWALLS OF THE CONTACT HOLE,” by Soon-Kyou JANG, Ser. No. 09/335,784, filed on Jun. 18, 1999, the contents of which are herein incorporated by reference in their entirety, which relies for priority upon Korean Patent Application No. [0001] 98-25172, filed on Jun. 29, 1998, the contents of which are herein incorporated by reference in their entirety.
    • FIELD OF THE INVENTION
  • The present invention relates to a contact hole fabrication, and more particularly to a method of forming a contact hole using oxide spacers on sidewalls of a contact hole to protect gate protecting spacers. [0002]
    • BACKGROUND OF THE INVENTION
  • One important technique for fabricating a semiconductor device involves forming a connection between an upper level wiring layer and either a conductive region of an impurity-diffused layer in a semiconductor substrate or a lower level wiring layer. Such a connection is preferably formed through a contact hole formed in an interlayer insulating film. [0003]
  • Recently as the density of integrated circuits has increased, the design rule, i.e., the minimum feature size, has decreased. As a result, the distance between gate stacks in a semiconductor device is being shortened to coordinate this reduced design rule. Accordingly, a contact hole opened in the interlayer insulating layer between the gate stacks has a high aspect ratio and an over-etch is implemented during a step of etching the interlayer insulating layer. However, such an over-etch may also etch a silicon nitride gate spacer that operates to protect the gate stacks. [0004]
  • FIGS. 1A to [0005] 1D are cross-sectional views at selected stages of a conventional fabrication process for forming a contact hole between gate stacks. FIG. 1A schematically shows a semiconductor substrate 10 having a cell array region and a core region, each area having a plurality of gate stacks 18. Each gate stack 18 includes a gate oxide layer 11, a gate electrode 15, and a silicon nitride capping layer 16. The gate electrode 15 is generally made of a multilayer structure of a polysilicon layer 12 and a tungsten silicide layer 14. A first silicon nitride layer 20 is generally deposited over the entire surface of the semiconductor substrate 10 and the plurality of gate stacks 18 by a conventional method such as chemical vapor deposition (CVD).
  • The first [0006] silicon nitride layer 20 is then etched back to form spacers 21 on both sidewalls of the gate stacks 18 as shown in FIG. 1 B. A second silicon nitride layer 22 is then deposited over the resulting structure, including the substrate 10 and the gate stacks 18, to serve as an etching stopper. An interlayer insulating layer 24 is then deposited over the gate stacks 18 and in the spaces between the gate stacks 18.
  • Referring to FIG. 1C, selected portions of the [0007] interlayer insulating layer 24 are etched to form a plurality of contact holes 26 between the gate stacks 18 using the second silicon nitride layer 22 as an etching stopper.
  • After forming the [0008] contact holes 26, the second silicon nitride layer 22 between the gate stacks is removed as shown in FIG. 1D.
  • The above-mentioned method uses silicon nitride for the [0009] capping layer 16, the gate spacer 21, and the etching stopper 22. As a result, the gate spacer 21 and the capping layer 16 are also etched during the step of etching the second silicon nitride layer 22, as shown in inside the dotted circle of FIG. 1D. Accordingly, the gate electrode 15 may electrically contact the subsequently-formed conductive bit line and storage node pads (or landing pads).
    • SUMMARY OF THE INVENTION
  • The present invention was made in view of the above problem, and it is therefore an object of the invention to provide a method of forming a contact hole between the gate stacks without etching the gate spacer and gate capping layer. A key feature of this invention is to form a protective spacer layer having an etching selectivity with respect to the silicon nitride layer after forming the contact hole. The protective layer is preferably formed on the sidewalls of the contact hole with a silicon oxide layer. The protective silicon oxide layer acts to protect an underlying silicon nitride layer. The silicon oxide layer forms a gate stack spacer together with the underlying silicon nitride layer on sidewalls of the gate stacks. The present invention provides double gate spacers comprised of two different layers having an etching selectivity with respect to each other. [0010]
  • In accordance with these and other objects, a method of forming a contact hole in a semiconductor device is provided, including forming at least two gate stacks over a semiconductor substrate, forming a first insulating layer over the semiconductor substrate and at least two gate stacks, forming an interlayer insulating layer over the first insulating layer, etching a selected portion of the interlayer insulating layer to form a contact hole between the gate stacks, forming a second insulating layer over the interlayer insulating layer, the contact hole and the semiconductor substrate, etching back the second insulating layer to form spacers on sidewalls of the contact hole, and using the interlayer insulating layer and the spacers as a mask to etch the first insulating layer to expose a top surface of the semiconductor substrate. [0011]
  • In this method, the first insulating layer preferably comprises silicon nitride and has a thickness of about 50 Å to 100 Å. The first insulating layer preferably serves as an etching stopper during the etching of the interlayer insulating layer. The second insulating layer comprises silicon oxide and has a thickness of about 300 Å to 500 Å. [0012]
  • Each of the gate stacks preferably comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer. The gate capping insulating layer preferably comprises silicon nitride. [0013]
  • A method of forming a contact hole in a semiconductor substrate is also provided in which the semiconductor substrate has a cell array region and a core region, the cell array region having at least two first gate stacks and the core region having at least two second gate stacks. This method includes forming first and second insulating layers over the semiconductor substrate, the first gate stacks, and the second gate stacks, forming a first photoresist layer over the second insulating layer to cover the cell array region and to expose the core region, using the first photoresist layer as a mask to etch the first and second insulating layers to form first spacers on sidewalls of the second gate stacks, removing the first photoresist layer, forming a second photoresist layer to cover the core region and to expose the cell array region, using the second photoresist layer as a mask to etch the second insulating layer to expose the first insulating layer, removing the second photoresist layer, forming an interlayer insulating layer over the semiconductor substrate, the first gate stacks, and the second gate stacks, etching a selected portion of the interlayer insulating layer to form a contact hole between the first gate stacks, forming a third insulating layer over the semiconductor substrate, the first gate stacks, the second gate stacks, and the contact hole, etching the third insulating layer to form second spacers on sidewalls of the contact hole, and using the interlayer insulating layer and the second spacers as a mask to etch the first insulating layer to expose a top surface of the semiconductor substrate. [0014]
  • In this method, the first insulating layer preferably comprises silicon nitride and has a thickness of about 50 Å to 100 Å. The first insulating layer preferably serves as an etching stopper during the etching of the interlayer insulating layer. The second insulating layer preferably comprises silicon oxide and has a thickness of about 500 Å. The third insulating layer preferably comprises silicon oxide and has a thickness of about 300 Å to 500 Å. [0015]
  • Each of the gate stacks preferably comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer. The gate capping insulating layer preferably comprises silicon nitride [0016]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention may be understood and its objects will become apparent to those killed in the art by reference to the accompanying drawings as follows: [0017]
  • FIGS. 1A to [0018] 1D are cross-sectional views at selected stages of a conventional fabrication process for forming a contact hole between gate stacks;
  • FIG. 2 is a layout diagram of a DRAM in accordance with a preferred embodiment of the present invention; [0019]
  • FIGS. 3A to [0020] 3I are cross-sectional views at selected stages of a fabrication process for forming a contact hole between gate stacks, taken along line 3 a-3 a′ of FIG. 2.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 2 schematically shows a layout diagram of a DRAM device in accordance with a preferred embodiment of the present invention. As shown in FIG. 2, a plurality of [0021] gate electrodes 142 are running straight and spaced apart from each other by a predetermined distance over a semiconductor substrate 100. A plurality of bit line contact pads 162 b and storage node contact pads 162 a are disposed over selected portion of the spaces between the gate electrodes 142. A plurality of storage nodes 164 are aligned over corresponding storage node contact pads 162 a and are electrically connected to the storage node contact pads 162 a through storage contacts (not shown) formed in an interlayer insulating layer (not shown). A plurality of bit lines 110 intersect the gate electrodes 142 and are connected to the bit line contact pads 162 b through bit line contacts 112 in the interlayer insulating layer (not shown).
  • A preferred embodiment of the present invention will now be described with reference to the accompanying drawings. The present invention relates to a method of forming a contact hole between transistors, and more particularly to a contact hole formation process that can prevent transistor components (e.g., a silicon nitride capping layer and a silicon nitride spacer) from being etched during the step of etching the etching stopper silicon nitride layer. [0022]
  • FIGS. 3A to [0023] 3I are cross-sectional views at selected stages of the preferred embodiment of the fabrication process for forming a contact hole between gate stacks, taken along line 3 a-3 a′ of FIG. 2.
  • As shown in to FIG. 3A, a semiconductor topography is provided that has already undergone several processes according to the preferred embodiment of the present invention. A [0024] semiconductor substrate 100 is initially provided in which a cell array region and a core region are defined. A device isolation layer is formed in and over the semiconductor substrate 100 to isolate active areas. A plurality of gate electrode patterns 142 (i.e., gate stacks) are conventionally formed over both the cell array and core regions. Each gate stack 142 preferably includes a gate oxide layer 132, a gate electrode 140, and a silicon nitride capping layer 138.
  • In a preferred embodiment of this invention, the [0025] gate electrode 140 comprises a multilayer structure including a polysilicon layer 134 that is about 700 Å thick and a tungsten silicide layer 136 that is about 1,000 Å thick. A first insulating layer 144 and a second insulating layer 146 are then sequentially formed over the entire surface of the semiconductor substrate 100 and the gate stacks 142. The first insulating layer 144 is preferably made of silicon nitride and preferably has a thickness in the range of about 50 Å to 100 Å. The second insulating layer 146 is preferably made of silicon oxide and preferably has a thickness of about 500 Å.
  • Referring to FIG. 3B, a first photoresist layer is deposited over the second insulating [0026] layer 146 and is patterned into a desired configuration as a first patterned photoresist layer 148 that exposes only the core region. The second insulating layer 146 and first insulating layer 144 exposed by the first patterned photoresist layer 148 are etched back to form spacers 150 on both sidewalls of the gate stacks 142 in the core region.
  • After removing the first [0027] patterned photoresist layer 148 by a conventional method such as plasma ashing, a second patterned photoresist layer 152 is formed to expose only the cell array region, as shown in FIG. 3C. Using the second patterned photoresist layer 152 to shield the core region, the silicon oxide layer 146 in the cell array region is etched to expose the silicon nitride layer 144. The etching of the oxide layer 146 is preferably carried out by conventional wet etching process. The second patterned photoresist layer 152 is then preferably removed by plasma ashing.
  • Referring to FIG. 3D, a planar [0028] interlayer insulating layer 154 is then formed over the resulting structure, preferably by the process of depositing and planarizing. The planarizing process step itself preferably includes a chemical mechanical polishing (CMP) step. A third photoresist layer (not shown) is then deposited over the interlayer insulating layer 154 and is patterned into a desired configuration that exposes a desired portion of the cell array region.
  • Using the third patterned photoresist layer, the [0029] interlayer insulating layer 154 is etched down to the silicon nitride layer 144 in certain areas, to form a plurality of contact holes 156 between the gate stacks as shown in FIG. 3E. During this process, the silicon nitride layer 144 preferably serves as etching stopper.
  • Referring to FIG. 3F, a third [0030] insulating layer 158 is deposited over the resulting structure shown in FIG. 3E. The third insulating layer 158 is preferably made of silicon oxide and preferably has a thickness in the range of about 300 Å to 500 Å. This silicon oxide layer 158 protects the silicon nitride capping layer 138 and a first insulating layer, i.e., silicon nitride layer 144.
  • The third [0031] silicon oxide layer 158 is then etched to form oxide spacers 160 on the first silicon nitride layer 144 that is formed on sidewalls of the contact holes 156 as shown in FIG. 3G.
  • Using the [0032] oxide spacers 160 as a mask, the first silicon nitride layer 144 between the gate stacks is then removed as shown in FIG. 3H.
  • After completely forming the contact hole, [0033] contact pads 162 for a bit line (corresponding to bit line contact pads 162 b from FIG. 2) and contact pads 162 for a storage node (corresponding to storage node contact pads 162 a from FIG. 2) are conventionally formed, as shown in FIG. 3I. A fourth insulating layer 163 is deposited over the resulting structure. Storage nodes 164 are then formed to electrically be connected to the contact pads 162 for the storage node.
  • It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementations can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modification and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variation in the disclosed novel concepts. [0034]

Claims (13)

What is claimed is:
1. A method of forming a contact hole in a semiconductor device, comprising:
forming at least two gate stacks over a semiconductor substrate;
forming a first insulating layer over the semiconductor substrate and at least two gate stacks;
forming an interlayer insulating layer over the first insulating layer;
etching a selected portion of the interlayer insulating layer to form a contact hole between the gate stacks;
forming a second insulating layer over the interlayer insulating layer, the contact hole and the semiconductor substrate;
etching back the second insulating layer to form spacers on sidewalls of the contact hole; and
using the interlayer insulating layer and the spacers as a mask to etch the first insulating layer to expose a top surface of the semiconductor substrate.
2. A method of forming a contact hole in a semiconductor device, as recited in
claim 1
, wherein the first insulating layer comprises silicon nitride and has a thickness of about 50 Å to 100 Å.
3. A method of forming a contact hole in a semiconductor device, as recited in
claim 1
, wherein the first insulating layer serves as an etching stopper during the etching of the interlayer insulating layer.
4. A method of forming a contact hole in a semiconductor device, as recited in
claim 1
, wherein the second insulating layer comprises silicon oxide and has a thickness of about 300 Å to 500 Å.
5. A method of forming a contact hole in a semiconductor device, as recited in
claim 1
, wherein each of the gate stacks comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer.
6. A method of forming a contact hole in a semiconductor device, as recited in
claim 5
, wherein each of the gate capping insulating layer comprises silicon nitride.
7. A method of forming a contact hole in a semiconductor substrate, the semiconductor substrate having a cell array region and a core region, the cell array region having at least two first gate stacks and the core region having at least two second gate stacks, the method comprising:
forming first and second insulating layers over the semiconductor substrate, the first gate stacks, and the second gate stacks;
forming a first photoresist layer over the second insulating layer to cover the cell array region and to expose the core region;
using the first photoresist layer as a mask to etch the first and second insulating layers to form first spacers on sidewalls of the second gate stacks;
removing the first photoresist layer;
forming a second photoresist layer to cover the core region and to expose the cell array region;
using the second photoresist layer as a mask to etch the second insulating layer to expose the first insulating layer;
removing the second photoresist layer;
forming an interlayer insulating layer over the semiconductor substrate, the first gate stacks, and the second gate stacks;
etching a selected portion of the interlayer insulating layer to form a contact hole between the first gate stacks;
forming a third insulating layer over the semiconductor substrate, the first gate stacks, the second gate stacks, and the contact hole;
etching the third insulating layer to form second spacers on sidewalls of the contact hole; and
using the interlayer insulating layer and the second spacers as a mask to etch the first insulating layer to expose a top surface of the semiconductor substrate.
8. A method of forming a contact hole in a semiconductor device, as recited in
claim 7
, wherein the first insulating layer comprises silicon nitride and has a thickness of about 50 Å to 100 Å.
9. A method of forming a contact hole in a semiconductor device, as recited in
claim 7
, wherein the second insulating layer comprises silicon oxide and has a thickness of about 500 Å.
10. A method of forming a contact hole in a semiconductor device, as recited in
claim 7
, wherein the third insulating layer comprises silicon oxide and has a thickness of about 300 Å to 500 Å.
11. A method of forming a contact hole in a semiconductor device, as recited in
claim 7
, wherein the first insulating layer serves as an etching stopper during the etching of the interlayer insulating layer.
12. A method of forming a contact hole in a semiconductor device, as recited in
claim 7
, wherein each of the first and second gate stacks comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer.
13. A method of forming a contact hole in a semiconductor device, as recited in
claim 12
, wherein each of the gate capping insulating layers comprises silicon nitride.
US09/783,044 1998-06-29 2001-02-15 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole Expired - Fee Related US6383862B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/783,044 US6383862B2 (en) 1998-06-29 2001-02-15 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR98-25172 1998-06-29
KR1019980025172A KR100282704B1 (en) 1998-06-29 1998-06-29 A METHOD OF FORMING A CONTACT HOLE OF SEMICONDUCTOR DEVICE
US09/335,784 US6221714B1 (en) 1998-06-29 1999-06-18 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole
US09/783,044 US6383862B2 (en) 1998-06-29 2001-02-15 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/335,784 Continuation US6221714B1 (en) 1998-06-29 1999-06-18 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole

Publications (2)

Publication Number Publication Date
US20010019866A1 true US20010019866A1 (en) 2001-09-06
US6383862B2 US6383862B2 (en) 2002-05-07

Family

ID=19541663

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/335,784 Expired - Lifetime US6221714B1 (en) 1998-06-29 1999-06-18 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole
US09/783,044 Expired - Fee Related US6383862B2 (en) 1998-06-29 2001-02-15 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/335,784 Expired - Lifetime US6221714B1 (en) 1998-06-29 1999-06-18 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole

Country Status (3)

Country Link
US (2) US6221714B1 (en)
JP (1) JP3803208B2 (en)
KR (1) KR100282704B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649508B1 (en) * 2000-02-03 2003-11-18 Samsung Electronics Co., Ltd. Methods of forming self-aligned contact structures in semiconductor integrated circuit devices
US20060292498A1 (en) * 2005-06-22 2006-12-28 Chang-Youn Hwang Method for forming contact hole in semiconductor device
US20160049310A1 (en) * 2014-08-18 2016-02-18 Imec Vzw Method for Selective Oxide Removal

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5112577B2 (en) * 1999-10-13 2013-01-09 ソニー株式会社 Manufacturing method of semiconductor device
JP4665140B2 (en) * 2000-03-01 2011-04-06 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
KR100416607B1 (en) * 2001-10-19 2004-02-05 삼성전자주식회사 Semiconductor device including transistor and manufacturing methode thereof
JP2003152176A (en) * 2001-11-14 2003-05-23 Matsushita Electric Ind Co Ltd Method of cleaning semiconductor device and its manufacturing method
KR100500439B1 (en) * 2002-08-14 2005-07-12 삼성전자주식회사 method for fabricating semiconductor device with gate spacer of positive slope
KR100557997B1 (en) 2003-01-29 2006-03-06 삼성전자주식회사 Method of fabricating semiconductor device including landing pad
US6960523B2 (en) * 2003-04-03 2005-11-01 Infineon Technolgies Ag Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device
KR100519642B1 (en) * 2003-12-31 2005-10-07 동부아남반도체 주식회사 Method for fabricating semiconductor device
KR100685677B1 (en) * 2004-09-30 2007-02-23 주식회사 하이닉스반도체 Method for fabrication of semiconductor device
KR100724568B1 (en) * 2005-10-12 2007-06-04 삼성전자주식회사 Semiconductor memory device and method of fabricating the same
US10050118B2 (en) 2014-05-05 2018-08-14 Globalfoundries Inc. Semiconductor device configured for avoiding electrical shorting

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786248A (en) 1995-10-12 1998-07-28 Micron Technology, Inc. Semiconductor processing method of forming a tantalum oxide containing capacitor
US5786249A (en) * 1996-03-07 1998-07-28 Micron Technology, Inc. Method of forming dram circuitry on a semiconductor substrate
KR100224720B1 (en) * 1996-10-31 1999-10-15 윤종용 Method for forming of contact hole in semiconductor device
JPH10150162A (en) * 1996-11-18 1998-06-02 Oki Electric Ind Co Ltd Semiconductor device and its manufacture
US6004843A (en) * 1998-05-07 1999-12-21 Taiwan Semiconductor Manufacturing Company Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip
TW404009B (en) * 1999-01-27 2000-09-01 United Microelectronics Corp The method of manufacturing self-aligned contact (SAC)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649508B1 (en) * 2000-02-03 2003-11-18 Samsung Electronics Co., Ltd. Methods of forming self-aligned contact structures in semiconductor integrated circuit devices
US6881659B2 (en) * 2000-02-03 2005-04-19 Samsung Electronics Co., Ltd. Methods of forming self-aligned contact structures in semiconductor integrated circuit devices
US20060292498A1 (en) * 2005-06-22 2006-12-28 Chang-Youn Hwang Method for forming contact hole in semiconductor device
US20160049310A1 (en) * 2014-08-18 2016-02-18 Imec Vzw Method for Selective Oxide Removal
US9502264B2 (en) * 2014-08-18 2016-11-22 Imec Vzw Method for selective oxide removal

Also Published As

Publication number Publication date
JP2000031088A (en) 2000-01-28
US6383862B2 (en) 2002-05-07
KR20000003872A (en) 2000-01-25
US6221714B1 (en) 2001-04-24
KR100282704B1 (en) 2001-03-02
JP3803208B2 (en) 2006-08-02

Similar Documents

Publication Publication Date Title
KR0155886B1 (en) High integrated dram cell fabrication method
US5776825A (en) Method for forming a semiconductor device having reduced stepped portions
US6383862B2 (en) Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole
US6337275B1 (en) Method for forming a self aligned contact in a semiconductor device
US6348375B1 (en) Method of fabricating a bit line structure for a semiconductor device
KR100349986B1 (en) Manufacturing method of via hole for bit line of memory cell
US6808975B2 (en) Method for forming a self-aligned contact hole in a semiconductor device
JP2568036B2 (en) Semiconductor device contact forming method
US20050054189A9 (en) Methods of fabricating integrated circuit devices providing improved short prevention
US6429107B2 (en) Method for forming conductive contact of semiconductor device
US5960293A (en) Methods including oxide masks for fabricating capacitor structures for integrated circuit devices
US6777343B2 (en) Method of forming contacts for a bit line and a storage node in a semiconductor device
JP3594213B2 (en) Method of forming connection portion and semiconductor chip
US6245657B1 (en) Self-aligned, low contact resistance, via fabrication process
US6291355B1 (en) Method of fabricating a self-aligned contact opening
US6248636B1 (en) Method for forming contact holes of semiconductor memory device
JP3352114B2 (en) Method for manufacturing semiconductor memory cell
JPH05343636A (en) Manufacture of semiconductor storage device
US7022567B2 (en) Method of fabricating self-aligned contact structures
US20020074665A1 (en) Metal contact structure in semiconductor device and method for forming the same
JPH08236721A (en) Semiconductor device and method of its fabrication
JP3172229B2 (en) Method for manufacturing semiconductor device
KR100248806B1 (en) Semiconductor memory device and the manufacturing method thereof
JPH088349A (en) Fabrication of semiconductor device
KR100200740B1 (en) Manufacturing method of semiconductor device in contact structure

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140507