US20010017806A1 - Method of repairing defective memory cells of an integrated memory - Google Patents
Method of repairing defective memory cells of an integrated memory Download PDFInfo
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- US20010017806A1 US20010017806A1 US09/793,789 US79378901A US2001017806A1 US 20010017806 A1 US20010017806 A1 US 20010017806A1 US 79378901 A US79378901 A US 79378901A US 2001017806 A1 US2001017806 A1 US 2001017806A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
Definitions
- the invention lies in the integrated technology field and relates, more specifically, to a method for repairing defective memory cells of an integrated memory.
- U.S. Pat. No. 5,206,583 describes an integrated circuit which has separable connections (fuses) for a permanent programming of redundant elements.
- the integrated circuit also has reversibly programmable elements in the form of latches which are connected in parallel with the fuses and which are used for testing the reversible programming of the redundant elements.
- the object of the present invention is to provide a method of repairing defective memory cells of an integrated memory device which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and wherein the necessary hardware components require the smallest possible area.
- a method of repairing defective memory cells of an integrated memory has memory cells arranged at cross points of row lines and column lines and reversibly programmable redundant lines including redundant row lines and redundant column lines.
- the method comprises the steps of:
- the memory cells are successively checked. Immediately following the detection of a defect of the memory cell checked in each case, the row line affected or the column line affected is replaced by programming one of the redundant lines. After a certain number of the redundant lines has been programmed, the programming of at least one redundant line is canceled when a further defect is detected, and this redundant line is programmed for repairing a defect of another memory cell.
- the column lines can be, for example, bit lines and the row lines can be, for example, word lines of the integrated memory.
- the column lines can also be word lines and the word lines can be bit lines of the memory.
- the method has the advantage that (in contrast with the above-noted U.S. Pat. No. 5,410,687) no error counters are required for each column line and row line to be checked since a defect is in each case repaired immediately after it has been detected. To achieve a certain optimization of the repair to be carried out, nevertheless, the programming of at least one of the redundant lines is canceled in dependence on the number of redundant lines already programmed previously so that this redundant line can then be used to repair a defect found later.
- the reversible programming of the redundant lines can be done, for example, by means of reversibly programmable elements such as the latches described in U.S. Pat. No. 5,206,583.
- the repair method according to the invention is distinguished by an extremely small hardware expenditure so that it is particularly suitable for implementing a self-test and a self repair of the integrated memory to be repaired. This means that all components required for carrying out the repair method are components of the integrated memory or, respectively, are arranged in the same integrated circuit together with this memory.
- the method according to the invention can also be implemented in software or can also be performed by an external tester of the integrated memory.
- the affected column line is replaced with one of the redundant column lines if a number of the programmed redundant column lines does not exceed a threshold value
- the threshold value i.e., the limit value for the number of redundant column lines to be programmed
- the threshold value is changed during the checking. This provides for an adaptation to the number of redundant column lines not yet programmed which still exists.
- the memory cells are checked for defects row by row and, when a defect of the memory cell just checked is detected, the column line affected is replaced by a redundant column line if the number of programmed redundant column lines does not then exceed a limit value.
- the limit value is exceeded, any programming of redundant column lines which has taken place on the basis of defects detected in the row line affected are canceled and the row line affected is replaced by one of the redundant row lines.
- a repair of detected defects in each case takes place perpendicularly to the direction of testing. This is because testing takes place row by row and replacement initially takes place column by column. It is only when the number of the redundant column lines already used exceeds the limit value that the preceding programming operations are at least partially canceled. However, it is only the programming operations of those redundant column lines which have been programmed on the basis of defects recognized in the relevant row line which are being canceled. Since the row line affected is then replaced by a redundant row line and the programming of redundant column lines which has taken place on the basis of row lines previously tested is not canceled, all defects detected are repaired in the manner described within a single test run through the memory cells if there are sufficient redundant lines.
- the novel method provides for the following steps:
- the memory cells are tested beginning with a start address. Once all redundant lines have been programmed, the programming of one of the redundant lines is canceled when another defect is detected. The memory cells are then tested again beginning with the start address. If then a defect is detected, the address of which is arranged before the further defect, the cancellation of the programming of the corresponding redundant line is reversed. This means that the corresponding redundant line is programmed to replace the same normal line as before the cancellation of its programming. After that, the three preceding method steps are repeated with respect to the cancellation of the programming of another one of the redundant lines. If, after the cancellation of the programming of one of the redundant lines, no defect with an address arranged before the further defect is detected during the subsequent testing of the memory cells, it is repaired with the redundant line which has become free due to the cancellation of its programming.
- This embodiment of the invention provides for the cancellation of the programming of those redundant lines which only repair defects which have already been detected and which, in addition, have already been eliminated by other redundant lines. These defects, therefore, stay repaired after the programming of the relevant redundant line has been canceled.
- the memory is marked unrepairable if, after the further defect has been found, the successive canceling of the programming of all redundant lines does not provide for a repair of all the detected defects.
- FIG. 1 is a flowchart of a first embodiment of the repair method according to the invention.
- FIG. 2 is a supplement to the flowchart of FIG. 1;
- FIG. 3 is a flowchart illustrating a second embodiment of the repair method
- FIGS. 4 to 10 are diagrammatic plan views and related tabular layouts showing an exemplary embodiment for carrying out the repair method of FIG. 3;
- FIGS. 11 and 12 are diagrammatic plan views and related tabular layouts of an exemplary embodiment of the execution of the repair method illustrated in FIG. 1.
- the memory cells of the integrated memory are successively tested.
- the address is correspondingly incremented.
- a counter X is set to zero. If a defect is detected, the counter X is incremented by one and the count of the counter X is compared with a limit value Y.
- the limit value Y applies to the number of maximum column lines permitted and programmed for the repair in the current row line. This is because the memory cells are tested row by row whereas the repair is carried out column by column when a defect is found.
- the counter X does not exceed the limit value Y when a defect is found, the defect is eliminated by a redundant column line. If, however, the counter X exceeds the limit value Y, the programming of the redundant column lines which have been programmed for the repair of defects detected in the current row line is canceled. After that, the current row line is repaired by a redundant row line.
- the redundant row line acting as replacement itself is checked for errors after the replacement.
- the repair method is continued with the check of the memory cell of the redundant row line which has the lowest column address. If errors are detected on the redundant row line, a repair is initially effected via the redundant column lines as before. If their number exceeds the permissible limit value, their programming is canceled and the redundant row line is replaced by another redundant row line.
- the checking of the memory cells of a programmed redundant row line can be omitted if the redundant lines have been tested before they were programmed and only error-free redundant lines are subsequently used for a repair.
- FIG. 11 An exemplary embodiment of the first embodiment of the repair method according to the invention will be explained with reference to FIGS. 11 and 12 in the text which follows.
- a memory cell array of the integrated memory is shown in the left-hand part and an overview of the redundant lines is shown in the right-hand part.
- FIGS. 11 and 12 and 4 to 10 essentially use the same type of representation which is why this will only be discussed once.
- the memory cells MC of the integrated memory are arranged at cross points of bit lines BL and word lines WL.
- the bit lines BL are numbered through from 0 to 3 and the word lines WL are numbered through from 0 to 4.
- Defective memory cells MC are marked by crosses.
- Memory cells MC already repaired by redundant lines are marked by squares.
- a circle marks the current defect, that is to say one that has just been found, of the memory cells MC.
- a table is shown which contains all available redundant lines of the memory as an illustration.
- the memory has two redundant word lines RWL 0 , RWL 1 and three redundant bit lines RBL 0 , RBL 1 , RBL 2 .
- the table specifies which of these redundant lines has already been programmed for replacing one of the normal lines BL, WL.
- a zero means that the associated redundant line has not yet been programmed and a one means that programming has already taken place.
- FIG. 11 The left-hand part of FIG. 11 also shows the manner in which the defective memory cells MC have been repaired.
- the redundant bit lines RBLi programmed for replacing the respective normal bit lines BL have been entered and below the memory cell array, the redundant word lines RWLi programmed for replacing the normal word lines are entered.
- a sequential test of the memory cells MC has already taken place before the state shown in FIG. 11, beginning with memory cell address 0,0 (that is to say word line WL 0 and bit line BL 0 ) in the direction of the word lines WL.
- Memory cell 0,0 does not exhibit a defect.
- memory cell 0,1 was tested (word line WL 0 , bit line BL 1 ) and a defect was found.
- FIG. 12 shows this state of the integrated memory.
- the limit value Y is again set to the value 2 since two of the redundant bit lines RBLi are again available for programming. These are redundant bit lines RBL 1 and RBL 2 , the programming of which has been canceled as has just been described.
- the memory cells are continuously tested so that next the defect having address 3,0 is detected. This is again repaired by means of one of the redundant bit lines RBLi.
- the repair method is analogously continued, the programming of some of the redundant bit lines being canceled whenever the count of counter X exceeds the limit value Y.
- the limit value Y is newly established at the beginning of the testing of the next word line WLi.
- FIG. 2 a supplement to the flowchart of FIG. 1 can be found at the point designated by A and B, according to which the limit value Y is adapted, for example, if the number of redundant column lines already programmed exceeds a value Z. In this case, only a relatively small number of redundant column lines is now available for programming so that the limit value Y must be reduced to a value Y′.
- FIG. 3 shows the flowchart for a second embodiment of the repair method according to the invention.
- the integrated memory has two redundant word lines RWL 0 , RWL 1 and two redundant bit lines RBL 0 , RBL 1 .
- Defective memory cells MC are again identified by crosses in the memory cell array. A circle identifies the current defect found.
- the repair of known defects is effected by programming the redundant lines in the order shown in the table in the right-hand part of the figures. To repair the first defect having address 0,1 (word line WL 0 , bit line BL 1 ), the redundant word line RWL 0 is, therefore, used.
- a pointer P points to the redundant line which is to be used next in each case.
- FIG. 5 shows the integrated memory after word line WL 0 has been replaced by redundant word line RBL 0 with respect to the address.
- the programming of the redundant word line RWL 0 which has taken place is marked by a 1 in the table.
- the pointer P points to the redundant line RWL 1 to be programmed next.
- Testing of the memory cells is sequentially continued and the defect of memory cell 1,0 is found next. According to FIG. 6, this defect is repaired by programming the redundant word line RWL 1 .
- the other defects on word line WL 1 are also repaired automatically without this having to be tested. It is assumed here that the programmed redundant lines are in each case free of errors. This can be detected by a test performed before they are programmed. Only the redundant lines found to be free of errors during this process are used for a repair.
- next word line WL 2 does not have a defect
- the next defect found is the one having address 3,0.
- the pointer P points to the third redundant line RBL 0 so that the current defect is replaced by redundant bit line RBL 0 .
- FIG. 7 the next defect having address 3,1 is replaced by redundant bit line RBL 1 .
- next defect found and having address 3,3 can now no longer be repaired without problems since all redundant lines have already been programmed and the pointer P again points to the first redundant line RWL 0 .
- the programming of the redundant line to which pointer P points (this is redundant line RBL 0 which was programmed first) is now canceled. Since the only defect which has hitherto been repaired by the redundant word line RWL 0 is the one having address 0,1 and this defect has also been eliminated by the programming of the redundant bit line RBL 1 , no defect having an address which is arranged before the current defect having address 3,3 is found during the subsequent test of all memory cells.
- the redundant word line RWL 0 which has become available due to the cancellation of its programming is, therefore, used for repairing the defect of memory cell 3,3. This state is shown in FIG. 9. Pointer P advances to the next redundant line.
- the memory test is continued with the memory cells MC not yet tested and the defect having address 4,2 is found.
- the programming of the redundant word line RWL 1 to which pointer P is pointing, is subsequently canceled.
- the memory cells are again tested beginning at address 0,0, the defect having address 1,2 being found first. Its address is smaller than address 4,2 of the current defect.
- the cancellation of the programming of the redundant word line RWL 1 is, therefore, reversed again.
- the pointer advances to the next redundant line RBL 0 (FIG. 10). Since the current defect having address 4,2 has still not been repaired, the programming of this redundant line RBL 0 is now canceled.
- the memory cells are tested again beginning at start address 0,0. During this testing, no defect is found which is before the current defect having address 4,2. The reason for this is that the defects having addresses 1,0 and 3,0 have already been repaired by the redundant word lines RBL 1 and RWL 0 .
- the redundant bit line RBL 0 which has become available can thus be programmed for repairing the current defect. This state is shown in FIG. 10.
- the pointer P advances to the next programmed redundant line RBL 1 .
- the memory cell having address 4,3 is also tested and does not exhibit a defect. The repair method is thus concluded with an integrated memory which is completely repaired.
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Abstract
Description
- This application is a continuation of copending International Application PCT/DE99/02571, filed Aug. 17, 1999, which designated the United States.
- Field of the Invention
- The invention lies in the integrated technology field and relates, more specifically, to a method for repairing defective memory cells of an integrated memory.
- Such a method is described in U.S. Pat. No. 5,410,687. There, individual memory cells of a memory are tested which are located at cross points of rows and columns. The memory has, for each column and each row, an error counter in which the errors detected for this column or row, respectively, are added together. After all memory cells have been checked, a repair of defective memory cells is effected by means of redundant column and row lines on the basis of the information stored in the error counters. The method described has the disadvantage that the error counters needed for its execution require a relatively large space.
- U.S. Pat. No. 5,206,583 describes an integrated circuit which has separable connections (fuses) for a permanent programming of redundant elements. The integrated circuit also has reversibly programmable elements in the form of latches which are connected in parallel with the fuses and which are used for testing the reversible programming of the redundant elements.
- The object of the present invention is to provide a method of repairing defective memory cells of an integrated memory device which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and wherein the necessary hardware components require the smallest possible area.
- With the above and other objects in view there is provided, in accordance with the invention, a method of repairing defective memory cells of an integrated memory. The memory has memory cells arranged at cross points of row lines and column lines and reversibly programmable redundant lines including redundant row lines and redundant column lines. The method comprises the steps of:
- successively testing the memory cells;
- immediately upon detecting a defect of a memory cell being tested, replacing the respectively affected row line or column line by programming one of the redundant lines;
- after a certain number of the redundant lines have been programmed, canceling a programming of a given one of the redundant lines upon detecting a further defect; and
- programming the given redundant line for repairing a defect of another memory cell.
- In other words, according to the novel testing method, the memory cells are successively checked. Immediately following the detection of a defect of the memory cell checked in each case, the row line affected or the column line affected is replaced by programming one of the redundant lines. After a certain number of the redundant lines has been programmed, the programming of at least one redundant line is canceled when a further defect is detected, and this redundant line is programmed for repairing a defect of another memory cell.
- The column lines can be, for example, bit lines and the row lines can be, for example, word lines of the integrated memory. In other exemplary embodiments, the column lines can also be word lines and the word lines can be bit lines of the memory.
- The method has the advantage that (in contrast with the above-noted U.S. Pat. No. 5,410,687) no error counters are required for each column line and row line to be checked since a defect is in each case repaired immediately after it has been detected. To achieve a certain optimization of the repair to be carried out, nevertheless, the programming of at least one of the redundant lines is canceled in dependence on the number of redundant lines already programmed previously so that this redundant line can then be used to repair a defect found later.
- The reversible programming of the redundant lines can be done, for example, by means of reversibly programmable elements such as the latches described in U.S. Pat. No. 5,206,583. The repair method according to the invention is distinguished by an extremely small hardware expenditure so that it is particularly suitable for implementing a self-test and a self repair of the integrated memory to be repaired. This means that all components required for carrying out the repair method are components of the integrated memory or, respectively, are arranged in the same integrated circuit together with this memory. On the other hand, naturally, the method according to the invention can also be implemented in software or can also be performed by an external tester of the integrated memory.
- In accordance with an added feature of the invention:
- the memory cells are tested for defects row by row;
- upon finding a defect of the memory cell being tested, the affected column line is replaced with one of the redundant column lines if a number of the programmed redundant column lines does not exceed a threshold value;
- if the threshold value is exceeded, any programming of redundant column lines which has taken place due to defects having been found in the affected row line is canceled; and
- the affected row line is replaced with one of the redundant row lines.
- In accordance with an additional feature of the invention, the threshold value, i.e., the limit value for the number of redundant column lines to be programmed, is changed during the checking. This provides for an adaptation to the number of redundant column lines not yet programmed which still exists.
- According to this first embodiment of the repair method, the memory cells are checked for defects row by row and, when a defect of the memory cell just checked is detected, the column line affected is replaced by a redundant column line if the number of programmed redundant column lines does not then exceed a limit value. When the limit value is exceeded, any programming of redundant column lines which has taken place on the basis of defects detected in the row line affected are canceled and the row line affected is replaced by one of the redundant row lines.
- In this embodiment, a repair of detected defects in each case takes place perpendicularly to the direction of testing. This is because testing takes place row by row and replacement initially takes place column by column. It is only when the number of the redundant column lines already used exceeds the limit value that the preceding programming operations are at least partially canceled. However, it is only the programming operations of those redundant column lines which have been programmed on the basis of defects recognized in the relevant row line which are being canceled. Since the row line affected is then replaced by a redundant row line and the programming of redundant column lines which has taken place on the basis of row lines previously tested is not canceled, all defects detected are repaired in the manner described within a single test run through the memory cells if there are sufficient redundant lines.
- In accordance with an alternative feature of the invention, the novel method provides for the following steps:
- testing the memory cells, beginning at a start address;
- once all redundant lines have been programmed, canceling the programming of one of the redundant lines if a further defect is found;
- retesting the memory cells, beginning at the start address;
- if, during the retesting step, a defect is found, with an address before the further defect, reversing the canceling of the programming of the corresponding redundant line;
- subsequently repeating the three preceding method steps with respect to the step of canceling the programming of another one of the redundant lines;
- if, after canceling the programming of one of the redundant lines, during the subsequent testing of the memory cells, no defect is found with an address before the further defect, repairing the further defect with the redundant line that has become available due to the canceling of its programming.
- In other words, the memory cells are tested beginning with a start address. Once all redundant lines have been programmed, the programming of one of the redundant lines is canceled when another defect is detected. The memory cells are then tested again beginning with the start address. If then a defect is detected, the address of which is arranged before the further defect, the cancellation of the programming of the corresponding redundant line is reversed. This means that the corresponding redundant line is programmed to replace the same normal line as before the cancellation of its programming. After that, the three preceding method steps are repeated with respect to the cancellation of the programming of another one of the redundant lines. If, after the cancellation of the programming of one of the redundant lines, no defect with an address arranged before the further defect is detected during the subsequent testing of the memory cells, it is repaired with the redundant line which has become free due to the cancellation of its programming.
- This embodiment of the invention provides for the cancellation of the programming of those redundant lines which only repair defects which have already been detected and which, in addition, have already been eliminated by other redundant lines. These defects, therefore, stay repaired after the programming of the relevant redundant line has been canceled.
- In accordance with a concomitant feature of the invention, the memory is marked unrepairable if, after the further defect has been found, the successive canceling of the programming of all redundant lines does not provide for a repair of all the detected defects.
- Other features which are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in a method for repairing defective memory cells of an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
- FIG. 1 is a flowchart of a first embodiment of the repair method according to the invention;
- FIG. 2 is a supplement to the flowchart of FIG. 1;
- FIG. 3 is a flowchart illustrating a second embodiment of the repair method;
- FIGS.4 to 10 are diagrammatic plan views and related tabular layouts showing an exemplary embodiment for carrying out the repair method of FIG. 3; and
- FIGS. 11 and 12 are diagrammatic plan views and related tabular layouts of an exemplary embodiment of the execution of the repair method illustrated in FIG. 1.
- Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, the memory cells of the integrated memory are successively tested. To test the next memory cell in each case, the address is correspondingly incremented. With each beginning of the testing of a new row line, a counter X is set to zero. If a defect is detected, the counter X is incremented by one and the count of the counter X is compared with a limit value Y. The limit value Y applies to the number of maximum column lines permitted and programmed for the repair in the current row line. This is because the memory cells are tested row by row whereas the repair is carried out column by column when a defect is found. As long as the counter X does not exceed the limit value Y when a defect is found, the defect is eliminated by a redundant column line. If, however, the counter X exceeds the limit value Y, the programming of the redundant column lines which have been programmed for the repair of defects detected in the current row line is canceled. After that, the current row line is repaired by a redundant row line.
- It is particularly advantageous if the redundant row line acting as replacement itself is checked for errors after the replacement. For this purpose, the repair method is continued with the check of the memory cell of the redundant row line which has the lowest column address. If errors are detected on the redundant row line, a repair is initially effected via the redundant column lines as before. If their number exceeds the permissible limit value, their programming is canceled and the redundant row line is replaced by another redundant row line. Naturally, the checking of the memory cells of a programmed redundant row line can be omitted if the redundant lines have been tested before they were programmed and only error-free redundant lines are subsequently used for a repair.
- An exemplary embodiment of the first embodiment of the repair method according to the invention will be explained with reference to FIGS. 11 and 12 in the text which follows. In FIG. 11, a memory cell array of the integrated memory is shown in the left-hand part and an overview of the redundant lines is shown in the right-hand part. FIGS. 11 and 12 and4 to 10 essentially use the same type of representation which is why this will only be discussed once. The memory cells MC of the integrated memory are arranged at cross points of bit lines BL and word lines WL. The bit lines BL are numbered through from 0 to 3 and the word lines WL are numbered through from 0 to 4. Defective memory cells MC are marked by crosses. Memory cells MC already repaired by redundant lines are marked by squares. A circle marks the current defect, that is to say one that has just been found, of the memory cells MC. In the right-hand part of FIG. 11, a table is shown which contains all available redundant lines of the memory as an illustration. In the exemplary embodiment explained with reference to FIGS. 11 and 12, the memory has two redundant word lines RWL0, RWL1 and three redundant bit lines RBL0, RBL1, RBL2. The table specifies which of these redundant lines has already been programmed for replacing one of the normal lines BL, WL. A zero means that the associated redundant line has not yet been programmed and a one means that programming has already taken place.
- The left-hand part of FIG. 11 also shows the manner in which the defective memory cells MC have been repaired. To the right of the memory cell array, the redundant bit lines RBLi programmed for replacing the respective normal bit lines BL have been entered and below the memory cell array, the redundant word lines RWLi programmed for replacing the normal word lines are entered. In the present case, a sequential test of the memory cells MC has already taken place before the state shown in FIG. 11, beginning with
memory cell address 0,0 (that is to say word line WL0 and bit line BL0) in the direction of the word lines WL.Memory cell memory cell bit line 1 with the redundant bit line RLB0. After that, testing of the memory cells continued and, at the beginning of the next word line WL1, the error counter X was reset to zero. Thedefective memory cell value 1. Since bit line BL1 has already been replaced by the redundant bit line RBL0, the next error found is the one having theaddress memory cell addresses address - FIG. 12 shows this state of the integrated memory. The limit value Y is again set to the
value 2 since two of the redundant bit lines RBLi are again available for programming. These are redundant bit lines RBL1 and RBL2, the programming of which has been canceled as has just been described. The memory cells are continuously tested so that next thedefect having address - If the number of available redundant bit lines RBLi not yet programmed changes, the limit value Y is newly established at the beginning of the testing of the next word line WLi. In FIG. 2, a supplement to the flowchart of FIG. 1 can be found at the point designated by A and B, according to which the limit value Y is adapted, for example, if the number of redundant column lines already programmed exceeds a value Z. In this case, only a relatively small number of redundant column lines is now available for programming so that the limit value Y must be reduced to a value Y′.
- FIG. 3 shows the flowchart for a second embodiment of the repair method according to the invention. The memory cells are tested sequentially, beginning with an address ADR=0. As long as no fault is found, the address is continuously incremented. When the last address has been reached and no defect remains as unrepairable, the integrated circuit is considered to be repaired and the repair method is terminated. As soon as a defective memory cell has been found, the defect is repaired by replacing the row line affected, or the column line affected, by means of a corresponding redundant line as long as a redundant line is still available for programming. If, however, all redundant lines have already been programmed, the programming of one of the redundant lines is canceled so that the original, normal column or row line, respectively, is addressed again. After that, all memory cells are again sequentially tested beginning with start address ADR=0. If then no defect is found, the address of which is before the defect last found, it is certain that the defects repaired by the redundant line, the programming of which has been canceled, have also been repaired by other redundant lines (that is to say several times). The redundant line which has become available can therefore be used for repairing the defect last found. If, however, a defect having a lower address than that of the defect last found is found, the canceling of the programming of the redundant line affected is reversed. This means that it is newly programmed in exactly the same manner as was the case before the cancellation of its programming. This redundant line can thus not be used for repairing the current defect. Instead, the programming of another one of the redundant lines is canceled and the cells are tested again. This method is repeated until the cancellation of the programming of one of the redundant lines is successful or until the programming of all redundant lines has been successively canceled without having been able to repair the current defect. In the latter case, the chip is marked as defective and the repair method is terminated.
- In the text which follows, an actual exemplary embodiment of the repair method shown in FIG. 3 is described with reference to FIGS.4 to 10. In this exemplary embodiment, the integrated memory has two redundant word lines RWL0, RWL1 and two redundant bit lines RBL0, RBL1. Defective memory cells MC are again identified by crosses in the memory cell array. A circle identifies the current defect found. In this exemplary embodiment the repair of known defects is effected by programming the redundant lines in the order shown in the table in the right-hand part of the figures. To repair the first
defect having address 0,1 (word line WL0, bit line BL1), the redundant word line RWL0 is, therefore, used. A pointer P points to the redundant line which is to be used next in each case. - FIG. 5 shows the integrated memory after word line WL0 has been replaced by redundant word line RBL0 with respect to the address. The programming of the redundant word line RWL0 which has taken place is marked by a 1 in the table. The pointer P points to the redundant line RWL1 to be programmed next. Testing of the memory cells is sequentially continued and the defect of
memory cell - Since the next word line WL2 does not have a defect, the next defect found is the one having
address defect having address - The next defect found and having
address address defect having address memory cell defect having address address defect having address address - The pointer advances to the next redundant line RBL0 (FIG. 10). Since the current
defect having address start address defect having address defects having addresses cell having address
Claims (5)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19838861A DE19838861A1 (en) | 1998-08-26 | 1998-08-26 | Process for repairing defective memory cells of an integrated memory |
DE19838861.6 | 1998-08-26 | ||
DE19838861 | 1998-08-26 | ||
PCT/DE1999/002571 WO2000013087A1 (en) | 1998-08-26 | 1999-08-17 | Method for repairing faulty storage cells of an integrated memory |
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PCT/DE1999/002571 Continuation WO2000013087A1 (en) | 1998-08-26 | 1999-08-17 | Method for repairing faulty storage cells of an integrated memory |
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US6418069B2 US6418069B2 (en) | 2002-07-09 |
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US (1) | US6418069B2 (en) |
EP (1) | EP1105802B1 (en) |
JP (1) | JP3734709B2 (en) |
KR (1) | KR100404016B1 (en) |
DE (2) | DE19838861A1 (en) |
TW (1) | TW440855B (en) |
WO (1) | WO2000013087A1 (en) |
Cited By (9)
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US20020133770A1 (en) * | 2001-03-15 | 2002-09-19 | Cowles Timothy B. | Circuit and method for test and repair |
US20030172325A1 (en) * | 2002-03-06 | 2003-09-11 | Wyatt Stewart R. | Verifying data in a data storage device |
US20100157703A1 (en) * | 2007-04-26 | 2010-06-24 | Frederick Harrison Fischer | Embedded Memory Repair |
US10157097B2 (en) * | 2016-08-11 | 2018-12-18 | SK Hynix Inc. | Redundant bytes utilization in error correction code |
US20190096455A1 (en) * | 2016-08-02 | 2019-03-28 | SK Hynix Inc. | Semiconductor devices and semiconductor systems |
US10685697B2 (en) | 2016-08-02 | 2020-06-16 | SK Hynix Inc. | Semiconductor devices and operations thereof |
US10847195B2 (en) | 2016-06-27 | 2020-11-24 | SK Hynix Inc. | Semiconductor device having ranks that performs a termination operation |
US11133042B2 (en) | 2016-06-27 | 2021-09-28 | SK Hynix Inc. | Semiconductor memory system and semiconductor memory device, which can be remotely initialized |
US11217286B2 (en) | 2016-06-27 | 2022-01-04 | SK Hynix Inc. | Semiconductor memory device with power down operation |
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DE19901206C2 (en) | 1999-01-14 | 2003-02-06 | Infineon Technologies Ag | Method for repairing defective memory cells of an integrated semiconductor memory |
US20020133769A1 (en) * | 2001-03-15 | 2002-09-19 | Cowles Timothy B. | Circuit and method for test and repair |
JP2002343098A (en) * | 2001-05-18 | 2002-11-29 | Mitsubishi Electric Corp | Test method for semiconductor memory |
US7509543B2 (en) * | 2003-06-17 | 2009-03-24 | Micron Technology, Inc. | Circuit and method for error test, recordation, and repair |
JP2006185569A (en) * | 2004-12-01 | 2006-07-13 | Toshiba Corp | Semiconductor memory device |
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US7260004B2 (en) * | 2006-01-12 | 2007-08-21 | International Busniess Machines Corporation | Method and apparatus for increasing yield in a memory circuit |
JP4877396B2 (en) * | 2010-01-20 | 2012-02-15 | 日本電気株式会社 | Memory fault processing system and memory fault processing method |
US11682471B2 (en) | 2020-05-28 | 2023-06-20 | International Business Machines Corporation | Dual damascene crossbar array for disabling a defective resistive switching device in the array |
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US4586178A (en) | 1983-10-06 | 1986-04-29 | Eaton Corporation | High speed redundancy processor |
JP2842923B2 (en) * | 1990-03-19 | 1999-01-06 | 株式会社アドバンテスト | Semiconductor memory test equipment |
US5206583A (en) * | 1991-08-20 | 1993-04-27 | International Business Machines Corporation | Latch assisted fuse testing for customized integrated circuits |
US6026505A (en) * | 1991-10-16 | 2000-02-15 | International Business Machines Corporation | Method and apparatus for real time two dimensional redundancy allocation |
FR2699301B1 (en) * | 1992-12-16 | 1995-02-10 | Sgs Thomson Microelectronics | Method for treating defective elements in a memory. |
JP3774500B2 (en) * | 1995-05-12 | 2006-05-17 | 株式会社ルネサステクノロジ | Semiconductor memory device |
JPH1064294A (en) * | 1996-08-20 | 1998-03-06 | Advantest Corp | Failure rescue analysis method of memory device |
DE19725581C2 (en) | 1997-06-17 | 2000-06-08 | Siemens Ag | Method for checking the function of memory cells of an integrated memory |
-
1998
- 1998-08-26 DE DE19838861A patent/DE19838861A1/en not_active Withdrawn
-
1999
- 1999-08-17 WO PCT/DE1999/002571 patent/WO2000013087A1/en active IP Right Grant
- 1999-08-17 DE DE59901516T patent/DE59901516D1/en not_active Expired - Lifetime
- 1999-08-17 JP JP2000568008A patent/JP3734709B2/en not_active Expired - Fee Related
- 1999-08-17 EP EP99952423A patent/EP1105802B1/en not_active Expired - Lifetime
- 1999-08-17 KR KR10-2001-7002435A patent/KR100404016B1/en not_active IP Right Cessation
- 1999-08-19 TW TW088114175A patent/TW440855B/en not_active IP Right Cessation
-
2001
- 2001-02-26 US US09/793,789 patent/US6418069B2/en not_active Expired - Lifetime
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US20020133770A1 (en) * | 2001-03-15 | 2002-09-19 | Cowles Timothy B. | Circuit and method for test and repair |
US20020133767A1 (en) * | 2001-03-15 | 2002-09-19 | Cowles Timothy B. | Circuit and method for test and repair |
US6904552B2 (en) | 2001-03-15 | 2005-06-07 | Micron Technolgy, Inc. | Circuit and method for test and repair |
US6918072B2 (en) | 2001-03-15 | 2005-07-12 | Micron Technology, Inc. | Circuit and method for time-efficient memory repair |
US20030172325A1 (en) * | 2002-03-06 | 2003-09-11 | Wyatt Stewart R. | Verifying data in a data storage device |
US6968479B2 (en) * | 2002-03-06 | 2005-11-22 | Hewlett-Packard Development Company, L.P. | Verifying data in a data storage device |
US20100157703A1 (en) * | 2007-04-26 | 2010-06-24 | Frederick Harrison Fischer | Embedded Memory Repair |
US7895482B2 (en) * | 2007-04-26 | 2011-02-22 | Agere Systems Inc. | Embedded memory repair |
US10847195B2 (en) | 2016-06-27 | 2020-11-24 | SK Hynix Inc. | Semiconductor device having ranks that performs a termination operation |
US11133042B2 (en) | 2016-06-27 | 2021-09-28 | SK Hynix Inc. | Semiconductor memory system and semiconductor memory device, which can be remotely initialized |
US11217286B2 (en) | 2016-06-27 | 2022-01-04 | SK Hynix Inc. | Semiconductor memory device with power down operation |
US20190096455A1 (en) * | 2016-08-02 | 2019-03-28 | SK Hynix Inc. | Semiconductor devices and semiconductor systems |
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US10777241B2 (en) * | 2016-08-02 | 2020-09-15 | SK Hynix Inc. | Semiconductor devices and semiconductor systems |
US10157097B2 (en) * | 2016-08-11 | 2018-12-18 | SK Hynix Inc. | Redundant bytes utilization in error correction code |
Also Published As
Publication number | Publication date |
---|---|
JP3734709B2 (en) | 2006-01-11 |
KR100404016B1 (en) | 2003-11-05 |
JP2002523856A (en) | 2002-07-30 |
EP1105802A1 (en) | 2001-06-13 |
US6418069B2 (en) | 2002-07-09 |
DE19838861A1 (en) | 2000-03-02 |
WO2000013087A1 (en) | 2000-03-09 |
DE59901516D1 (en) | 2002-06-27 |
EP1105802B1 (en) | 2002-05-22 |
KR20010072986A (en) | 2001-07-31 |
TW440855B (en) | 2001-06-16 |
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