US20010017797A1 - Low consumption voltage boost device - Google Patents
Low consumption voltage boost device Download PDFInfo
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- US20010017797A1 US20010017797A1 US09/747,312 US74731200A US2001017797A1 US 20010017797 A1 US20010017797 A1 US 20010017797A1 US 74731200 A US74731200 A US 74731200A US 2001017797 A1 US2001017797 A1 US 2001017797A1
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- voltage boost
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- the present invention refers to a voltage boost device for nonvolatile memories, which operates in a low consumption standby condition.
- nonvolatile memories are used, i.a., in systems comprising various devices and a microprocessor performing instructions and data transfer. In such devices it is important that, while a device is selected for interacting with the microprocessor, all the other devices are disabled, in order to prevent undesirable interference from causing errors.
- nonvolatile memories in particular, the most critical operation is reading, both because, as compared to other operations, such as programming and erasure, it must be performed in a very short time, and because it is necessary to supply the gate terminals of the cells to be read with high voltages, i.e., higher than the supply voltage.
- high voltages i.e., higher than the supply voltage.
- the value of the read voltage supplied it is moreover essential for the value of the read voltage supplied to be precise and close to the value of the nominal read voltage.
- a known solution consists in using voltage boosters employing charge pumps and regulation circuits, so as to obtain the required high read voltages and precision when the memory is selected to interact with the microprocessor.
- Such voltage boosters have a drawback.
- the charge pumps and the regulation circuits have consumption levels which are too high to enable these devices to remain active also while the memory is in standby, and consequently they must be deactivated; on the other hand, when they are not supplied, the output terminals of the charge pumps, which are to supply the read voltage to the gate terminals of the addressed cells to be read, are discharged by leakage currents. Consequently, when the memory returns to the active state from the standby state, it is necessary to wait for a charge transient and it is not possible to reach the necessary read voltage rapidly and with the required precision. In this case, therefore, the reading operation requires a longer time as compared to when the memory is already in the active state.
- the aim of the present invention is to provide a voltage boost device which is free from the drawbacks described above, and in particular which enables a terminal to be kept at a desired voltage during the standby phases, and at the same time has low consumption levels.
- a voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage.
- the input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state.
- the first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal;
- the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.
- FIG. 1 shows a block diagram of a voltage boost device according to the present invention
- FIG. 2 shows a more detailed diagram of two blocks of the device of FIG. 1;
- FIG. 3 is a simplified circuit diagram of a detail of the device of FIG. 1.
- a nonvolatile memory 1 for example a four-level flash memory supplied at 3 V, comprises a memory array 2 and a voltage boost device 3 comprising a read voltage boost stage 4 of a known type, which is shown only partially, and a standby voltage boost stage 5 .
- the memory array 2 comprises a plurality of memory cells 6 arranged on rows and columns.
- the memory cells 6 belonging to a same row have their gate terminals connected to a word line 7 .
- a row decoder 8 connects selectively one of the word lines 7 of the memory array 2 with an output terminal 10 of the voltage boost device 3 .
- the row decoder 8 has a capacitance represented symbolically by a parasitic capacitor 11 connected between the output terminal 10 and ground.
- the read voltage boost stage 4 comprises a read charge pump 12 having an output supplying a read voltage V R and is connected, via a first switch 13 , to a first node 15 .
- the first node 15 is connected to a first terminal of a read capacitor 16 , which has a second terminal grounded, and to an input of a voltage regulator 17 having an output supplying a regulated read voltage V RR and connected to the output terminal 10 via a second switch 18 .
- the read charge pump 12 , the voltage regulator 17 , and respective control terminals of the first switch 13 and of the second switch 18 receive, from a known control unit 20 , a standby signal SB.
- the standby voltage boost stage 5 comprises a divider 21 , a phase generator 30 , a voltage booster 31 , a standby charge pump 32 , and an auxiliary regulator 37 .
- the divider 21 is arranged between the output terminal 10 of the voltage boost device 3 and ground, and comprises a first resistive element 22 and a second resistive element 23 which are connected together at an intermediate node 25 , on which an intermediate voltage V X is present.
- the divider 21 has a variable division ratio, as described in detail hereinbelow.
- a comparator 27 has an inverting input connected to the intermediate node 25 and a non-inverting input connected to a voltage generator 28 , which supplies a constant reference voltage V REF .
- an output of the comparator 27 is connected to an activation terminal of the phase generator 30 .
- a control signal V C is supplied by output of the comparator 27 and determines activation and deactivation of the standby charge pump 32 during the standby phase.
- the phase generator 30 is also connected to the control unit 20 , from which it receives the standby signal SB and an active operation timing signal CK 1 having one first frequency, as well as to an output of the auxiliary regulator 37 supplying a frequency selection signal SEL.
- the phase generator 30 has a phase output 30 a supplying a phase signal CK.
- the divider 21 , the comparator 27 , and the phase generator 30 form an activation circuit 29 activating the standby charge pump 32 , the activation circuit 29 having an input connected to the output terminal 10 of the voltage boost device 3 and an output forming the phase output 30 a.
- the standby charge pump 32 has an input connected to the phase output 30 a and a high voltage output 33 , supplying a boosted voltage V P and connected to the output terminal 10 of the voltage boost device 3 via a first high voltage switch 34 and a second high voltage switches 35 , and to the input of the auxiliary regulator 37 .
- a second node 38 arranged between the first and the second high voltage switch 34 , 35 , is connected to the first node 15 .
- the voltage booster 31 has a high voltage input connected to the high voltage output 33 and a control input receiving the standby signal SB. In addition, the voltage booster 31 has an output connected with respective control terminals of the first and second high voltage switches 34 , 35 and supplies a driving voltage V D .
- the auxiliary regulator 37 has a first input connected to the high voltage output 33 of the standby charge pump 32 and a second input connected to the control unit 20 , and receiving the standby signal SB.
- the control unit 20 assigns to the standby signal SB a first logic level, for example a high logic level, thus determining opening of the first and of the second switches 13 , 18 , and deactivation of the read charge pump 12 and of the voltage regulator 17 .
- the standby signal SB disables the auxiliary regulator 37 , which thus generates a first logic level of the frequency selection signal SEL (for example, a low level), and enables the phase generator 30 .
- the first logic level of the standby signal SB brings the driving voltage V D of the voltage booster 31 to 0 V, so determining the first and the second high voltage switches 34 , 35 to close.
- the first and the second high voltage switches 34 , 35 are preferably formed by PMOS transistors.
- the phase generator 30 causes the phase signal CK to oscillate between two preset logic levels at a second frequency, which is determined internally by the phase generator 30 .
- the phase generator 30 maintains the phase signal CK at a preset logic level, for example low, interrupting operation of the standby charge pump 32 .
- Standby voltage V SB represents an output voltage of the standby voltage boost stage 5 and is initially equal to the regulated read voltage V RR because of the connection existing (before entry into the standby state) on the output of the voltage regulator 17 .
- the intermediate voltage V X which is proportional to the standby voltage V SB according to the dividing ratio of the divider 21 , is at a value slightly higher than the reference voltage V REF , and, therefore, the control signal V C is at the low logic level. Consequently, the phase signal CK remains at low logic level, and the voltage booster 31 keeps the first high voltage switch 34 and the second high voltage switch 35 open.
- the standby voltage V SB and the intermediate voltage V X decrease by virtue of leakage currents and of a current flowing in the divider 21 .
- the control signal V C switches to the high logic level, and the phase generator 30 causes the phase signal CK to oscillate with a frequency determined by the phase generator 30 .
- the standby charge pump 32 receives an oscillating signal (i.e., the phase signal CK), it is activated, so determining the sequence of phases of charging and transfer of charge, in a per se known manner.
- the standby charge pump 32 starts charging the high voltage output 33 , the standby voltage V SB , which is equal to the boosted voltage V P , and the voltage V X increase.
- the control signal V C returns low, so deactivating the phase generator 30 , as explained previously with reference to the description of the entry into the standby state.
- the standby voltage regulator stage 5 is activated and deactivated automatically, so as to keep the output terminal 10 charged at the desired value (standby voltage V SB ), and to enable fast reading when exiting the standby state, at the same time limiting consumption to what is strictly indispensable.
- control unit 20 sends the standby signal SB to a second logic level, for example the low logic level, causing the switches 13 , 18 to close, and the read charge pump 12 and the voltage regulator 17 to be activated.
- the standby signal SB sets the driving voltage V D of the voltage booster 31 to the high value (equal to the boosted voltage V P ), keeping the first high voltage switch 34 and the second high voltage switch 35 open. Consequently, the first high voltage switch 34 and the second high voltage switch 35 are kept open, and the high voltage output 33 of the standby charge pump 32 is disconnected from the output terminal 10 and from the first node 15 .
- the read charge pump 12 supplies the read voltage V R to the voltage regulator 17 , which, in turn, generates the regulated read voltage V RR .
- This regulated read voltage V RR is supplied to the word line 7 selected by the line decoder 8 for reading the addressed memory cells 6 , in a per se known manner.
- the standby charge pump 32 is enabled and driven by the timing signal of the other voltage boosters (not shown) present in the nonvolatile memory 1 ; it is, however, regulated through the auxiliary regulator 37 , as described below.
- the auxiliary regulator 37 is active, and the frequency selection signal SEL assumes a logic level that depends upon the value of the boosted voltage V P , which, owing to the presence of leakage currents, decreases.
- the auxiliary regulator 37 causes the frequency selection signal SEL to switch to a second logic level (e.g., high) which controls the phase generator 30 , as described hereinbelow, to transfer the active operation timing signal CK 1 to the standby charge pump 32 . Consequently, the standby charge pump 32 is activated at the frequency of the active operation timing signal CK 1 until the boosted voltage V P returns above the preset threshold. Then, the frequency selection signal SEL switches and inhibits transfer of the active operation timing signal CK 1 to the standby charge pump 32 , thus deactivating the latter again.
- a second logic level e.g., high
- the standby voltage V SB on the output terminal 10 is regulated at a slightly higher value than the regulated read voltage V RR (present in the active operation state).
- the high voltage output 33 of the standby charge pump 32 is regulated at the value of the regulated read voltage V RR .
- FIG. 2 shows a more detailed diagram of the phase generator 30 and of the standby charge pump 32 .
- the phase generator 30 comprises an oscillator 40 comprising a plurality of inverters 41 , in an odd number and connected together to form a loop.
- An enabling node 42 is connected, via an enabling switch 43 , preferably formed by a PMOS transistor, to a supply line 44 supplying a supply voltage V CC , for example 3 V.
- the enabling node 42 is connected to an input of a toggle-type flip-flop 45 having a set terminal connected to the control unit 20 , supplying the standby signal SB.
- An OR gate 46 has a first input connected to the output of the comparator 27 , a second input connected to an output of the flip-flop 45 , and an output connected to a control terminal of the enabling switch 43 .
- the phase generator 30 further comprises a selector 47 having a first selectable input 47 a connected to the output of the flip-flop 45 , a second selectable input 47 b connected to the control unit 20 supplying the active operation timing signal CK 1 , a selection terminal 47 c receiving the frequency selection signal SEL, and an output defining the phase output 30 a of the phase generator 30 .
- the standby charge pump 32 comprises a driving circuit 49 and a pump device 50 .
- the driving circuit 49 comprises a first driving inverter 51 and a second driving inverter 52 .
- the first driving inverter 51 has an input connected to the phase output 30 a and an output forming a first phase terminal 53 of the driving circuit 49 , supplying a first phase A having a frequency equal to the frequency of the phase signal CK.
- the second driving inverter 52 has an input connected to the first phase terminal 53 and an output forming a second phase terminal 54 of the driving circuit 49 , supplying a second phase B, which is phase-shifted 180° with respect to the first phase A.
- the pump device 50 comprises a first stage 55 a, a second stage 55 b, and a third stage 55 c, cascade-connected, each of which includes a charge capacitor 56 and a diode 57 .
- each diode 57 has a cathode terminal connected to a first terminal of a respective charge capacitor 56 .
- the diode 57 belonging to the first stage 55 a has its anode terminal connected to the supply line 44
- a cathode terminal of the diode 57 belonging to the third stage 55 c forms the high voltage output 33 of the standby charge pump 32 .
- Second terminals of the charge capacitors 56 form phase inputs of the first stage 55 a, second stage 55 b, and third stage 55 c.
- the phase inputs of the first and third stages 55 a 55 c are connected to the first phase terminal 53
- the phase input of the second stage 55 b is connected to the second phase terminal 54 .
- phase generator 30 The operation of the phase generator 30 is described hereinbelow.
- the standby signal SB enables the flip-flop 45
- the frequency selection signal SEL is set by the auxiliary regulator 37 at the low logic level and controls the selector 47 so as to connect the phase output 30 a to the first selectable input 47 a.
- the control signal V C is set at the high logic level. Consequently, also the output of the OR gate 46 supplies the high logic level to the control terminal of the enabling switch 43 , thus causing the enabling switch 43 to open and to trigger oscillation of the oscillator 40 .
- the flip-flop 45 operating as a frequency divider, generates and supplies to the selector 47 a standby timing signal CK 2 having a frequency equal to half the oscillation frequency of the oscillator 40 .
- phase signal CK present on the phase output of the phase generator 30 is equal to the standby timing signal CK 2 , which is oscillating, and the driving circuit 49 is able to operate the pump device 50 , thus supplying the first phase A and the second phase B.
- the control signal V C is set at the low logic level.
- the output of the OR gate 46 is at the low logic level if also the output of the flip-flop 45 is at the low logic level. Otherwise, the output of the OR gate 46 remains at the high logic level until the subsequent switching of the flip-flop 45 , then goes to the low logic level and remains there.
- the standby signal SB deactivates the flip-flop 45 and the output of the flip-flop 45 feeds the first selectable input 47 a of the selector 47 with a constant logic level, for example, low.
- the auxiliary regulator 37 sets the frequency selection signal SEL at the low logic level and controls the selector 47 so as to connect the phase output 30 a with the first selectable input 47 a. Consequently, the phase signal CK does not oscillate, and the driving circuit 49 supplies constant values both for the first phase A and for the second phase B, so interrupting the operation of the pump device 50 .
- the auxiliary regulator 37 sets the frequency selection signal SEL at the high logic level and controls the selector 47 so as to connect the phase output 30 a with the second selectable input 47 b.
- the phase signal CK is equal to the active operation timing signal CK 1 , which is oscillating, and the driving circuit 49 operates the pump device 50 through the first and second phases A, B.
- FIG. 3 shows a circuit diagram of the divider 21 .
- the first resistive element 22 of the divider 21 comprises a first transistor 60 , of PMOS type, diode-connected, having its gate terminal and drain terminal short-circuited and grounded, and its source terminal connected to the intermediate node 25 .
- the first transistor 60 has a nominal form factor (W/L).
- the second resistive element 23 comprises a plurality of second transistors 61 , of PMOS type, having a form factor equal to the nominal form factor (W/L), and a number N of selectable branches 62 , for example three.
- the second transistors 61 are diode-connected, i.e., they have their gate and drain terminals connected together, and are coupled in series between the intermediate node 25 and a third node 63 .
- the selectable branches 62 are connected in parallel and each of them comprises a selectable transistor 65 and a selection switch 66 .
- each selectable transistor 65 of PMOS type and diode-connected, has its gate and drain terminals connected to the third node 63 , and its source terminal connected to the output terminal 10 via a respective selection switch 66 .
- One among the selectable transistors 65 has a form factor equal to the nominal form factor (W/L), and the others have preset form factors different from the nominal form factor (W/L) and different from one another.
- the selection switches 66 comprising, for example, PMOS transistors, receive respective selection signals S 1 , S 2 , . . . , SN on respective control terminals.
- the dividing ratio of the divider 21 can be modified by inserting, through the selection signals S 1 , S 2 , . . . , SN, an appropriate selectable branch 62 .
- only one of the selection signals S 1 , S 2 , . . . , SN is set at the high logic level, corresponding to a high voltage value, such as to control closing of the corresponding selection switch 66 , while the other selection switches 66 remain open. Since, as known, the resistivity of MOS transistors depends upon the form factor, it is clear that the voltage drop between the output node 10 and the third node 63 , and consequently the dividing ratio of the divider 21 , depend upon which selectable transistor 65 has been inserted.
- the voltage boost device has the following advantages. First, it allows the standby voltage on the output terminal 10 to remain at a value close to the regulated read voltage necessary for reading throughout the standby state operation. Consequently, it is not necessary to wait for charge or stabilization transients when the memory 1 exits the standby state, and thus the time required for reading does not differ from the time required for the same operation during normal functioning in the active state.
- the standby charge pump is operated only when it is necessary, energy consumption is not substantially increased as compared to memories where all the charge pumps are deactivated in the standby state.
- the auxiliary regulator 37 allows the boosted voltage V P to remain at a high value also during active state operation, thus determining a negligible increase in the absorbed power.
- a further advantage is due to that the standby voltage V SB is regulated with precision, so as to reduce the risk of reading errors, even in the case of multilevel memories, which are more sensitive.
- the structure of the divider 21 advantageously increases the regulation precision of the standby voltage V SB . Because of inevitable spread in the process parameters, in fact, the reference voltage V REF may differ from the nominal value. Since the divider 21 includes selectable transistors 65 having different form factors, it is possible to vary the dividing ratio of the divider 21 and to compensate any deviations of the reference voltage V REF from the nominal value.
- the use of MOS transistors in the divider 21 enables high resistance values, and hence reduced consumption, for just a small area occupied.
- the resistance obtainable with a MOS divider is such as not to increase significantly the discharge currents of the output terminal 10 of the voltage boost device 3 .
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Abstract
Description
- The present invention refers to a voltage boost device for nonvolatile memories, which operates in a low consumption standby condition.
- As is known, nonvolatile memories are used, i.a., in systems comprising various devices and a microprocessor performing instructions and data transfer. In such devices it is important that, while a device is selected for interacting with the microprocessor, all the other devices are disabled, in order to prevent undesirable interference from causing errors.
- In order to speed up the processes for enabling and disabling the devices, and hence optimize system performance, when the devices are not selected, they are not turned off (i.e., they are not disconnected from their respective power supply sources), but brought to waiting, or standby, condition. This enables an advantageous reduction in energy consumption to be achieved, as well as the elimination of the danger of interference with processes currently in progress.
- On the other hand, in order not to degrade the processing speed of the system, transition from the standby state to the active state must be fast, and transients must be avoided that might slow down execution of the operations requested.
- As regards nonvolatile memories in particular, the most critical operation is reading, both because, as compared to other operations, such as programming and erasure, it must be performed in a very short time, and because it is necessary to supply the gate terminals of the cells to be read with high voltages, i.e., higher than the supply voltage. For low supply voltage multilevel memories it is moreover essential for the value of the read voltage supplied to be precise and close to the value of the nominal read voltage.
- In order to meet this requirement, a known solution consists in using voltage boosters employing charge pumps and regulation circuits, so as to obtain the required high read voltages and precision when the memory is selected to interact with the microprocessor.
- Such voltage boosters, however, have a drawback. In fact, the charge pumps and the regulation circuits have consumption levels which are too high to enable these devices to remain active also while the memory is in standby, and consequently they must be deactivated; on the other hand, when they are not supplied, the output terminals of the charge pumps, which are to supply the read voltage to the gate terminals of the addressed cells to be read, are discharged by leakage currents. Consequently, when the memory returns to the active state from the standby state, it is necessary to wait for a charge transient and it is not possible to reach the necessary read voltage rapidly and with the required precision. In this case, therefore, the reading operation requires a longer time as compared to when the memory is already in the active state.
- The aim of the present invention is to provide a voltage boost device which is free from the drawbacks described above, and in particular which enables a terminal to be kept at a desired voltage during the standby phases, and at the same time has low consumption levels.
- A voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal; the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.
- For a better understanding of the invention, an embodiment thereof is now described, as a non-limiting example, with reference to the attached drawings, in which:
- FIG. 1 shows a block diagram of a voltage boost device according to the present invention;
- FIG. 2 shows a more detailed diagram of two blocks of the device of FIG. 1; and
- FIG. 3 is a simplified circuit diagram of a detail of the device of FIG. 1.
- With reference to FIG. 1, a
nonvolatile memory 1, for example a four-level flash memory supplied at 3 V, comprises amemory array 2 and avoltage boost device 3 comprising a readvoltage boost stage 4 of a known type, which is shown only partially, and a standbyvoltage boost stage 5. - The
memory array 2 comprises a plurality of memory cells 6 arranged on rows and columns. In particular, the memory cells 6 belonging to a same row have their gate terminals connected to aword line 7. Arow decoder 8, of known type, connects selectively one of theword lines 7 of thememory array 2 with anoutput terminal 10 of thevoltage boost device 3. In addition, therow decoder 8 has a capacitance represented symbolically by a parasitic capacitor 11 connected between theoutput terminal 10 and ground. - The read
voltage boost stage 4 comprises aread charge pump 12 having an output supplying a read voltage VR and is connected, via a first switch 13, to afirst node 15. Thefirst node 15 is connected to a first terminal of aread capacitor 16, which has a second terminal grounded, and to an input of avoltage regulator 17 having an output supplying a regulated read voltage VRR and connected to theoutput terminal 10 via asecond switch 18. In addition, theread charge pump 12, thevoltage regulator 17, and respective control terminals of the first switch 13 and of thesecond switch 18 receive, from aknown control unit 20, a standby signal SB. - The standby
voltage boost stage 5 comprises adivider 21, aphase generator 30, avoltage booster 31, astandby charge pump 32, and anauxiliary regulator 37. - In detail, the
divider 21 is arranged between theoutput terminal 10 of thevoltage boost device 3 and ground, and comprises a firstresistive element 22 and a secondresistive element 23 which are connected together at anintermediate node 25, on which an intermediate voltage VX is present. In addition, thedivider 21 has a variable division ratio, as described in detail hereinbelow. - A
comparator 27 has an inverting input connected to theintermediate node 25 and a non-inverting input connected to avoltage generator 28, which supplies a constant reference voltage VREF. In addition, an output of thecomparator 27 is connected to an activation terminal of thephase generator 30. A control signal VC is supplied by output of thecomparator 27 and determines activation and deactivation of thestandby charge pump 32 during the standby phase. - The
phase generator 30, illustrated in greater detail hereinbelow, is also connected to thecontrol unit 20, from which it receives the standby signal SB and an active operation timing signal CK1 having one first frequency, as well as to an output of theauxiliary regulator 37 supplying a frequency selection signal SEL. In addition, thephase generator 30 has aphase output 30 a supplying a phase signal CK. - The
divider 21, thecomparator 27, and thephase generator 30 form anactivation circuit 29 activating thestandby charge pump 32, theactivation circuit 29 having an input connected to theoutput terminal 10 of thevoltage boost device 3 and an output forming thephase output 30 a. - The
standby charge pump 32 has an input connected to thephase output 30 a and ahigh voltage output 33, supplying a boosted voltage VP and connected to theoutput terminal 10 of thevoltage boost device 3 via a firsthigh voltage switch 34 and a secondhigh voltage switches 35, and to the input of theauxiliary regulator 37. In addition, asecond node 38, arranged between the first and the secondhigh voltage switch first node 15. - The
voltage booster 31 has a high voltage input connected to thehigh voltage output 33 and a control input receiving the standby signal SB. In addition, thevoltage booster 31 has an output connected with respective control terminals of the first and secondhigh voltage switches - The
auxiliary regulator 37 has a first input connected to thehigh voltage output 33 of thestandby charge pump 32 and a second input connected to thecontrol unit 20, and receiving the standby signal SB. - During operation of the
memory 1 in the standby state, thecontrol unit 20 assigns to the standby signal SB a first logic level, for example a high logic level, thus determining opening of the first and of thesecond switches 13, 18, and deactivation of theread charge pump 12 and of thevoltage regulator 17. In addition, the standby signal SB disables theauxiliary regulator 37, which thus generates a first logic level of the frequency selection signal SEL (for example, a low level), and enables thephase generator 30. The first logic level of the standby signal SB brings the driving voltage VD of thevoltage booster 31 to 0 V, so determining the first and the secondhigh voltage switches high voltage switches phase generator 30 causes the phase signal CK to oscillate between two preset logic levels at a second frequency, which is determined internally by thephase generator 30. Instead, when the control signal VC is at the low logic level and in a standby condition, thephase generator 30 maintains the phase signal CK at a preset logic level, for example low, interrupting operation of thestandby charge pump 32. - Upon entry into the standby state, a standby voltage VSB is present on the
output terminal 10. Standby voltage VSB represents an output voltage of the standbyvoltage boost stage 5 and is initially equal to the regulated read voltage VRR because of the connection existing (before entry into the standby state) on the output of thevoltage regulator 17. In this situation, the intermediate voltage VX, which is proportional to the standby voltage VSB according to the dividing ratio of thedivider 21, is at a value slightly higher than the reference voltage VREF, and, therefore, the control signal VC is at the low logic level. Consequently, the phase signal CK remains at low logic level, and thevoltage booster 31 keeps the firsthigh voltage switch 34 and the secondhigh voltage switch 35 open. - Subsequently, the standby voltage VSB and the intermediate voltage VX decrease by virtue of leakage currents and of a current flowing in the
divider 21. When the intermediate voltage VX drops below the reference voltage VREF, the control signal VC switches to the high logic level, and thephase generator 30 causes the phase signal CK to oscillate with a frequency determined by thephase generator 30. When thestandby charge pump 32 receives an oscillating signal (i.e., the phase signal CK), it is activated, so determining the sequence of phases of charging and transfer of charge, in a per se known manner. - Since the
standby charge pump 32 starts charging thehigh voltage output 33, the standby voltage VSB, which is equal to the boosted voltage VP, and the voltage VX increase. When the intermediate voltage VX exceeds the reference voltage VREF (and hence the standby read voltage VSB is slightly higher than the regulated read voltage VRR), the control signal VC returns low, so deactivating thephase generator 30, as explained previously with reference to the description of the entry into the standby state. In this way, the standbyvoltage regulator stage 5 is activated and deactivated automatically, so as to keep theoutput terminal 10 charged at the desired value (standby voltage VSB), and to enable fast reading when exiting the standby state, at the same time limiting consumption to what is strictly indispensable. - When the
memory 2 is set in the active state,control unit 20 sends the standby signal SB to a second logic level, for example the low logic level, causing theswitches 13, 18 to close, and theread charge pump 12 and thevoltage regulator 17 to be activated. In addition, the standby signal SB sets the driving voltage VD of thevoltage booster 31 to the high value (equal to the boosted voltage VP), keeping the firsthigh voltage switch 34 and the secondhigh voltage switch 35 open. Consequently, the firsthigh voltage switch 34 and the secondhigh voltage switch 35 are kept open, and thehigh voltage output 33 of thestandby charge pump 32 is disconnected from theoutput terminal 10 and from thefirst node 15. - During a reading operation, the
read charge pump 12 supplies the read voltage VR to thevoltage regulator 17, which, in turn, generates the regulated read voltage VRR. This regulated read voltage VRR is supplied to theword line 7 selected by theline decoder 8 for reading the addressed memory cells 6, in a per se known manner. - In the active operation state, the
standby charge pump 32 is enabled and driven by the timing signal of the other voltage boosters (not shown) present in thenonvolatile memory 1; it is, however, regulated through theauxiliary regulator 37, as described below. In fact, theauxiliary regulator 37 is active, and the frequency selection signal SEL assumes a logic level that depends upon the value of the boosted voltage VP, which, owing to the presence of leakage currents, decreases. When the boosted voltage VP drops below a preset threshold, theauxiliary regulator 37 causes the frequency selection signal SEL to switch to a second logic level (e.g., high) which controls thephase generator 30, as described hereinbelow, to transfer the active operation timing signal CK1 to thestandby charge pump 32. Consequently, thestandby charge pump 32 is activated at the frequency of the active operation timing signal CK1 until the boosted voltage VP returns above the preset threshold. Then, the frequency selection signal SEL switches and inhibits transfer of the active operation timing signal CK1 to thestandby charge pump 32, thus deactivating the latter again. - In this way, in standby, the standby voltage VSB on the
output terminal 10 is regulated at a slightly higher value than the regulated read voltage VRR (present in the active operation state). In addition, when thememory 1 is in the active state, thehigh voltage output 33 of thestandby charge pump 32 is regulated at the value of the regulated read voltage VRR. - FIG. 2 shows a more detailed diagram of the
phase generator 30 and of thestandby charge pump 32. - In particular, the
phase generator 30 comprises anoscillator 40 comprising a plurality ofinverters 41, in an odd number and connected together to form a loop. An enablingnode 42 is connected, via an enablingswitch 43, preferably formed by a PMOS transistor, to asupply line 44 supplying a supply voltage VCC, for example 3 V. In addition, the enablingnode 42 is connected to an input of a toggle-type flip-flop 45 having a set terminal connected to thecontrol unit 20, supplying the standby signal SB. - An OR
gate 46 has a first input connected to the output of thecomparator 27, a second input connected to an output of the flip-flop 45, and an output connected to a control terminal of the enablingswitch 43. - The
phase generator 30 further comprises aselector 47 having a firstselectable input 47 a connected to the output of the flip-flop 45, a secondselectable input 47 b connected to thecontrol unit 20 supplying the active operation timing signal CK1, a selection terminal 47 c receiving the frequency selection signal SEL, and an output defining thephase output 30 a of thephase generator 30. - The
standby charge pump 32 comprises a drivingcircuit 49 and apump device 50. - The driving
circuit 49 comprises afirst driving inverter 51 and asecond driving inverter 52. Thefirst driving inverter 51 has an input connected to thephase output 30 a and an output forming afirst phase terminal 53 of the drivingcircuit 49, supplying a first phase A having a frequency equal to the frequency of the phase signal CK. Thesecond driving inverter 52 has an input connected to thefirst phase terminal 53 and an output forming asecond phase terminal 54 of the drivingcircuit 49, supplying a second phase B, which is phase-shifted 180° with respect to the first phase A. - The
pump device 50 comprises afirst stage 55 a, asecond stage 55 b, and athird stage 55 c, cascade-connected, each of which includes acharge capacitor 56 and adiode 57. In particular, eachdiode 57 has a cathode terminal connected to a first terminal of arespective charge capacitor 56. In addition, thediode 57 belonging to thefirst stage 55 a has its anode terminal connected to thesupply line 44, and a cathode terminal of thediode 57 belonging to thethird stage 55 c forms thehigh voltage output 33 of thestandby charge pump 32. - Second terminals of the
charge capacitors 56 form phase inputs of thefirst stage 55 a,second stage 55 b, andthird stage 55 c. In detail, the phase inputs of the first andthird stages 55 a 55 c are connected to thefirst phase terminal 53, whereas the phase input of thesecond stage 55 b is connected to thesecond phase terminal 54. - The operation of the
phase generator 30 is described hereinbelow. During operation of thememory 1 in the standby state, the standby signal SB enables the flip-flop 45, and the frequency selection signal SEL is set by theauxiliary regulator 37 at the low logic level and controls theselector 47 so as to connect thephase output 30 a to the firstselectable input 47 a. - If the intermediate voltage VX is smaller than the reference voltage VREF (i.e., if the standby voltage VSB is smaller than the regulated read voltage VRR), the control signal VC is set at the high logic level. Consequently, also the output of the
OR gate 46 supplies the high logic level to the control terminal of the enablingswitch 43, thus causing the enablingswitch 43 to open and to trigger oscillation of theoscillator 40. In this way, the flip-flop 45, operating as a frequency divider, generates and supplies to theselector 47 a standby timing signal CK2 having a frequency equal to half the oscillation frequency of theoscillator 40. Consequently, the phase signal CK present on the phase output of thephase generator 30 is equal to the standby timing signal CK2, which is oscillating, and the drivingcircuit 49 is able to operate thepump device 50, thus supplying the first phase A and the second phase B. - When the intermediate voltage VX exceeds the reference voltage VREF, the control signal VC is set at the low logic level. In this condition, the output of the
OR gate 46 is at the low logic level if also the output of the flip-flop 45 is at the low logic level. Otherwise, the output of theOR gate 46 remains at the high logic level until the subsequent switching of the flip-flop 45, then goes to the low logic level and remains there. - As soon as the output of the
OR gate 46 reaches the low logic level, the enablingswitch 43 is closed. Consequently, the enablingnode 42 is connected to thesupply line 44 at a constant voltage, and the oscillation of theoscillator 40 is stopped. The flip-flop 45 therefore supplies a constant logic level (namely, the low logic level), the phase signal CK does not oscillate, and hence the drivingcircuit 49 is not able to drive thepump device 50, which is thus deactivated. - When the
memory 1 is in the active operating state, the standby signal SB deactivates the flip-flop 45 and the output of the flip-flop 45 feeds the firstselectable input 47 a of theselector 47 with a constant logic level, for example, low. - If the boosted voltage VP on the high voltage output is greater than a preset threshold, the
auxiliary regulator 37 sets the frequency selection signal SEL at the low logic level and controls theselector 47 so as to connect thephase output 30 a with the firstselectable input 47 a. Consequently, the phase signal CK does not oscillate, and the drivingcircuit 49 supplies constant values both for the first phase A and for the second phase B, so interrupting the operation of thepump device 50. - If, instead, the boosted voltage VP is lower than the aforesaid preset threshold, the
auxiliary regulator 37 sets the frequency selection signal SEL at the high logic level and controls theselector 47 so as to connect thephase output 30 a with the secondselectable input 47 b. Thereby, the phase signal CK is equal to the active operation timing signal CK1, which is oscillating, and the drivingcircuit 49 operates thepump device 50 through the first and second phases A, B. - FIG. 3 shows a circuit diagram of the
divider 21. In particular, the firstresistive element 22 of thedivider 21 comprises afirst transistor 60, of PMOS type, diode-connected, having its gate terminal and drain terminal short-circuited and grounded, and its source terminal connected to theintermediate node 25. In addition, thefirst transistor 60 has a nominal form factor (W/L). - The second
resistive element 23 comprises a plurality ofsecond transistors 61, of PMOS type, having a form factor equal to the nominal form factor (W/L), and a number N ofselectable branches 62, for example three. In particular, thesecond transistors 61 are diode-connected, i.e., they have their gate and drain terminals connected together, and are coupled in series between theintermediate node 25 and athird node 63. - The
selectable branches 62 are connected in parallel and each of them comprises aselectable transistor 65 and aselection switch 66. In detail, eachselectable transistor 65, of PMOS type and diode-connected, has its gate and drain terminals connected to thethird node 63, and its source terminal connected to theoutput terminal 10 via arespective selection switch 66. One among theselectable transistors 65 has a form factor equal to the nominal form factor (W/L), and the others have preset form factors different from the nominal form factor (W/L) and different from one another. - In addition, the selection switches66, comprising, for example, PMOS transistors, receive respective selection signals S1, S2, . . . , SN on respective control terminals.
- The dividing ratio of the
divider 21 can be modified by inserting, through the selection signals S1, S2, . . . , SN, an appropriateselectable branch 62. In particular, only one of the selection signals S1, S2, . . . , SN is set at the high logic level, corresponding to a high voltage value, such as to control closing of thecorresponding selection switch 66, while the other selection switches 66 remain open. Since, as known, the resistivity of MOS transistors depends upon the form factor, it is clear that the voltage drop between theoutput node 10 and thethird node 63, and consequently the dividing ratio of thedivider 21, depend upon whichselectable transistor 65 has been inserted. - The voltage boost device according to the present invention has the following advantages. First, it allows the standby voltage on the
output terminal 10 to remain at a value close to the regulated read voltage necessary for reading throughout the standby state operation. Consequently, it is not necessary to wait for charge or stabilization transients when thememory 1 exits the standby state, and thus the time required for reading does not differ from the time required for the same operation during normal functioning in the active state. - In addition, since the standby charge pump is operated only when it is necessary, energy consumption is not substantially increased as compared to memories where all the charge pumps are deactivated in the standby state. Furthermore, the
auxiliary regulator 37 allows the boosted voltage VP to remain at a high value also during active state operation, thus determining a negligible increase in the absorbed power. - A further advantage is due to that the standby voltage VSB is regulated with precision, so as to reduce the risk of reading errors, even in the case of multilevel memories, which are more sensitive.
- The structure of the
divider 21 advantageously increases the regulation precision of the standby voltage VSB. Because of inevitable spread in the process parameters, in fact, the reference voltage VREF may differ from the nominal value. Since thedivider 21 includesselectable transistors 65 having different form factors, it is possible to vary the dividing ratio of thedivider 21 and to compensate any deviations of the reference voltage VREF from the nominal value. - In addition, the use of MOS transistors in the
divider 21 enables high resistance values, and hence reduced consumption, for just a small area occupied. In particular, the resistance obtainable with a MOS divider is such as not to increase significantly the discharge currents of theoutput terminal 10 of thevoltage boost device 3. - Finally, it is clear that numerous variations and modifications may be made to the voltage boost device described and illustrated herein, all falling within the scope of the invention, as defined in the attached claims.
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99830825A EP1113450B1 (en) | 1999-12-30 | 1999-12-30 | Voltage boost device for nonvolatile memories, operating in a low consumption standby condition |
EP99830825.8 | 1999-12-30 | ||
EP99830825 | 1999-12-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010017797A1 true US20010017797A1 (en) | 2001-08-30 |
US6437636B2 US6437636B2 (en) | 2002-08-20 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/747,312 Expired - Lifetime US6437636B2 (en) | 1999-12-30 | 2000-12-22 | Low consumption voltage boost device |
Country Status (3)
Country | Link |
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US (1) | US6437636B2 (en) |
EP (1) | EP1113450B1 (en) |
DE (1) | DE69935919D1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20070035973A1 (en) * | 2005-08-12 | 2007-02-15 | Kazuhiro Kitazaki | Semiconductor device and method for boosting word line |
US20080012627A1 (en) * | 2006-07-13 | 2008-01-17 | Yosuke Kato | System and method for low voltage booster circuits |
US20230188038A1 (en) * | 2021-12-09 | 2023-06-15 | Renesas Electronics America Inc. | Regulator booster |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3836279B2 (en) * | 1999-11-08 | 2006-10-25 | 株式会社東芝 | Semiconductor memory device and control method thereof |
JP4149637B2 (en) * | 2000-05-25 | 2008-09-10 | 株式会社東芝 | Semiconductor device |
IT1316002B1 (en) * | 2000-11-08 | 2003-03-26 | St Microelectronics Srl | VOLTAGE REGULATOR FOR LOW CONSUMPTION CIRCUITS. |
US6661682B2 (en) * | 2001-02-16 | 2003-12-09 | Imec (Interuniversitair Microelectronica Centrum) | High voltage generating charge pump circuit |
FR2838861A1 (en) * | 2002-04-23 | 2003-10-24 | St Microelectronics Sa | Electrically erasable and programmable memory comprising a device for managing an internal voltage supply |
ITMI20021486A1 (en) * | 2002-07-05 | 2004-01-05 | St Microelectronics Srl | VOLTAGE ELEVATOR DEVICE AND MEMORY SYSTEM |
JP2004103153A (en) * | 2002-09-11 | 2004-04-02 | Seiko Epson Corp | Voltage generating circuit for nonvolatile semiconductor memory device |
JP4384541B2 (en) * | 2004-05-21 | 2009-12-16 | 株式会社ケーヒン | Actuator drive |
IT1400747B1 (en) * | 2010-06-30 | 2013-07-02 | St Microelectronics Srl | POWER CONSUMPTION REDUCTION OF ELECTRONIC DEVICES |
Family Cites Families (10)
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US5337284A (en) * | 1993-01-11 | 1994-08-09 | United Memories, Inc. | High voltage generator having a self-timed clock circuit and charge pump, and a method therefor |
US6031411A (en) * | 1993-06-28 | 2000-02-29 | Texas Instruments Incorporated | Low power substrate bias circuit |
JPH07105681A (en) * | 1993-10-07 | 1995-04-21 | Mitsubishi Electric Corp | Semiconductor device |
JP3413298B2 (en) * | 1994-12-02 | 2003-06-03 | 三菱電機株式会社 | Semiconductor storage device |
KR960024788U (en) * | 1994-12-30 | 1996-07-22 | Drive unit of the disc player | |
US5880622A (en) * | 1996-12-17 | 1999-03-09 | Intel Corporation | Method and apparatus for controlling a charge pump for rapid initialization |
JP3378457B2 (en) * | 1997-02-26 | 2003-02-17 | 株式会社東芝 | Semiconductor device |
TW423162B (en) * | 1997-02-27 | 2001-02-21 | Toshiba Corp | Power voltage supplying circuit and semiconductor memory including the same |
US5801997A (en) * | 1997-06-24 | 1998-09-01 | Etron Technology, Inc. | Ping-pong boost circuit |
KR100273278B1 (en) * | 1998-02-11 | 2001-01-15 | 김영환 | Pumping circuit of semiconductor memory device |
-
1999
- 1999-12-30 DE DE69935919T patent/DE69935919D1/en not_active Expired - Lifetime
- 1999-12-30 EP EP99830825A patent/EP1113450B1/en not_active Expired - Lifetime
-
2000
- 2000-12-22 US US09/747,312 patent/US6437636B2/en not_active Expired - Lifetime
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070035973A1 (en) * | 2005-08-12 | 2007-02-15 | Kazuhiro Kitazaki | Semiconductor device and method for boosting word line |
US7525853B2 (en) * | 2005-08-12 | 2009-04-28 | Spansion Llc | Semiconductor device and method for boosting word line |
US20090175096A1 (en) * | 2005-08-12 | 2009-07-09 | Kazuhiro Kitazaki | Semiconductor device and method for boosting word line |
US7791961B2 (en) | 2005-08-12 | 2010-09-07 | Spansion Llc | Semiconductor device and method for boosting word line |
US20080012627A1 (en) * | 2006-07-13 | 2008-01-17 | Yosuke Kato | System and method for low voltage booster circuits |
US20230188038A1 (en) * | 2021-12-09 | 2023-06-15 | Renesas Electronics America Inc. | Regulator booster |
Also Published As
Publication number | Publication date |
---|---|
EP1113450B1 (en) | 2007-04-25 |
EP1113450A1 (en) | 2001-07-04 |
US6437636B2 (en) | 2002-08-20 |
DE69935919D1 (en) | 2007-06-06 |
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