US20010002709A1 - Process to produce ultrathin crystalline silicon nitride on Si (111 ) for advanced gate dielectrics - Google Patents
Process to produce ultrathin crystalline silicon nitride on Si (111 ) for advanced gate dielectrics Download PDFInfo
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- US20010002709A1 US20010002709A1 US09/747,966 US74796600A US2001002709A1 US 20010002709 A1 US20010002709 A1 US 20010002709A1 US 74796600 A US74796600 A US 74796600A US 2001002709 A1 US2001002709 A1 US 2001002709A1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 64
- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims description 18
- 239000003989 dielectric material Substances 0.000 title description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 11
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 239000004408 titanium dioxide Substances 0.000 claims abstract 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 239000000758 substrate Substances 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000005641 tunneling Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
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Definitions
- This invention relates to a method of producing ultrathin crystalline silicon nitride on Si ( 111 ) and formation of semiconductor devices using such ultrathin crystalline silicon nitride.
- a further problem with silicon dioxide dielectrics over Si ( 100 ) substrates is that boron from boron-doped polysilicon gate structures can diffuse through the silicon dioxide, this problem increasing with decreased gate oxide thickness geometries, thereby degrading the properties of the device, particularly in the channel region.
- Boron does not diffuise through silicon nitride, however, the interface between silicon nitride and Si ( 100 ) results in an amorphous silicon nitride and provides an inferior structure to that with silicon dioxide by causing a disruption of the electron flow in the channel of the active semiconductor devices.
- silicon dioxide dielectrics A separate problem with silicon dioxide dielectrics is that the extremely small thicknesses allow unacceptable leakage currents as a result of electrons tunneling from the gate to the drain regions of transistors. Since silicon nitride has a larger bulk dielectric constant than silicon dioxide ( ⁇ 7 compared to about 3.9), a thicker silicon nitride layer can be used which has the same capacitance density as a thinner silicon dioxide layer. Since electron tunneling currents depend exponentially on layer thickness, even an increase in dielectric thickness of about 10 to about 20 Angstroms could reduce leakage current by several orders of magnitude.
- the cleaning process could include, for example, a standard semiconductor wet clean followed by oxidation (chemical or thermal), then followed by HF-last stripping of the oxide for H-termination.
- the hydrogen is then desorbed in the course of the temperature ramp-up for nitride deposition.
- the cleaning can take place by ultra high vacuum (UHV), from about 10 ⁇ 11 to about 10 ⁇ 9 Torr, “flash heating” to about 1100° C. and cooling to room temperature to form a well-ordered surface. Under the proper temperature conditions (850° C.
- the nitride film covered Si ( 111 ) surface is atomically flat, i.e., where only single height steps between nitride terraces exist.
- the resultant crystalline film is thus useful for an epitaxial nitride layer, or it will be useful for the purpose of surface passivation and subsequent crystalline or amorphous dielectric film overgrowth.
- Interface state densities associated with such an epitaxial layer are low because the dangling bonds are consumed with the epitaxial growth process.
- the smooth interface afforded by the Si ( 111 ) surface preparation results in an atomically flat nitride layer as well.
- Such sharp smooth interfaces result in enhanced electron mobility properties (less interface scattering) as well as a superior dopant diffuision barrier. Any residual dangling bonds can be satiated from a H 2 or D 2 sintering process.
- Another problem of the prior art that is minimized in accordance with the present invention is based upon the fact that as that the drive current is proportional to the capacitance between the gate electrode and the substrate. Therefore, for a given drive current as the contact area of the dielectric decreases the dielectric thickness must also decrease. The result is that electrons from the gate electrode are then capable of tunneling through the dielectric and add to the channel or drain current, resulting in lack of device control. Since the dielectric constant of silicon dioxide is about 3.9 and the dielectric constant of silicon nitride is about 7 , a thicker layer of silicon nitride can be provided with the same capacitance and drive current properties, yet prevent electron tunneling through the dielectric.
- a surface of Si ( 111 ) which has been cleaned and is atomically flat as defined hereinabove.
- the Si( 111 ) surface is placed in a standard reaction chamber and the chamber purged and filled with ammonia (NH 3 ) at an ammonia partial pressure of from about 1 ⁇ 10 ⁇ 7 to about 1 ⁇ 10 ⁇ 5 Torr at a temperature of from about 850° C. to about 1000° C. for from about 5 seconds to about 5 minutes to provide a thin layer of crystalline silicon nitride on the Si ( 111 ) of from about 0.3 nm to about 3 nm.
- NH 3 ammonia
- the remainder of the semiconductor device is then fabricated in standard manner by, for example, depositing a doped layer of polysilicon or a metal layer over the silicon nitride layer.
- a doped layer of polysilicon or a metal layer over the silicon nitride layer.
- the boron will be prevented from diffusing through the dielectric due to the use of silicon nitride as the dielectric.
- silicon nitride has been discussed above as being the dielectric material, it should be understood that other materials can be used that have a higher dielectric constant than and are compatible with silicon nitride.
- a very thin layer of silicon nitride can be used to separate the dielectric material from the Si ( 111 ) substrate and/or the electrode over the dielectric, such thin layer having a thickness of about 2 monolayers.
- FIG. 1 is a cross sectional view of a semiconductor device fabricated in accordance with a first embodiment in accordance with the present invention.
- FIG. 2 is a cross sectional view of a semiconductor device fabricated in accordance with a second embodiment in accordance with the present invention.
- FIG. 1 there is shown a semiconductor device fabricated in accordance with a first embodiment of the present invention.
- the semiconductor device includes a Si ( 111 ) substrate 1 over which is formed a dielectric layer of crystalline silicon nitride (Si 3 N 4 )3.
- An electrode layer 5 of boron- or phosphorous- or arsenic-doped polycrystalline silicon is formed over the dielectric layer to form the completed semiconductor active transistor structure.
- the semiconductor device of FIG. 1 is fabricated by providing a substrate 1 having an exposed surface which is cleaned in a manner as described above and is atomically flat.
- the substrate was placed in a reaction chamber which was purged and then filled with ammonia gas at a pressure of 1 ⁇ 10 ⁇ 6 Torr at a temperature of 900° C. for 4 minutes to form the layer of crystalline silicon nitride 3 having a thickness of 0.5 nm on the cleaned surface.
- the reaction chamber was then purged and polycrystalline silicon with boron or phosphorous or arsenic was deposited over the silicon nitride layer in standard manner to provide the electrode layer 5 .
- FIG. 2 there is shown a semiconductor device fabricated in accordance with a second embodiment of the present invention.
- the semiconductor device includes a Si ( 111 ) substrate 11 over which is formed a first dielectric layer of crystalline silicon nitride (Si 3 N 4 ) 13 having a two monolayer thickness.
- a second layer of tantalum pentoxide 15 is then deposited over the silicon nitride having a thickness of 4 nm followed by a third dielectric layer of silicon nitride 17 having a two monolayer thickness
- An electrode layer 19 of boron- or phorphorous- or arsenic-doped polycrystalline silicon is formed over the third dielectric layer 17 to form the completed semiconductor active transistor structure.
- the semiconductor device of FIG. 2 is fabricated by providing a substrate 11 having an exposed surface as in the first embodiment.
- the substrate was placed in a reaction chamber which was purged and then filled with ammonia gas at a pressure of 1 ⁇ 10 ⁇ 6 Torr at a temperature of 900° C. for 4 minutes to form the first dielectric layer of crystalline silicon nitride 13 having a thickness of two monolayers on the cleaned surface.
- the reaction chamber was then purged and the second dielectric layer of tantalum pentoxide 15 having a thickness of 4 nm was deposited over the first dielectric layer in standard manner.
- the reaction chamber was again purged and the third dielectric layer of crystalline silicon nitride 17 was deposited over the second dielectric layer 15 using the same procedure as used for the first dielectric layer.
- a layer of polycrystalline silicon with boron or phosphorous or arsenic was deposited over the silicon nitride layer in standard manner to provide the electrode layer 5 .
Abstract
A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10 −7 to about 1×10 −5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers. A second dielectric layer compatible with silicon nitride and having a higher dielectric constant than silicon nitride is formed on the first dielectric layer and an electrode layer is formed over the second dielectric layer. A third dielectric layer of silicon nitride having a thickness of about 2 monolayers can be formed between the second dielectric layer and the electrode layer. The second dielectric layer is preferably taken from the class consisting of tantalum pentoxide, titanium dioxide and a perovskite material. Both silicon nitride layers can be formed as in the first embodiment. The electrode layer is preferably heavily doped silicon
Description
- 1. Field of the Invention
- This invention relates to a method of producing ultrathin crystalline silicon nitride on Si (111) and formation of semiconductor devices using such ultrathin crystalline silicon nitride.
- 2. Brief Description of the Prior Art
- The continued down-scaling of the geometries in VLSI technology has involved, as a result of such down-scaling, a reduction in component film thicknesses, examples being gate dielectrics for FET semiconductor devices and the capacitor dielectric for semiconductor memory devices. Thickness uniformity requirements for such films (about 0.14 nanometers in thickeness in present technology) requires extraordinary control over the silicon wafer surface morphology (i.e., subsequent interfacial roughness) to achieve necessary scaling. The acute sensitivity of interface roughness with ultrathin films is evident when one considers the control required over large (200 mm or 300 mm) wafers.
- Conventional silicon semiconductor technology incorporates Si (100) substrates, largely because of interface trap density (Dit) considerations associated with oxide films on Si (100) which has been extensively researched over the past two decades. Moreover, it has been demonstrated that surface preparation methods currently developed, such as HF-last treatments, can result in a Si (100) hydrogen-terminated surface with a roughness which is unacceptable for prospective dielectric film thickness uniformity requirements. The use of alternative dielectric materials, such as silicon nitride, has been considered as a means to increase the gate dielectric constant and also to serve as a diffusion barrier to dopants in the gate material. However, the current silicon nitride fabrication techniques on Si (100) result in an amorphous nitride or oxynitride layer which may exhibit deleterious interface states (traps) which degrade ultimate device performance.
- A further problem with silicon dioxide dielectrics over Si (100) substrates is that boron from boron-doped polysilicon gate structures can diffuse through the silicon dioxide, this problem increasing with decreased gate oxide thickness geometries, thereby degrading the properties of the device, particularly in the channel region. Boron, on the other hand, does not diffuise through silicon nitride, however, the interface between silicon nitride and Si (100) results in an amorphous silicon nitride and provides an inferior structure to that with silicon dioxide by causing a disruption of the electron flow in the channel of the active semiconductor devices.
- A separate problem with silicon dioxide dielectrics is that the extremely small thicknesses allow unacceptable leakage currents as a result of electrons tunneling from the gate to the drain regions of transistors. Since silicon nitride has a larger bulk dielectric constant than silicon dioxide (˜7 compared to about 3.9), a thicker silicon nitride layer can be used which has the same capacitance density as a thinner silicon dioxide layer. Since electron tunneling currents depend exponentially on layer thickness, even an increase in dielectric thickness of about10 to about 20 Angstroms could reduce leakage current by several orders of magnitude.
- Recent work has demonstrated that the Dit from oxides on Si (111) can be made comparable to those on Si (100), thus making devices on such substrates feasible. The silicon (111) surface can be controlled to be made hydrogen-terminated and atomically flat from a careful control of the surface preparation solution pH. The resultant smooth surface can therefore result in a low roughness (<0.1 nm, rms) interface after subsequent film deposition. Recent research has also demonstrated the potential formation of an ordered silicon nitride film on the Si (111 ) surface from the reaction of NH3 with an atomically clean Si (111) surface, i.e., where no surface impurities are detected, at temperatures between 800° C. and 1130° C. under high vacuum conditions of from about 10−7 to about 10−5 Torr NH3 partial pressures. The cleaning process could include, for example, a standard semiconductor wet clean followed by oxidation (chemical or thermal), then followed by HF-last stripping of the oxide for H-termination. The hydrogen is then desorbed in the course of the temperature ramp-up for nitride deposition. Alternatively, the cleaning can take place by ultra high vacuum (UHV), from about 10−11 to about 10−9 Torr, “flash heating” to about 1100° C. and cooling to room temperature to form a well-ordered surface. Under the proper temperature conditions (850° C. to 1000° C.), the nitride film covered Si (111) surface is atomically flat, i.e., where only single height steps between nitride terraces exist. The resultant crystalline film is thus useful for an epitaxial nitride layer, or it will be useful for the purpose of surface passivation and subsequent crystalline or amorphous dielectric film overgrowth.
- Interface state densities associated with such an epitaxial layer are low because the dangling bonds are consumed with the epitaxial growth process. Moreover, the smooth interface afforded by the Si (111) surface preparation results in an atomically flat nitride layer as well. Such sharp smooth interfaces result in enhanced electron mobility properties (less interface scattering) as well as a superior dopant diffuision barrier. Any residual dangling bonds can be satiated from a H2 or D2 sintering process.
- In accordance with the present invention, the above described problems of the prior art are therefore minimized and there is provided an ultrathin crystalline silicon nitride layer on Si (111) for use, primarily though not exclusively as a gate dielectric for semiconductor devices and as a capacitor dielectric in semiconductor memory devices.
- Briefly, by growing crystalline silicon nitride on Si (111), the barrier to boron diffusion is retained and, in addition, the channel is not disrupted as in the case of amorphous silicon nitride over a Si (100) substrate.
- Another problem of the prior art that is minimized in accordance with the present invention is based upon the fact that as that the drive current is proportional to the capacitance between the gate electrode and the substrate. Therefore, for a given drive current as the contact area of the dielectric decreases the dielectric thickness must also decrease. The result is that electrons from the gate electrode are then capable of tunneling through the dielectric and add to the channel or drain current, resulting in lack of device control. Since the dielectric constant of silicon dioxide is about 3.9 and the dielectric constant of silicon nitride is about7, a thicker layer of silicon nitride can be provided with the same capacitance and drive current properties, yet prevent electron tunneling through the dielectric.
- To form a semiconductor device in accordance with the present invention, there is initially provided a surface of Si (111) which has been cleaned and is atomically flat as defined hereinabove. The Si(111) surface is placed in a standard reaction chamber and the chamber purged and filled with ammonia (NH3) at an ammonia partial pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. for from about 5 seconds to about 5 minutes to provide a thin layer of crystalline silicon nitride on the Si (111) of from about 0.3 nm to about 3 nm. The remainder of the semiconductor device is then fabricated in standard manner by, for example, depositing a doped layer of polysilicon or a metal layer over the silicon nitride layer. In the case of a boron-doped polysilicon electrode, the boron will be prevented from diffusing through the dielectric due to the use of silicon nitride as the dielectric.
- While silicon nitride has been discussed above as being the dielectric material, it should be understood that other materials can be used that have a higher dielectric constant than and are compatible with silicon nitride. When there is a lack of silicon compatibility resulting in SiOx formation at the interface, such as, for example, with tantalum pentoxide (Ta2O5), titanium dioxide (TiO2) or a perovskite material, a very thin layer of silicon nitride can be used to separate the dielectric material from the Si (111) substrate and/or the electrode over the dielectric, such thin layer having a thickness of about 2 monolayers.
- FIG. 1 is a cross sectional view of a semiconductor device fabricated in accordance with a first embodiment in accordance with the present invention; and
- FIG. 2 is a cross sectional view of a semiconductor device fabricated in accordance with a second embodiment in accordance with the present invention.
- Referring first to FIG. 1, there is shown a semiconductor device fabricated in accordance with a first embodiment of the present invention. The semiconductor device includes a Si (111)
substrate 1 over which is formed a dielectric layer of crystalline silicon nitride (Si3N4)3. Anelectrode layer 5 of boron- or phosphorous- or arsenic-doped polycrystalline silicon is formed over the dielectric layer to form the completed semiconductor active transistor structure. - The semiconductor device of FIG. 1 is fabricated by providing a
substrate 1 having an exposed surface which is cleaned in a manner as described above and is atomically flat. The substrate was placed in a reaction chamber which was purged and then filled with ammonia gas at a pressure of 1×10−6 Torr at a temperature of 900° C. for 4 minutes to form the layer ofcrystalline silicon nitride 3 having a thickness of 0.5 nm on the cleaned surface. The reaction chamber was then purged and polycrystalline silicon with boron or phosphorous or arsenic was deposited over the silicon nitride layer in standard manner to provide theelectrode layer 5. - Referring first to FIG. 2, there is shown a semiconductor device fabricated in accordance with a second embodiment of the present invention. The semiconductor device includes a Si (111) substrate 11 over which is formed a first dielectric layer of crystalline silicon nitride (Si3N4) 13 having a two monolayer thickness. A second layer of
tantalum pentoxide 15 is then deposited over the silicon nitride having a thickness of 4 nm followed by a third dielectric layer ofsilicon nitride 17 having a two monolayer thickness Anelectrode layer 19 of boron- or phorphorous- or arsenic-doped polycrystalline silicon is formed over the thirddielectric layer 17 to form the completed semiconductor active transistor structure. - The semiconductor device of FIG. 2 is fabricated by providing a substrate11 having an exposed surface as in the first embodiment. The substrate was placed in a reaction chamber which was purged and then filled with ammonia gas at a pressure of 1×10−6 Torr at a temperature of 900° C. for 4 minutes to form the first dielectric layer of
crystalline silicon nitride 13 having a thickness of two monolayers on the cleaned surface. The reaction chamber was then purged and the second dielectric layer oftantalum pentoxide 15 having a thickness of 4 nm was deposited over the first dielectric layer in standard manner. The reaction chamber was again purged and the third dielectric layer ofcrystalline silicon nitride 17 was deposited over the seconddielectric layer 15 using the same procedure as used for the first dielectric layer. A layer of polycrystalline silicon with boron or phosphorous or arsenic was deposited over the silicon nitride layer in standard manner to provide theelectrode layer 5. - Though the invention has been described with reference to specific preferred embodiments thereof, many variations and modification will immediately become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.
Claims (21)
1. A method of making a semiconductor device which comprises the steps of:
(a) providing a silicon (111) surface;
(b) forming on said surface a dielectric layer of crystalline silicon nitride; and
(c) forming an electrode layer on said dielectric layer of silicon nitride.
2. The method of further including the step of cleaning said surface and making said surface atomically flat.
claim 1
3. The method wherein said step of forming said dielectric layer of crystalline silicon nitride comprises the steps of placing said surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×1−5 Torr at a temperature of from about 850° C. to about 1000° C.
claim 1
4. The method wherein said step of forming said dielectric layer of crystalline silicon nitride comprises the steps of placing said surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C.
claim 2
5. The method of wherein said electrode layer is boron doped silicon.
claim 3
6. The method of wherein said electrode layer is boron doped silicon.
claim 4
7. A semiconductor device which comprises:
(a) a silicon (111) surface;
(b) a dielectric layer of crystalline silicon nitride on said surface; and
(c) an electrode layer on said dielectric layer of silicon nitride.
8. The device of wherein said surface is cleaned and atomically flat.
claim 7
9. The device of wherein said electrode layer is boron doped silicon.
claim 7
10. The device of wherein said electrode layer is boron doped silicon.
claim 8
11. A method of making a semiconductor device which comprises the steps of:
(a) providing a silicon (111) surface;
(b) forming on said surface a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers;
(c) forming on said first dielectric layer a second dielectric layer compatible with silicon nitride and having a higher dielectric constant than silicon nitride; and
(d) forming an electrode layer over said second dielectric layer.
12. The method of further including the step of forming between said second dielectric layer and said electrode layer a third dielectric layer of silicon nitride having a thickness of about 2 monolayers.
claim 11
13. The method of wherein said second dielectric layer is taken from the class consisting of tantalum pentoxide, titanium dioxide and a perovskite material.
claim 11
14. The method of wherein said second dielectric layer is taken from the class consisting of tantalum pentoxide, titanium dioxide and a perovskite material.
claim 12
15. The method wherein said step of forming said first dielectric layer of crystalline silicon nitride comprises the steps of placing said surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C.
claim 11
16. The method wherein said step of forming said dielectric layer of crystalline silicon nitride comprises the steps of placing said surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C.
claim 14
17. The method of wherein said electrode layer is boron doped silicon.
claim 16
18. A semiconductor device which comprises:
(a) a silicon (111) surface;
(b) a first dielectric layer of crystalline silicon nitride on said surface having a thickness of about 2 monolayers;
(c) a second dielectric layer on said first dielectric layer compatible with silicon nitride and having a higher dielectric constant than silicon nitride; and
(d) an electrode layer over said second dielectric layer.
19. The device of further including, between said second dielectric layer and said electrode layer, a third dielectric layer of silicon nitride having a thickness of about 2 monolayers.
claim 18
20. The device of wherein said second dielectric layer is taken from the class consisting of tantalum pentoxide, titanium dioxide and a perovskite material an electrode layer on said dielectric layer of silicon nitride.
claim 19
21. The device of wherein said electrode layer is boron doped silicon.
claim 20
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